1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_NUM_SLOTS 10 /*forcing this to 10 */
23 #define SCH_MAX_SFN 1024
24 #define MAX_NUM_RB 106 /* value for numerology 0 15Khz */
25 #define SCH_MIB_TRANS 80
26 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
27 #define SCH_MAX_SSB_BEAM 4 /* since we are supporting only SCS=15KHz */
28 #define SCH_SCS_15KHZ 0 /* numerology 0 and 15Khz */
29 #define SCH_SYMBOL_PER_SLOT 14
30 #define SCH_SSB_NUM_SYMB 4
31 #define SCH_SSB_NUM_PRB 20
36 #define PUSCH_START_RB 15
37 #define PUCCH_NUM_PRB_FORMAT_0 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
38 #define SI_RNTI 0xFFFF
40 #define DMRS_MAP_TYPE_A 1
41 #define NUM_DMRS_SYMBOLS 12
42 #define DMRS_ADDITIONAL_POS 2
46 #define UL_GRANT_SIZE 224
48 typedef struct schCellCb SchCellCb;
49 typedef struct schUeCb SchUeCb;
53 SCH_UE_STATE_INACTIVE,
59 * Structure holding LTE MAC's General Configuration information.
61 typedef struct schGenCb
63 uint8_t tmrRes; /*!< Timer resolution */
64 uint8_t startCellId; /*!< Starting Cell Id */
66 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
67 of RLC control BO and SRB BO on
68 PCell. val 0 means don't force*/
69 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
75 * scheduler allocationsfor DL per cell.
77 typedef struct schDlSlotInfo
79 uint16_t totalPrb; /*!< Number of RBs in the cell */
80 uint16_t assignedPrb[SCH_SYMBOL_PER_SLOT]; /*!< Num RBs and corresponding symbols allocated */
81 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
82 uint8_t ssbIdxSupported; /*!< Max SSB index */
83 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
84 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
85 RarInfo *rarInfo; /*!< RAR info */
86 Msg4Info *msg4Info; /*!< msg4 info */
89 typedef struct schRaCb
96 * scheduler allocationsfor UL per cell.
98 typedef struct schUlSlotInfo
100 uint16_t totalPrb; /*!< Number of RBs in the cell */
101 uint16_t assignedPrb[SCH_SYMBOL_PER_SLOT]; /*!< Num RBs and corresponding symbols allocated */
102 uint8_t puschCurrentPrb; /* Current PRB for PUSCH allocation */
103 bool puschPres; /*!< PUSCH presence field */
104 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
105 bool pucchPres; /*!< PUCCH presence field */
106 SchPucchInfo schPucchInfo; /*!< PUCCH info */
111 * BSR info per slot per UE.
113 typedef struct bsrInfo
115 uint8_t priority; /* CG priority */
116 uint32_t dataVol; /* Data volume requested in bytes */
125 typedef struct schUeCb
133 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
138 * Cell Control block per cell.
140 typedef struct schCellCb
142 uint16_t cellId; /*!< Cell ID */
143 Inst instIdx; /*!< Index of the scheduler instance */
144 Inst macInst; /*!< Index of the MAC instance */
145 uint8_t numSlots; /*!< Number of slots in current frame */
146 SlotIndInfo slotInfo; /*!< SFN, Slot info being processed*/
147 SchDlSlotInfo *schDlSlotInfo[SCH_NUM_SLOTS]; /*!< SCH resource allocations in DL */
148 SchUlSlotInfo *schUlSlotInfo[SCH_NUM_SLOTS]; /*!< SCH resource allocations in UL */
149 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
150 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
151 SchRaCb raCb[MAX_NUM_UE]; /*!< Rach Cb */
153 SchUeCb ueCb[MAX_NUM_UE];
158 * Control block for sch
162 TskInit schInit; /*!< Task Init info */
163 SchGenCb genCfg; /*!< General Config info */
164 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
167 /* Declaration for scheduler control blocks */
168 SchCb schCb[SCH_MAX_INST];
170 /* function declarations */
171 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,uint16_t slot);
172 uint8_t schProcessSlotInd(SlotIndInfo *slotInd, Inst inst);
173 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
174 uint8_t schDlRsrcAllocMsg4(Msg4Alloc *msg4Alloc, SchCellCb *cell, uint16_t slot);
175 uint16_t schCalcTbSize(uint16_t payLoadSize);
176 uint16_t schCalcNumPrb(uint16_t tbSize, uint16_t mcs, uint8_t numSymbols);
177 uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot);
178 uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
179 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo puschInfo, DciInfo *dciInfo);
180 uint8_t schFillPuschAlloc(SchUeCb *ueCb, uint16_t pdcchSlot, uint32_t dataVol, SchPuschInfo *puschInfo);
182 /**********************************************************************
184 **********************************************************************/