1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
29 #define MAX_NUM_RB 275 /* value for numerology 1, 100 MHz */
31 #define MAX_NUM_RB 106 /* value for numerology 0, 20 MHz */
33 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
34 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
35 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
36 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
37 #define SCH_SSB_NUM_SYMB 4
38 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
43 #define PDSCH_START_RB 10
44 /* Considering pdsch region from 3 to 13, DMRS exclued.
45 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
46 #define NUM_PDSCH_SYMBOL 11
47 #define PUSCH_START_RB 15
48 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
49 #define SI_RNTI 0xFFFF
51 #define DMRS_MAP_TYPE_A 1
52 #define NUM_DMRS_SYMBOLS 1
53 #define DMRS_ADDITIONAL_POS 0
54 #define SCH_DEFAULT_K1 1
55 #define SCH_TQ_SIZE 10
56 #define SSB_IDX_SUPPORTED 1
61 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
62 #define UL_GRANT_SIZE 224
64 #define PRB_BITMAP_IDX_LEN 64
65 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
67 typedef struct schCellCb SchCellCb;
68 typedef struct schUeCb SchUeCb;
81 SCH_UE_STATE_INACTIVE,
87 SCH_LC_STATE_INACTIVE,
100 * Structure holding LTE MAC's General Configuration information.
102 typedef struct schGenCb
104 uint8_t tmrRes; /*!< Timer resolution */
105 uint8_t startCellId; /*!< Starting Cell Id */
107 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
108 of RLC control BO and SRB BO on
109 PCell. val 0 means don't force*/
110 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
114 typedef struct freePrbBlock
123 * PRB allocations for a symbol within a slot
125 typedef struct schPrbAlloc
127 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
128 uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
133 * scheduler allocationsfor DL per cell.
135 typedef struct schDlSlotInfo
137 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
138 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
139 uint8_t ssbIdxSupported; /*!< Max SSB index */
140 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
141 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
142 RarAlloc *rarAlloc; /*!< RAR allocation */
143 DlMsgInfo *dlMsgInfo; /*!< DL dedicated Msg info */
146 typedef struct schRaCb
153 * scheduler allocationsfor UL per cell.
155 typedef struct schUlSlotInfo
157 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
158 uint8_t puschCurrentPrb; /* Current PRB for PUSCH allocation */
159 bool puschPres; /*!< PUSCH presence field */
160 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
161 bool pucchPres; /*!< PUCCH presence field */
162 SchPucchInfo schPucchInfo; /*!< PUCCH info */
167 * BSR info per slot per UE.
169 typedef struct bsrInfo
171 uint8_t priority; /* CG priority */
172 uint32_t dataVol; /* Data volume requested in bytes */
175 typedef struct schLcCtxt
177 uint8_t lcId; // logical Channel ID
178 uint8_t lcp; // logical Channel Prioritization
181 uint16_t pduSessionId; /*Pdu Session Id*/
182 Snssai *snssai; /*S-NSSAI assoc with LCID*/
185 typedef struct schDlCb
188 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
191 typedef struct schUlLcCtxt
198 uint8_t pbr; // prioritisedBitRate
199 uint8_t bsd; // bucketSizeDuration
200 uint16_t pduSessionId; /*Pdu Session Id*/
201 Snssai *snssai; /*S-NSSAI assoc with LCID*/
204 typedef struct schUlCb
207 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
210 typedef struct schUeCfgCb
214 bool macCellGrpCfgPres;
215 SchMacCellGrpCfg macCellGrpCfg;
216 bool phyCellGrpCfgPres;
217 SchPhyCellGrpCfg phyCellGrpCfg;
219 SchSpCellCfg spCellCfg;
221 SchModulationInfo dlModInfo;
222 SchModulationInfo ulModInfo;
229 typedef struct schUeCb
237 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
246 typedef struct schRaReq
249 RachIndInfo *rachInd;
250 SlotTimingInfo winStartTime;
251 SlotTimingInfo winEndTime;
256 * Cell Control block per cell.
258 typedef struct schCellCb
260 uint16_t cellId; /*!< Cell ID */
261 Inst instIdx; /*!< Index of the scheduler instance */
262 Inst macInst; /*!< Index of the MAC instance */
263 uint8_t numSlots; /*!< Number of slots in current frame */
264 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
265 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
266 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
267 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
268 bool firstSsbTransmitted;
269 bool firstSib1Transmitted;
270 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
271 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
272 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
273 uint16_t numActvUe; /*!<Number of active UEs */
274 uint32_t actvUeBitMap; /*!<Bit map to find active UEs */
275 uint32_t boIndBitMap; /*!<Bit map to indicate UEs that have recevied BO */
276 SchUeCb ueCb[MAX_NUM_UE]; /*!<Pointer to UE contexts of this cell */
278 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
279 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
280 uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
286 * Control block for sch
290 TskInit schInit; /*!< Task Init info */
291 SchGenCb genCfg; /*!< General Config info */
292 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
293 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
294 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
297 /* Declaration for scheduler control blocks */
298 SchCb schCb[SCH_MAX_INST];
300 /* function declarations */
301 short int schActvTmr(Ent ent,Inst inst);
303 /* Configuration related function declarations */
304 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
305 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
306 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
307 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
308 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
309 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
310 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
311 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
313 /* Incoming message handler function declarations */
314 uint8_t schProcessSlotInd(SlotTimingInfo *slotInd, Inst inst);
315 uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
317 /* DL scheduling related function declarations */
318 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
319 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
320 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
321 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
322 void schProcessRaReq(SlotTimingInfo currTime, SchCellCb *cellCb);
323 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueIdx, RarAlloc *rarAlloc, uint8_t k0Index);
324 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo slotTime, DlMsgAlloc *msg4Alloc);
325 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
326 uint32_t *accumalatedSize, DlMsgAlloc *dlMsgAlloc);
327 uint16_t schAccumalateLcBoSize(SchCellCb *cell, uint16_t ueIdx);
329 /* UL scheduling related function declarations */
330 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
331 uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot);
332 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo puschInfo, DciInfo *dciInfo);
333 uint8_t schFillPuschAlloc(SchUeCb *ueCb, uint16_t pdcchSlot, uint32_t dataVol, SchPuschInfo *puschInfo);
334 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
335 uint16_t *startPrb, uint16_t numPrb);
337 /**********************************************************************
339 **********************************************************************/