1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
28 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
29 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
30 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
31 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
32 #define SCH_SSB_NUM_SYMB 4
33 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
38 #define PDSCH_START_RB 10
39 /* Considering pdsch region from 3 to 13, DMRS exclued.
40 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
41 #define NUM_PDSCH_SYMBOL 11
42 #define PUSCH_START_RB 15
43 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
44 #define SI_RNTI 0xFFFF
46 #define DMRS_MAP_TYPE_A 1
47 #define NUM_DMRS_SYMBOLS 1
48 #define DMRS_ADDITIONAL_POS 0
49 #define SCH_DEFAULT_K1 1
50 #define SCH_TQ_SIZE 10
51 #define SSB_IDX_SUPPORTED 1
56 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
57 #define UL_GRANT_SIZE 224
59 #define PRB_BITMAP_IDX_LEN 64
60 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
62 #define SCH_MAX_NUM_UL_HQ_PROC 16
63 #define SCH_MAX_NUM_DL_HQ_PROC 16
64 #define SCH_MAX_NUM_MSG3_TX 2
65 #define SCH_MAX_NUM_DL_HQ_TX 3
66 #define SCH_MAX_NUM_UL_HQ_TX 3
67 #define SCH_MAX_NUM_MSG4_TX 2
72 typedef struct schDlHqProcCb SchDlHqProcCb;
73 typedef struct schUlHqEnt SchUlHqEnt;
74 typedef struct schRaReq SchRaReq;
75 typedef struct schDlHqEnt SchDlHqEnt;
76 typedef struct schCellCb SchCellCb;
77 typedef struct schUeCb SchUeCb;
90 SCH_UE_STATE_INACTIVE,
92 SCH_UE_HANDIN_IN_PROGRESS
97 SCH_RA_STATE_MSG2_HANDLE,
98 SCH_RA_STATE_MSG3_PENDING,
99 SCH_RA_STATE_MSG4_PENDING,
100 SCH_RA_STATE_MSG4_DONE
105 SCH_LC_STATE_INACTIVE,
123 /*Following structures to keep record and estimations of PRB allocated for each
124 * LC taking into consideration the RRM policies*/
125 typedef struct lcInfo
127 uint8_t lcId; /*LCID for which BO are getting recorded*/
128 uint32_t reqBO; /*Size of the BO requested/to be allocated for this LC*/
129 uint32_t allocBO; /*TBS/BO Size which is actually allocated*/
130 uint8_t allocPRB; /*PRB count which is allocated based on RRM policy/FreePRB*/
133 typedef struct schLcPrbEstimate
135 /* TODO: For Multiple RRMPolicies, Make DedicatedLcInfo as array/Double Pointer
136 * and have separate DedLCInfo for each RRMPolcyMemberList*/
137 /* Dedicated LC List will be allocated, if any available*/
138 CmLListCp dedLcList; /*Contain LCInfo per RRMPolicy*/
139 CmLListCp defLcList; /*Linklist of LC assoc with Default S-NSSAI(s)*/
140 /* SharedPRB number can be used by any LC.
141 * Need to calculate in every Slot based on PRB availability*/
142 uint16_t sharedNumPrb;
144 typedef struct schUlHqTbCb
152 SchMcsTable mcsTable;
158 uint8_t cntrRetxAllocFail;
162 typedef struct schDlHqTbCb
175 uint8_t isAckNackDtx;
176 uint8_t cntrRetxAllocFail;
177 //InfUeTbInfo tbCompInfo;
181 typedef struct schUlHqProcCb
183 uint8_t procId; /*!< HARQ Process ID */
185 uint8_t maxHqTxPerHqP;
191 SchLcPrbEstimate ulLcPrbEst; /*UL PRB Alloc Estimate among different LC*/
192 CmLList ulHqProcLink;
193 uint8_t puschResType; /* Resource allocation type */
194 uint16_t puschStartPrb;
195 uint16_t puschNumPrb;
196 uint8_t dmrsMappingType;
197 uint8_t nrOfDmrsSymbols;
203 uint8_t procId; /*!< HARQ Process ID */
205 uint8_t maxHqTxPerHqP;
208 SchDlHqTbCb tbInfo[2];
210 SchLcPrbEstimate dlLcPrbEst; /*DL PRB Alloc Estimate among different LC*/
211 CmLList dlHqProcLink;
215 SchCellCb *cell; /*!< Contains the pointer to cell*/
216 SchUeCb *ue; /*!< Contains the pointer to ue*/
217 CmLListCp free; /*!< List of free HARQ processes */
218 CmLListCp inUse; /*!< List of in-use HARQ processes */
219 uint8_t maxHqTx; /*!< Maximum number of harq re-transmissions */
220 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
221 SchUlHqProcCb procs[SCH_MAX_NUM_UL_HQ_PROC]; /*!< Uplink harq process info */
225 SchCellCb *cell; /*!< Contains the pointer to cell */
226 SchUeCb *ue; /*!< Contains the pointer to UE */
227 CmLListCp free; /*!< List of free HARQ processes */
228 CmLListCp inUse; /*!< List of in-use HARQ processes */
229 uint8_t maxHqTx; /*!< Maximum number of harq transmissions */
230 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
231 SchDlHqProcCb procs[SCH_MAX_NUM_DL_HQ_PROC];/*!< Downlink harq processes */
236 * Structure holding LTE MAC's General Configuration information.
238 typedef struct schGenCb
240 uint8_t tmrRes; /*!< Timer resolution */
241 uint8_t startCellId; /*!< Starting Cell Id */
243 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
244 of RLC control BO and SRB BO on
245 PCell. val 0 means don't force*/
246 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
250 typedef struct freePrbBlock
259 * PRB allocations for a symbol within a slot
261 typedef struct schPrbAlloc
263 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
264 uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
269 * scheduler allocationsfor DL per cell.
271 typedef struct schDlSlotInfo
273 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
274 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
275 uint8_t ssbIdxSupported; /*!< Max SSB index */
276 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
277 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
278 uint8_t pdcchUe; /*!< UE for which PDCCH is scheduled in this slot */
279 uint8_t pdschUe; /*!< UE for which PDSCH is scheduled in this slot */
280 RarAlloc *rarAlloc[MAX_NUM_UE]; /*!< RAR allocation per UE*/
282 DlMsgAlloc *dlMsgAlloc[MAX_NUM_UE]; /*!< Dl msg allocation per UE*/
285 typedef struct schRaCb
290 uint16_t dlMsgPduLen;
291 SchUlHqProcCb msg3HqProc;
292 SchUlHqProcCb *retxMsg3HqProc;
300 * scheduler allocationsfor UL per cell.
302 typedef struct schUlSlotInfo
304 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
305 uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */
306 bool puschPres; /*!< PUSCH presence field */
307 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
308 bool pucchPres; /*!< PUCCH presence field */
309 SchPucchInfo schPucchInfo; /*!< PUCCH info */
310 uint8_t pucchUe; /*!< Store UE id for which PUCCH is scheduled */
311 uint8_t puschUe; /*!< Store UE id for which PUSCH is scheduled */
316 * BSR info per slot per UE.
318 typedef struct bsrInfo
320 uint8_t priority; /* CG priority */
321 uint32_t dataVol; /* Data volume requested in bytes */
324 typedef struct schLcCtxt
326 uint8_t lcId; // logical Channel ID
327 uint8_t lcp; // logical Channel Prioritization
330 uint16_t pduSessionId; /*Pdu Session Id*/
331 Snssai *snssai; /*S-NSSAI assoc with LCID*/
332 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
333 uint16_t rsvdDedicatedPRB;
336 typedef struct schDlCb
338 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
341 typedef struct schUlLcCtxt
348 uint8_t pbr; // prioritisedBitRate
349 uint8_t bsd; // bucketSizeDuration
350 uint16_t pduSessionId; /*Pdu Session Id*/
351 Snssai *snssai; /*S-NSSAI assoc with LCID*/
352 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
353 uint16_t rsvdDedicatedPRB;
356 typedef struct schUlCb
358 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
361 typedef struct schUeCfgCb
366 bool macCellGrpCfgPres;
367 SchMacCellGrpCfg macCellGrpCfg;
368 bool phyCellGrpCfgPres;
369 SchPhyCellGrpCfg phyCellGrpCfg;
371 SchSpCellCfg spCellCfg;
373 SchModulationInfo dlModInfo;
374 SchModulationInfo ulModInfo;
375 SchDataTransmission dataTransmissionAction;
378 typedef struct schHqDlMap
383 typedef struct schHqUlMap
392 typedef struct schUeCb
399 SchCfraResource cfraResource;
402 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
407 SchDlHqProcCb *msg4Proc;
408 SchDlHqProcCb *retxMsg4HqProc;
409 SchHqDlMap **hqDlmap;
410 SchHqUlMap **hqUlmap;
411 CmLListCp ulRetxHqList;
412 CmLListCp dlRetxHqList;
419 typedef struct schRaReq
422 RachIndInfo *rachInd;
424 SchUeCb *ueCb; /* Filled only if isCFRA = true */
425 SlotTimingInfo winStartTime;
426 SlotTimingInfo winEndTime;
429 typedef struct schPageInfo
431 uint16_t pf; /*Value of Paging Frame received from DUAPP*/
432 uint8_t i_s; /*Value of Paging Occ Index received from DUAPP*/
433 SlotTimingInfo pageTxTime; /*Start Paging window*/
434 uint8_t mcs; /*MCS index*/
435 uint16_t msgLen; /*Pdu length */
436 uint8_t *pagePdu; /*RRC Page PDU bit string*/
439 typedef struct schPagingOcc
442 uint8_t pagingOccSlot;
445 typedef struct schPageCb
447 CmLListCp pageIndInfoRecord[MAX_SFN]; /*List of Page Records received which are stored per sfn*/
448 SchPagingOcc pagMonOcc[MAX_PO_PER_PF]; /*Paging Occasion Slot/FrameOffset are stored*/
453 * Cell Control block per cell.
455 typedef struct schCellCb
457 uint16_t cellId; /*!< Cell ID */
458 Inst instIdx; /*!< Index of the scheduler instance */
459 Inst macInst; /*!< Index of the MAC instance */
460 uint8_t numSlots; /*!< Number of slots in current frame */
461 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
462 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
463 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
464 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
465 bool firstSsbTransmitted;
466 bool firstSib1Transmitted;
467 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!< start symbol per SSB beam */
468 uint64_t dedPreambleBitMap; /*!< Bit map to find used/free preambles index */
469 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
470 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
471 uint16_t numActvUe; /*!< Number of active UEs */
472 uint32_t actvUeBitMap; /*!< Bit map to find active UEs */
473 uint32_t boIndBitMap; /*!< Bit map to indicate UEs that have recevied BO */
474 SchUeCb ueCb[MAX_NUM_UE]; /*!< Pointer to UE contexts of this cell */
475 CmLListCp ueToBeScheduled; /*!< Linked list to store UEs pending to be scheduled, */
476 SchPageCb pageCb; /*!< Page Record at Schedular*/
478 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
479 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
480 uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
485 typedef struct schSliceCfg
487 uint8_t numOfSliceConfigured;
488 SchRrmPolicyOfSlice **listOfConfirguration;
493 * Control block for sch
497 TskInit schInit; /*!< Task Init info */
498 SchGenCb genCfg; /*!< General Config info */
499 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
500 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
501 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
502 SchSliceCfg sliceCfg;
505 /* Declaration for scheduler control blocks */
506 SchCb schCb[SCH_MAX_INST];
508 /* function declarations */
509 short int schActvTmr(Ent ent,Inst inst);
511 /* Configuration related function declarations */
512 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
513 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
514 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
515 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
516 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
517 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
518 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
519 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
520 uint8_t addUeToBeScheduled(SchCellCb *cell, uint8_t ueId);
522 /* Incoming message handler function declarations */
523 uint8_t schProcessSlotInd(SlotTimingInfo *slotInd, Inst inst);
524 uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
525 uint8_t schProcessCrcInd(CrcIndInfo *crcInd, Inst schInst);
527 /* DL scheduling related function declarations */
528 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
529 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
530 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
531 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
532 bool schProcessRaReq(Inst schInst, SchCellCb *cellCb, SlotTimingInfo currTime, uint8_t ueId);
533 uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId,bool isRetxMsg4, SchDlHqProcCb **hqP);
534 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAlloc *rarAlloc, uint8_t k0Index);
535 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
536 uint32_t tbSize, DlMsgAlloc *dlMsgAlloc, uint16_t startPRB, uint8_t pdschStartSymbol, uint8_t pdschNumSymbols,bool isRetx, SchDlHqProcCb* hqP);
537 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueId, DlMsgAlloc *msg4Alloc,\
538 uint8_t pdschStartSymbol, uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP);
539 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
540 uint16_t *startPrb, uint16_t numPrb);
541 void fillDlMsgInfo(DlMsgInfo *dlMsgInfo, uint8_t crnti, bool isRetx, SchDlHqProcCb* hqP);
542 bool findValidK0K1Value(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool dedMsg, uint8_t *pdschStartSymbol,\
543 uint8_t *pdschSymblLen, SlotTimingInfo *pdcchTime, SlotTimingInfo *pdschTime, SlotTimingInfo *pucchTime, bool isRetx, SchDlHqProcCb *hqP);
544 RaRspWindowStatus isInRaRspWindow(SchRaReq *raReq, SlotTimingInfo frameToCheck, uint16_t numSlotsPerSystemFrame);
545 /* UL scheduling related function declarations */
546 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
547 bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo);
548 uint8_t schCalcPrachNumRb(SchCellCb *cell);
549 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo);
550 uint16_t schAllocPucchResource(SchCellCb *cell, SlotTimingInfo pucchTime, uint16_t crnti,SchUeCb *ueCb, bool isRetx, SchDlHqProcCb *hqP);
551 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo *puschInfo, DciInfo *dciInfo, bool isRetx, SchUlHqProcCb *hqP);
552 uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo puschTime, uint32_t tbSize,
553 uint8_t startSymb, uint8_t symbLen, uint16_t startPrb, bool isRetx, SchUlHqProcCb *hqP);
554 uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
555 uint16_t *startPrb, uint16_t numPrb);
556 bool schProcessSrOrBsrReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchUlHqProcCb **hqP);
557 uint8_t schCalculateUlTbs(SchUeCb *ueCb, SlotTimingInfo puschTime, uint8_t symbLen,\
558 uint16_t *startPrb, uint32_t *totTBS, bool isRetx, SchUlHqProcCb *hqP);
560 /*Generic Functions*/
561 void updateGrantSizeForBoRpt(CmLListCp *lcLL, DlMsgAlloc *dlMsgAlloc, BsrInfo *bsrInfo, uint32_t *accumalatedBOSize);
562 uint16_t searchLargestFreeBlock(SchCellCb *cell, SlotTimingInfo slotTime,uint16_t *startPrb, Direction dir);
563 LcInfo* handleLcLList(CmLListCp *lcLL, uint8_t lcId, ActionTypeLL action);
564 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
565 uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd);
566 void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status);
569 void schProcPagingCfg(SchCellCb *cell);
570 void schCfgPdcchMonOccOfPO(SchCellCb *cell);
571 void schIncrSlot(SlotTimingInfo *timingInfo, uint8_t incr, uint16_t numSlotsPerRF);
572 uint8_t schFillPagePdschCfg(SchCellCb *cell, PdschCfg *pagePdschCfg, SlotTimingInfo slotTime, \
573 uint16_t tbSize, uint8_t mcs, uint16_t startPrb);
574 /*DL HARQ Functions*/
575 void schDlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
576 void schMsg4FeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk);
577 void schDlHqFeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk1, uint8_t fdbk2);
578 uint8_t schDlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchDlHqProcCb **hqP);
579 void schDlReleaseHqProcess(SchDlHqProcCb *hqP);
581 /*UL HARQ Functions*/
582 void schUlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
583 uint8_t schMsg3RetxSchedulingForUe(SchRaCb *raCb);
584 void schUlHqProcessNack(SchUlHqProcCb *hqP);
585 void schUlHqProcessAck(SchUlHqProcCb *hqP);
586 uint8_t schUlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchUlHqProcCb **hqP);
587 void schUlReleaseHqProcess(SchUlHqProcCb *hqP, Bool togNdi);
589 /* UE Manager HARQ Fun*/
590 void schUpdateHarqFdbk(SchUeCb *ueCb, uint8_t numHarq, uint8_t *harqPayload,SlotTimingInfo *slotInd);
592 /* Round Robbin Scheduler funtions*/
593 uint8_t schFillUlDciForMsg3Retx(SchRaCb *raCb, SchPuschInfo *puschInfo, DciInfo *dciInfo);
594 bool schGetMsg3K2(SchCellCb *cell, SchUlHqProcCb* msg3HqProc, uint16_t dlTime, SlotTimingInfo *msg3Time, bool isRetx);
595 void schMsg4Complete(SchUeCb *ueCb);
596 /**********************************************************************
598 **********************************************************************/