1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_INST_START 1
21 #define SCH_MAX_INST 1
22 #define SCH_MU0_NUM_SLOTS 10
23 #define SCH_MU1_NUM_SLOTS 20
24 #define SCH_MU2_NUM_SLOTS 30
25 #define SCH_MU3_NUM_SLOTS 40
26 #define SCH_MU4_NUM_SLOTS 50
27 #define SCH_MAX_SFN 1024
28 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
29 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
30 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
31 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
32 #define SCH_SSB_NUM_SYMB 4
33 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
38 #define PDSCH_START_RB 10
39 /* Considering pdsch region from 3 to 13, DMRS exclued.
40 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
41 #define NUM_PDSCH_SYMBOL 11
42 #define PUSCH_START_RB 15
43 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
44 #define SI_RNTI 0xFFFF
46 #define DMRS_MAP_TYPE_A 1
47 #define NUM_DMRS_SYMBOLS 1
48 #define DMRS_ADDITIONAL_POS 0
49 #define SCH_DEFAULT_K1 1
50 #define SCH_TQ_SIZE 10
51 #define SSB_IDX_SUPPORTED 1
56 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
57 #define UL_GRANT_SIZE 224
59 #define PRB_BITMAP_IDX_LEN 64
60 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
62 typedef struct schCellCb SchCellCb;
63 typedef struct schUeCb SchUeCb;
76 SCH_UE_STATE_INACTIVE,
82 SCH_LC_STATE_INACTIVE,
101 * Structure holding LTE MAC's General Configuration information.
103 typedef struct schGenCb
105 uint8_t tmrRes; /*!< Timer resolution */
106 uint8_t startCellId; /*!< Starting Cell Id */
108 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
109 of RLC control BO and SRB BO on
110 PCell. val 0 means don't force*/
111 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
115 typedef struct freePrbBlock
124 * PRB allocations for a symbol within a slot
126 typedef struct schPrbAlloc
128 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
129 uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
134 * scheduler allocationsfor DL per cell.
136 typedef struct schDlSlotInfo
138 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
139 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
140 uint8_t ssbIdxSupported; /*!< Max SSB index */
141 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
142 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
143 RarAlloc *rarAlloc; /*!< RAR allocation */
144 DlMsgInfo *dlMsgInfo; /*!< DL dedicated Msg info */
147 typedef struct schRaCb
154 * scheduler allocationsfor UL per cell.
156 typedef struct schUlSlotInfo
158 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
159 uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */
160 bool puschPres; /*!< PUSCH presence field */
161 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
162 bool pucchPres; /*!< PUCCH presence field */
163 SchPucchInfo schPucchInfo; /*!< PUCCH info */
168 * BSR info per slot per UE.
170 typedef struct bsrInfo
172 uint8_t priority; /* CG priority */
173 uint32_t dataVol; /* Data volume requested in bytes */
176 typedef struct schLcCtxt
178 uint8_t lcId; // logical Channel ID
179 uint8_t lcp; // logical Channel Prioritization
182 uint16_t pduSessionId; /*Pdu Session Id*/
183 Snssai *snssai; /*S-NSSAI assoc with LCID*/
184 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
187 typedef struct schDlCb
189 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
192 typedef struct schUlLcCtxt
199 uint8_t pbr; // prioritisedBitRate
200 uint8_t bsd; // bucketSizeDuration
201 uint16_t pduSessionId; /*Pdu Session Id*/
202 Snssai *snssai; /*S-NSSAI assoc with LCID*/
203 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
206 typedef struct schUlCb
208 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
211 typedef struct schUeCfgCb
215 bool macCellGrpCfgPres;
216 SchMacCellGrpCfg macCellGrpCfg;
217 bool phyCellGrpCfgPres;
218 SchPhyCellGrpCfg phyCellGrpCfg;
220 SchSpCellCfg spCellCfg;
222 SchModulationInfo dlModInfo;
223 SchModulationInfo ulModInfo;
226 /*Following structures to keep record and estimations of PRB allocated for each
227 * LC taking into consideration the RRM policies*/
228 typedef struct lcInfo
230 uint8_t lcId; /*LCID for which BO are getting recorded*/
231 uint32_t reqBO; /*Size of the BO requested/to be allocated for this LC*/
232 uint32_t allocBO; /*TBS/BO Size which is actually allocated*/
233 uint8_t allocPRB; /*PRB count which is allocated based on RRM policy/FreePRB*/
236 typedef struct dedicatedLCInfo
238 CmLListCp dedLcList; /*Linklist of LC assoc with RRMPolicyMemberList*/
239 uint16_t rsvdDedicatedPRB; /*Number of PRB reserved for this Dedicated S-NSSAI*/
242 typedef struct schLcPrbEstimate
244 /* TODO: For Multiple RRMPolicies, Make DedicatedLcInfo as array/Double Pointer
245 * and have separate DedLCInfo for each RRMPolcyMemberList*/
246 /* Dedicated LC List will be allocated, if any available*/
247 DedicatedLCInfo *dedLcInfo; /*Contain LCInfo per RRMPolicy*/
249 CmLListCp defLcList; /*Linklist of LC assoc with Default S-NSSAI(s)*/
251 /* SharedPRB number can be used by any LC.
252 * Need to calculate in every Slot based on PRB availability*/
253 uint16_t sharedNumPrb;
260 typedef struct schUeCb
268 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
271 SchLcPrbEstimate dlLcPrbEst; /*DL PRB Alloc Estimate among different LC*/
272 SchLcPrbEstimate ulLcPrbEst; /*UL PRB Alloc Estimate among different LC*/
279 typedef struct schRaReq
282 RachIndInfo *rachInd;
283 SlotTimingInfo winStartTime;
284 SlotTimingInfo winEndTime;
289 * Cell Control block per cell.
291 typedef struct schCellCb
293 uint16_t cellId; /*!< Cell ID */
294 Inst instIdx; /*!< Index of the scheduler instance */
295 Inst macInst; /*!< Index of the MAC instance */
296 uint8_t numSlots; /*!< Number of slots in current frame */
297 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
298 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
299 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
300 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
301 bool firstSsbTransmitted;
302 bool firstSib1Transmitted;
303 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
304 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
305 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
306 uint16_t numActvUe; /*!<Number of active UEs */
307 uint32_t actvUeBitMap; /*!<Bit map to find active UEs */
308 uint32_t boIndBitMap; /*!<Bit map to indicate UEs that have recevied BO */
309 SchUeCb ueCb[MAX_NUM_UE]; /*!<Pointer to UE contexts of this cell */
311 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
312 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
313 uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
319 * Control block for sch
323 TskInit schInit; /*!< Task Init info */
324 SchGenCb genCfg; /*!< General Config info */
325 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
326 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
327 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
330 /* Declaration for scheduler control blocks */
331 SchCb schCb[SCH_MAX_INST];
333 /* function declarations */
334 short int schActvTmr(Ent ent,Inst inst);
336 /* Configuration related function declarations */
337 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
338 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
339 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
340 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
341 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
342 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
343 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
344 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
346 /* Incoming message handler function declarations */
347 uint8_t schProcessSlotInd(SlotTimingInfo *slotInd, Inst inst);
348 uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst);
350 /* DL scheduling related function declarations */
351 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
352 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
353 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
354 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
355 void schProcessRaReq(SlotTimingInfo currTime, SchCellCb *cellCb);
356 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueIdx, RarAlloc *rarAlloc, uint8_t k0Index);
357 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo slotTime, DlMsgAlloc *msg4Alloc);
358 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,\
359 uint32_t tbSize, DlMsgAlloc *dlMsgAlloc, uint16_t startPRB);
360 uint16_t schAccumalateLcBoSize(SchCellCb *cell, uint16_t ueIdx);
361 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
362 uint16_t *startPrb, uint16_t numPrb);
363 uint16_t searchLargestFreeBlockDL(SchCellCb *cell, SlotTimingInfo slotTime,uint16_t *startPrb);
364 void updateGrantSizeForBoRpt(CmLListCp *lcLL, DlMsgAlloc *dlMsgAlloc, uint32_t *accumalatedBOSize);
366 /* UL scheduling related function declarations */
367 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
368 bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo);
369 uint8_t schCalcPrachNumRb(SchCellCb *cell);
370 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo);
371 uint16_t schAllocPucchResource(SchCellCb *cell, uint16_t crnti, uint16_t slot);
372 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo puschInfo, DciInfo *dciInfo);
373 uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo pdcchSlotTime, uint32_t dataVol, SchPuschInfo *puschInfo);
374 uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
375 uint16_t *startPrb, uint16_t numPrb);
377 /*Generic Functions*/
378 LcInfo* handleLcLList(CmLListCp *lcLL, uint8_t lcId, ActionTypeLcLL action);
379 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
380 uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded);
382 /**********************************************************************
384 **********************************************************************/