1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
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14 # See the License for the specific language governing permissions and #
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17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for scheduler fucntions
29 **********************************************************************/
32 @brief This file implements the schedulers main access to MAC layer code.
34 #include "common_def.h"
35 #include "du_app_mac_inf.h"
40 #include "rg_sch_inf.h"
43 #include "tfu.x" /* TFU types */
44 #include "lrg.x" /* layer management typedefs for MAC */
45 #include "rgr.x" /* layer management typedefs for MAC */
46 #include "rg_sch_inf.x" /* typedefs for Scheduler */
47 #include "mac_sch_interface.h"
49 #include "sch_utils.h"
51 SchCb schCb[SCH_MAX_INST];
52 void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
55 SchCellCfgCfmFunc SchCellCfgCfmOpts[] =
57 packSchCellCfgCfm, /* LC */
58 MacProcSchCellCfgCfm, /* TC */
59 packSchCellCfgCfm /* LWLC */
64 * @brief Task Initiation function.
68 * Function : schActvInit
70 * This function is supplied as one of parameters during MAC's
71 * task registration. MAC will invoke this function once, after
72 * it creates and attaches this TAPA Task to a system task.
74 * @param[in] Ent Entity, the entity ID of this task.
75 * @param[in] Inst Inst, the instance ID of this task.
76 * @param[in] Region Region, the region ID registered for memory
78 * @param[in] Reason Reason.
82 uint8_t schActvInit(Ent entity, Inst instId, Region region, Reason reason)
84 Inst inst = (instId - SCH_INST_START);
86 /* Initialize the MAC TskInit structure to zero */
87 memset ((uint8_t *)&schCb[inst], 0, sizeof(schCb));
89 /* Initialize the MAC TskInit with received values */
90 schCb[inst].schInit.ent = entity;
91 schCb[inst].schInit.inst = inst;
92 schCb[inst].schInit.region = region;
93 schCb[inst].schInit.pool = 0;
94 schCb[inst].schInit.reason = reason;
95 schCb[inst].schInit.cfgDone = FALSE;
96 schCb[inst].schInit.acnt = FALSE;
97 schCb[inst].schInit.usta = FALSE;
98 schCb[inst].schInit.trc = FALSE;
99 schCb[inst].schInit.procId = ODU_GET_PROCID();
105 * @brief Scheduler instance Configuration Handler.
109 * Function : SchInstCfg
111 * This function in called by SchProcGenCfgReq(). It handles the
112 * general configurations of the scheduler instance. Returns
113 * reason for success/failure of this function.
115 * @param[in] RgCfg *cfg, the Configuaration information
117 * -# LCM_REASON_NOT_APPL
118 * -# LCM_REASON_INVALID_MSGTYPE
119 * -# LCM_REASON_MEM_NOAVAIL
121 uint8_t SchInstCfg(RgCfg *cfg, Inst dInst)
123 uint16_t ret = LCM_REASON_NOT_APPL;
124 Inst inst = (dInst - SCH_INST_START);
126 DU_LOG("\nDEBUG --> SCH : Entered SchInstCfg()");
127 /* Check if Instance Configuration is done already */
128 if (schCb[inst].schInit.cfgDone == TRUE)
130 return LCM_REASON_INVALID_MSGTYPE;
132 /* Update the Pst structure for LM interface */
133 memcpy(&schCb[inst].schInit.lmPst,
134 &cfg->s.schInstCfg.genCfg.lmPst,
137 schCb[inst].schInit.inst = inst;
138 schCb[inst].schInit.lmPst.srcProcId = schCb[inst].schInit.procId;
139 schCb[inst].schInit.lmPst.srcEnt = schCb[inst].schInit.ent;
140 schCb[inst].schInit.lmPst.srcInst = schCb[inst].schInit.inst +
142 schCb[inst].schInit.lmPst.event = EVTNONE;
144 schCb[inst].schInit.region = cfg->s.schInstCfg.genCfg.mem.region;
145 schCb[inst].schInit.pool = cfg->s.schInstCfg.genCfg.mem.pool;
146 schCb[inst].genCfg.tmrRes = cfg->s.schInstCfg.genCfg.tmrRes;
148 schCb[inst].genCfg.forceCntrlSrbBoOnPCel = cfg->s.schInstCfg.genCfg.forceCntrlSrbBoOnPCel;
149 schCb[inst].genCfg.isSCellActDeactAlgoEnable = cfg->s.schInstCfg.genCfg.isSCellActDeactAlgoEnable;
151 schCb[inst].genCfg.startCellId = cfg->s.schInstCfg.genCfg.startCellId;
153 /* Initialzie the timer queue */
154 memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType) * SCH_TQ_SIZE);
155 /* Initialize the timer control point */
156 memset(&schCb[inst].tmrTqCp, 0, sizeof(CmTqCp));
157 schCb[inst].tmrTqCp.tmrLen = RGSCH_TQ_SIZE;
159 /* SS_MT_TMR needs to be enabled as schActvTmr needs instance information */
160 /* Timer Registration request to system services */
161 if (ODU_REG_TMR_MT(schCb[inst].schInit.ent, dInst,
162 (int)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK)
164 DU_LOG("\nERROR --> SCH : SchInstCfg(): Failed to "
166 return (LCM_REASON_MEM_NOAVAIL);
169 /* Set Config done in TskInit */
170 schCb[inst].schInit.cfgDone = TRUE;
171 DU_LOG("\nINFO --> SCH : Scheduler gen config done");
177 * @brief Layer Manager Configuration request handler.
181 * Function : SchProcGenCfgReq
183 * This function handles the configuration
184 * request received at scheduler instance from the Layer Manager.
185 * -# Based on the cfg->hdr.elmId.elmnt value it invokes one of the
186 * functions rgHdlGenCfg() or rgHdlSapCfg().
187 * -# Invokes RgMiLrgSchCfgCfm() to send back the confirmation to the LM.
189 * @param[in] Pst *pst, the post structure
190 * @param[in] RgMngmt *cfg, the configuration parameter's structure
194 uint8_t SchProcGenCfgReq(Pst *pst, RgMngmt *cfg)
196 uint8_t ret = LCM_PRIM_OK;
197 uint16_t reason = LCM_REASON_NOT_APPL;
201 if(pst->dstInst < SCH_INST_START)
203 DU_LOG("\nERROR --> SCH : Invalid inst ID");
204 DU_LOG("\nERROR --> SCH : SchProcGenCfgReq(): "
205 "pst->dstInst=%d SCH_INST_START=%d", pst->dstInst,SCH_INST_START);
208 DU_LOG("\nINFO --> SCH : Received scheduler gen config");
209 /* Fill the post structure for sending the confirmation */
210 memset(&cfmPst, 0 , sizeof(Pst));
211 SchFillCfmPst(pst, &cfmPst, cfg);
213 memset(&cfm, 0, sizeof(RgMngmt));
220 cfm.hdr.elmId.elmnt = cfg->hdr.elmId.elmnt;
221 switch(cfg->hdr.elmId.elmnt)
224 reason = SchInstCfg(&cfg->t.cfg,pst->dstInst );
228 reason = LCM_REASON_INVALID_ELMNT;
229 DU_LOG("\nERROR --> SCH : Invalid Elmnt=%d", cfg->hdr.elmId.elmnt);
233 if (reason != LCM_REASON_NOT_APPL)
238 cfm.cfm.status = ret;
239 cfm.cfm.reason = reason;
241 SchSendCfgCfm(&cfmPst, &cfm);
242 /* SPutSBuf(pst->region, pst->pool, (Data *)cfg, sizeof(RgMngmt)); */
245 }/*-- SchProcGenCfgReq --*/
248 * @brief slot indication from MAC to SCH.
252 * Function : MacSchSlotInd
254 * This API is invoked by PHY to indicate slot indication to Scheduler for
257 * @param[in] Pst *pst
258 * @param[in] SlotIndInfo *slotInd
263 uint8_t MacSchSlotInd(Pst *pst, SlotIndInfo *slotInd)
265 Inst inst = pst->dstInst-SCH_INST_START;
267 schProcessSlotInd(slotInd, inst);
270 } /* MacSchSlotInd */
272 /*******************************************************************
274 * @brief Processes Rach indication from MAC
278 * Function : MacSchRachInd
281 * Processes Rach indication from MAC
284 * @return ROK - success
287 * ****************************************************************/
288 uint8_t MacSchRachInd(Pst *pst, RachIndInfo *rachInd)
290 Inst inst = pst->dstInst-SCH_INST_START;
291 DU_LOG("\nINFO --> SCH : Received Rach indication");
292 schProcessRachInd(rachInd, inst);
296 /*******************************************************************
298 * @brief Processes CRC indication from MAC
302 * Function : MacSchCrcInd
305 * Processes CRC indication from MAC
307 * @params[in] Post structure
309 * @return ROK - success
312 * ****************************************************************/
313 uint8_t MacSchCrcInd(Pst *pst, CrcIndInfo *crcInd)
315 switch(crcInd->crcInd[0])
318 DU_LOG("\nDEBUG --> SCH : Received CRC indication. CRC Status [FAILURE]");
321 DU_LOG("\nDEBUG --> SCH : Received CRC indication. CRC Status [PASS]");
324 DU_LOG("\nDEBUG --> SCH : Invalid CRC state %d", crcInd->crcInd[0]);
332 *@brief Returns TDD periodicity in micro seconds
336 * Function : schGetPeriodicityInMsec
338 * This API retunrs TDD periodicity in micro seconds
340 * @param[in] DlUlTxPeriodicity
341 * @return periodicityInMsec
344 uint16_t schGetPeriodicityInMsec(DlUlTxPeriodicity tddPeriod)
346 uint16_t periodicityInMsec = 0;
349 case TX_PRDCTY_MS_0P5:
351 periodicityInMsec = 500;
354 case TX_PRDCTY_MS_0P625:
356 periodicityInMsec = 625;
361 periodicityInMsec = 1000;
364 case TX_PRDCTY_MS_1P25:
366 periodicityInMsec = 1250;
371 periodicityInMsec = 2000;
374 case TX_PRDCTY_MS_2P5:
376 periodicityInMsec = 2500;
381 periodicityInMsec = 5000;
384 case TX_PRDCTY_MS_10:
386 periodicityInMsec = 10000;
391 DU_LOG("\nERROR --> SCH : Invalid DlUlTxPeriodicity:%d", tddPeriod);
395 return periodicityInMsec;
400 * @brief init TDD slot config
404 * Function : schInitTddSlotCfg
406 * This API is invoked after receiving schCellCfg
408 * @param[in] schCellCb *cell
409 * @param[in] SchCellCfg *schCellCfg
412 void schInitTddSlotCfg(SchCellCb *cell, SchCellCfg *schCellCfg)
414 uint16_t periodicityInMicroSec = 0;
415 int8_t slotIdx, symbIdx;
417 periodicityInMicroSec = schGetPeriodicityInMsec(schCellCfg->tddCfg.tddPeriod);
418 cell->numSlotsInPeriodicity = (periodicityInMicroSec * pow(2, schCellCfg->numerology))/1000;
419 cell->slotFrmtBitMap = 0;
420 cell->symbFrmtBitMap = 0;
421 for(slotIdx = cell->numSlotsInPeriodicity-1; slotIdx >= 0; slotIdx--)
424 /* If the first and last symbol are the same, the entire slot is the same type */
425 if((schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx] == schCellCfg->tddCfg.slotCfg[slotIdx][MAX_SYMB_PER_SLOT-1]) &&
426 schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx] != FLEXI_SLOT)
428 switch(schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx])
432 /*BitMap to be set to 00 */
433 cell->slotFrmtBitMap = (cell->slotFrmtBitMap<<2);
438 /*BitMap to be set to 01 */
439 cell->slotFrmtBitMap = ((cell->slotFrmtBitMap<<2) | (UL_SLOT));
443 DU_LOG("\nERROR --> SCH : Invalid slot Config in schInitTddSlotCfg");
447 /* slot config is flexible. First set slotBitMap to 10 */
448 cell->slotFrmtBitMap = ((cell->slotFrmtBitMap<<2) | (FLEXI_SLOT));
450 /* Now set symbol bitmap */
451 for(symbIdx = MAX_SYMB_PER_SLOT-1; symbIdx >= 0; symbIdx--)
453 switch(schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx])
457 /*symbol BitMap to be set to 00 */
458 cell->symbFrmtBitMap = (cell->symbFrmtBitMap<<2);
463 /*symbol BitMap to be set to 01 */
464 cell->symbFrmtBitMap = ((cell->symbFrmtBitMap<<2) | (UL_SLOT));
469 /*symbol BitMap to be set to 10 */
470 cell->symbFrmtBitMap = ((cell->symbFrmtBitMap<<2) | (FLEXI_SLOT));
474 DU_LOG("\nERROR --> SCH : Invalid slot Config in schInitTddSlotCfg");
482 * @brief Fill SSB start symbol
486 * Function : fillSsbStartSymb
488 * This API stores SSB start index per beam
490 * @param[in] SchCellCb *cellCb
495 void fillSsbStartSymb(SchCellCb *cellCb)
497 uint8_t cnt, scs, symbIdx, ssbStartSymbArr[SCH_MAX_SSB_BEAM];
499 scs = cellCb->cellCfg.ssbSchCfg.scsCommon;
501 memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
503 /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */
508 if(cellCb->cellCfg.dlFreq <= 300000)
509 cnt = 2;/* n = 0, 1 */
511 cnt = 4; /* n = 0, 1, 2, 3 */
512 for(uint8_t idx=0; idx<cnt; idx++)
514 /* start symbol determined using {2, 8} + 14n */
515 ssbStartSymbArr[symbIdx++] = 2 + SCH_SYMBOL_PER_SLOT*idx;
516 ssbStartSymbArr[symbIdx++] = 8 + SCH_SYMBOL_PER_SLOT*idx;
522 if(cellCb->cellCfg.dlFreq <= 300000)
525 cnt = 2; /* n = 0, 1 */
526 for(uint8_t idx=0; idx<cnt; idx++)
528 /* start symbol determined using {4, 8, 16, 20} + 28n */
529 ssbStartSymbArr[symbIdx++] = 4 + SCH_SYMBOL_PER_SLOT*idx;
530 ssbStartSymbArr[symbIdx++] = 8 + SCH_SYMBOL_PER_SLOT*idx;
531 ssbStartSymbArr[symbIdx++] = 16 + SCH_SYMBOL_PER_SLOT*idx;
532 ssbStartSymbArr[symbIdx++] = 20 + SCH_SYMBOL_PER_SLOT*idx;
537 DU_LOG("\nERROR --> SCH : SCS %d is currently not supported", scs);
539 memset(cellCb->ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
540 memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM);
546 * @brief init cellCb based on cellCfg
550 * Function : schInitCellCb
552 * This API is invoked after receiving schCellCfg
554 * @param[in] schCellCb *cell
555 * @param[in] SchCellCfg *schCellCfg
560 uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg)
562 SchCellCb *cell= NULLP;
563 SCH_ALLOC(cell, sizeof(SchCellCb));
566 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb");
570 cell->cellId = schCellCfg->cellId;
571 cell->instIdx = inst;
572 switch(schCellCfg->numerology)
574 case SCH_NUMEROLOGY_0:
576 cell->numSlots = SCH_MU0_NUM_SLOTS;
579 case SCH_NUMEROLOGY_1:
581 cell->numSlots = SCH_MU1_NUM_SLOTS;
584 case SCH_NUMEROLOGY_2:
586 cell->numSlots = SCH_MU2_NUM_SLOTS;
589 case SCH_NUMEROLOGY_3:
591 cell->numSlots = SCH_MU3_NUM_SLOTS;
594 case SCH_NUMEROLOGY_4:
596 cell->numSlots = SCH_MU4_NUM_SLOTS;
600 DU_LOG("\nERROR --> SCH : Numerology %d not supported", schCellCfg->numerology);
603 schInitTddSlotCfg(cell, schCellCfg);
606 SCH_ALLOC(cell->schDlSlotInfo, cell->numSlots * sizeof(SchDlSlotInfo*));
607 if(!cell->schDlSlotInfo)
609 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb for schDlSlotInfo");
613 SCH_ALLOC(cell->schUlSlotInfo, cell->numSlots * sizeof(SchUlSlotInfo*));
614 if(!cell->schUlSlotInfo)
616 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb for schUlSlotInfo");
620 for(uint8_t idx=0; idx<cell->numSlots; idx++)
622 SchDlSlotInfo *schDlSlotInfo;
623 SchUlSlotInfo *schUlSlotInfo;
626 SCH_ALLOC(schDlSlotInfo, sizeof(SchDlSlotInfo));
629 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb");
634 SCH_ALLOC(schUlSlotInfo, sizeof(SchUlSlotInfo));
637 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb");
641 schInitDlSlot(schDlSlotInfo);
642 schInitUlSlot(schUlSlotInfo);
644 cell->schDlSlotInfo[idx] = schDlSlotInfo;
645 cell->schUlSlotInfo[idx] = schUlSlotInfo;
648 cell->firstSsbTransmitted = false;
649 cell->firstSib1Transmitted = false;
650 fillSsbStartSymb(cell);
651 schCb[inst].cells[inst] = cell;
653 DU_LOG("\nINFO --> SCH : Cell init completed for cellId:%d", cell->cellId);
659 * @brief Fill SIB1 configuration
663 * Function : fillSchSib1Cfg
665 * Fill SIB1 configuration
667 * @param[in] uint8_t bandwidth : total available bandwidth
668 * uint8_t numSlots : total slots per SFN
669 * SchSib1Cfg *sib1SchCfg : cfg to be filled
670 * uint16_t pci : physical cell Id
671 * uint8_t offsetPointA : offset
674 void fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA)
676 uint8_t coreset0Idx = 0;
677 uint8_t searchSpace0Idx = 0;
678 //uint8_t ssbMuxPattern = 0;
680 uint8_t numSymbols = 0;
683 //uint8_t numSearchSpacePerSlot = 0;
685 uint8_t firstSymbol = 0; /* need to calculate using formula mentioned in 38.213 */
686 uint8_t slotIndex = 0;
687 uint8_t FreqDomainResource[6] = {0};
689 uint8_t numPdschSymbols = 11; /* considering pdsch region from symbols 3 to 13 */
692 PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg);
693 PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg);
694 BwpCfg *bwp = &(sib1SchCfg->bwp);
696 coreset0Idx = sib1SchCfg->coresetZeroIndex;
697 searchSpace0Idx = sib1SchCfg->searchSpaceZeroIndex;
699 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
700 //ssbMuxPattern = coresetIdxTable[coreset0Idx][0];
701 numRbs = coresetIdxTable[coreset0Idx][1];
702 numSymbols = coresetIdxTable[coreset0Idx][2];
703 offset = coresetIdxTable[coreset0Idx][3];
705 /* derive the search space params from table 13-11 spec 38.213 */
706 oValue = searchSpaceIdxTable[searchSpace0Idx][0];
707 //numSearchSpacePerSlot = searchSpaceIdxTable[searchSpace0Idx][1];
708 mValue = searchSpaceIdxTable[searchSpace0Idx][2];
709 firstSymbol = searchSpaceIdxTable[searchSpace0Idx][3];
711 /* calculate the n0, need to add the formulae, as of now the value is 0
712 * Need to add the even and odd values of i during configuration
713 * [(O . 2^u + i . M ) ] mod numSlotsPerSubframe
714 * assuming u = 0, i = 0, numSlotsPerSubframe = 10
715 * Also, from this configuration, coreset0 is only on even subframe */
716 slotIndex = (int)((oValue*pow(2, mu)) + floor(ssbIdx*mValue))%numSlots;
717 sib1SchCfg->n0 = slotIndex;
719 /* calculate the PRBs */
720 freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
725 case BANDWIDTH_20MHZ:
727 bwp->freqAlloc.numPrb = TOTAL_PRB_20MHZ_MU0;
730 case BANDWIDTH_100MHZ:
732 bwp->freqAlloc.numPrb = TOTAL_PRB_100MHZ_MU1;
736 DU_LOG("\nERROR --> SCH : Bandwidth %d not supported", bandwidth);
739 bwp->freqAlloc.startPrb = 0;
740 bwp->subcarrierSpacing = 0; /* 15Khz */
741 bwp->cyclicPrefix = 0; /* normal */
743 /* fill the PDCCH PDU */
744 pdcch->coresetCfg.coreSetSize = numRbs;
745 pdcch->coresetCfg.startSymbolIndex = firstSymbol;
746 pdcch->coresetCfg.durationSymbols = numSymbols;
747 memcpy(pdcch->coresetCfg.freqDomainResource,FreqDomainResource,6);
748 pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
749 pdcch->coresetCfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
750 pdcch->coresetCfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
751 pdcch->coresetCfg.coreSetType = 0;
752 pdcch->coresetCfg.shiftIndex = pci;
753 pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
755 pdcch->dci.rnti = SI_RNTI;
756 pdcch->dci.scramblingId = pci;
757 pdcch->dci.scramblingRnti = 0;
758 pdcch->dci.cceIndex = 0;
759 pdcch->dci.aggregLevel = 4;
760 pdcch->dci.beamPdcchInfo.numPrgs = 1;
761 pdcch->dci.beamPdcchInfo.prgSize = 1;
762 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
763 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
764 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
765 pdcch->dci.txPdcchPower.powerValue = 0;
766 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
767 /* Storing pdschCfg pointer here. Required to access pdsch config while
768 fillig up pdcch pdu */
769 pdcch->dci.pdschCfg = pdsch;
771 /* fill the PDSCH PDU */
773 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
774 pdsch->rnti = 0xFFFF; /* SI-RNTI */
776 pdsch->numCodewords = 1;
777 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
779 pdsch->codeword[cwCount].targetCodeRate = 308;
780 pdsch->codeword[cwCount].qamModOrder = 2;
781 pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs;
782 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
783 pdsch->codeword[cwCount].rvIndex = 0;
784 tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen + TX_PAYLOAD_HDR_LEN);
785 pdsch->codeword[cwCount].tbSize = tbSize;
787 pdsch->dataScramblingId = pci;
788 pdsch->numLayers = 1;
789 pdsch->transmissionScheme = 0;
791 pdsch->dmrs.dlDmrsSymbPos = 4; /* Bitmap value 00000000000100 i.e. using 3rd symbol for PDSCH DMRS */
792 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
793 pdsch->dmrs.dlDmrsScramblingId = pci;
794 pdsch->dmrs.scid = 0;
795 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
796 pdsch->dmrs.dmrsPorts = 0;
797 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Type-A */
798 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
799 pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
801 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
802 pdsch->pdschFreqAlloc.freqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB + 1; /* the RB numbering starts from coreset0,
803 and PDSCH is always above SSB */
804 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols);
805 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
806 pdsch->pdschTimeAlloc.rowIndex = 1;
807 /* This is Intel's requirement. PDSCH should start after PDSCH DRMS symbol */
808 pdsch->pdschTimeAlloc.timeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */
809 pdsch->pdschTimeAlloc.timeAlloc.numSymb = numPdschSymbols;
810 pdsch->beamPdschInfo.numPrgs = 1;
811 pdsch->beamPdschInfo.prgSize = 1;
812 pdsch->beamPdschInfo.digBfInterfaces = 0;
813 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
814 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
815 pdsch->txPdschPower.powerControlOffset = 0;
816 pdsch->txPdschPower.powerControlOffsetSS = 0;
821 * @brief cell config from MAC to SCH.
825 * Function : macSchCellCfgReq
827 * This API is invoked by MAC to send cell config to SCH
829 * @param[in] Pst *pst
830 * @param[in] SchCellCfg *schCellCfg
835 uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg)
839 SchCellCfgCfm schCellCfgCfm;
841 Inst inst = pst->dstInst-1;
843 schInitCellCb(inst, schCellCfg);
844 cellCb = schCb[inst].cells[inst]; //cells is of MAX_CELLS, why inst
845 cellCb->macInst = pst->srcInst;
847 /* derive the SIB1 config parameters */
848 fillSchSib1Cfg(schCellCfg->numerology, schCellCfg->bandwidth, cellCb->numSlots,
849 &(schCellCfg->sib1SchCfg), schCellCfg->phyCellId,
850 schCellCfg->ssbSchCfg.ssbOffsetPointA);
851 memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg));
853 /* Initializing global variables */
854 cellCb->actvUeBitMap = 0;
855 cellCb->boIndBitMap = 0;
857 /* Fill and send Cell config confirm */
858 memset(&rspPst, 0, sizeof(Pst));
859 FILL_PST_SCH_TO_MAC(rspPst, pst->dstInst);
860 rspPst.event = EVENT_SCH_CELL_CFG_CFM;
862 schCellCfgCfm.cellId = schCellCfg->cellId;
863 schCellCfgCfm.rsp = RSP_OK;
865 ret = (*SchCellCfgCfmOpts[rspPst.selector])(&rspPst, &schCellCfgCfm);
871 /*******************************************************************
873 * @brief Processes DL RLC BO info from MAC
877 * Function : MacSchDlRlcBoInfo
880 * Processes DL RLC BO info from MAC
883 * @return ROK - success
886 * ****************************************************************/
887 uint8_t MacSchDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo)
893 uint16_t slotIdx = 0;
895 SchUeCb *ueCb = NULLP;
896 SchCellCb *cell = NULLP;
897 SchDlSlotInfo *schDlSlotInfo = NULLP;
899 Inst inst = pst->dstInst-SCH_INST_START;
900 DU_LOG("\nDEBUG --> SCH : Received RLC BO Status indication");
901 cell = schCb[inst].cells[inst];
903 GET_UE_IDX(dlBoInfo->crnti, ueIdx);
904 ueCb = &cell->ueCb[ueIdx-1];
905 lcId = dlBoInfo->lcId;
907 if(lcId == SRB1_LCID || lcId == SRB2_LCID || lcId == SRB3_LCID || \
908 (lcId >= MIN_DRB_LCID && lcId <= MAX_DRB_LCID))
910 SET_ONE_BIT(ueIdx, cell->boIndBitMap);
911 ueCb->dlInfo.dlLcCtxt[lcId].bo = dlBoInfo->dataVolume;
913 else if(lcId != SRB0_LCID)
915 DU_LOG("\nERROR --> SCH : Invalid LC Id %d in MacSchDlRlcBoInfo", lcId);
919 slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA_DL + BO_DELTA) % cell->numSlots;
921 while(schGetSlotSymbFrmt(cell->slotFrmtBitMap, slot) != DL_SLOT)
923 slot = (slot + 1)%cell->numSlots;
925 if(slotIdx==cell->numSlots)
927 DU_LOG("\nERROR --> SCH : No DL Slot available");
932 schDlSlotInfo = cell->schDlSlotInfo[slot];
934 SCH_ALLOC(schDlSlotInfo->dlMsgInfo, sizeof(DlMsgInfo));
935 if(!schDlSlotInfo->dlMsgInfo)
937 DU_LOG("\nERROR --> SCH : Memory allocation failed for dlMsgInfo");
938 schDlSlotInfo = NULL;
941 schDlSlotInfo->dlMsgInfo->crnti = dlBoInfo->crnti;
942 schDlSlotInfo->dlMsgInfo->ndi = 1;
943 schDlSlotInfo->dlMsgInfo->harqProcNum = 0;
944 schDlSlotInfo->dlMsgInfo->dlAssignIdx = 0;
945 schDlSlotInfo->dlMsgInfo->pucchTpc = 0;
946 schDlSlotInfo->dlMsgInfo->pucchResInd = 0;
947 schDlSlotInfo->dlMsgInfo->harqFeedbackInd = 0;
948 schDlSlotInfo->dlMsgInfo->dciFormatId = 1;
949 if(lcId == SRB0_LCID)
950 schDlSlotInfo->dlMsgInfo->isMsg4Pdu = true;
955 /*******************************************************************
957 * @brief Processes BSR indiation from MAC
961 * Function : MacSchBsr
964 * Processes DL BSR from MAC
966 * @params[in] Pst pst
967 * UlBufferStatusRptInd bsrInd
968 * @return ROK - success
971 * ****************************************************************/
972 uint8_t MacSchBsr(Pst *pst, UlBufferStatusRptInd *bsrInd)
974 Inst schInst = pst->dstInst-SCH_INST_START;
975 SchCellCb *cellCb = NULLP;
976 SchUeCb *ueCb = NULLP;
979 DU_LOG("\nDEBUG --> SCH : Received BSR");
980 cellCb = schCb[schInst].cells[schInst];
981 ueCb = schGetUeCb(cellCb, bsrInd->crnti);
983 /* store dataVolume per lcg in uecb */
984 for(lcgIdx = 0; lcgIdx < bsrInd->numLcg; lcgIdx++)
986 ueCb->bsrInfo[lcgIdx].priority = 1; //TODO: determining LCG priority?
987 ueCb->bsrInfo[lcgIdx].dataVol = bsrInd->dataVolInfo[lcgIdx].dataVol;
992 /*******************************************************************
994 * @brief Processes SR UCI indication from MAC
998 * Function : MacSchSrUciInd
1001 * Processes SR UCI indication from MAC
1003 * @params[in] Post structure
1005 * @return ROK - success
1008 * ****************************************************************/
1009 uint8_t MacSchSrUciInd(Pst *pst, SrUciIndInfo *uciInd)
1011 Inst inst = pst->dstInst-SCH_INST_START;
1014 SchCellCb *cellCb = schCb[inst].cells[inst];
1016 DU_LOG("\nDEBUG --> SCH : Received SR");
1018 ueCb = schGetUeCb(cellCb, uciInd->crnti);
1020 if(uciInd->numSrBits)
1022 ueCb->srRcvd = true;
1026 /**********************************************************************
1028 **********************************************************************/