1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
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14 # See the License for the specific language governing permissions and #
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17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for scheduler fucntions
29 **********************************************************************/
32 @brief This file implements the schedulers main access to MAC layer code.
34 #include "common_def.h"
35 #include "du_app_mac_inf.h"
40 #include "rg_sch_inf.h"
43 #include "tfu.x" /* TFU types */
44 #include "lrg.x" /* layer management typedefs for MAC */
45 #include "rgr.x" /* layer management typedefs for MAC */
46 #include "rg_sch_inf.x" /* typedefs for Scheduler */
47 #include "mac_sch_interface.h"
49 #include "sch_utils.h"
51 extern SchCb schCb[SCH_MAX_INST];
52 void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
54 SchCellCfgCfmFunc SchCellCfgCfmOpts[] =
56 packSchCellCfgCfm, /* LC */
57 MacProcSchCellCfgCfm, /* TC */
58 packSchCellCfgCfm /* LWLC */
63 * @brief Task Initiation function.
67 * Function : schActvInit
69 * This function is supplied as one of parameters during MAC's
70 * task registration. MAC will invoke this function once, after
71 * it creates and attaches this TAPA Task to a system task.
73 * @param[in] Ent Entity, the entity ID of this task.
74 * @param[in] Inst Inst, the instance ID of this task.
75 * @param[in] Region Region, the region ID registered for memory
77 * @param[in] Reason Reason.
81 uint8_t schActvInit(Ent entity, Inst instId, Region region, Reason reason)
83 Inst inst = (instId - SCH_INST_START);
85 /* Initialize the MAC TskInit structure to zero */
86 cmMemset ((uint8_t *)&schCb[inst], 0, sizeof(schCb));
88 /* Initialize the MAC TskInit with received values */
89 schCb[inst].schInit.ent = entity;
90 schCb[inst].schInit.inst = inst;
91 schCb[inst].schInit.region = region;
92 schCb[inst].schInit.pool = 0;
93 schCb[inst].schInit.reason = reason;
94 schCb[inst].schInit.cfgDone = FALSE;
95 schCb[inst].schInit.acnt = FALSE;
96 schCb[inst].schInit.usta = FALSE;
97 schCb[inst].schInit.trc = FALSE;
98 schCb[inst].schInit.procId = SFndProcId();
104 * @brief Scheduler instance Configuration Handler.
108 * Function : SchInstCfg
110 * This function in called by SchProcGenCfgReq(). It handles the
111 * general configurations of the scheduler instance. Returns
112 * reason for success/failure of this function.
114 * @param[in] RgCfg *cfg, the Configuaration information
116 * -# LCM_REASON_NOT_APPL
117 * -# LCM_REASON_INVALID_MSGTYPE
118 * -# LCM_REASON_MEM_NOAVAIL
120 PUBLIC U16 SchInstCfg(RgCfg *cfg, Inst dInst)
122 uint16_t ret = LCM_REASON_NOT_APPL;
123 Inst inst = (dInst - SCH_INST_START);
125 printf("\nEntered SchInstCfg()");
126 /* Check if Instance Configuration is done already */
127 if (schCb[inst].schInit.cfgDone == TRUE)
129 return LCM_REASON_INVALID_MSGTYPE;
131 /* Update the Pst structure for LM interface */
132 cmMemcpy((U8 *)&schCb[inst].schInit.lmPst,
133 (U8 *)&cfg->s.schInstCfg.genCfg.lmPst,
136 schCb[inst].schInit.inst = inst;
137 schCb[inst].schInit.lmPst.srcProcId = schCb[inst].schInit.procId;
138 schCb[inst].schInit.lmPst.srcEnt = schCb[inst].schInit.ent;
139 schCb[inst].schInit.lmPst.srcInst = schCb[inst].schInit.inst +
141 schCb[inst].schInit.lmPst.event = EVTNONE;
143 schCb[inst].schInit.region = cfg->s.schInstCfg.genCfg.mem.region;
144 schCb[inst].schInit.pool = cfg->s.schInstCfg.genCfg.mem.pool;
145 schCb[inst].genCfg.tmrRes = cfg->s.schInstCfg.genCfg.tmrRes;
147 schCb[inst].genCfg.forceCntrlSrbBoOnPCel = cfg->s.schInstCfg.genCfg.forceCntrlSrbBoOnPCel;
148 schCb[inst].genCfg.isSCellActDeactAlgoEnable = cfg->s.schInstCfg.genCfg.isSCellActDeactAlgoEnable;
150 schCb[inst].genCfg.startCellId = cfg->s.schInstCfg.genCfg.startCellId;
152 /* Initialzie the timer queue */
153 cmMemset((U8 *)&schCb[inst].tmrTq, 0, sizeof(CmTqType)*RGSCH_TQ_SIZE);
154 /* Initialize the timer control point */
155 cmMemset((U8 *)&schCb[inst].tmrTqCp, 0, sizeof(CmTqCp));
156 schCb[inst].tmrTqCp.tmrLen = RGSCH_TQ_SIZE;
158 /* SS_MT_TMR needs to be enabled as schActvTmr needs instance information */
159 /* Timer Registration request to SSI */
160 if (SRegTmrMt(schCb[inst].schInit.ent, dInst,
161 (S16)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK)
163 RLOG_ARG0(L_ERROR,DBG_INSTID,inst, "SchInstCfg(): Failed to "
165 RETVALUE(LCM_REASON_MEM_NOAVAIL);
168 /* Set Config done in TskInit */
169 schCb[inst].schInit.cfgDone = TRUE;
170 printf("\nScheduler gen config done");
176 * @brief Layer Manager Configuration request handler.
180 * Function : SchProcGenCfgReq
182 * This function handles the configuration
183 * request received at scheduler instance from the Layer Manager.
184 * -# Based on the cfg->hdr.elmId.elmnt value it invokes one of the
185 * functions rgHdlGenCfg() or rgHdlSapCfg().
186 * -# Invokes RgMiLrgSchCfgCfm() to send back the confirmation to the LM.
188 * @param[in] Pst *pst, the post structure
189 * @param[in] RgMngmt *cfg, the configuration parameter's structure
193 int SchProcGenCfgReq(Pst *pst, RgMngmt *cfg)
195 uint16_t ret = LCM_PRIM_OK;
196 uint16_t reason = LCM_REASON_NOT_APPL;
200 if(pst->dstInst < SCH_INST_START)
202 DU_LOG("\nInvalid inst ID");
203 DU_LOG("\nSchProcGenCfgReq(): "
204 "pst->dstInst=%d SCH_INST_START=%d", pst->dstInst,SCH_INST_START);
207 printf("\nReceived scheduler gen config");
208 /* Fill the post structure for sending the confirmation */
209 memset(&cfmPst, 0 , sizeof(Pst));
210 SchFillCfmPst(pst, &cfmPst, cfg);
212 cmMemset((U8 *)&cfm, 0, sizeof(RgMngmt));
219 cfm.hdr.elmId.elmnt = cfg->hdr.elmId.elmnt;
220 switch(cfg->hdr.elmId.elmnt)
223 reason = SchInstCfg(&cfg->t.cfg,pst->dstInst );
227 reason = LCM_REASON_INVALID_ELMNT;
228 DU_LOG("\nInvalid Elmnt=%d", cfg->hdr.elmId.elmnt);
232 if (reason != LCM_REASON_NOT_APPL)
237 cfm.cfm.status = ret;
238 cfm.cfm.reason = reason;
240 SchSendCfgCfm(&cfmPst, &cfm);
241 /* SPutSBuf(pst->region, pst->pool, (Data *)cfg, sizeof(RgMngmt)); */
244 }/*-- SchProcGenCfgReq --*/
247 * @brief slot indication from MAC to SCH.
251 * Function : macSchSlotInd
253 * This API is invoked by PHY to indicate slot indication to Scheduler for
256 * @param[in] Pst *pst
257 * @param[in] SlotIndInfo *slotInd
262 uint8_t macSchSlotInd(Pst *pst, SlotIndInfo *slotInd)
264 Inst inst = pst->dstInst-SCH_INST_START;
266 /* Now call the TOM (Tfu ownership module) primitive to process further */
267 schProcessSlotInd(slotInd, inst);
270 } /* macSchSlotInd */
272 /*******************************************************************
274 * @brief Processes Rach indication from MAC
278 * Function : macSchRachInd
281 * Processes Rach indication from MAC
284 * @return ROK - success
287 * ****************************************************************/
288 uint8_t macSchRachInd(Pst *pst, RachIndInfo *rachInd)
290 Inst inst = pst->dstInst-SCH_INST_START;
291 DU_LOG("\nSCH : Received Rach indication");
292 schProcessRachInd(rachInd, inst);
296 /*******************************************************************
298 * @brief Processes CRC indication from MAC
302 * Function : macSchCrcInd
305 * Processes CRC indication from MAC
307 * @params[in] Post structure
309 * @return ROK - success
312 * ****************************************************************/
313 uint8_t macSchCrcInd(Pst *pst, CrcIndInfo *crcInd)
315 switch(crcInd->crcInd[0])
318 DU_LOG("\nSCH : Received CRC indication. CRC Status [FAILURE]");
321 DU_LOG("\nSCH : Received CRC indication. CRC Status [PASS]");
324 DU_LOG("\nSCH : Invalid CRC state %d", crcInd->crcInd[0]);
332 * @brief inti cellCb based on cellCfg
336 * Function : InitSchCellCb
338 * This API is invoked after receiving schCellCfg
340 * @param[in] schCellCb *cell
341 * @param[in] SchCellCfg *schCellCfg
346 int InitSchCellCb(Inst inst, SchCellCfg *schCellCfg)
349 SCH_ALLOC(cell, sizeof(SchCellCb));
352 DU_LOG("\nMemory allocation failed in InitSchCellCb");
356 cell->cellId = schCellCfg->cellId;
357 cell->instIdx = inst;
358 switch(schCellCfg->ssbSchCfg.scsCommon)
362 cell->numSlots = SCH_NUM_SLOTS;
366 DU_LOG("\nSCS %d not supported", schCellCfg->ssbSchCfg.scsCommon);
369 for(uint8_t idx=0; idx<SCH_NUM_SLOTS; idx++)
371 SchDlSlotInfo *schDlSlotInfo;
372 SchUlSlotInfo *schUlSlotInfo;
375 SCH_ALLOC(schDlSlotInfo, sizeof(SchDlSlotInfo));
378 DU_LOG("\nMemory allocation failed in InitSchCellCb");
383 SCH_ALLOC(schUlSlotInfo, sizeof(SchUlSlotInfo));
386 DU_LOG("\nMemory allocation failed in InitSchCellCb");
390 memset(schDlSlotInfo, 0, sizeof(SchDlSlotInfo));
391 memset(schUlSlotInfo, 0, sizeof(SchUlSlotInfo));
393 schDlSlotInfo->totalPrb = schUlSlotInfo->totalPrb = MAX_NUM_RB;
395 for(uint8_t itr=0; itr<SCH_SYMBOL_PER_SLOT; itr++)
397 schDlSlotInfo->assignedPrb[itr] = 0;
398 schUlSlotInfo->assignedPrb[itr] = 0;
400 schUlSlotInfo->schPuschInfo = NULLP;
402 for(uint8_t itr=0; itr<MAX_SSB_IDX; itr++)
404 memset(&schDlSlotInfo->ssbInfo[itr], 0, sizeof(SsbInfo));
407 cell->schDlSlotInfo[idx] = schDlSlotInfo;
408 cell->schUlSlotInfo[idx] = schUlSlotInfo;
411 schCb[inst].cells[inst] = cell;
413 DU_LOG("\nCell init completed for cellId:%d", cell->cellId);
419 * @brief Fill SIB1 configuration
423 * Function : fillSchSib1Cfg
425 * Fill SIB1 configuration
427 * @param[in] Inst schInst : scheduler instance
428 * SchSib1Cfg *sib1SchCfg : cfg to be filled
429 * uint16_t pci : physical cell Id
430 * uint8_t offsetPointA : offset
433 void fillSchSib1Cfg(Inst schInst, SchSib1Cfg *sib1SchCfg, uint16_t pci, \
434 uint8_t offsetPointA)
436 uint8_t coreset0Idx = 0;
437 uint8_t searchSpace0Idx = 0;
438 //uint8_t ssbMuxPattern = 0;
440 uint8_t numSymbols = 0;
443 //uint8_t numSearchSpacePerSlot = 0;
445 uint8_t firstSymbol = 0; /* need to calculate using formula mentioned in 38.213 */
446 uint8_t slotIndex = 0;
447 uint8_t FreqDomainResource[6] = {0};
449 uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
451 PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg);
452 PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg);
453 BwpCfg *bwp = &(sib1SchCfg->bwp);
455 coreset0Idx = sib1SchCfg->coresetZeroIndex;
456 searchSpace0Idx = sib1SchCfg->searchSpaceZeroIndex;
458 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
459 //ssbMuxPattern = coresetIdxTable[coreset0Idx][0];
460 numRbs = coresetIdxTable[coreset0Idx][1];
461 numSymbols = coresetIdxTable[coreset0Idx][2];
462 offset = coresetIdxTable[coreset0Idx][3];
464 /* derive the search space params from table 13-11 spec 38.213 */
465 oValue = searchSpaceIdxTable[searchSpace0Idx][0];
466 //numSearchSpacePerSlot = searchSpaceIdxTable[searchSpace0Idx][1];
467 mValue = searchSpaceIdxTable[searchSpace0Idx][2];
468 firstSymbol = searchSpaceIdxTable[searchSpace0Idx][3];
470 /* calculate the n0, need to add the formulae, as of now the value is 0
471 * Need to add the even and odd values of i during configuration
472 * [(O . 2^u + i . M ) ] mod numSlotsPerSubframe
473 * assuming u = 0, i = 0, numSlotsPerSubframe = 10
474 * Also, from this configuration, coreset0 is only on even subframe */
475 slotIndex = ((oValue * 1) + (0 * mValue)) % 10;
476 sib1SchCfg->n0 = slotIndex;
478 /* calculate the PRBs */
479 schAllocFreqDomRscType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
482 bwp->freqAlloc.numPrb = MAX_NUM_RB; /* whole of BW */
483 bwp->freqAlloc.startPrb = 0;
484 bwp->subcarrierSpacing = 0; /* 15Khz */
485 bwp->cyclicPrefix = 0; /* normal */
487 /* fill the PDCCH PDU */
488 pdcch->coreset0Cfg.coreSet0Size = numRbs;
489 pdcch->coreset0Cfg.startSymbolIndex = firstSymbol;
490 pdcch->coreset0Cfg.durationSymbols = numSymbols;
491 memcpy(pdcch->coreset0Cfg.freqDomainResource,FreqDomainResource,6);
492 pdcch->coreset0Cfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
493 pdcch->coreset0Cfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
494 pdcch->coreset0Cfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
495 pdcch->coreset0Cfg.coreSetType = 0;
496 pdcch->coreset0Cfg.shiftIndex = pci;
497 pdcch->coreset0Cfg.precoderGranularity = 0; /* sameAsRegBundle */
499 pdcch->dci.rnti = SI_RNTI;
500 pdcch->dci.scramblingId = pci;
501 pdcch->dci.scramblingRnti = 0;
502 pdcch->dci.cceIndex = 0;
503 pdcch->dci.aggregLevel = 4;
504 pdcch->dci.beamPdcchInfo.numPrgs = 1;
505 pdcch->dci.beamPdcchInfo.prgSize = 1;
506 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
507 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
508 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
509 pdcch->dci.txPdcchPower.powerValue = 0;
510 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
511 /* Storing pdschCfg pointer here. Required to access pdsch config while
512 fillig up pdcch pdu */
513 pdcch->dci.pdschCfg = pdsch;
515 /* fill the PDSCH PDU */
517 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
518 pdsch->rnti = 0xFFFF; /* SI-RNTI */
520 pdsch->numCodewords = 1;
521 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
523 pdsch->codeword[cwCount].targetCodeRate = 308;
524 pdsch->codeword[cwCount].qamModOrder = 2;
525 pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs;
526 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
527 pdsch->codeword[cwCount].rvIndex = 0;
528 tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen);
529 pdsch->codeword[cwCount].tbSize = tbSize;
531 pdsch->dataScramblingId = pci;
532 pdsch->numLayers = 1;
533 pdsch->transmissionScheme = 0;
535 pdsch->dmrs.dlDmrsSymbPos = 2;
536 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
537 pdsch->dmrs.dlDmrsScramblingId = pci;
538 pdsch->dmrs.scid = 0;
539 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
540 pdsch->dmrs.dmrsPorts = 0;
541 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Type-A */
542 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
543 pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
545 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
546 pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB; /* the RB numbering starts from coreset0,
547 and PDSCH is always above SSB */
548 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols);
549 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
550 pdsch->pdschTimeAlloc.rowIndex = 1;
551 pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
552 pdsch->pdschTimeAlloc.timeAlloc.numSymb = numPdschSymbols;
553 pdsch->beamPdschInfo.numPrgs = 1;
554 pdsch->beamPdschInfo.prgSize = 1;
555 pdsch->beamPdschInfo.digBfInterfaces = 0;
556 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
557 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
558 pdsch->txPdschPower.powerControlOffset = 0;
559 pdsch->txPdschPower.powerControlOffsetSS = 0;
564 * @brief Fill SSB start symbol
568 * Function : fillSsbStartSymb
570 * This API stores SSB start index per beam
572 * @param[in] SchCellCb *cellCb
577 void fillSsbStartSymb(SchCellCb *cellCb)
581 scs = cellCb->cellCfg.ssbSchCfg.scsCommon;
582 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM];
584 memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
585 /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */
591 cnt = 2;/* n = 0, 1 for SCS = 15KHz */
592 for(uint8_t idx=0; idx<cnt; idx++)
594 /* start symbol determined using {2, 8} + 14n */
595 ssbStartSymbArr[symbIdx++] = 2 + SCH_SYMBOL_PER_SLOT*idx;
596 ssbStartSymbArr[symbIdx++] = 8 + SCH_SYMBOL_PER_SLOT*idx;
601 DU_LOG("\nSCS %d is currently not supported", scs);
603 memset(cellCb->ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
604 memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM);
609 * @brief cell config from MAC to SCH.
613 * Function : macSchCellCfgReq
615 * This API is invoked by MAC to send cell config to SCH
617 * @param[in] Pst *pst
618 * @param[in] SchCellCfg *schCellCfg
623 uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg)
627 SchCellCfgCfm schCellCfgCfm;
629 Inst inst = pst->dstInst-1;
631 InitSchCellCb(inst, schCellCfg);
632 cellCb = schCb[inst].cells[inst]; //cells is of MAX_CELLS, why inst
633 cellCb->macInst = pst->srcInst;
635 /* derive the SIB1 config parameters */
638 &(schCellCfg->sib1SchCfg),
639 schCellCfg->phyCellId,
640 schCellCfg->ssbSchCfg.ssbOffsetPointA);
641 memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg));
643 /* Fill and send Cell config confirm */
644 memset(&rspPst, 0, sizeof(Pst));
645 FILL_PST_SCH_TO_MAC(rspPst, pst->dstInst);
646 rspPst.event = EVENT_SCH_CELL_CFG_CFM;
648 schCellCfgCfm.cellId = schCellCfg->cellId;
649 schCellCfgCfm.rsp = RSP_OK;
651 ret = (*SchCellCfgCfmOpts[rspPst.selector])(&rspPst, &schCellCfgCfm);
657 /*******************************************************************
659 * @brief Processes DL RLC BO info from MAC
663 * Function : macSchDlRlcBoInfo
666 * Processes DL RLC BO info from MAC
669 * @return ROK - success
672 * ****************************************************************/
673 uint8_t macSchDlRlcBoInfo(Pst *pst, DlRlcBOInfo *dlBoInfo)
676 Inst inst = pst->dstInst-SCH_INST_START;
677 DU_LOG("\nSCH : Received RLC BO Status indication");
679 SchCellCb *cell = schCb[inst].cells[inst];
680 SchDlSlotInfo *schDlSlotInfo = \
681 cell->schDlSlotInfo[(cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA + MSG4_DELAY) % SCH_NUM_SLOTS];
683 for(lcIdx = 0; lcIdx < dlBoInfo->numLc; lcIdx++)
685 if(dlBoInfo->boInfo[lcIdx].lcId == CCCH_LCID)
687 SCH_ALLOC(schDlSlotInfo->msg4Info, sizeof(Msg4Info));
688 if(!schDlSlotInfo->msg4Info)
690 DU_LOG("\nSCH : Memory allocation failed for msg4Info");
691 schDlSlotInfo = NULL;
694 schDlSlotInfo->msg4Info->crnti = dlBoInfo->crnti;
695 schDlSlotInfo->msg4Info->ndi = 1;
696 schDlSlotInfo->msg4Info->harqProcNum = 0;
697 schDlSlotInfo->msg4Info->dlAssignIdx = 0;
698 schDlSlotInfo->msg4Info->pucchTpc = 0;
699 schDlSlotInfo->msg4Info->pucchResInd = 0;
700 schDlSlotInfo->msg4Info->harqFeedbackInd = 0;
701 schDlSlotInfo->msg4Info->dciFormatId = 1;
708 /**********************************************************************
710 **********************************************************************/