1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
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13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
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16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for scheduler fucntions
29 **********************************************************************/
32 @brief This file implements the schedulers main access to MAC layer code.
34 #include "common_def.h"
35 #include "du_app_mac_inf.h"
40 #include "rg_sch_inf.h"
43 #include "tfu.x" /* TFU types */
44 #include "lrg.x" /* layer management typedefs for MAC */
45 #include "rgr.x" /* layer management typedefs for MAC */
46 #include "rg_sch_inf.x" /* typedefs for Scheduler */
47 #include "mac_sch_interface.h"
49 #include "sch_utils.h"
51 SchCb schCb[SCH_MAX_INST];
52 void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
54 SchCellCfgCfmFunc SchCellCfgCfmOpts[] =
56 packSchCellCfgCfm, /* LC */
57 MacProcSchCellCfgCfm, /* TC */
58 packSchCellCfgCfm /* LWLC */
63 * @brief Task Initiation function.
67 * Function : schActvInit
69 * This function is supplied as one of parameters during MAC's
70 * task registration. MAC will invoke this function once, after
71 * it creates and attaches this TAPA Task to a system task.
73 * @param[in] Ent Entity, the entity ID of this task.
74 * @param[in] Inst Inst, the instance ID of this task.
75 * @param[in] Region Region, the region ID registered for memory
77 * @param[in] Reason Reason.
81 uint8_t schActvInit(Ent entity, Inst instId, Region region, Reason reason)
83 Inst inst = (instId - SCH_INST_START);
85 /* Initialize the MAC TskInit structure to zero */
86 memset ((uint8_t *)&schCb[inst], 0, sizeof(schCb));
88 /* Initialize the MAC TskInit with received values */
89 schCb[inst].schInit.ent = entity;
90 schCb[inst].schInit.inst = inst;
91 schCb[inst].schInit.region = region;
92 schCb[inst].schInit.pool = 0;
93 schCb[inst].schInit.reason = reason;
94 schCb[inst].schInit.cfgDone = FALSE;
95 schCb[inst].schInit.acnt = FALSE;
96 schCb[inst].schInit.usta = FALSE;
97 schCb[inst].schInit.trc = FALSE;
98 schCb[inst].schInit.procId = ODU_GET_PROCID();
104 * @brief Scheduler instance Configuration Handler.
108 * Function : SchInstCfg
110 * This function in called by SchProcGenCfgReq(). It handles the
111 * general configurations of the scheduler instance. Returns
112 * reason for success/failure of this function.
114 * @param[in] RgCfg *cfg, the Configuaration information
116 * -# LCM_REASON_NOT_APPL
117 * -# LCM_REASON_INVALID_MSGTYPE
118 * -# LCM_REASON_MEM_NOAVAIL
120 uint8_t SchInstCfg(RgCfg *cfg, Inst dInst)
122 uint16_t ret = LCM_REASON_NOT_APPL;
123 Inst inst = (dInst - SCH_INST_START);
125 DU_LOG("\nDEBUG --> SCH : Entered SchInstCfg()");
126 /* Check if Instance Configuration is done already */
127 if (schCb[inst].schInit.cfgDone == TRUE)
129 return LCM_REASON_INVALID_MSGTYPE;
131 /* Update the Pst structure for LM interface */
132 memcpy(&schCb[inst].schInit.lmPst,
133 &cfg->s.schInstCfg.genCfg.lmPst,
136 schCb[inst].schInit.inst = inst;
137 schCb[inst].schInit.lmPst.srcProcId = schCb[inst].schInit.procId;
138 schCb[inst].schInit.lmPst.srcEnt = schCb[inst].schInit.ent;
139 schCb[inst].schInit.lmPst.srcInst = schCb[inst].schInit.inst +
141 schCb[inst].schInit.lmPst.event = EVTNONE;
143 schCb[inst].schInit.region = cfg->s.schInstCfg.genCfg.mem.region;
144 schCb[inst].schInit.pool = cfg->s.schInstCfg.genCfg.mem.pool;
145 schCb[inst].genCfg.tmrRes = cfg->s.schInstCfg.genCfg.tmrRes;
147 schCb[inst].genCfg.forceCntrlSrbBoOnPCel = cfg->s.schInstCfg.genCfg.forceCntrlSrbBoOnPCel;
148 schCb[inst].genCfg.isSCellActDeactAlgoEnable = cfg->s.schInstCfg.genCfg.isSCellActDeactAlgoEnable;
150 schCb[inst].genCfg.startCellId = cfg->s.schInstCfg.genCfg.startCellId;
152 /* Initialzie the timer queue */
153 memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType) * SCH_TQ_SIZE);
154 /* Initialize the timer control point */
155 memset(&schCb[inst].tmrTqCp, 0, sizeof(CmTqCp));
156 schCb[inst].tmrTqCp.tmrLen = RGSCH_TQ_SIZE;
158 /* SS_MT_TMR needs to be enabled as schActvTmr needs instance information */
159 /* Timer Registration request to system services */
160 if (ODU_REG_TMR_MT(schCb[inst].schInit.ent, dInst,
161 (int)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK)
163 DU_LOG("\nERROR --> SCH : SchInstCfg(): Failed to "
165 return (LCM_REASON_MEM_NOAVAIL);
168 /* Set Config done in TskInit */
169 schCb[inst].schInit.cfgDone = TRUE;
170 DU_LOG("\nINFO --> SCH : Scheduler gen config done");
176 * @brief Layer Manager Configuration request handler.
180 * Function : SchProcGenCfgReq
182 * This function handles the configuration
183 * request received at scheduler instance from the Layer Manager.
184 * -# Based on the cfg->hdr.elmId.elmnt value it invokes one of the
185 * functions rgHdlGenCfg() or rgHdlSapCfg().
186 * -# Invokes RgMiLrgSchCfgCfm() to send back the confirmation to the LM.
188 * @param[in] Pst *pst, the post structure
189 * @param[in] RgMngmt *cfg, the configuration parameter's structure
193 uint8_t SchProcGenCfgReq(Pst *pst, RgMngmt *cfg)
195 uint8_t ret = LCM_PRIM_OK;
196 uint16_t reason = LCM_REASON_NOT_APPL;
200 #ifdef CALL_FLOW_DEBUG_LOG
201 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : GENERAL_CFG_REQ\n");
204 if(pst->dstInst < SCH_INST_START)
206 DU_LOG("\nERROR --> SCH : Invalid inst ID");
207 DU_LOG("\nERROR --> SCH : SchProcGenCfgReq(): "
208 "pst->dstInst=%d SCH_INST_START=%d", pst->dstInst,SCH_INST_START);
211 DU_LOG("\nINFO --> SCH : Received scheduler gen config");
212 /* Fill the post structure for sending the confirmation */
213 memset(&cfmPst, 0 , sizeof(Pst));
214 SchFillCfmPst(pst, &cfmPst, cfg);
216 memset(&cfm, 0, sizeof(RgMngmt));
223 cfm.hdr.elmId.elmnt = cfg->hdr.elmId.elmnt;
224 switch(cfg->hdr.elmId.elmnt)
227 reason = SchInstCfg(&cfg->t.cfg,pst->dstInst );
231 reason = LCM_REASON_INVALID_ELMNT;
232 DU_LOG("\nERROR --> SCH : Invalid Elmnt=%d", cfg->hdr.elmId.elmnt);
236 if (reason != LCM_REASON_NOT_APPL)
241 cfm.cfm.status = ret;
242 cfm.cfm.reason = reason;
244 SchSendCfgCfm(&cfmPst, &cfm);
245 /* SCH_FREE(pst->region, pst->pool, (Data *)cfg, sizeof(RgMngmt)); */
248 }/*-- SchProcGenCfgReq --*/
251 * @brief slot indication from MAC to SCH.
255 * Function : MacSchSlotInd
257 * This API is invoked by PHY to indicate slot indication to Scheduler for
260 * @param[in] Pst *pst
261 * @param[in] SlotTimingInfo *slotInd
266 uint8_t MacSchSlotInd(Pst *pst, SlotTimingInfo *slotInd)
268 Inst inst = pst->dstInst-SCH_INST_START;
270 #ifdef CALL_FLOW_DEBUG_LOG
271 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_SLOT_IND_TO_SCH\n");
274 schProcessSlotInd(slotInd, inst);
277 } /* MacSchSlotInd */
279 /*******************************************************************
281 * @brief Processes Rach indication from MAC
285 * Function : MacSchRachInd
288 * Processes Rach indication from MAC
291 * @return ROK - success
294 * ****************************************************************/
295 uint8_t MacSchRachInd(Pst *pst, RachIndInfo *rachInd)
297 Inst inst = pst->dstInst-SCH_INST_START;
299 #ifdef CALL_FLOW_DEBUG_LOG
300 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_RACH_IND_TO_SCH\n");
303 DU_LOG("\nINFO --> SCH : Received Rach indication");
304 schProcessRachInd(rachInd, inst);
308 /*******************************************************************
310 * @brief Processes CRC indication from MAC
314 * Function : MacSchCrcInd
317 * Processes CRC indication from MAC
319 * @params[in] Post structure
321 * @return ROK - success
324 * ****************************************************************/
325 uint8_t MacSchCrcInd(Pst *pst, CrcIndInfo *crcInd)
327 #ifdef CALL_FLOW_DEBUG_LOG
328 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_CRC_IND_TO_SCH\n");
331 switch(crcInd->crcInd[0])
334 DU_LOG("\nDEBUG --> SCH : Received CRC indication. CRC Status [FAILURE]");
337 DU_LOG("\nDEBUG --> SCH : Received CRC indication. CRC Status [PASS]");
340 DU_LOG("\nDEBUG --> SCH : Invalid CRC state %d", crcInd->crcInd[0]);
348 *@brief Returns TDD periodicity in micro seconds
352 * Function : schGetPeriodicityInMsec
354 * This API retunrs TDD periodicity in micro seconds
356 * @param[in] DlUlTxPeriodicity
357 * @return periodicityInMsec
360 uint16_t schGetPeriodicityInMsec(DlUlTxPeriodicity tddPeriod)
362 uint16_t periodicityInMsec = 0;
365 case TX_PRDCTY_MS_0P5:
367 periodicityInMsec = 500;
370 case TX_PRDCTY_MS_0P625:
372 periodicityInMsec = 625;
377 periodicityInMsec = 1000;
380 case TX_PRDCTY_MS_1P25:
382 periodicityInMsec = 1250;
387 periodicityInMsec = 2000;
390 case TX_PRDCTY_MS_2P5:
392 periodicityInMsec = 2500;
397 periodicityInMsec = 5000;
400 case TX_PRDCTY_MS_10:
402 periodicityInMsec = 10000;
407 DU_LOG("\nERROR --> SCH : Invalid DlUlTxPeriodicity:%d", tddPeriod);
411 return periodicityInMsec;
416 * @brief init TDD slot config
420 * Function : schInitTddSlotCfg
422 * This API is invoked after receiving schCellCfg
424 * @param[in] schCellCb *cell
425 * @param[in] SchCellCfg *schCellCfg
428 void schInitTddSlotCfg(SchCellCb *cell, SchCellCfg *schCellCfg)
430 uint16_t periodicityInMicroSec = 0;
431 int8_t slotIdx, symbIdx;
433 periodicityInMicroSec = schGetPeriodicityInMsec(schCellCfg->tddCfg.tddPeriod);
434 cell->numSlotsInPeriodicity = (periodicityInMicroSec * pow(2, schCellCfg->numerology))/1000;
435 cell->slotFrmtBitMap = 0;
436 cell->symbFrmtBitMap = 0;
437 for(slotIdx = cell->numSlotsInPeriodicity-1; slotIdx >= 0; slotIdx--)
440 /* If the first and last symbol are the same, the entire slot is the same type */
441 if((schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx] == schCellCfg->tddCfg.slotCfg[slotIdx][MAX_SYMB_PER_SLOT-1]) &&
442 schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx] != FLEXI_SLOT)
444 switch(schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx])
448 /*BitMap to be set to 00 */
449 cell->slotFrmtBitMap = (cell->slotFrmtBitMap<<2);
454 /*BitMap to be set to 01 */
455 cell->slotFrmtBitMap = ((cell->slotFrmtBitMap<<2) | (UL_SLOT));
459 DU_LOG("\nERROR --> SCH : Invalid slot Config in schInitTddSlotCfg");
463 /* slot config is flexible. First set slotBitMap to 10 */
464 cell->slotFrmtBitMap = ((cell->slotFrmtBitMap<<2) | (FLEXI_SLOT));
466 /* Now set symbol bitmap */
467 for(symbIdx = MAX_SYMB_PER_SLOT-1; symbIdx >= 0; symbIdx--)
469 switch(schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx])
473 /*symbol BitMap to be set to 00 */
474 cell->symbFrmtBitMap = (cell->symbFrmtBitMap<<2);
479 /*symbol BitMap to be set to 01 */
480 cell->symbFrmtBitMap = ((cell->symbFrmtBitMap<<2) | (UL_SLOT));
485 /*symbol BitMap to be set to 10 */
486 cell->symbFrmtBitMap = ((cell->symbFrmtBitMap<<2) | (FLEXI_SLOT));
490 DU_LOG("\nERROR --> SCH : Invalid slot Config in schInitTddSlotCfg");
498 * @brief Fill SSB start symbol
502 * Function : fillSsbStartSymb
504 * This API stores SSB start index per beam
506 * @param[in] SchCellCb *cellCb
511 void fillSsbStartSymb(SchCellCb *cellCb)
513 uint8_t cnt, scs, symbIdx, ssbStartSymbArr[SCH_MAX_SSB_BEAM];
515 scs = cellCb->cellCfg.ssbSchCfg.scsCommon;
517 memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
519 /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */
524 if(cellCb->cellCfg.dlFreq <= 300000)
525 cnt = 2;/* n = 0, 1 */
527 cnt = 4; /* n = 0, 1, 2, 3 */
528 for(uint8_t idx=0; idx<cnt; idx++)
530 /* start symbol determined using {2, 8} + 14n */
531 ssbStartSymbArr[symbIdx++] = 2 + SCH_SYMBOL_PER_SLOT*idx;
532 ssbStartSymbArr[symbIdx++] = 8 + SCH_SYMBOL_PER_SLOT*idx;
538 if(cellCb->cellCfg.dlFreq <= 300000)
541 cnt = 2; /* n = 0, 1 */
542 for(uint8_t idx=0; idx<cnt; idx++)
544 /* start symbol determined using {4, 8, 16, 20} + 28n */
545 ssbStartSymbArr[symbIdx++] = 4 + SCH_SYMBOL_PER_SLOT*idx;
546 ssbStartSymbArr[symbIdx++] = 8 + SCH_SYMBOL_PER_SLOT*idx;
547 ssbStartSymbArr[symbIdx++] = 16 + SCH_SYMBOL_PER_SLOT*idx;
548 ssbStartSymbArr[symbIdx++] = 20 + SCH_SYMBOL_PER_SLOT*idx;
553 DU_LOG("\nERROR --> SCH : SCS %d is currently not supported", scs);
555 memset(cellCb->ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
556 memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM);
562 * @brief init cellCb based on cellCfg
566 * Function : schInitCellCb
568 * This API is invoked after receiving schCellCfg
570 * @param[in] schCellCb *cell
571 * @param[in] SchCellCfg *schCellCfg
576 uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg)
578 SchCellCb *cell= NULLP;
579 SCH_ALLOC(cell, sizeof(SchCellCb));
582 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb");
586 cell->cellId = schCellCfg->cellId;
587 cell->instIdx = inst;
588 switch(schCellCfg->numerology)
590 case SCH_NUMEROLOGY_0:
592 cell->numSlots = SCH_MU0_NUM_SLOTS;
595 case SCH_NUMEROLOGY_1:
597 cell->numSlots = SCH_MU1_NUM_SLOTS;
600 case SCH_NUMEROLOGY_2:
602 cell->numSlots = SCH_MU2_NUM_SLOTS;
605 case SCH_NUMEROLOGY_3:
607 cell->numSlots = SCH_MU3_NUM_SLOTS;
610 case SCH_NUMEROLOGY_4:
612 cell->numSlots = SCH_MU4_NUM_SLOTS;
616 DU_LOG("\nERROR --> SCH : Numerology %d not supported", schCellCfg->numerology);
619 schInitTddSlotCfg(cell, schCellCfg);
622 SCH_ALLOC(cell->schDlSlotInfo, cell->numSlots * sizeof(SchDlSlotInfo*));
623 if(!cell->schDlSlotInfo)
625 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb for schDlSlotInfo");
629 SCH_ALLOC(cell->schUlSlotInfo, cell->numSlots * sizeof(SchUlSlotInfo*));
630 if(!cell->schUlSlotInfo)
632 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb for schUlSlotInfo");
636 for(uint8_t idx=0; idx<cell->numSlots; idx++)
638 SchDlSlotInfo *schDlSlotInfo;
639 SchUlSlotInfo *schUlSlotInfo;
642 SCH_ALLOC(schDlSlotInfo, sizeof(SchDlSlotInfo));
645 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb");
650 SCH_ALLOC(schUlSlotInfo, sizeof(SchUlSlotInfo));
653 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb");
657 schInitDlSlot(schDlSlotInfo);
658 schInitUlSlot(schUlSlotInfo);
660 cell->schDlSlotInfo[idx] = schDlSlotInfo;
661 cell->schUlSlotInfo[idx] = schUlSlotInfo;
664 cell->firstSsbTransmitted = false;
665 cell->firstSib1Transmitted = false;
666 fillSsbStartSymb(cell);
667 schCb[inst].cells[inst] = cell;
669 DU_LOG("\nINFO --> SCH : Cell init completed for cellId:%d", cell->cellId);
675 * @brief Fill SIB1 configuration
679 * Function : fillSchSib1Cfg
681 * Fill SIB1 configuration
683 * @param[in] uint8_t bandwidth : total available bandwidth
684 * uint8_t numSlots : total slots per SFN
685 * SchSib1Cfg *sib1SchCfg : cfg to be filled
686 * uint16_t pci : physical cell Id
687 * uint8_t offsetPointA : offset
690 void fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA)
692 uint8_t coreset0Idx = 0;
693 uint8_t searchSpace0Idx = 0;
694 //uint8_t ssbMuxPattern = 0;
696 uint8_t numSymbols = 0;
699 //uint8_t numSearchSpacePerSlot = 0;
701 uint8_t firstSymbol = 0; /* need to calculate using formula mentioned in 38.213 */
702 uint8_t slotIndex = 0;
703 /* TODO : This should be filled through freqDomRscAllocType0() */
704 uint8_t FreqDomainResource[6] = {15, 0, 0, 0, 0, 0};
706 uint8_t numPdschSymbols = 11; /* considering pdsch region from symbols 3 to 13 */
709 PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg);
710 PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg);
711 BwpCfg *bwp = &(sib1SchCfg->bwp);
713 coreset0Idx = sib1SchCfg->coresetZeroIndex;
714 searchSpace0Idx = sib1SchCfg->searchSpaceZeroIndex;
716 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
717 //ssbMuxPattern = coresetIdxTable[coreset0Idx][0];
718 numRbs = coresetIdxTable[coreset0Idx][1];
719 numSymbols = coresetIdxTable[coreset0Idx][2];
720 offset = coresetIdxTable[coreset0Idx][3];
722 /* derive the search space params from table 13-11 spec 38.213 */
723 oValue = searchSpaceIdxTable[searchSpace0Idx][0];
724 //numSearchSpacePerSlot = searchSpaceIdxTable[searchSpace0Idx][1];
725 mValue = searchSpaceIdxTable[searchSpace0Idx][2];
726 firstSymbol = searchSpaceIdxTable[searchSpace0Idx][3];
728 /* calculate the n0, need to add the formulae, as of now the value is 0
729 * Need to add the even and odd values of i during configuration
730 * [(O . 2^u + i . M ) ] mod numSlotsPerSubframe
731 * assuming u = 0, i = 0, numSlotsPerSubframe = 10
732 * Also, from this configuration, coreset0 is only on even subframe */
733 slotIndex = (int)((oValue*pow(2, mu)) + floor(ssbIdx*mValue))%numSlots;
734 sib1SchCfg->n0 = slotIndex;
736 /* calculate the PRBs */
737 //freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
742 case BANDWIDTH_20MHZ:
744 bwp->freqAlloc.numPrb = TOTAL_PRB_20MHZ_MU0;
747 case BANDWIDTH_100MHZ:
749 bwp->freqAlloc.numPrb = TOTAL_PRB_100MHZ_MU1;
753 DU_LOG("\nERROR --> SCH : Bandwidth %d not supported", bandwidth);
756 bwp->freqAlloc.startPrb = 0;
757 bwp->subcarrierSpacing = 0; /* 15Khz */
758 bwp->cyclicPrefix = 0; /* normal */
760 /* fill the PDCCH PDU */
761 pdcch->coresetCfg.coreSetSize = numRbs;
762 pdcch->coresetCfg.startSymbolIndex = firstSymbol;
763 pdcch->coresetCfg.durationSymbols = numSymbols;
764 memcpy(pdcch->coresetCfg.freqDomainResource,FreqDomainResource,6);
765 pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
766 pdcch->coresetCfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
767 pdcch->coresetCfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
768 pdcch->coresetCfg.coreSetType = 0;
769 pdcch->coresetCfg.shiftIndex = pci;
770 pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
772 pdcch->dci.rnti = SI_RNTI;
773 pdcch->dci.scramblingId = pci;
774 pdcch->dci.scramblingRnti = 0;
775 pdcch->dci.cceIndex = 0;
776 pdcch->dci.aggregLevel = 4;
777 pdcch->dci.beamPdcchInfo.numPrgs = 1;
778 pdcch->dci.beamPdcchInfo.prgSize = 1;
779 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
780 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
781 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
782 pdcch->dci.txPdcchPower.powerValue = 0;
783 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
784 /* Storing pdschCfg pointer here. Required to access pdsch config while
785 fillig up pdcch pdu */
786 pdcch->dci.pdschCfg = pdsch;
788 /* fill the PDSCH PDU */
790 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
791 pdsch->rnti = 0xFFFF; /* SI-RNTI */
793 pdsch->numCodewords = 1;
794 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
796 pdsch->codeword[cwCount].targetCodeRate = 308;
797 pdsch->codeword[cwCount].qamModOrder = 2;
798 pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs;
799 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
800 pdsch->codeword[cwCount].rvIndex = 0;
801 tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen + TX_PAYLOAD_HDR_LEN);
802 pdsch->codeword[cwCount].tbSize = tbSize;
804 pdsch->dataScramblingId = pci;
805 pdsch->numLayers = 1;
806 pdsch->transmissionScheme = 0;
808 pdsch->dmrs.dlDmrsSymbPos = 4; /* Bitmap value 00000000000100 i.e. using 3rd symbol for PDSCH DMRS */
809 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
810 pdsch->dmrs.dlDmrsScramblingId = pci;
811 pdsch->dmrs.scid = 0;
812 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
813 pdsch->dmrs.dmrsPorts = 0x0001;
814 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Type-A */
815 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
816 pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
818 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
819 pdsch->pdschFreqAlloc.freqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB + 1; /* the RB numbering starts from coreset0,
820 and PDSCH is always above SSB */
821 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols);
822 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
823 pdsch->pdschTimeAlloc.rowIndex = 1;
824 /* This is Intel's requirement. PDSCH should start after PDSCH DRMS symbol */
825 pdsch->pdschTimeAlloc.timeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */
826 pdsch->pdschTimeAlloc.timeAlloc.numSymb = numPdschSymbols;
827 pdsch->beamPdschInfo.numPrgs = 1;
828 pdsch->beamPdschInfo.prgSize = 1;
829 pdsch->beamPdschInfo.digBfInterfaces = 0;
830 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
831 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
832 pdsch->txPdschPower.powerControlOffset = 0;
833 pdsch->txPdschPower.powerControlOffsetSS = 0;
838 * @brief cell config from MAC to SCH.
842 * Function : macSchCellCfgReq
844 * This API is invoked by MAC to send cell config to SCH
846 * @param[in] Pst *pst
847 * @param[in] SchCellCfg *schCellCfg
852 uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg)
856 SchCellCfgCfm schCellCfgCfm;
858 Inst inst = pst->dstInst-1;
859 SchPdschConfig pdschCfg;
861 #ifdef CALL_FLOW_DEBUG_LOG
862 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_SCH_CELL_CFG\n");
865 schInitCellCb(inst, schCellCfg);
866 cellCb = schCb[inst].cells[inst]; //cells is of MAX_CELLS, why inst
867 cellCb->macInst = pst->srcInst;
869 /* derive the SIB1 config parameters */
870 fillSchSib1Cfg(schCellCfg->numerology, schCellCfg->bandwidth, cellCb->numSlots,
871 &(schCellCfg->sib1SchCfg), schCellCfg->phyCellId,
872 schCellCfg->ssbSchCfg.ssbOffsetPointA);
873 memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg));
875 /* Fill K0 - K1 table for common cfg*/
876 BuildK0K1Table(cellCb, &cellCb->cellCfg.schInitialDlBwp.k0K1InfoTbl, true, cellCb->cellCfg.schInitialDlBwp.pdschCommon,
877 pdschCfg, DEFAULT_UL_ACK_LIST_COUNT, defaultUlAckTbl);
879 BuildK2InfoTable(cellCb, cellCb->cellCfg.schInitialUlBwp.puschCommon.timeDomRsrcAllocList,\
880 cellCb->cellCfg.schInitialUlBwp.puschCommon.numTimeDomRsrcAlloc, &cellCb->cellCfg.schInitialUlBwp.msg3K2InfoTbl, \
881 &cellCb->cellCfg.schInitialUlBwp.k2InfoTbl);
882 /* Initializing global variables */
883 cellCb->actvUeBitMap = 0;
884 cellCb->boIndBitMap = 0;
886 /* Fill and send Cell config confirm */
887 memset(&rspPst, 0, sizeof(Pst));
888 FILL_PST_SCH_TO_MAC(rspPst, pst->dstInst);
889 rspPst.event = EVENT_SCH_CELL_CFG_CFM;
891 schCellCfgCfm.cellId = schCellCfg->cellId;
892 schCellCfgCfm.rsp = RSP_OK;
894 ret = (*SchCellCfgCfmOpts[rspPst.selector])(&rspPst, &schCellCfgCfm);
899 /*******************************************************************
901 * @brief Processes DL RLC BO info from MAC
905 * Function : MacSchDlRlcBoInfo
908 * Processes DL RLC BO info from MAC
911 * @return ROK - success
914 * ****************************************************************/
915 uint8_t MacSchDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo)
921 uint16_t slotIdx = 0;
923 SchUeCb *ueCb = NULLP;
924 SchCellCb *cell = NULLP;
925 SchDlSlotInfo *schDlSlotInfo = NULLP;
926 Inst inst = pst->dstInst-SCH_INST_START;
928 #ifdef CALL_FLOW_DEBUG_LOG
929 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_DL_RLC_BO_INFO_TO_SCH\n");
932 DU_LOG("\nDEBUG --> SCH : Received RLC BO Status indication");
933 cell = schCb[inst].cells[inst];
937 DU_LOG("\nERROR --> SCH : MacSchDlRlcBoInfo(): Cell does not exists");
941 GET_UE_IDX(dlBoInfo->crnti, ueIdx);
942 ueCb = &cell->ueCb[ueIdx-1];
943 lcId = dlBoInfo->lcId;
945 if(lcId == SRB1_LCID || lcId == SRB2_LCID || lcId == SRB3_LCID || \
946 (lcId >= MIN_DRB_LCID && lcId <= MAX_DRB_LCID))
948 SET_ONE_BIT(ueIdx, cell->boIndBitMap);
949 ueCb->dlInfo.dlLcCtxt[lcId].bo = dlBoInfo->dataVolume;
951 else if(lcId != SRB0_LCID)
953 DU_LOG("\nERROR --> SCH : Invalid LC Id %d in MacSchDlRlcBoInfo", lcId);
957 slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA_DL + BO_DELTA) % cell->numSlots;
959 while(schGetSlotSymbFrmt(cell->slotFrmtBitMap, slot) != DL_SLOT)
961 slot = (slot + 1)%cell->numSlots;
963 if(slotIdx==cell->numSlots)
965 DU_LOG("\nERROR --> SCH : No DL Slot available");
971 schDlSlotInfo = cell->schDlSlotInfo[slot];
973 if(schDlSlotInfo == NULLP)
975 DU_LOG("\nERROR --> SCH : MacSchDlRlcBoInfo(): schDlSlotInfo does not exists");
978 SCH_ALLOC(schDlSlotInfo->dlMsgInfo, sizeof(DlMsgInfo));
979 if(schDlSlotInfo->dlMsgInfo == NULLP)
981 DU_LOG("\nERROR --> SCH : Memory allocation failed for dlMsgInfo");
982 schDlSlotInfo = NULL;
986 schDlSlotInfo->dlMsgInfo->crnti = dlBoInfo->crnti;
987 schDlSlotInfo->dlMsgInfo->ndi = 1;
988 schDlSlotInfo->dlMsgInfo->harqProcNum = 0;
989 schDlSlotInfo->dlMsgInfo->dlAssignIdx = 0;
990 schDlSlotInfo->dlMsgInfo->pucchTpc = 0;
991 schDlSlotInfo->dlMsgInfo->pucchResInd = 0;
992 schDlSlotInfo->dlMsgInfo->harqFeedbackInd = 0;
993 schDlSlotInfo->dlMsgInfo->dciFormatId = 1;
994 if(lcId == SRB0_LCID)
996 schDlSlotInfo->dlMsgInfo->isMsg4Pdu = true;
997 schDlSlotInfo->dlMsgInfo->dlMsgPduLen = dlBoInfo->dataVolume;
1002 /*******************************************************************
1004 * @brief Processes BSR indiation from MAC
1008 * Function : MacSchBsr
1011 * Processes DL BSR from MAC
1013 * @params[in] Pst pst
1014 * UlBufferStatusRptInd bsrInd
1015 * @return ROK - success
1018 * ****************************************************************/
1019 uint8_t MacSchBsr(Pst *pst, UlBufferStatusRptInd *bsrInd)
1021 Inst schInst = pst->dstInst-SCH_INST_START;
1022 SchCellCb *cellCb = NULLP;
1023 SchUeCb *ueCb = NULLP;
1026 #ifdef CALL_FLOW_DEBUG_LOG
1027 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_SHORT_BSR\n");
1030 DU_LOG("\nDEBUG --> SCH : Received BSR");
1031 cellCb = schCb[schInst].cells[schInst];
1032 ueCb = schGetUeCb(cellCb, bsrInd->crnti);
1034 /* store dataVolume per lcg in uecb */
1035 for(lcgIdx = 0; lcgIdx < bsrInd->numLcg; lcgIdx++)
1037 ueCb->bsrInfo[lcgIdx].priority = 1; //TODO: determining LCG priority?
1038 ueCb->bsrInfo[lcgIdx].dataVol = bsrInd->dataVolInfo[lcgIdx].dataVol;
1043 /*******************************************************************
1045 * @brief Processes SR UCI indication from MAC
1049 * Function : MacSchSrUciInd
1052 * Processes SR UCI indication from MAC
1054 * @params[in] Post structure
1056 * @return ROK - success
1059 * ****************************************************************/
1060 uint8_t MacSchSrUciInd(Pst *pst, SrUciIndInfo *uciInd)
1062 Inst inst = pst->dstInst-SCH_INST_START;
1065 SchCellCb *cellCb = schCb[inst].cells[inst];
1067 #ifdef CALL_FLOW_DEBUG_LOG
1068 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_UCI_IND_TO_SCH\n");
1071 DU_LOG("\nDEBUG --> SCH : Received SR");
1073 ueCb = schGetUeCb(cellCb, uciInd->crnti);
1075 if(uciInd->numSrBits)
1077 ueCb->srRcvd = true;
1081 /**********************************************************************
1083 **********************************************************************/