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3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
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17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for scheduler fucntions
29 **********************************************************************/
32 @brief This file implements the schedulers main access to MAC layer code.
34 #include "common_def.h"
35 #include "du_app_mac_inf.h"
40 #include "rg_sch_inf.h"
43 #include "tfu.x" /* TFU types */
44 #include "lrg.x" /* layer management typedefs for MAC */
45 #include "rgr.x" /* layer management typedefs for MAC */
46 #include "rg_sch_inf.x" /* typedefs for Scheduler */
47 #include "mac_sch_interface.h"
49 #include "sch_utils.h"
51 void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
54 SchCellCfgCfmFunc SchCellCfgCfmOpts[] =
56 packSchCellCfgCfm, /* LC */
57 MacProcSchCellCfgCfm, /* TC */
58 packSchCellCfgCfm /* LWLC */
63 * @brief Task Initiation function.
67 * Function : schActvInit
69 * This function is supplied as one of parameters during MAC's
70 * task registration. MAC will invoke this function once, after
71 * it creates and attaches this TAPA Task to a system task.
73 * @param[in] Ent Entity, the entity ID of this task.
74 * @param[in] Inst Inst, the instance ID of this task.
75 * @param[in] Region Region, the region ID registered for memory
77 * @param[in] Reason Reason.
81 uint8_t schActvInit(Ent entity, Inst instId, Region region, Reason reason)
83 Inst inst = (instId - SCH_INST_START);
85 /* Initialize the MAC TskInit structure to zero */
86 memset ((uint8_t *)&schCb[inst], 0, sizeof(schCb));
88 /* Initialize the MAC TskInit with received values */
89 schCb[inst].schInit.ent = entity;
90 schCb[inst].schInit.inst = inst;
91 schCb[inst].schInit.region = region;
92 schCb[inst].schInit.pool = 0;
93 schCb[inst].schInit.reason = reason;
94 schCb[inst].schInit.cfgDone = FALSE;
95 schCb[inst].schInit.acnt = FALSE;
96 schCb[inst].schInit.usta = FALSE;
97 schCb[inst].schInit.trc = FALSE;
98 schCb[inst].schInit.procId = ODU_GET_PROCID();
104 * @brief Scheduler instance Configuration Handler.
108 * Function : SchInstCfg
110 * This function in called by SchProcGenCfgReq(). It handles the
111 * general configurations of the scheduler instance. Returns
112 * reason for success/failure of this function.
114 * @param[in] RgCfg *cfg, the Configuaration information
116 * -# LCM_REASON_NOT_APPL
117 * -# LCM_REASON_INVALID_MSGTYPE
118 * -# LCM_REASON_MEM_NOAVAIL
120 uint8_t SchInstCfg(RgCfg *cfg, Inst dInst)
122 uint16_t ret = LCM_REASON_NOT_APPL;
123 Inst inst = (dInst - SCH_INST_START);
125 DU_LOG("\nDEBUG --> SCH : Entered SchInstCfg()");
126 /* Check if Instance Configuration is done already */
127 if (schCb[inst].schInit.cfgDone == TRUE)
129 return LCM_REASON_INVALID_MSGTYPE;
131 /* Update the Pst structure for LM interface */
132 memcpy(&schCb[inst].schInit.lmPst,
133 &cfg->s.schInstCfg.genCfg.lmPst,
136 schCb[inst].schInit.inst = inst;
137 schCb[inst].schInit.lmPst.srcProcId = schCb[inst].schInit.procId;
138 schCb[inst].schInit.lmPst.srcEnt = schCb[inst].schInit.ent;
139 schCb[inst].schInit.lmPst.srcInst = schCb[inst].schInit.inst +
141 schCb[inst].schInit.lmPst.event = EVTNONE;
143 schCb[inst].schInit.region = cfg->s.schInstCfg.genCfg.mem.region;
144 schCb[inst].schInit.pool = cfg->s.schInstCfg.genCfg.mem.pool;
145 schCb[inst].genCfg.tmrRes = cfg->s.schInstCfg.genCfg.tmrRes;
147 schCb[inst].genCfg.forceCntrlSrbBoOnPCel = cfg->s.schInstCfg.genCfg.forceCntrlSrbBoOnPCel;
148 schCb[inst].genCfg.isSCellActDeactAlgoEnable = cfg->s.schInstCfg.genCfg.isSCellActDeactAlgoEnable;
150 schCb[inst].genCfg.startCellId = cfg->s.schInstCfg.genCfg.startCellId;
152 /* Initialzie the timer queue */
153 memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType) * SCH_TQ_SIZE);
154 /* Initialize the timer control point */
155 memset(&schCb[inst].tmrTqCp, 0, sizeof(CmTqCp));
156 schCb[inst].tmrTqCp.tmrLen = RGSCH_TQ_SIZE;
158 /* SS_MT_TMR needs to be enabled as schActvTmr needs instance information */
159 /* Timer Registration request to system services */
160 if (ODU_REG_TMR_MT(schCb[inst].schInit.ent, dInst,
161 (int)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK)
163 DU_LOG("\nERROR --> SCH : SchInstCfg(): Failed to "
165 return (LCM_REASON_MEM_NOAVAIL);
168 /* Set Config done in TskInit */
169 schCb[inst].schInit.cfgDone = TRUE;
170 DU_LOG("\nINFO --> SCH : Scheduler gen config done");
176 * @brief Layer Manager Configuration request handler.
180 * Function : SchProcGenCfgReq
182 * This function handles the configuration
183 * request received at scheduler instance from the Layer Manager.
184 * -# Based on the cfg->hdr.elmId.elmnt value it invokes one of the
185 * functions rgHdlGenCfg() or rgHdlSapCfg().
186 * -# Invokes RgMiLrgSchCfgCfm() to send back the confirmation to the LM.
188 * @param[in] Pst *pst, the post structure
189 * @param[in] RgMngmt *cfg, the configuration parameter's structure
193 uint8_t SchProcGenCfgReq(Pst *pst, RgMngmt *cfg)
195 uint8_t ret = LCM_PRIM_OK;
196 uint16_t reason = LCM_REASON_NOT_APPL;
200 #ifdef CALL_FLOW_DEBUG_LOG
201 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : GENERAL_CFG_REQ\n");
204 if(pst->dstInst < SCH_INST_START)
206 DU_LOG("\nERROR --> SCH : Invalid inst ID");
207 DU_LOG("\nERROR --> SCH : SchProcGenCfgReq(): "
208 "pst->dstInst=%d SCH_INST_START=%d", pst->dstInst,SCH_INST_START);
211 DU_LOG("\nINFO --> SCH : Received scheduler gen config");
212 /* Fill the post structure for sending the confirmation */
213 memset(&cfmPst, 0 , sizeof(Pst));
214 SchFillCfmPst(pst, &cfmPst, cfg);
216 memset(&cfm, 0, sizeof(RgMngmt));
223 cfm.hdr.elmId.elmnt = cfg->hdr.elmId.elmnt;
224 switch(cfg->hdr.elmId.elmnt)
227 reason = SchInstCfg(&cfg->t.cfg,pst->dstInst );
231 reason = LCM_REASON_INVALID_ELMNT;
232 DU_LOG("\nERROR --> SCH : Invalid Elmnt=%d", cfg->hdr.elmId.elmnt);
236 if (reason != LCM_REASON_NOT_APPL)
241 cfm.cfm.status = ret;
242 cfm.cfm.reason = reason;
244 SchSendCfgCfm(&cfmPst, &cfm);
245 /* SCH_FREE(pst->region, pst->pool, (Data *)cfg, sizeof(RgMngmt)); */
248 }/*-- SchProcGenCfgReq --*/
251 * @brief slot indication from MAC to SCH.
255 * Function : MacSchSlotInd
257 * This API is invoked by PHY to indicate slot indication to Scheduler for
260 * @param[in] Pst *pst
261 * @param[in] SlotTimingInfo *slotInd
266 uint8_t MacSchSlotInd(Pst *pst, SlotTimingInfo *slotInd)
268 Inst inst = pst->dstInst-SCH_INST_START;
270 #ifdef CALL_FLOW_DEBUG_LOG
271 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_SLOT_IND_TO_SCH\n");
274 schProcessSlotInd(slotInd, inst);
277 } /* MacSchSlotInd */
279 /*******************************************************************
281 * @brief Processes Rach indication from MAC
285 * Function : MacSchRachInd
288 * Processes Rach indication from MAC
291 * @return ROK - success
294 * ****************************************************************/
295 uint8_t MacSchRachInd(Pst *pst, RachIndInfo *rachInd)
297 Inst inst = pst->dstInst-SCH_INST_START;
299 #ifdef CALL_FLOW_DEBUG_LOG
300 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_RACH_IND_TO_SCH\n");
303 DU_LOG("\nINFO --> SCH : Received Rach indication");
304 schProcessRachInd(rachInd, inst);
308 /*******************************************************************
310 * @brief Processes CRC indication from MAC
314 * Function : MacSchCrcInd
317 * Processes CRC indication from MAC
319 * @params[in] Post structure
321 * @return ROK - success
324 * ****************************************************************/
325 uint8_t MacSchCrcInd(Pst *pst, CrcIndInfo *crcInd)
327 #ifdef CALL_FLOW_DEBUG_LOG
328 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_CRC_IND_TO_SCH\n");
331 switch(crcInd->crcInd[0])
334 DU_LOG("\nDEBUG --> SCH : Received CRC indication. CRC Status [FAILURE]");
337 DU_LOG("\nDEBUG --> SCH : Received CRC indication. CRC Status [PASS]");
340 DU_LOG("\nDEBUG --> SCH : Invalid CRC state %d", crcInd->crcInd[0]);
348 *@brief Returns TDD periodicity in micro seconds
352 * Function : schGetPeriodicityInMsec
354 * This API retunrs TDD periodicity in micro seconds
356 * @param[in] DlUlTxPeriodicity
357 * @return periodicityInMsec
360 uint16_t schGetPeriodicityInMsec(DlUlTxPeriodicity tddPeriod)
362 uint16_t periodicityInMsec = 0;
365 case TX_PRDCTY_MS_0P5:
367 periodicityInMsec = 500;
370 case TX_PRDCTY_MS_0P625:
372 periodicityInMsec = 625;
377 periodicityInMsec = 1000;
380 case TX_PRDCTY_MS_1P25:
382 periodicityInMsec = 1250;
387 periodicityInMsec = 2000;
390 case TX_PRDCTY_MS_2P5:
392 periodicityInMsec = 2500;
397 periodicityInMsec = 5000;
400 case TX_PRDCTY_MS_10:
402 periodicityInMsec = 10000;
407 DU_LOG("\nERROR --> SCH : Invalid DlUlTxPeriodicity:%d", tddPeriod);
411 return periodicityInMsec;
416 * @brief init TDD slot config
420 * Function : schInitTddSlotCfg
422 * This API is invoked after receiving schCellCfg
424 * @param[in] schCellCb *cell
425 * @param[in] SchCellCfg *schCellCfg
428 void schInitTddSlotCfg(SchCellCb *cell, SchCellCfg *schCellCfg)
430 uint16_t periodicityInMicroSec = 0;
431 int8_t slotIdx, symbIdx;
433 periodicityInMicroSec = schGetPeriodicityInMsec(schCellCfg->tddCfg.tddPeriod);
434 cell->numSlotsInPeriodicity = (periodicityInMicroSec * pow(2, schCellCfg->numerology))/1000;
435 cell->slotFrmtBitMap = 0;
436 cell->symbFrmtBitMap = 0;
437 for(slotIdx = cell->numSlotsInPeriodicity-1; slotIdx >= 0; slotIdx--)
440 /* If the first and last symbol are the same, the entire slot is the same type */
441 if((schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx] == schCellCfg->tddCfg.slotCfg[slotIdx][MAX_SYMB_PER_SLOT-1]) &&
442 schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx] != FLEXI_SLOT)
444 switch(schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx])
448 /*BitMap to be set to 00 */
449 cell->slotFrmtBitMap = (cell->slotFrmtBitMap<<2);
454 /*BitMap to be set to 01 */
455 cell->slotFrmtBitMap = ((cell->slotFrmtBitMap<<2) | (UL_SLOT));
459 DU_LOG("\nERROR --> SCH : Invalid slot Config in schInitTddSlotCfg");
463 /* slot config is flexible. First set slotBitMap to 10 */
464 cell->slotFrmtBitMap = ((cell->slotFrmtBitMap<<2) | (FLEXI_SLOT));
466 /* Now set symbol bitmap */
467 for(symbIdx = MAX_SYMB_PER_SLOT-1; symbIdx >= 0; symbIdx--)
469 switch(schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx])
473 /*symbol BitMap to be set to 00 */
474 cell->symbFrmtBitMap = (cell->symbFrmtBitMap<<2);
479 /*symbol BitMap to be set to 01 */
480 cell->symbFrmtBitMap = ((cell->symbFrmtBitMap<<2) | (UL_SLOT));
485 /*symbol BitMap to be set to 10 */
486 cell->symbFrmtBitMap = ((cell->symbFrmtBitMap<<2) | (FLEXI_SLOT));
490 DU_LOG("\nERROR --> SCH : Invalid slot Config in schInitTddSlotCfg");
498 * @brief Fill SSB start symbol
502 * Function : fillSsbStartSymb
504 * This API stores SSB start index per beam
506 * @param[in] SchCellCb *cellCb
511 void fillSsbStartSymb(SchCellCb *cellCb)
513 uint8_t cnt, scs, symbIdx, ssbStartSymbArr[SCH_MAX_SSB_BEAM];
515 scs = cellCb->cellCfg.ssbSchCfg.scsCommon;
517 memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
519 /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */
524 if(cellCb->cellCfg.dlFreq <= 300000)
525 cnt = 2;/* n = 0, 1 */
527 cnt = 4; /* n = 0, 1, 2, 3 */
528 for(uint8_t idx=0; idx<cnt; idx++)
530 /* start symbol determined using {2, 8} + 14n */
531 ssbStartSymbArr[symbIdx++] = 2 + MAX_SYMB_PER_SLOT*idx;
532 ssbStartSymbArr[symbIdx++] = 8 + MAX_SYMB_PER_SLOT*idx;
538 if(cellCb->cellCfg.dlFreq <= 300000)
541 cnt = 2; /* n = 0, 1 */
542 for(uint8_t idx=0; idx<cnt; idx++)
544 /* start symbol determined using {4, 8, 16, 20} + 28n */
545 ssbStartSymbArr[symbIdx++] = 4 + MAX_SYMB_PER_SLOT*idx;
546 ssbStartSymbArr[symbIdx++] = 8 + MAX_SYMB_PER_SLOT*idx;
547 ssbStartSymbArr[symbIdx++] = 16 + MAX_SYMB_PER_SLOT*idx;
548 ssbStartSymbArr[symbIdx++] = 20 + MAX_SYMB_PER_SLOT*idx;
553 DU_LOG("\nERROR --> SCH : SCS %d is currently not supported", scs);
555 memset(cellCb->ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
556 memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM);
562 * @brief init cellCb based on cellCfg
566 * Function : schInitCellCb
568 * This API is invoked after receiving schCellCfg
570 * @param[in] schCellCb *cell
571 * @param[in] SchCellCfg *schCellCfg
576 uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg)
578 SchCellCb *cell= NULLP;
579 SCH_ALLOC(cell, sizeof(SchCellCb));
582 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb");
586 cell->cellId = schCellCfg->cellId;
587 cell->instIdx = inst;
588 switch(schCellCfg->numerology)
590 case SCH_NUMEROLOGY_0:
592 cell->numSlots = SCH_MU0_NUM_SLOTS;
595 case SCH_NUMEROLOGY_1:
597 cell->numSlots = SCH_MU1_NUM_SLOTS;
600 case SCH_NUMEROLOGY_2:
602 cell->numSlots = SCH_MU2_NUM_SLOTS;
605 case SCH_NUMEROLOGY_3:
607 cell->numSlots = SCH_MU3_NUM_SLOTS;
610 case SCH_NUMEROLOGY_4:
612 cell->numSlots = SCH_MU4_NUM_SLOTS;
616 DU_LOG("\nERROR --> SCH : Numerology %d not supported", schCellCfg->numerology);
619 schInitTddSlotCfg(cell, schCellCfg);
622 SCH_ALLOC(cell->schDlSlotInfo, cell->numSlots * sizeof(SchDlSlotInfo*));
623 if(!cell->schDlSlotInfo)
625 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb for schDlSlotInfo");
629 SCH_ALLOC(cell->schUlSlotInfo, cell->numSlots * sizeof(SchUlSlotInfo*));
630 if(!cell->schUlSlotInfo)
632 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb for schUlSlotInfo");
636 for(uint8_t idx=0; idx<cell->numSlots; idx++)
638 SchDlSlotInfo *schDlSlotInfo;
639 SchUlSlotInfo *schUlSlotInfo;
642 SCH_ALLOC(schDlSlotInfo, sizeof(SchDlSlotInfo));
645 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb");
650 SCH_ALLOC(schUlSlotInfo, sizeof(SchUlSlotInfo));
653 DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb");
657 schInitDlSlot(schDlSlotInfo);
658 schInitUlSlot(schUlSlotInfo);
660 cell->schDlSlotInfo[idx] = schDlSlotInfo;
661 cell->schUlSlotInfo[idx] = schUlSlotInfo;
664 cell->firstSsbTransmitted = false;
665 cell->firstSib1Transmitted = false;
666 fillSsbStartSymb(cell);
667 schCb[inst].cells[inst] = cell;
669 DU_LOG("\nINFO --> SCH : Cell init completed for cellId:%d", cell->cellId);
675 * @brief Fill SIB1 configuration
679 * Function : fillSchSib1Cfg
681 * Fill SIB1 configuration
683 * @param[in] uint8_t bandwidth : total available bandwidth
684 * uint8_t numSlots : total slots per SFN
685 * SchSib1Cfg *sib1SchCfg : cfg to be filled
686 * uint16_t pci : physical cell Id
687 * uint8_t offsetPointA : offset
690 void fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA)
692 uint8_t coreset0Idx = 0;
693 uint8_t searchSpace0Idx = 0;
694 //uint8_t ssbMuxPattern = 0;
696 uint8_t numSymbols = 0;
699 //uint8_t numSearchSpacePerSlot = 0;
701 uint8_t firstSymbol = 0; /* need to calculate using formula mentioned in 38.213 */
702 uint8_t slotIndex = 0;
703 uint8_t FreqDomainResource[FREQ_DOM_RSRC_SIZE] = {0};
707 PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg);
708 PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg);
709 BwpCfg *bwp = &(sib1SchCfg->bwp);
711 coreset0Idx = sib1SchCfg->coresetZeroIndex;
712 searchSpace0Idx = sib1SchCfg->searchSpaceZeroIndex;
714 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
715 //ssbMuxPattern = coresetIdxTable[coreset0Idx][0];
716 numRbs = coresetIdxTable[coreset0Idx][1];
717 numSymbols = coresetIdxTable[coreset0Idx][2];
718 offset = coresetIdxTable[coreset0Idx][3];
720 /* derive the search space params from table 13-11 spec 38.213 */
721 oValue = searchSpaceIdxTable[searchSpace0Idx][0];
722 //numSearchSpacePerSlot = searchSpaceIdxTable[searchSpace0Idx][1];
723 mValue = searchSpaceIdxTable[searchSpace0Idx][2];
724 firstSymbol = searchSpaceIdxTable[searchSpace0Idx][3];
726 /* calculate the n0, need to add the formulae, as of now the value is 0
727 * Need to add the even and odd values of i during configuration
728 * [(O . 2^u + i . M ) ] mod numSlotsPerSubframe
729 * assuming u = 0, i = 0, numSlotsPerSubframe = 10
730 * Also, from this configuration, coreset0 is only on even subframe */
731 slotIndex = (int)((oValue*pow(2, mu)) + floor(ssbIdx*mValue))%numSlots;
732 sib1SchCfg->n0 = slotIndex;
737 case BANDWIDTH_20MHZ:
739 bwp->freqAlloc.numPrb = TOTAL_PRB_20MHZ_MU0;
742 case BANDWIDTH_100MHZ:
744 bwp->freqAlloc.numPrb = TOTAL_PRB_100MHZ_MU1;
748 DU_LOG("\nERROR --> SCH : Bandwidth %d not supported", bandwidth);
751 bwp->freqAlloc.startPrb = 0;
752 bwp->subcarrierSpacing = 0; /* 15Khz */
753 bwp->cyclicPrefix = 0; /* normal */
755 /* fill the PDCCH PDU */
756 pdcch->coresetCfg.coreSetSize = numRbs;
757 pdcch->coresetCfg.startSymbolIndex = firstSymbol;
758 pdcch->coresetCfg.durationSymbols = numSymbols;
760 /* Fill Bitmap for PRBs in coreset */
761 fillCoresetFeqDomAllocMap(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
762 covertFreqDomRsrcMapToIAPIFormat(FreqDomainResource, pdcch->coresetCfg.freqDomainResource);
764 pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
765 pdcch->coresetCfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
766 pdcch->coresetCfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
767 pdcch->coresetCfg.coreSetType = 0;
768 pdcch->coresetCfg.shiftIndex = pci;
769 pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
771 pdcch->dci.rnti = SI_RNTI;
772 pdcch->dci.scramblingId = pci;
773 pdcch->dci.scramblingRnti = 0;
774 pdcch->dci.cceIndex = 0;
775 pdcch->dci.aggregLevel = 4;
776 pdcch->dci.beamPdcchInfo.numPrgs = 1;
777 pdcch->dci.beamPdcchInfo.prgSize = 1;
778 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
779 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
780 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
781 pdcch->dci.txPdcchPower.powerValue = 0;
782 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
783 /* Storing pdschCfg pointer here. Required to access pdsch config while
784 fillig up pdcch pdu */
785 pdcch->dci.pdschCfg = pdsch;
787 /* fill the PDSCH PDU */
789 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
790 pdsch->rnti = 0xFFFF; /* SI-RNTI */
792 pdsch->numCodewords = 1;
793 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
795 pdsch->codeword[cwCount].targetCodeRate = 308;
796 pdsch->codeword[cwCount].qamModOrder = 2;
797 pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs;
798 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
799 pdsch->codeword[cwCount].rvIndex = 0;
800 tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen + TX_PAYLOAD_HDR_LEN);
801 pdsch->codeword[cwCount].tbSize = tbSize;
803 pdsch->dataScramblingId = pci;
804 pdsch->numLayers = 1;
805 pdsch->transmissionScheme = 0;
807 pdsch->dmrs.dlDmrsSymbPos = 4; /* Bitmap value 00000000000100 i.e. using 3rd symbol for PDSCH DMRS */
808 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
809 pdsch->dmrs.dlDmrsScramblingId = pci;
810 pdsch->dmrs.scid = 0;
811 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
812 pdsch->dmrs.dmrsPorts = 0x0001;
813 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Type-A */
814 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
815 pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
817 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
818 /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
819 pdsch->pdschFreqAlloc.freqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB;
820 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs, NUM_PDSCH_SYMBOL);
821 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
822 pdsch->pdschTimeAlloc.rowIndex = 1;
823 /* This is Intel's requirement. PDSCH should start after PDSCH DRMS symbol */
824 pdsch->pdschTimeAlloc.timeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */
825 pdsch->pdschTimeAlloc.timeAlloc.numSymb = NUM_PDSCH_SYMBOL;
826 pdsch->beamPdschInfo.numPrgs = 1;
827 pdsch->beamPdschInfo.prgSize = 1;
828 pdsch->beamPdschInfo.digBfInterfaces = 0;
829 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
830 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
831 pdsch->txPdschPower.powerControlOffset = 0;
832 pdsch->txPdschPower.powerControlOffsetSS = 0;
837 * @brief cell config from MAC to SCH.
841 * Function : macSchCellCfgReq
843 * This API is invoked by MAC to send cell config to SCH
845 * @param[in] Pst *pst
846 * @param[in] SchCellCfg *schCellCfg
851 uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg)
855 SchCellCfgCfm schCellCfgCfm;
857 Inst inst = pst->dstInst-1;
858 uint8_t coreset0Idx = 0;
861 uint8_t freqDomainResource[FREQ_DOM_RSRC_SIZE] = {0};
862 SchPdschConfig pdschCfg;
864 #ifdef CALL_FLOW_DEBUG_LOG
865 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_SCH_CELL_CFG\n");
868 schInitCellCb(inst, schCellCfg);
869 cellCb = schCb[inst].cells[inst]; //cells is of MAX_CELLS, why inst
870 cellCb->macInst = pst->srcInst;
872 /* derive the SIB1 config parameters */
873 fillSchSib1Cfg(schCellCfg->numerology, schCellCfg->bandwidth, cellCb->numSlots,
874 &(schCellCfg->sib1SchCfg), schCellCfg->phyCellId,
875 schCellCfg->ssbSchCfg.ssbOffsetPointA);
876 memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg));
878 /* Fill coreset frequencyDomainResource bitmap */
879 coreset0Idx = cellCb->cellCfg.schInitialDlBwp.pdcchCommon.commonSearchSpace.coresetId;
880 numRbs = coresetIdxTable[coreset0Idx][1];
881 offset = coresetIdxTable[coreset0Idx][3];
882 fillCoresetFeqDomAllocMap(((cellCb->cellCfg.ssbSchCfg.ssbOffsetPointA - offset)/6), (numRbs/6), freqDomainResource);
883 covertFreqDomRsrcMapToIAPIFormat(freqDomainResource, \
884 cellCb->cellCfg.schInitialDlBwp.pdcchCommon.commonSearchSpace.freqDomainRsrc);
886 /* Fill K0 - K1 table for common cfg*/
887 BuildK0K1Table(cellCb, &cellCb->cellCfg.schInitialDlBwp.k0K1InfoTbl, true, cellCb->cellCfg.schInitialDlBwp.pdschCommon,
888 pdschCfg, DEFAULT_UL_ACK_LIST_COUNT, defaultUlAckTbl);
890 BuildK2InfoTable(cellCb, cellCb->cellCfg.schInitialUlBwp.puschCommon.timeDomRsrcAllocList,\
891 cellCb->cellCfg.schInitialUlBwp.puschCommon.numTimeDomRsrcAlloc, &cellCb->cellCfg.schInitialUlBwp.msg3K2InfoTbl, \
892 &cellCb->cellCfg.schInitialUlBwp.k2InfoTbl);
893 /* Initializing global variables */
894 cellCb->actvUeBitMap = 0;
895 cellCb->boIndBitMap = 0;
897 /* Fill and send Cell config confirm */
898 memset(&rspPst, 0, sizeof(Pst));
899 FILL_PST_SCH_TO_MAC(rspPst, pst->dstInst);
900 rspPst.event = EVENT_SCH_CELL_CFG_CFM;
902 schCellCfgCfm.cellId = schCellCfg->cellId;
903 schCellCfgCfm.rsp = RSP_OK;
905 ret = (*SchCellCfgCfmOpts[rspPst.selector])(&rspPst, &schCellCfgCfm);
910 /*******************************************************************
912 * @brief Processes DL RLC BO info from MAC
916 * Function : MacSchDlRlcBoInfo
919 * Processes DL RLC BO info from MAC
922 * @return ROK - success
925 * ****************************************************************/
926 uint8_t MacSchDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo)
932 uint16_t slotIdx = 0;
934 SchUeCb *ueCb = NULLP;
935 SchCellCb *cell = NULLP;
936 SchDlSlotInfo *schDlSlotInfo = NULLP;
937 Inst inst = pst->dstInst-SCH_INST_START;
939 #ifdef CALL_FLOW_DEBUG_LOG
940 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_DL_RLC_BO_INFO_TO_SCH\n");
943 DU_LOG("\nDEBUG --> SCH : Received RLC BO Status indication");
944 cell = schCb[inst].cells[inst];
948 DU_LOG("\nERROR --> SCH : MacSchDlRlcBoInfo(): Cell does not exists");
952 GET_UE_IDX(dlBoInfo->crnti, ueIdx);
953 ueCb = &cell->ueCb[ueIdx-1];
954 lcId = dlBoInfo->lcId;
956 if(lcId == SRB1_LCID || lcId == SRB2_LCID || lcId == SRB3_LCID || \
957 (lcId >= MIN_DRB_LCID && lcId <= MAX_DRB_LCID))
959 SET_ONE_BIT(ueIdx, cell->boIndBitMap);
960 ueCb->dlInfo.dlLcCtxt[lcId].bo = dlBoInfo->dataVolume;
962 else if(lcId != SRB0_LCID)
964 DU_LOG("\nERROR --> SCH : Invalid LC Id %d in MacSchDlRlcBoInfo", lcId);
968 slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA_DL + BO_DELTA) % cell->numSlots;
970 while(schGetSlotSymbFrmt(cell->slotFrmtBitMap, slot) != DL_SLOT)
972 slot = (slot + 1)%cell->numSlots;
974 if(slotIdx==cell->numSlots)
976 DU_LOG("\nERROR --> SCH : No DL Slot available");
982 schDlSlotInfo = cell->schDlSlotInfo[slot];
984 if(schDlSlotInfo == NULLP)
986 DU_LOG("\nERROR --> SCH : MacSchDlRlcBoInfo(): schDlSlotInfo does not exists");
989 SCH_ALLOC(schDlSlotInfo->dlMsgInfo, sizeof(DlMsgInfo));
990 if(schDlSlotInfo->dlMsgInfo == NULLP)
992 DU_LOG("\nERROR --> SCH : Memory allocation failed for dlMsgInfo");
993 schDlSlotInfo = NULL;
997 schDlSlotInfo->dlMsgInfo->crnti = dlBoInfo->crnti;
998 schDlSlotInfo->dlMsgInfo->ndi = 1;
999 schDlSlotInfo->dlMsgInfo->harqProcNum = 0;
1000 schDlSlotInfo->dlMsgInfo->dlAssignIdx = 0;
1001 schDlSlotInfo->dlMsgInfo->pucchTpc = 0;
1002 schDlSlotInfo->dlMsgInfo->pucchResInd = 0;
1003 schDlSlotInfo->dlMsgInfo->harqFeedbackInd = 0;
1004 schDlSlotInfo->dlMsgInfo->dciFormatId = 1;
1005 if(lcId == SRB0_LCID)
1007 schDlSlotInfo->dlMsgInfo->isMsg4Pdu = true;
1008 schDlSlotInfo->dlMsgInfo->dlMsgPduLen = dlBoInfo->dataVolume;
1013 /*******************************************************************
1015 * @brief Processes BSR indiation from MAC
1019 * Function : MacSchBsr
1022 * Processes DL BSR from MAC
1024 * @params[in] Pst pst
1025 * UlBufferStatusRptInd bsrInd
1026 * @return ROK - success
1029 * ****************************************************************/
1030 uint8_t MacSchBsr(Pst *pst, UlBufferStatusRptInd *bsrInd)
1032 Inst schInst = pst->dstInst-SCH_INST_START;
1033 SchCellCb *cellCb = NULLP;
1034 SchUeCb *ueCb = NULLP;
1037 #ifdef CALL_FLOW_DEBUG_LOG
1038 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_SHORT_BSR\n");
1041 DU_LOG("\nDEBUG --> SCH : Received BSR");
1042 cellCb = schCb[schInst].cells[schInst];
1043 ueCb = schGetUeCb(cellCb, bsrInd->crnti);
1045 /* store dataVolume per lcg in uecb */
1046 for(lcgIdx = 0; lcgIdx < bsrInd->numLcg; lcgIdx++)
1048 ueCb->bsrInfo[lcgIdx].priority = 1; //TODO: determining LCG priority?
1049 ueCb->bsrInfo[lcgIdx].dataVol = bsrInd->dataVolInfo[lcgIdx].dataVol;
1054 /*******************************************************************
1056 * @brief Processes SR UCI indication from MAC
1060 * Function : MacSchSrUciInd
1063 * Processes SR UCI indication from MAC
1065 * @params[in] Post structure
1067 * @return ROK - success
1070 * ****************************************************************/
1071 uint8_t MacSchSrUciInd(Pst *pst, SrUciIndInfo *uciInd)
1073 Inst inst = pst->dstInst-SCH_INST_START;
1076 SchCellCb *cellCb = schCb[inst].cells[inst];
1078 #ifdef CALL_FLOW_DEBUG_LOG
1079 DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_UCI_IND_TO_SCH\n");
1082 DU_LOG("\nDEBUG --> SCH : Received SR");
1084 ueCb = schGetUeCb(cellCb, uciInd->crnti);
1086 if(uciInd->numSrBits)
1088 ueCb->srRcvd = true;
1093 /*******************************************************************
1095 * @brief Allocates requested PRBs for DL
1099 * Function : allocatePrbDl
1102 * Allocates requested PRBs in DL
1103 * Keeps track of allocated PRB (using bitmap) and remaining PRBs
1105 * @params[in] prbAlloc table
1111 * @return ROK - success
1114 * ****************************************************************/
1115 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, \
1116 uint8_t startSymbol, uint8_t symbolLength, uint16_t *startPrb, uint16_t numPrb)
1119 uint16_t broadcastPrbStart=0, broadcastPrbEnd=0;
1120 FreePrbBlock *freePrbBlock = NULLP;
1121 CmLList *freePrbNode = NULLP;
1122 PduTxOccsaion ssbOccasion=0, sib1Occasion=0;
1123 SchDlSlotInfo *schDlSlotInfo = cell->schDlSlotInfo[slotTime.slot];
1124 SchPrbAlloc *prbAlloc = &schDlSlotInfo->prbAlloc;
1126 /* If startPrb is set to MAX_NUM_RB, it means startPrb is not known currently.
1127 * Search for an appropriate location in PRB grid and allocate requested resources */
1128 if(*startPrb == MAX_NUM_RB)
1130 /* Check if SSB/SIB1 is also scheduled in this slot */
1131 ssbOccasion = schCheckSsbOcc(cell, slotTime);
1132 sib1Occasion = schCheckSib1Occ(cell, slotTime);
1134 if(ssbOccasion && sib1Occasion)
1136 broadcastPrbStart = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
1137 broadcastPrbEnd = broadcastPrbStart + SCH_SSB_NUM_PRB + cell->cellCfg.sib1SchCfg.sib1PdschCfg.pdschFreqAlloc.freqAlloc.numPrb -1;
1139 else if(ssbOccasion)
1141 broadcastPrbStart = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
1142 broadcastPrbEnd = broadcastPrbStart + SCH_SSB_NUM_PRB -1;
1144 else if(sib1Occasion)
1146 broadcastPrbStart = cell->cellCfg.sib1SchCfg.sib1PdschCfg.pdschFreqAlloc.freqAlloc.startPrb;
1147 broadcastPrbEnd = broadcastPrbStart + cell->cellCfg.sib1SchCfg.sib1PdschCfg.pdschFreqAlloc.freqAlloc.numPrb -1;
1150 /* Iterate through all free PRB blocks */
1151 freePrbNode = prbAlloc->freePrbBlockList.first;
1154 freePrbBlock = (FreePrbBlock *)freePrbNode->node;
1156 /* If broadcast message is scheduled in this slot, then check if its PRBs belong to the current free block.
1157 * Since SSB/SIB1 PRB location is fixed, these PRBs cannot be allocated to other message in same slot */
1158 if((ssbOccasion || sib1Occasion) &&
1159 ((broadcastPrbStart >= freePrbBlock->startPrb) && (broadcastPrbStart <= freePrbBlock->endPrb)) && \
1160 ((broadcastPrbEnd >= freePrbBlock->startPrb) && (broadcastPrbEnd <= freePrbBlock->endPrb)))
1162 /* Implmentation is done such that highest-numbered free-RB is allocated first */
1163 if((freePrbBlock->endPrb > broadcastPrbEnd) && ((freePrbBlock->endPrb - broadcastPrbEnd) >= numPrb))
1165 /* If sufficient free PRBs are available above bradcast message then,
1166 * endPrb = freePrbBlock->endPrb
1167 * startPrb = endPrb - numPrb +1;
1169 *startPrb = freePrbBlock->endPrb - numPrb +1;
1172 else if((broadcastPrbStart > freePrbBlock->startPrb) && ((broadcastPrbStart - freePrbBlock->startPrb) >= numPrb))
1174 /* If free PRBs are available below broadcast message then,
1175 * endPrb = broadcastPrbStart - 1
1176 * startPrb = endPrb - numPrb +1
1178 *startPrb = broadcastPrbStart - numPrb;
1183 freePrbNode = freePrbNode->next;
1189 /* Check if requested number of blocks can be allocated from the current block */
1190 if (freePrbBlock->numFreePrb < numPrb)
1192 freePrbNode = freePrbNode->next;
1195 *startPrb = freePrbBlock->endPrb - numPrb +1;
1200 /* If no free block can be used to allocated request number of RBs */
1201 if(*startPrb == MAX_NUM_RB)
1205 /* If startPrb is known already, check if requested PRBs are available for allocation */
1208 freePrbNode = isPrbAvailable(&prbAlloc->freePrbBlockList, *startPrb, numPrb);
1211 DU_LOG("\nERROR --> SCH: Requested DL PRB unavailable");
1216 /* Update bitmap to allocate PRBs */
1217 for(symbol=startSymbol; symbol < (startSymbol+symbolLength); symbol++)
1219 if(fillPrbBitmap(prbAlloc->prbBitMap[symbol], *startPrb, numPrb) != ROK)
1221 DU_LOG("\nERROR --> SCH: fillPrbBitmap() failed for symbol [%d] in DL", symbol);
1226 /* Update the remaining number for free PRBs */
1227 removeAllocatedPrbFromFreePrbList(&prbAlloc->freePrbBlockList, freePrbNode, *startPrb, numPrb);
1232 /*******************************************************************
1234 * @brief Allocates requested PRBs for UL
1238 * Function : allocatePrbUl
1241 * Allocates requested PRBs in UL
1242 * Keeps track of allocated PRB (using bitmap) and remaining PRBs
1244 * @params[in] prbAlloc table
1250 * @return ROK - success
1253 * ****************************************************************/
1254 uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, \
1255 uint8_t startSymbol, uint8_t symbolLength, uint16_t *startPrb, uint16_t numPrb)
1258 uint16_t prachStartPrb, prachNumPrb, prachEndPrb;
1259 bool isPrachOccasion;
1260 FreePrbBlock *freePrbBlock = NULLP;
1261 CmLList *freePrbNode = NULLP;
1262 SchPrbAlloc *prbAlloc = &cell->schUlSlotInfo[slotTime.slot]->prbAlloc;
1264 /* If startPrb is set to MAX_NUM_RB, it means startPrb is not known currently.
1265 * Search for an appropriate location in PRB grid and allocate requested resources */
1266 if(*startPrb == MAX_NUM_RB)
1268 /* Check if PRACH is also scheduled in this slot */
1269 isPrachOccasion = schCheckPrachOcc(cell, slotTime);
1272 prachStartPrb = cell->cellCfg.schRachCfg.msg1FreqStart;
1273 prachNumPrb = schCalcPrachNumRb(cell);
1274 prachEndPrb = prachStartPrb + prachNumPrb -1;
1277 /* Iterate through all free PRB blocks */
1278 freePrbNode = prbAlloc->freePrbBlockList.first;
1281 freePrbBlock = (FreePrbBlock *)freePrbNode->node;
1283 /* If PRACH is scheduled in this slot, then check if its PRBs belong to the current free block.
1284 * PRBs required for PRACH cannot be allocated to any other message */
1285 if((isPrachOccasion) &&
1286 ((prachStartPrb >= freePrbBlock->startPrb) && (prachStartPrb <= freePrbBlock->endPrb)) &&
1287 ((prachEndPrb >= freePrbBlock->startPrb) && (prachEndPrb <= freePrbBlock->endPrb)))
1289 /* Implmentation is done such that highest-numbered free-RB is allocated first */
1290 if((freePrbBlock->endPrb > prachEndPrb) && ((freePrbBlock->endPrb - prachEndPrb) >= numPrb))
1292 /* If sufficient free PRBs are available above PRACH message then,
1293 * endPrb = freePrbBlock->endPrb
1294 * startPrb = endPrb - numPrb +1;
1296 *startPrb = freePrbBlock->endPrb - numPrb +1;
1299 else if((prachStartPrb > freePrbBlock->startPrb) && ((prachStartPrb - freePrbBlock->startPrb) >= numPrb))
1301 /* If free PRBs are available below PRACH message then,
1302 * endPrb = prachStartPrb - 1
1303 * startPrb = endPrb - numPrb +1
1305 *startPrb = prachStartPrb - numPrb;
1310 freePrbNode = freePrbNode->next;
1316 /* Check if requested number of PRBs can be allocated from currect block */
1317 if(freePrbBlock->numFreePrb < numPrb)
1319 freePrbNode = freePrbNode->next;
1322 *startPrb = freePrbBlock->endPrb - numPrb +1;
1327 /* If no free block can be used to allocated requested number of RBs */
1328 if(*startPrb == MAX_NUM_RB)
1333 /* If startPrb is known already, check if requested PRBs are available for allocation */
1334 freePrbNode = isPrbAvailable(&prbAlloc->freePrbBlockList, *startPrb, numPrb);
1337 DU_LOG("\nERROR --> SCH: Requested UL PRB unavailable");
1342 /* Update bitmap to allocate PRBs */
1343 for(symbol=startSymbol; symbol < (startSymbol+symbolLength); symbol++)
1345 if(fillPrbBitmap(prbAlloc->prbBitMap[symbol], *startPrb, numPrb) != ROK)
1347 DU_LOG("\nERROR --> SCH: fillPrbBitmap() failed for symbol [%d] in UL", symbol);
1352 /* Update the remaining number for free PRBs */
1353 removeAllocatedPrbFromFreePrbList(&prbAlloc->freePrbBlockList, freePrbNode, *startPrb, numPrb);
1358 /**********************************************************************
1360 **********************************************************************/