1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
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11 # Unless required by applicable law or agreed to in writing, software #
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14 # See the License for the specific language governing permissions and #
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17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for scheduler fucntions
29 **********************************************************************/
32 @brief This file implements the schedulers main access to MAC layer code.
35 #include "envopt.h" /* environment options */
36 #include "envdep.h" /* environment dependent */
37 #include "envind.h" /* environment independent */
38 #include "gen.h" /* general layer */
39 #include "ssi.h" /* system service interface */
40 #include "cm_tkns.h" /* Common Token Defines */
41 #include "cm_llist.h" /* Common Link List Defines */
42 #include "cm_hash.h" /* Common Hash List Defines */
43 #include "cm_mblk.h" /* common memory link list library */
44 #include "cm_lte.h" /* Common LTE Defines */
48 #include "rg_sch_inf.h"
50 #include "gen.x" /* general layer typedefs */
51 #include "ssi.x" /* system services typedefs */
52 #include "cm5.x" /* system services */
53 #include "cm_tkns.x" /* Common Token Definitions */
54 #include "cm_llist.x" /* Common Link List Definitions */
55 #include "cm_lib.x" /* Common Library Definitions */
56 #include "cm_hash.x" /* Common Hash List Definitions */
57 #include "cm_mblk.x" /* common memory link list library */
58 #include "cm_lte.x" /* Common LTE Defines */
59 #include "tfu.x" /* TFU types */
60 #include "lrg.x" /* layer management typedefs for MAC */
61 #include "rgr.x" /* layer management typedefs for MAC */
62 #include "rg_sch_inf.x" /* typedefs for Scheduler */
63 #include "du_app_mac_inf.h"
64 #include "mac_sch_interface.h"
66 #include "sch_utils.h"
68 extern SchCb schCb[SCH_MAX_INST];
69 extern int8_t coresetIdxTable[MAX_CORESET_INDEX][4];
70 extern int8_t searchSpaceIdxTable[MAX_SEARCH_SPACE_INDEX][4];
71 void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
73 SchCellCfgCfmFunc SchCellCfgCfmOpts[] =
75 packSchCellCfgCfm, /* LC */
76 MacProcSchCellCfgCfm, /* TC */
77 packSchCellCfgCfm /* LWLC */
82 * @brief Task Initiation function.
86 * Function : schActvInit
88 * This function is supplied as one of parameters during MAC's
89 * task registration. MAC will invoke this function once, after
90 * it creates and attaches this TAPA Task to a system task.
92 * @param[in] Ent Entity, the entity ID of this task.
93 * @param[in] Inst Inst, the instance ID of this task.
94 * @param[in] Region Region, the region ID registered for memory
96 * @param[in] Reason Reason.
102 Ent entity, /* entity */
103 Inst instId, /* instance */
104 Region region, /* region */
105 Reason reason /* reason */
108 Inst inst = (instId - SCH_INST_START);
110 /* Initialize the MAC TskInit structure to zero */
111 cmMemset ((uint8_t *)&schCb[inst], 0, sizeof(schCb));
113 /* Initialize the MAC TskInit with received values */
114 schCb[inst].schInit.ent = entity;
115 schCb[inst].schInit.inst = inst;
116 schCb[inst].schInit.region = region;
117 schCb[inst].schInit.pool = 0;
118 schCb[inst].schInit.reason = reason;
119 schCb[inst].schInit.cfgDone = FALSE;
120 schCb[inst].schInit.acnt = FALSE;
121 schCb[inst].schInit.usta = FALSE;
122 schCb[inst].schInit.trc = FALSE;
123 schCb[inst].schInit.procId = SFndProcId();
129 * @brief Scheduler instance Configuration Handler.
133 * Function : SchInstCfg
135 * This function in called by HandleSchGenCfgReq(). It handles the
136 * general configurations of the scheduler instance. Returns
137 * reason for success/failure of this function.
139 * @param[in] RgCfg *cfg, the Configuaration information
141 * -# LCM_REASON_NOT_APPL
142 * -# LCM_REASON_INVALID_MSGTYPE
143 * -# LCM_REASON_MEM_NOAVAIL
145 PUBLIC U16 SchInstCfg
147 RgCfg *cfg, /* Configuaration information */
151 uint16_t ret = LCM_REASON_NOT_APPL;
152 Inst inst = (dInst - SCH_INST_START);
154 printf("\nEntered SchInstCfg()");
155 /* Check if Instance Configuration is done already */
156 if (schCb[inst].schInit.cfgDone == TRUE)
158 RETVALUE(LCM_REASON_INVALID_MSGTYPE);
160 /* Update the Pst structure for LM interface */
161 cmMemcpy((U8 *)&schCb[inst].schInit.lmPst,
162 (U8 *)&cfg->s.schInstCfg.genCfg.lmPst,
165 schCb[inst].schInit.inst = inst;
166 schCb[inst].schInit.lmPst.srcProcId = schCb[inst].schInit.procId;
167 schCb[inst].schInit.lmPst.srcEnt = schCb[inst].schInit.ent;
168 schCb[inst].schInit.lmPst.srcInst = schCb[inst].schInit.inst +
170 schCb[inst].schInit.lmPst.event = EVTNONE;
172 schCb[inst].schInit.region = cfg->s.schInstCfg.genCfg.mem.region;
173 schCb[inst].schInit.pool = cfg->s.schInstCfg.genCfg.mem.pool;
174 schCb[inst].genCfg.tmrRes = cfg->s.schInstCfg.genCfg.tmrRes;
176 schCb[inst].genCfg.forceCntrlSrbBoOnPCel = cfg->s.schInstCfg.genCfg.forceCntrlSrbBoOnPCel;
177 schCb[inst].genCfg.isSCellActDeactAlgoEnable = cfg->s.schInstCfg.genCfg.isSCellActDeactAlgoEnable;
179 schCb[inst].genCfg.startCellId = cfg->s.schInstCfg.genCfg.startCellId;
181 /* Initialzie the timer queue */
182 cmMemset((U8 *)&schCb[inst].tmrTq, 0, sizeof(CmTqType)*RGSCH_TQ_SIZE);
183 /* Initialize the timer control point */
184 cmMemset((U8 *)&schCb[inst].tmrTqCp, 0, sizeof(CmTqCp));
185 schCb[inst].tmrTqCp.tmrLen = RGSCH_TQ_SIZE;
187 /* SS_MT_TMR needs to be enabled as schActvTmr needs instance information */
188 /* Timer Registration request to SSI */
189 if (SRegTmrMt(schCb[inst].schInit.ent, dInst,
190 (S16)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK)
192 RLOG_ARG0(L_ERROR,DBG_INSTID,inst, "SchInstCfg(): Failed to "
194 RETVALUE(LCM_REASON_MEM_NOAVAIL);
197 /* Set Config done in TskInit */
198 schCb[inst].schInit.cfgDone = TRUE;
199 printf("\nScheduler gen config done");
205 * @brief Layer Manager Configuration request handler.
209 * Function : HandleSchGenCfgReq
211 * This function handles the configuration
212 * request received at scheduler instance from the Layer Manager.
213 * -# Based on the cfg->hdr.elmId.elmnt value it invokes one of the
214 * functions rgHdlGenCfg() or rgHdlSapCfg().
215 * -# Invokes RgMiLrgSchCfgCfm() to send back the confirmation to the LM.
217 * @param[in] Pst *pst, the post structure
218 * @param[in] RgMngmt *cfg, the configuration parameter's structure
222 int HandleSchGenCfgReq
224 Pst *pst, /* post structure */
225 RgMngmt *cfg /* config structure */
228 uint16_t ret = LCM_PRIM_OK;
229 uint16_t reason = LCM_REASON_NOT_APPL;
233 if(pst->dstInst < SCH_INST_START)
235 DU_LOG("\nInvalid inst ID");
236 DU_LOG("\nHandleSchGenCfgReq(): "
237 "pst->dstInst=%d SCH_INST_START=%d", pst->dstInst,SCH_INST_START);
240 printf("\nReceived scheduler gen config");
241 /* Fill the post structure for sending the confirmation */
242 memset(&cfmPst, 0 , sizeof(Pst));
243 SchFillCfmPst(pst, &cfmPst, cfg);
245 cmMemset((U8 *)&cfm, 0, sizeof(RgMngmt));
252 cfm.hdr.elmId.elmnt = cfg->hdr.elmId.elmnt;
253 switch(cfg->hdr.elmId.elmnt)
256 reason = SchInstCfg(&cfg->t.cfg,pst->dstInst );
260 reason = LCM_REASON_INVALID_ELMNT;
261 DU_LOG("\nInvalid Elmnt=%d", cfg->hdr.elmId.elmnt);
265 if (reason != LCM_REASON_NOT_APPL)
270 cfm.cfm.status = ret;
271 cfm.cfm.reason = reason;
273 SchSendCfgCfm(&cfmPst, &cfm);
274 /* SPutSBuf(pst->region, pst->pool, (Data *)cfg, sizeof(RgMngmt)); */
277 }/*-- HandleSchGenCfgReq --*/
280 * @brief slot indication from MAC to SCH.
284 * Function : macSchSlotInd
286 * This API is invoked by PHY to indicate slot indication to Scheduler for
289 * @param[in] Pst *pst
290 * @param[in] SlotIndInfo *slotInd
301 Inst inst = pst->dstInst-SCH_INST_START;
303 /* Now call the TOM (Tfu ownership module) primitive to process further */
304 schProcessSlotInd(slotInd, inst);
307 } /* macSchSlotInd */
310 * @brief inti cellCb based on cellCfg
314 * Function : InitSchCellCb
316 * This API is invoked after receiving schCellCfg
318 * @param[in] schCellCb *cell
319 * @param[in] SchCellCfg *schCellCfg
324 int InitSchCellCb(Inst inst, SchCellCfg *schCellCfg)
327 SCH_ALLOC(cell, sizeof(SchCellCb));
330 DU_LOG("\nMemory allocation failed in InitSchCellCb");
334 cell->cellId = schCellCfg->cellId;
335 cell->instIdx = inst;
336 switch(schCellCfg->ssbSchCfg.scsCommon)
340 cell->numSlots = SCH_NUM_SLOTS;
344 DU_LOG("\nSCS %d not supported", schCellCfg->ssbSchCfg.scsCommon);
347 for(uint8_t idx=0; idx<SCH_NUM_SLOTS; idx++)
349 SchDlAlloc *schDlAlloc;
350 SchUlAlloc *schUlAlloc;
353 SCH_ALLOC(schDlAlloc, sizeof(SchDlAlloc));
356 DU_LOG("\nMemory allocation failed in InitSchCellCb");
361 SCH_ALLOC(schUlAlloc, sizeof(SchUlAlloc));
364 DU_LOG("\nMemory allocation failed in InitSchCellCb");
368 schDlAlloc->totalPrb = schUlAlloc->totalPrb = MAX_NUM_RB;
370 for(uint8_t itr=0; itr<SCH_SYMBOL_PER_SLOT; itr++)
372 schDlAlloc->assignedPrb[itr] = 0;
373 schUlAlloc->assignedPrb[itr] = 0;
376 for(uint8_t itr=0; itr<MAX_SSB_IDX; itr++)
378 memset(&schDlAlloc->ssbInfo[itr], 0, sizeof(SsbInfo));
381 cell->dlAlloc[idx] = schDlAlloc;
382 cell->ulAlloc[idx] = schUlAlloc;
385 schCb[inst].cells[inst] = cell;
387 DU_LOG("\nCell init completed for cellId:%d", cell->cellId);
394 SchSib1Cfg *sib1SchCfg,
399 uint8_t coreset0Idx = 0;
400 uint8_t searchSpace0Idx = 0;
401 uint8_t ssbMuxPattern = 0;
403 uint8_t numSymbols = 0;
406 uint8_t numSearchSpacePerSlot = 0;
408 uint8_t firstSymbol = 0; /* need to calculate using formula mentioned in 38.213 */
409 uint8_t slotIndex = 0;
410 uint8_t FreqDomainResource[6] = {0};
412 Sib1PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg);
413 Sib1PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg);
415 coreset0Idx = sib1SchCfg->coresetZeroIndex;
416 searchSpace0Idx = sib1SchCfg->searchSpaceZeroIndex;
418 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
419 ssbMuxPattern = coresetIdxTable[coreset0Idx][0];
420 numRbs = coresetIdxTable[coreset0Idx][1];
421 numSymbols = coresetIdxTable[coreset0Idx][2];
422 offset = coresetIdxTable[coreset0Idx][3];
424 /* derive the search space params from table 13-11 spec 38.213 */
425 oValue = searchSpaceIdxTable[searchSpace0Idx][0];
426 numSearchSpacePerSlot = searchSpaceIdxTable[searchSpace0Idx][1];
427 mValue = searchSpaceIdxTable[searchSpace0Idx][2];
428 firstSymbol = searchSpaceIdxTable[searchSpace0Idx][3];
430 /* calculate the n0, need to add the formulae, as of now the value is 0
431 * Need to add the even and odd values of i during configuration
432 * [(O . 2^u + i . M ) ] mod numSlotsPerSubframe
433 * assuming u = 0, i = 0, numSlotsPerSubframe = 10
434 * Also, from this configuration, coreset0 is only on even subframe */
435 slotIndex = ((oValue * 1) + (0 * mValue)) % 10;
436 sib1SchCfg->n0 = slotIndex;
438 /* calculate the PRBs */
439 freqDomResourceAlloc( ((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
441 /* fill the PDCCH PDU */
442 pdcch->sib1PdcchBwpCfg.BWPSize = MAX_NUM_RB; /* whole of BW */
443 pdcch->sib1PdcchBwpCfg.BWPStart = 0;
444 pdcch->sib1PdcchBwpCfg.subcarrierSpacing = 0; /* 15Khz */
445 pdcch->sib1PdcchBwpCfg.cyclicPrefix = 0; /* normal */
446 pdcch->sib1Coreset0Cfg.coreSet0Size = numRbs;
447 pdcch->sib1Coreset0Cfg.startSymbolIndex = firstSymbol;
448 pdcch->sib1Coreset0Cfg.durationSymbols = numSymbols;
449 memcpy(pdcch->sib1Coreset0Cfg.freqDomainResource,FreqDomainResource,6);
450 pdcch->sib1Coreset0Cfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
451 pdcch->sib1Coreset0Cfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
452 pdcch->sib1Coreset0Cfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
453 pdcch->sib1Coreset0Cfg.coreSetType = 0;
454 pdcch->sib1Coreset0Cfg.shiftIndex = pci;
455 pdcch->sib1Coreset0Cfg.precoderGranularity = 0; /* sameAsRegBundle */
457 pdcch->sib1DlDci.rnti = 0xFFFF; /* SI-RNTI */
458 pdcch->sib1DlDci.scramblingId = pci;
459 pdcch->sib1DlDci.scramblingRnti = 0;
460 pdcch->sib1DlDci.cceIndex = 0;
461 pdcch->sib1DlDci.aggregLevel = 4;
462 pdcch->sib1DlDci.beamPdcchInfo.numPrgs = 1;
463 pdcch->sib1DlDci.beamPdcchInfo.prgSize = 1;
464 pdcch->sib1DlDci.beamPdcchInfo.digBfInterfaces = 0;
465 pdcch->sib1DlDci.beamPdcchInfo.prg[0].pmIdx = 0;
466 pdcch->sib1DlDci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
467 pdcch->sib1DlDci.txPdcchPower.powerValue = 0;
468 pdcch->sib1DlDci.txPdcchPower.powerControlOffsetSS = 0;
469 /* Storing pdschCfg pointer here. Required to access pdsch config while
470 fillig up pdcch pdu */
471 pdcch->sib1DlDci.pdschCfg = pdsch;
473 /* fill the PDSCH PDU */
475 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
476 pdsch->rnti = 0xFFFF; /* SI-RNTI */
478 pdsch->sib1PdschBwpCfg.BWPSize = MAX_NUM_RB; /* whole of BW */
479 pdsch->sib1PdschBwpCfg.BWPStart = 0;
480 pdsch->numCodewords = 1;
481 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
483 pdsch->codeword[cwCount].targetCodeRate = 308;
484 pdsch->codeword[cwCount].qamModOrder = 2;
485 pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs;
486 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
487 pdsch->codeword[cwCount].rvIndex = 0;
488 pdsch->codeword[cwCount].tbSize = 768;
490 pdsch->dataScramblingId = pci;
491 pdsch->numLayers = 1;
492 pdsch->transmissionScheme = 0;
494 pdsch->dmrs.dlDmrsSymbPos = 2;
495 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
496 pdsch->dmrs.dlDmrsScramblingId = pci;
497 pdsch->dmrs.scid = 0;
498 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
499 pdsch->dmrs.dmrsPorts = 0;
500 pdsch->sib1FreqAlloc.resourceAlloc = 1; /* RAT type-1 RIV format */
501 pdsch->sib1FreqAlloc.rbStart = offset + SCH_SSB_PRB_DURATION; /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
502 /* formula used for calculation of rbSize, 38.213 section 5.1.3.2 *
503 * Ninfo = Nre . R . Qm . v *
504 * Nre' = Nsc . NsymPdsch - NdmrsSymb - Noh *
505 * Nre = min(156,Nre') . nPrb */
506 pdsch->sib1FreqAlloc.rbSize = 10; /* This value is calculated from above formulae */
507 pdsch->sib1FreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
508 pdsch->sib1TimeAlloc.rowIndex = 1;
509 pdsch->sib1TimeAlloc.startSymbolIndex = 2; /* spec-38.214, Table 5.1.2.1-1 */
510 pdsch->sib1TimeAlloc.numSymbols = 12;
511 pdsch->beamPdschInfo.numPrgs = 1;
512 pdsch->beamPdschInfo.prgSize = 1;
513 pdsch->beamPdschInfo.digBfInterfaces = 0;
514 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
515 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
516 pdsch->txPdschPower.powerControlOffset = 0;
517 pdsch->txPdschPower.powerControlOffsetSS = 0;
522 * @brief cell config from MAC to SCH.
526 * Function : macSchCellCfgReq
528 * This API is invoked by MAC to send cell config to SCH
530 * @param[in] Pst *pst
531 * @param[in] SchCellCfg *schCellCfg
539 SchCellCfg *schCellCfg
544 SchCellCfgCfm schCellCfgCfm;
546 Inst inst = pst->dstInst-1;
548 InitSchCellCb(inst, schCellCfg);
549 cellCb = schCb[inst].cells[inst]; //cells is of MAX_CELLS, why inst
550 cellCb->macInst = pst->srcInst;
552 /* derive the SIB1 config parameters */
555 &(schCellCfg->sib1SchCfg),
556 schCellCfg->phyCellId,
557 schCellCfg->ssbSchCfg.ssbOffsetPointA);
558 memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg));
560 memset(&rspPst, 0, sizeof(Pst));
561 SCH_FILL_RSP_PST(rspPst, inst);
562 rspPst.event = EVENT_SCH_CELL_CFG_CFM;
563 schCellCfgCfm.rsp = RSP_OK;
565 ret = (*SchCellCfgCfmOpts[rspPst.selector])(&rspPst, &schCellCfgCfm);
571 /**********************************************************************
573 **********************************************************************/