1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for Entry point fucntions
29 **********************************************************************/
31 /** @file rg_sch_utl.c
32 @brief This file implements the schedulers main access to MAC layer code.
35 static const char* RLOG_MODULE_NAME="MAC";
36 static int RLOG_MODULE_ID=4096;
37 static int RLOG_FILE_ID=177;
39 /* header include files -- defines (.h) */
40 #include "common_def.h"
45 #include "rg_sch_err.h"
46 #include "rg_sch_inf.h"
48 #include "rg_sch_cmn.h"
50 #include "rl_interface.h"
51 #include "rl_common.h"
53 /* header/extern include files (.x) */
54 #include "tfu.x" /* TFU types */
55 #include "lrg.x" /* layer management typedefs for MAC */
56 #include "rgr.x" /* layer management typedefs for MAC */
58 #include "rg_sch_inf.x" /* typedefs for Scheduler */
59 #include "rg_sch.x" /* typedefs for Scheduler */
60 #include "rg_sch_cmn.x" /* typedefs for Scheduler */
62 #include "rg_sch_emtc_ext.x"
67 uint32_t rgNumPrachRecvd =0; /* Num of Rach Req received including dedicated preambles */
68 uint32_t rgNumRarSched =0; /* Num of RARs sent */
69 uint32_t rgNumBI =0; /* Num of BackOff Ind sent */
70 uint32_t rgNumMsg3CrcPassed =0; /* Num of CRC success for Msg3 */
71 uint32_t rgNumMsg3CrcFailed =0; /* Num of CRC fail for Msg 3 */
72 uint32_t rgNumMsg3FailMaxRetx =0; /* Num of Msg3 fail after Max Retx attempts */
73 uint32_t rgNumMsg4Ack =0; /* Num of Acks for Msg4 Tx */
74 uint32_t rgNumMsg4Nack =0;
75 /* Num of Nacks for Msg4 Tx */
76 uint32_t rgNumMsg4FailMaxRetx =0; /* Num of Msg4 Tx failed after Max Retx attempts */
77 uint32_t rgNumSrRecvd =0; /* Num of Sched Req received */
78 uint32_t rgNumSrGrant =0; /* Num of Sched Req Grants sent */
79 uint32_t rgNumMsg3CrntiCE =0; /* Num of Msg 3 CRNTI CE received */
80 uint32_t rgNumDedPream =0; /* Num of Dedicated Preambles recvd */
81 uint32_t rgNumMsg3CCCHSdu =0; /* Num of Msg 3 CCCH Sdus recvd */
82 uint32_t rgNumCCCHSduCrntiNotFound =0; /*UE Ctx not found for CCCH SDU Msg 3 */
83 uint32_t rgNumCrntiCeCrntiNotFound =0; /*UE Ctx not found for CRNTI CE Msg 3 */
84 uint32_t rgNumMsg4WithCCCHSdu =0; /* Num of Msg4 with CCCH Sdu */
85 uint32_t rgNumMsg4WoCCCHSdu =0; /* Num of Msg4 without CCCH Sdu */
86 uint32_t rgNumMsg4Dtx =0; /* Num of DTX received for Msg 4 */
87 uint32_t rgNumMsg3AckSent =0; /* Num of PHICH Ack sent for Msg 3 */
88 uint32_t rgNumMsg3NackSent =0; /* Num of PHICH Nack sent for Msg 3 */
89 uint32_t rgNumMsg4PdcchWithCrnti =0; /* Num of PDCCH for CRNTI based contention resolution */
90 uint32_t rgNumRarFailDuetoRntiExhaustion =0; /* Num of RACH Failures due to RNTI pool exhaution */
91 uint32_t rgNumTAModified =0; /* Num of times TA received is different from prev value */
92 uint32_t rgNumTASent =0; /* Num of TA Command sent */
93 uint32_t rgNumMsg4ToBeTx =0; /* Num of times MSG4 that should be sent */
94 uint32_t rgNumMsg4Txed =0; /* Num of MSG4 actually sent *//* ysNumMsg4ToBeTx -ysNumMsg4Txed == Failed MSG4 TX */
95 uint32_t rgNumMsg3DtxRcvd =0; /* CRC Fail with SINR < 0 */
97 uint32_t rgNumDedPreamUECtxtFound =0; /* Num of Dedicated Preambles recvd */
99 static uint8_t rgSchDciAmbigSizeTbl[61] = {0,0,0,0,0,0,0,0,0,0,0,
100 0,1,0,1,0,1,0,0,0,1,
101 0,0,0,1,0,1,0,0,0,0,
102 0,1,0,0,0,0,0,0,0,1,
103 0,0,0,1,0,0,0,0,0,0,
104 0,0,0,0,0,1,0,0,0,0};
108 uint32_t rgSchCmnBetaCqiOffstTbl[16];
109 uint32_t rgSchCmnBetaRiOffstTbl[16];
110 RgSchdApis rgSchCmnApis;
111 S16 RgUiRgmSendPrbRprtInd ARGS((
114 RgmPrbRprtInd *prbRprtInd
117 S16 RgUiRgmSendTmModeChangeInd ARGS((
120 RgmTransModeInd *txModeChngInd
123 S16 rgSCHEmtcUtlGetSfAlloc ARGS((
126 S16 rgSCHEmtcUtlPutSfAlloc ARGS((
129 Void rgSCHEmtcUtlUpdUeDciSize ARGS((
133 Void rgSCHEmtcGetDciFrmt61ASize ARGS((
136 Void rgSCHEmtcGetDciFrmt60ASize ARGS((
139 S16 rgSCHEmtcUtlFillPdschDciInfo ARGS((
140 TfuPdschDciInfo *pdsch,
143 Void rgSCHEmtcUtlRlsRnti ARGS((
145 RgSchRntiLnk *rntiLnk,
148 S16 rgSCHEmtcPdcchAlloc ARGS((
152 Void rgSCHEmtcPdcchFree ARGS((
157 /* Functions specific to TM1/TM2/TM6/TM7 for PRB calculation*/
158 Void rgSchUtlDlCalc1CwPrb ARGS(( RgSchCellCb *cell,
161 uint32_t *prbReqrd));
163 /* Functions specific to TM3/TM4 for PRB calculation*/
164 Void rgSchUtlDlCalc2CwPrb ARGS(( RgSchCellCb *cell,
167 uint32_t *prbReqrd));
170 RgSchCellCb* rgSchUtlGetCellCb ARGS(( Inst inst,
175 typedef Void (*RgSchUtlDlCalcPrbFunc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
176 uint32_t bo, uint32_t *prbRequrd));
178 /* Functions specific to each transmission mode for PRB calculation*/
179 RgSchUtlDlCalcPrbFunc dlCalcPrbFunc[7] = {rgSchUtlDlCalc1CwPrb,
180 rgSchUtlDlCalc1CwPrb, rgSchUtlDlCalc2CwPrb, rgSchUtlDlCalc2CwPrb,
181 NULLP, rgSchUtlDlCalc1CwPrb, rgSchUtlDlCalc1CwPrb};
184 /* Functions specific to each transmission mode for PRB calculation*/
185 RgSchUtlDlCalcPrbFunc dlCalcPrbFunc[9] = {rgSchUtlDlCalc1CwPrb,
186 rgSchUtlDlCalc1CwPrb, rgSchUtlDlCalc2CwPrb, rgSchUtlDlCalc2CwPrb,
187 NULLP, rgSchUtlDlCalc1CwPrb, rgSchUtlDlCalc1CwPrb, NULLP, NULLP};
192 /* The below table will be used to map the UL SF number in a TDD Cfg 0
193 frame to the ul Sf array maintained in cellCb */
194 static uint8_t rgSchTddCfg0UlSfTbl[] = {2, 3, 4, 7, 8, 9};
197 static S16 rgSCHUtlUlAllocDbInit ARGS((
202 static Void rgSCHUtlUlAllocDbDeinit ARGS((
206 static S16 rgSCHUtlUlHoleDbInit ARGS((
213 static Void rgSCHUtlUlHoleDbDeinit ARGS((
218 static S16 rgSCHChkBoUpdate ARGS((
220 RgInfCmnBoRpt *boUpdt
224 static uint8_t rgSCHUtlFetchPcqiBitSz ARGS((
231 /* sorted in ascending order of tbSz */
232 const struct rgSchUtlBcchPcchTbSz
234 uint8_t rbIndex; /* RB index {2,3} */
235 uint16_t tbSz; /* one of the Transport block size in bits of
237 /* Corrected allocation for common channels */
238 uint8_t mcs; /* imcs */
239 } rgSchUtlBcchPcchTbSzTbl[44] = {
240 { 2, 32, 0 }, { 2, 56, 1 }, { 2, 72, 2 }, { 3, 88, 1 },
241 { 2, 104, 3 }, { 2, 120, 4 }, { 2, 144, 5 }, { 2, 176, 6 },
242 { 3, 208, 4 }, { 2, 224, 7 }, { 2, 256, 8 }, { 2, 296, 9 },
243 { 2, 328, 10 }, { 2, 376, 11 }, { 3, 392, 8 }, { 2, 440, 12 },
244 { 3, 456, 9 }, { 2, 488, 13 }, { 3, 504, 10 }, { 2, 552, 14 },
245 { 3, 584, 11 }, { 2, 600, 15 }, { 2, 632, 16 }, { 3, 680, 12 },
246 { 2, 696, 17 }, { 3, 744, 13 }, { 2, 776, 18 }, { 2, 840, 19 },
247 { 2, 904, 20 }, { 3, 968, 16 }, { 2, 1000, 21 }, { 2, 1064, 22 },
248 { 2, 1128, 23 }, { 3, 1160, 18 }, { 2, 1192, 24 }, { 2, 1256, 25 },
249 { 3, 1288, 19 }, { 3, 1384, 20 }, { 2, 1480, 26 }, { 3, 1608, 22 },
250 { 3, 1736, 23 }, { 3, 1800, 24 }, { 3, 1864, 25 }, { 3, 2216, 26 }
257 /* forward references */
259 static Void rgSCHUtlUpdPrachOcc ARGS((
261 RgrTddPrachInfo *cellCfg));
264 #define RGSCH_NUM_PCFICH_REG 4
265 #define RGSCH_NUM_REG_PER_CCE 9
266 #define RGSCH_NUM_REG_PER_PHICH_GRP 3
269 #define RGSCH_INITPHICH(_phich, _hqFeedBack, _nDmrs, _rbStart, _iPhich) {\
270 (_phich)->hqFeedBack = _hqFeedBack; \
271 (_phich)->rbStart = _rbStart; \
272 (_phich)->nDmrs = _nDmrs; \
273 (_phich)->iPhich = _iPhich; \
274 (_phich)->lnk.next = NULLP; \
275 (_phich)->lnk.prev = NULLP; \
276 (_phich)->lnk.node = (PTR)(_phich); \
279 #define RGSCH_INITPHICH(_phich, _hqFeedBack, _nDmrs, _rbStart, _isForMsg3) {\
280 (_phich)->hqFeedBack = _hqFeedBack; \
281 (_phich)->rbStart = _rbStart; \
282 (_phich)->nDmrs = _nDmrs; \
283 (_phich)->isForMsg3 = _isForMsg3; \
284 (_phich)->lnk.next = NULLP; \
285 (_phich)->lnk.prev = NULLP; \
286 (_phich)->lnk.node = (PTR)(_phich); \
290 #define RGSCH_PHICH_ALLOC(_inst,_dataPtr, _size, _ret) {\
291 _ret = rgSCHUtlAllocSBuf(_inst, (Data **)&_dataPtr, _size); \
294 /* ccpu00117052 - MOD - Passing double pointer
295 for proper NULLP assignment*/
296 #define RGSCH_PHICH_FREE(_inst, _dataPtr, _size) {\
297 rgSCHUtlFreeSBuf(_inst, (Data **)(&(_dataPtr)), _size); \
301 #define RGSCH_GETBIT(a, b) ((((uint8_t*)a)[(b)>>3] >> ((7-((b)&7)))) & 1)
307 * Desc: This function finds of the Power of x raised to n
309 * Ret: value of x raised to n
323 F64 rgSCHUtlPower(x, n)
334 return ( x * rgSCHUtlPower( x, n-1 ) );
338 return ( (1/x) * rgSCHUtlPower( x, n+1 ) );
340 } /* end of rgSCHUtlPower*/
346 * Desc: This function parses bits x to y of an array and
347 * returns the integer value out of it.
349 * Ret: integer value of z bits
357 uint32_t rgSCHUtlParse
365 uint32_t rgSCHUtlParse(buff, startPos, endPos, buffSize)
372 uint8_t pointToChar,pointToEnd, loop;
373 uint8_t size = endPos - startPos;
375 pointToEnd = (startPos)%8;
376 for ( loop=0; loop<size; loop++)
378 pointToChar = (((startPos)+loop)/8);
379 if (RGSCH_GETBIT(buff+pointToChar,pointToEnd%8)==1)
381 result=result+(rgSCHUtlPower(2,(size-loop-1)));
385 return ((uint32_t)result);
386 } /* end of rgSCHUtlParse*/
390 * Fun: rgSCHUtlFindDist
392 * Desc: This function calculates the iterations need to cover
393 * before the valid Index can be used for next possible Reception
395 * Ret: integer value of z bits
403 uint8_t rgSCHUtlFindDist
409 uint8_t rgSCHUtlFindDist(crntTime, tempIdx)
415 /* ccpu00137113- Distance is not estimated properly if the periodicity is
416 * equal to RG_SCH_PCQI_SRS_SR_TRINS_SIZE.
418 while(crntTime<=tempIdx)
420 crntTime += RG_SCH_PCQI_SRS_SR_TRINS_SIZE;
424 } /* end of rgSCHUtlFindDist*/
429 * @brief This function checks availability of a PDCCH
433 * Function: rgSCHUtlPdcchAvail
434 * Purpose: This function checks if a particular PDCCH is in use.
435 * map field of PDCCH is used to track the CCEs arleady
436 * allocated. Each bit of map represents one CCE and the
437 * LSBit of first byte represents CCE 0.
439 * 1. Locate the set of bits that represent the PDCCH for
440 * the provided location.
441 * 2. If the value of the bits is non-zero one or many CCEs
442 * for the PDCCH are in use and hence the PDCCH is not available.
443 * 3. If pdcch is available, assign it to [out]pdcch.
444 * 4. Set all of the bits to one. There is no check performed
445 * to see if the PDCCH is available.
447 * Invoked by: scheduler
449 * @param[in] RgSchCellCb* cell
450 * @param[in] RgSchPdcchInfo* pdcchInfo
451 * @param[in] uint8_t loc
452 * @param[in] uint8_t aggrLvl
453 * @param[out] RgSchPdcch** pdcch
455 * -# TRUE if available
460 Bool rgSCHUtlPdcchAvail
463 RgSchPdcchInfo *pdcchInfo,
464 CmLteAggrLvl aggrLvl,
468 Bool rgSCHUtlPdcchAvail(cell, pdcchInfo, aggrLvl, pdcch)
470 RgSchPdcchInfo *pdcchInfo;
471 CmLteAggrLvl aggrLvl;
479 Inst inst = cell->instIdx;
481 uint16_t offsetStepMask;
485 byte = &pdcchInfo->map[0];
486 initMask = (0xffff >> (16 - aggrLvl));
488 /* if N(symbol, xPDCCH) =2, then xPDCCH will be candidates in
489 * search space of index {0,1,2,3} and {8,9,..14}
491 if ((cell->cell5gtfCb.cfi == 2) && (aggrLvl == CM_LTE_AGGR_LVL2))
493 offsetStepMask = 0xc;
497 offsetStepMask = 0xc0;
500 /* Loop till the number of bytes available in the CCE map */
501 while (offset < ((pdcchInfo->nCce+ 7) >> 3))
503 byte = &pdcchInfo->map[offset];
504 /* Checking for available CCE */
505 if ((*byte & currMask) == 0)
509 /* if the number of CCEs required are not available, move to next offset */
510 if (currMask & offsetStepMask)
517 /* Move to the next available CCE index in the current byte(cce map) */
518 currMask = currMask << aggrLvl;
522 if ((offset >= ((pdcchInfo->nCce + 7) >> 3)) ||
523 ((aggrLvl == CM_LTE_AGGR_LVL16) && (offset > 0)))
528 byte = &pdcchInfo->map[offset];
530 if (cell->pdcchLst.first != NULLP)
532 *pdcch = (RgSchPdcch *)(cell->pdcchLst.first->node);
533 cmLListDelFrm(&cell->pdcchLst, cell->pdcchLst.first);
537 ret = rgSCHUtlAllocSBuf(inst, (Data **)pdcch, sizeof(RgSchPdcch));
547 /* ALL CCEs will be used in case of level 16 */
548 if (aggrLvl == CM_LTE_AGGR_LVL16)
550 *(byte+1) |= currMask;
552 (*pdcch)->aggrLvl = aggrLvl;
553 cmLListAdd2Tail(&pdcchInfo->pdcchs, &((*pdcch)->lnk));
554 (*pdcch)->lnk.node = (PTR)*pdcch;
555 (*pdcch)->nCce = aggrLvl;
556 (*pdcch)->ue = NULLP;
564 * @brief This function releases a PDCCH
568 * Function: rgSCHUtlPdcchPut
569 * Purpose: This function releases a PDCCH.
571 * 1. Locate the set of bits that represent the PDCCH for
572 * the provided location.
573 * 2. Set all of the bits to zero.
574 * 3. Release the memory of PDCCH to the cell free Q
576 * Invoked by: scheduler
578 * @param[in] RgSchPdcchInfo* pdcchInfo
579 * @param[in] uint8_t loc
580 * @param[in] uint8_t aggrLvl
585 Void rgSCHUtlPdcchPut
588 RgSchPdcchInfo *pdcchInfo,
592 Void rgSCHUtlPdcchPut(cell, pdcchInfo, pdcch)
594 RgSchPdcchInfo *pdcchInfo;
602 switch(pdcch->aggrLvl)
604 case CM_LTE_AGGR_LVL2:
605 offset = (pdcch->nCce >> 1) & 3;
606 mask = 0x3 << (offset * 2); /*ccpu00128826 - Offset Correction */
608 case CM_LTE_AGGR_LVL4:
609 offset = (pdcch->nCce >> 2) & 1;
610 mask = 0xf << (offset * 4);/*ccpu00128826 - Offset Correction */
612 case CM_LTE_AGGR_LVL8:
615 case CM_LTE_AGGR_LVL16:
621 /* Placing common computation of byte from all the cases above here
623 byte = &pdcchInfo->map[pdcch->nCce >> 3];
625 cmLListDelFrm(&pdcchInfo->pdcchs, &pdcch->lnk);
626 cmLListAdd2Tail(&cell->pdcchLst, &pdcch->lnk);
627 pdcch->lnk.node = (PTR)pdcch;
636 * @brief This function initializes PDCCH information for frame
640 * Function: rgSCHUtlPdcchInit
641 * Purpose: This function initializes PDCCH information for
642 * a slot. It removes the list of PDCCHs allocated
643 * in the prior use of this slot structure.
645 * Invoked by: rgSCHUtlSubFrmPut
647 * @param[in] RgSchCellCb* cell
648 * @param[in] RgSubFrm* subFrm
653 Void rgSCHUtlPdcchInit
660 Void rgSCHUtlPdcchInit(cell, subFrm, nCce)
666 RgSchPdcchInfo *pdcchInfo;
668 Inst inst = cell->instIdx;
672 pdcchInfo = &subFrm->pdcchInfo;
673 while(pdcchInfo->pdcchs.first != NULLP)
675 pdcch = (RgSchPdcch *)pdcchInfo->pdcchs.first->node;
676 cmLListDelFrm(&pdcchInfo->pdcchs, pdcchInfo->pdcchs.first);
677 cmLListAdd2Tail(&cell->pdcchLst, &pdcch->lnk);
680 cmLListInit(&pdcchInfo->pdcchs);
683 subFrm->relPdcch = NULLP;
686 cceMapSz = ((pdcchInfo->nCce + 7) >> 3);
688 /* The bitMap array size is the number of ceiling(CCEs/8) */
689 /* If nCce received is not the same as the one stored in
690 * pdcchInfo, free the pdcchInfo map */
692 if(pdcchInfo->nCce != nCce)
696 rgSCHUtlFreeSBuf(inst, (Data **)(&(pdcchInfo->map)), cceMapSz);
698 pdcchInfo->nCce = nCce;
699 cceMapSz = ((pdcchInfo->nCce + 7) >> 3);
700 rgSCHUtlAllocSBuf(inst, (Data **)&pdcchInfo->map,
702 if (pdcchInfo->map == NULLP)
704 /* Generate log error here */
709 memset(subFrm->pdcchInfo.map, 0, cceMapSz);
710 /* If nCce is not exactly same as the bitMap size(no of bits allocated
711 * to represent the Cce's, then mark the extra bits as unavailable
712 extra bits = (((pdcchInfo->nCce + 7) >> 3)*8) - pdcchInfo->nCce
713 The last byte of bit map = subFrm->pdcchInfo.map[((pdcchInfo->nCce + 7) >> 3) - 1]
714 NOTE : extra bits are most significant of the last byte eg. */
715 extraBits = (cceMapSz)*8 - pdcchInfo->nCce;
716 subFrm->pdcchInfo.map[cceMapSz - 1] |=
717 ((1 << extraBits) - 1) << (8 - extraBits);
721 /* LTE_ADV_FLAG_REMOVED_START */
723 * @brief This function frees Pool
726 * Function: rgSchSFRTotalPoolFree
728 * Invoked by: rgSchSFRTotalPoolInit
730 * @param[in] RgSchCellCb* cell
731 * @param[in] RgSubFrm* subFrm
736 Void rgSchSFRTotalPoolFree
738 RgSchSFRTotalPoolInfo *sfrTotalPoolInfo,
742 Void rgSchSFRTotalPoolFree(sfrTotalPoolInfo, cell)
743 RgSchSFRTotalPoolInfo *sfrTotalPoolInfo;
750 /*Deinitialise if these cc pools and ce pools are already existent*/
751 l = &sfrTotalPoolInfo->ccPool;
755 /*REMOVING Cell Centred POOLS IF ANY*/
756 n = cmLListDelFrm(l, n);
758 /* Deallocate buffer */
759 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(n->node)), sizeof(RgSchSFRPoolInfo));
761 /* Deallocate buffer */
762 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(n)), sizeof(CmLList));
766 /*REMOVING Cell Edged POOLS IF ANY*/
767 l = &sfrTotalPoolInfo->cePool;
771 n = cmLListDelFrm(l, n);
773 /* Deallocate buffer */
774 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(n->node)), sizeof(RgSchSFRPoolInfo));
776 /* Deallocate buffer */
777 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(n)), sizeof(CmLList));
784 * @brief This function resets temporary variables in Pool
787 * Function: rgSchSFRResetPoolVariables
789 * Invoked by: rgSCHSFRUtlTotalPoolInit
791 * @param[in] RgSchCellCb* cell
792 * @param[in] RgSubFrm* subFrm
797 S16 rgSchSFRTotalPoolInit
803 static Void rgSchSFRTotalPoolInit(cell, sf)
808 /* Initialise the variables */
809 RgSchSFRPoolInfo *sfrCCPool;
810 RgSchSFRPoolInfo *sfrCEPool;
813 CmLList *temp = NULLP;
816 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo, cell);
817 sf->sfrTotalPoolInfo.CCPool1BwAvlbl = 0;
818 sf->sfrTotalPoolInfo.CCPool2BwAvlbl = 0;
819 sf->sfrTotalPoolInfo.CEPoolBwAvlbl = 0;
820 sf->sfrTotalPoolInfo.CC1 = FALSE;
821 sf->sfrTotalPoolInfo.CC2 = FALSE;
822 /*Initialise the CE Pools*/
823 cmLListInit (&(sf->sfrTotalPoolInfo.cePool));
825 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp, sizeof(CmLList));
828 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,
829 "CE Pool memory allocation FAILED for cell");
830 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo, cell);
834 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp->node, sizeof(RgSchSFRPoolInfo));
837 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,
838 "CE Pool memory allocation FAILED for cell ");
839 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
843 l = &sf->sfrTotalPoolInfo.cePool;
844 cmLListAdd2Tail(l, temp);
846 /*Initialise Bandwidth and startRB and endRB for each pool*/
849 /* Initialise the CE Pools */
850 sfrCEPool = (RgSchSFRPoolInfo*)n->node;
852 sfrCEPool->poolstartRB = cell->lteAdvCb.sfrCfg.cellEdgeRbRange.startRb;
853 sfrCEPool->poolendRB = cell->lteAdvCb.sfrCfg.cellEdgeRbRange.endRb;
854 sfrCEPool->bw = sfrCEPool->poolendRB - sfrCEPool->poolstartRB + 1;
855 sf->sfrTotalPoolInfo.CEPoolBwAvlbl = sfrCEPool->bw;
857 sfrCEPool->bwAlloced = 0;
858 sfrCEPool->type2Start = sfrCEPool->poolstartRB;
859 sfrCEPool->type2End = RGSCH_CEIL(sfrCEPool->poolstartRB, cell->rbgSize);
860 sfrCEPool->type0End = ((sfrCEPool->poolendRB + 1) / cell->rbgSize) - 1;
861 sfrCEPool->pwrHiCCRange.startRb = 0;
862 sfrCEPool->pwrHiCCRange.endRb = 0;
864 /*Initialise CC Pool*/
865 cmLListInit (&(sf->sfrTotalPoolInfo.ccPool));
867 /*Add memory and Update CCPool*/
868 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp, sizeof(CmLList));
871 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,
872 "CC Pool memory allocation FAILED for cell ");
873 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
877 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp->node, sizeof(RgSchSFRPoolInfo));
880 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,
881 "CC Pool memory allocation FAILED for cell ");
882 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
886 l = &sf->sfrTotalPoolInfo.ccPool;
887 cmLListAdd2Tail(l, temp);
889 /*Initialise Bandwidth and startRB and endRB for each pool*/
890 if(sfrCEPool->poolstartRB)
893 sfrCCPool = (RgSchSFRPoolInfo*)n->node;
895 sfrCCPool->poolstartRB = 0;
896 sfrCCPool->poolendRB = sfrCEPool->poolstartRB - 1;
897 sfrCCPool->bw = sfrCCPool->poolendRB - sfrCCPool->poolstartRB + 1;
898 sf->sfrTotalPoolInfo.CCPool1BwAvlbl = sfrCCPool->bw;
899 sfrCCPool->bwAlloced = 0;
900 sfrCCPool->type2Start = 0;
901 sfrCCPool->type2End = 0;
902 sfrCCPool->type0End = ((sfrCCPool->poolendRB + 1) / cell->rbgSize) - 1;
903 sf->sfrTotalPoolInfo.CC1 = TRUE;
904 sfrCCPool->pwrHiCCRange.startRb = 0;
905 sfrCCPool->pwrHiCCRange.endRb = 0;
910 sfrCCPool = (RgSchSFRPoolInfo*)n->node;
912 sfrCCPool->poolstartRB = sfrCEPool->poolendRB + 1;
913 sfrCCPool->poolendRB = sf->bw - 1;
914 sfrCCPool->bw = sfrCCPool->poolendRB - sfrCCPool->poolstartRB + 1;
915 sf->sfrTotalPoolInfo.CCPool2BwAvlbl = sfrCCPool->bw;
916 sfrCCPool->CCPool2Exists = TRUE;
917 sfrCCPool->bwAlloced = 0;
918 sfrCCPool->type2Start = sfrCCPool->poolstartRB;
919 sfrCCPool->type2End = RGSCH_CEIL(sfrCCPool->poolstartRB, cell->rbgSize);
920 sfrCCPool->type0End = ((sfrCCPool->poolendRB + 1) / cell->rbgSize) - 1;
921 sf->sfrTotalPoolInfo.CC2 = TRUE;
922 sfrCEPool->adjCCPool = sfrCCPool; /* SFR_FIX */
923 sfrCCPool->pwrHiCCRange.startRb = 0;
924 sfrCCPool->pwrHiCCRange.endRb = 0;
927 if((sfrCEPool->poolendRB != sf->bw - 1) && (!sfrCCPool->poolstartRB))
929 /*Add memory and Update CCPool*/
930 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp, sizeof(CmLList));
933 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,
934 "CC Pool memory allocation FAILED for cell ");
935 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
939 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp->node, sizeof(RgSchSFRPoolInfo));
942 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,
943 "CC Pool memory allocation FAILED for cell ");
944 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
948 cmLListAdd2Tail(l, temp);
951 sfrCCPool = (RgSchSFRPoolInfo*)n->node;
953 sfrCCPool->poolstartRB = sfrCEPool->poolendRB + 1;
954 sfrCCPool->poolendRB = sf->bw - 1;
955 sfrCCPool->bw = sfrCCPool->poolendRB - sfrCCPool->poolstartRB + 1;
956 sf->sfrTotalPoolInfo.CCPool2BwAvlbl = sfrCCPool->bw;
957 sfrCCPool->CCPool2Exists = TRUE;
958 sfrCCPool->bwAlloced = 0;
959 sfrCCPool->type2Start = sfrCCPool->poolstartRB;
960 sfrCCPool->type2End = RGSCH_CEIL(sfrCCPool->poolstartRB, cell->rbgSize);
961 sfrCCPool->type0End = ((sfrCCPool->poolendRB + 1) / cell->rbgSize) - 1;
962 sf->sfrTotalPoolInfo.CC2 = TRUE;
963 sfrCEPool->adjCCPool = sfrCCPool; /* SFR_FIX */
964 sfrCCPool->pwrHiCCRange.startRb = 0;
965 sfrCCPool->pwrHiCCRange.endRb = 0;
968 sf->sfrTotalPoolInfo.CCRetx = FALSE;
969 sf->sfrTotalPoolInfo.CERetx = FALSE;
971 sf->sfrTotalPoolInfo.ccBwFull = FALSE;
972 sf->sfrTotalPoolInfo.ceBwFull = FALSE;
973 sf->sfrTotalPoolInfo.isUeCellEdge = FALSE;
977 * @brief This function resets temporary variables in RNTP Prepration
980 * Function: rgSchDSFRRntpInfoInit
982 * Invoked by: rgSCHSFRUtlTotalPoolInit
984 * @param[in] TknStrOSXL* rntpPtr
985 * @param[in] RgSubFrm* subFrm
990 S16 rgSchDSFRRntpInfoInit
997 static Void rgSchDSFRRntpInfoInit(rntpPtr, cell, bw)
1003 Inst inst = cell->instIdx;
1006 rntpPtr->pres = PRSNT_NODEF;
1008 len = (bw % 8 == 0) ? (bw/8) : (bw/8 + 1);
1012 /* Allocate memory for "scheduled UE" Info */
1013 if((rgSCHUtlAllocSBuf(inst, (Data**)&(rntpPtr->val),
1014 (len * sizeof(uint8_t)))) != ROK)
1016 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,"Memory allocation FAILED for RNTP Alloc");
1024 * @brief This function release RNTP pattern from slot and Cell
1027 * Function: rgSchDSFRRntpInfoFree
1029 * Invoked by: rgSCHSFRUtlTotalPoolInit
1031 * @param[in] TknStrOSXL* rntpPtr
1032 * @param[in] RgSubFrm* subFrm
1037 S16 rgSchDSFRRntpInfoFree
1039 TknStrOSXL *rntpPtr,
1044 static Void rgSchDSFRRntpInfoFree(rntpPtr, cell, bw)
1045 TknStrOSXL *rntpPtr;
1050 Inst inst = cell->instIdx;
1053 len = (bw % 8 == 0) ? (bw/8) : (bw/8 + 1);
1055 if(rntpPtr->pres == PRSNT_NODEF)
1057 rgSCHUtlFreeSBuf(inst, (Data **)(&(rntpPtr->val)),(len * sizeof(uint8_t)));
1058 rntpPtr->pres = NOTPRSNT;
1066 * @brief This function resets temporary variables in Pool
1069 * Function: rgSchSFRResetPoolVariables
1070 * Purpose: Initialise the dynamic variables in each pool.
1071 * Reset bwAlloced, bwAssigned, type2End, type0End, type2Start
1072 * Invoked by: rgSCHSFRUtlTotalPoolReset
1074 * @param[in] RgSchCellCb* cell
1075 * @param[in] RgSchSFRPoolInfo *pool
1080 static Void rgSchSFRResetPoolVariables
1083 RgSchSFRPoolInfo *pool
1086 static Void rgSchSFRResetPoolVariables(cell, pool)
1088 RgSchSFRPoolInfo *pool;
1092 pool->bwAlloced = 0;
1094 /*type0end will be the last RBG in pool with all available RBs*/
1095 pool->type0End = (((pool->poolendRB + 1)/cell->rbgSize) - 1);
1097 /*type2end will be the first RBG in pool with all available RBs*/
1098 pool->type2End = RGSCH_CEIL(pool->poolstartRB, cell->rbgSize);
1099 pool->type2Start = pool->poolstartRB;
1100 pool->bw = pool->poolendRB - pool->poolstartRB + 1;
1105 * @brief This function resets SFR Pool information for frame
1109 * Function: rgSCHSFRUtlTotalPooReset
1110 * Purpose: Update the dynamic variables in each pool as they will be modified in each slot.
1111 * Dont modify the static variables like startRB, endRB, BW
1112 * Invoked by: rgSCHUtlSubFrmPut
1114 * @param[in] RgSchCellCb* cell
1115 * @param[in] RgSchDlSf* subFrm
1120 static Void rgSCHSFRUtlTotalPoolReset
1126 static Void rgSCHSFRUtlTotalPoolReset(cell, subFrm)
1131 RgSchSFRTotalPoolInfo *totalPoolInfo = &subFrm->sfrTotalPoolInfo;
1132 CmLListCp *ccPool = &totalPoolInfo->ccPool;
1133 CmLListCp *cePool = &totalPoolInfo->cePool;
1134 CmLList *node = NULLP;
1135 RgSchSFRPoolInfo *tempPool = NULLP;
1137 totalPoolInfo->ccBwFull = FALSE;
1138 totalPoolInfo->ceBwFull = FALSE;
1139 totalPoolInfo->isUeCellEdge = FALSE;
1140 totalPoolInfo->CCPool1BwAvlbl = 0;
1141 totalPoolInfo->CCPool2BwAvlbl = 0;
1142 totalPoolInfo->CEPoolBwAvlbl = 0;
1143 totalPoolInfo->CCRetx = FALSE;
1144 totalPoolInfo->CERetx = FALSE;
1146 node = ccPool->first;
1149 tempPool = (RgSchSFRPoolInfo *)(node->node);
1151 rgSchSFRResetPoolVariables(cell, tempPool);
1152 if(tempPool->poolstartRB == 0)
1153 totalPoolInfo->CCPool1BwAvlbl = tempPool->bw;
1155 totalPoolInfo->CCPool2BwAvlbl = tempPool->bw;
1158 node = cePool->first;
1161 tempPool = (RgSchSFRPoolInfo *)(node->node);
1163 rgSchSFRResetPoolVariables(cell, tempPool);
1164 totalPoolInfo->CEPoolBwAvlbl = tempPool->bw;
1169 /* LTE_ADV_FLAG_REMOVED_END */
1171 * @brief This function appends PHICH information for frame
1175 * Function: rgSCHUtlAddPhich
1176 * Purpose: This function appends PHICH information for
1181 * @param[in] RgSchCellCb* cell
1182 * @param[in] RgSubFrm* subFrm
1183 * @param[in] uint8_t hqFeedBack
1184 * @param[in] uint8_t nDmrs
1185 * @param[in] uint8_t rbStart
1192 S16 rgSCHUtlAddPhich
1195 CmLteTimingInfo frm,
1202 S16 rgSCHUtlAddPhich(cell, frm, hqFeedBack, nDmrs, rbStart, iPhich)
1204 CmLteTimingInfo frm;
1212 S16 rgSCHUtlAddPhich
1215 CmLteTimingInfo frm,
1222 S16 rgSCHUtlAddPhich(cell, frm, hqFeedBack, nDmrs, rbStart, isForMsg3)
1224 CmLteTimingInfo frm;
1235 Inst inst = cell->instIdx;
1237 dlSf = rgSCHUtlSubFrmGet(cell, frm);
1238 RGSCH_PHICH_ALLOC(inst, phich,sizeof(RgSchPhich), ret);
1242 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId, " rgSCHUtlAddPhich(): "
1243 "Allocation of RgSchPhich failed");
1247 RGSCH_INITPHICH(phich, hqFeedBack, nDmrs, rbStart, iPhich);
1249 RGSCH_INITPHICH(phich, hqFeedBack, nDmrs, rbStart, isForMsg3); /*SR_RACH_STATS */
1251 cmLListAdd2Tail(&dlSf->phichInfo.phichs, &phich->lnk);
1253 } /* rgSCHUtlAddPhich */
1256 * @brief This function resets PHICH information for frame
1260 * Function: rgSCHUtlPhichReset
1261 * Purpose: This function initializes PHICH information for
1262 * a slot. It removes the list of PHICHs allocated
1263 * in the prior use of this slot structure.
1265 * Invoked by: rgSCHUtlSubFrmPut
1267 * @param[in] RgSchCellCb* cell
1268 * @param[in] RgSubFrm* subFrm
1273 static Void rgSCHUtlPhichReset
1279 static Void rgSCHUtlPhichReset(cell, subFrm)
1284 RgSchPhichInfo *phichInfo;
1289 phichInfo = &subFrm->phichInfo;
1290 while(phichInfo->phichs.first != NULLP)
1292 phich = (RgSchPhich *)phichInfo->phichs.first->node;
1293 cmLListDelFrm(&phichInfo->phichs, phichInfo->phichs.first);
1294 RGSCH_PHICH_FREE(cell->instIdx, phich, sizeof(RgSchPhich));
1296 cmLListInit(&phichInfo->phichs);
1298 } /* rgSCHUtlPhichReset */
1302 * @brief This function returns slot data structure for a cell
1306 * Function: rgSCHUtlSubFrmGet
1307 * Purpose: This function resets the slot data structure
1308 * when the slot is released
1310 * Invoked by: scheduler
1312 * @param[in] RgSubFrm subFrm
1317 RgSchDlSf* rgSCHUtlSubFrmGet
1323 RgSchDlSf* rgSCHUtlSubFrmGet(cell, frm)
1325 CmLteTimingInfo frm;
1332 dlIdx = rgSCHUtlGetDlSfIdx(cell, &frm);
1333 //RGSCH_ARRAY_BOUND_CHECK(cell->instIdx, cell->subFrms, dlIdx);
1334 sf = cell->subFrms[dlIdx];
1336 /* Changing the idexing
1337 so that proper slot is selected */
1338 dlIdx = (((frm.sfn & 1) * RGSCH_NUM_SUB_FRAMES) + (frm.slot % RGSCH_NUM_SUB_FRAMES));
1339 RGSCH_ARRAY_BOUND_CHECK(cell->instIdx, cell->subFrms, dlIdx);
1340 sf = cell->subFrms[dlIdx];
1350 * @brief This function returns slot data structure for a cell
1354 * Function: rgSCHUtlSubFrmPut
1355 * Purpose: This function resets the slot data structure
1356 * when the slot is released
1358 * Invoked by: scheduler
1360 * @param[in] RgSubFrm subFrm
1365 Void rgSCHUtlSubFrmPut
1371 Void rgSCHUtlSubFrmPut(cell, sf)
1380 /* Release all the held PDCCH information */
1381 rgSCHUtlPdcchInit(cell, sf, sf->nCce);
1383 /* Release all the held PDCCH information */
1384 rgSCHUtlPdcchInit(cell, sf, cell->nCce);
1386 rgSCHUtlPhichReset(cell, sf);
1388 /* Reset the bw allocated. */
1391 /* Setting allocated bandwidth to SPS bandwidth for non-SPS RB allocator */
1392 sf->bwAlloced = ((cell->spsCellCfg.maxSpsDlBw +
1393 cell->rbgSize - 1)/cell->rbgSize) * cell->rbgSize;
1394 if (sf->bwAlloced > sf->bw)
1396 sf->bwAlloced = sf->bw;
1398 sf->spsAllocdBw = 0;
1399 sf->type2Start = sf->bwAlloced;
1400 memset( &sf->dlSfAllocInfo, 0, sizeof(RgSchDlSfAllocInfo));
1403 /* Fix for ccpu00123918*/
1405 /* LTE_ADV_FLAG_REMOVED_START */
1406 /* dsfr_pal_fixes ** 21-March-2013 ** SKS */
1407 if (cell->lteAdvCb.dsfrCfg.status == RGR_ENABLE)
1409 memset(sf->rntpInfo.val, 0, sf->rntpInfo.len);
1411 /* LTE_ADV_FLAG_REMOVED_END */
1414 /*[ccpu00138609]-ADD-Reset the CCCH UE counter */
1417 /* Non DLFS scheduling using Type0 RA requires the following
1418 * parameter's tracking */
1419 /* Type 2 localized allocations start from 0th RBG and onwards */
1420 /* Type 0 allocations start from last RBG and backwards*/
1424 sf->type2End = RGSCH_CEIL(sf->bwAlloced,cell->rbgSize);
1426 sf->type0End = cell->noOfRbgs - 1;
1427 /* If last RBG is of incomplete size then special handling */
1428 (sf->bw % cell->rbgSize == 0)? (sf->lstRbgDfct = 0) :
1429 (sf->lstRbgDfct = cell->rbgSize - (sf->bw % cell->rbgSize));
1430 /* This resets the allocation for BCCH and PDCCH */
1432 /* TODO we need to move this reset for emtc functions */
1433 if(!(cell->emtcEnable))
1442 sf->bcch.pdcch = NULLP;
1443 sf->pcch.pdcch = NULLP;
1445 noRaRsps = RGSCH_MAX_TDD_RA_RSP_ALLOC;
1447 noRaRsps = RGSCH_MAX_RA_RSP_ALLOC;
1449 for (i = 0; i < noRaRsps; i++)
1451 sf->raRsp[i].pdcch = NULLP;
1452 cmLListInit(&(sf->raRsp[i].raRspLst));
1454 /* LTE_ADV_FLAG_REMOVED_START */
1455 if (cell->lteAdvCb.sfrCfg.status == RGR_ENABLE)
1457 rgSCHSFRUtlTotalPoolReset(cell, sf);
1459 /* LTE_ADV_FLAG_REMOVED_END */
1461 cmLListInit(&sf->n1PucchResLst);
1465 sf->isCceFailure = FALSE;
1466 sf->dlUlBothCmplt = 0;
1472 * @brief This function computes log N (32 bit Unsigned) to the base 2
1476 * Function: rgSCHUtlLog32bitNbase2
1477 * Purpose: This function computes log N (32 bit Unsigned) to the base 2.
1478 * For n= 0,1 ret = 0.
1480 * Invoked by: Scheduler
1482 * @param[in] uint32_t n
1487 uint8_t rgSCHUtlLog32bitNbase2
1492 uint8_t rgSCHUtlLog32bitNbase2(n)
1496 uint32_t b[] = {0x2, 0xc, 0xf0, 0xff00, 0xffff0000};
1497 uint32_t s[] = {1, 2, 4, 8, 16};
1501 for (i=4; i >= 0; i--)
1515 * @brief This function is a wrapper to call scheduler specific API.
1519 * Function: rgSCHUtlDlRelPdcchFbk
1520 * Purpose: Calls scheduler's handler for SPS release PDCCH feedback
1525 * @param[in] RgSchCellCb *cell
1526 * @param[in] RgSchUeCb *ue
1527 * @param[in] uint8_t isAck
1532 Void rgSCHUtlDlRelPdcchFbk
1539 Void rgSCHUtlDlRelPdcchFbk(cell, ue, isAck)
1545 cell->sc.apis->rgSCHDlRelPdcchFbk(cell, ue, isAck);
1552 * @brief This function is a wrapper to call scheduler specific API.
1556 * Function: rgSCHUtlDlProcAck
1557 * Purpose: Calls scheduler's handler to process Ack
1562 * @param[in] RgSchCellCb *cell
1563 * @param[in] RgSchDlHqProcCb *hqP
1568 Void rgSCHUtlDlProcAck
1571 RgSchDlHqProcCb *hqP
1574 Void rgSCHUtlDlProcAck(cell, hqP)
1576 RgSchDlHqProcCb *hqP;
1579 cell->sc.apis->rgSCHDlProcAck(cell, hqP);
1584 * @brief CRNTI CE Handler
1588 * Function : rgSCHUtlHdlCrntiCE
1590 * - Call scheduler common API
1593 * @param[in] RgSchCellCb *cell
1594 * @param[in] RgSchUeCb *ue
1595 * @param[out] RgSchErrInfo *err
1599 Void rgSCHUtlHdlCrntiCE
1605 Void rgSCHUtlHdlCrntiCE(cell, ue)
1611 cell->sc.apis->rgSCHHdlCrntiCE(cell, ue);
1613 } /* rgSCHUtlHdlCrntiCE */
1614 #endif /* LTEMAC_SPS */
1616 /***********************************************************
1618 * Func : rgSCHUtlCalcTotalRegs
1620 * Desc : Calculate total REGs, given a bandwidth, CFI
1621 * and number of antennas.
1623 * Ret : Total REGs (uint16_t)
1625 * Notes: Could optimise if bw values are limited
1626 * (taken from RRC spec) by indexing values from
1628 * Input values are not validated. CFI is assumed
1633 **********************************************************/
1635 static uint16_t rgSCHUtlCalcTotalRegs
1643 static uint16_t rgSCHUtlCalcTotalRegs(bw, cfi, numAntna, isEcp)
1652 /*ccpu00116757- removed check for (ERRCLASS & ERRCLS_DEBUG)*/
1658 /* Refer 36.211 section 6.10.1.2
1659 * For symbols 2 and 4, the REGs per RB will be based on cyclic prefix
1660 * and number of antenna ports.
1661 * For symbol 1, there are 2 REGs per RB always. Similarly symbol 3
1665 /*CR changes [ccpu00124416] - MOD*/
1668 regs = bw * RGSCH_NUM_REGS_4TH_SYM_EXT_CP;
1672 regs = bw * RGSCH_NUM_REGS_4TH_SYM_NOR_CP;
1675 regs += bw * RGSCH_NUM_REGS_3RD_SYM;
1677 /*CR changes [ccpu00124416] - MOD using number of antenna ports*/
1678 regs += (numAntna == RGSCH_NUM_ANT_PORT_FOUR) ? \
1679 (bw * RGSCH_NUM_REGS_2ND_SYM_FOUR_ANT_PORT) : \
1680 (bw * RGSCH_NUM_REGS_2ND_SYM_1OR2_ANT_PORT);
1681 default: /* case 1 */
1682 regs += bw * RGSCH_NUM_REGS_1ST_SYM;
1687 /***********************************************************
1689 * Func : rgSCHUtlCalcPhichRegs
1691 * Desc : Calculates number of PHICH REGs
1693 * Ret : Number of PHICH REGs (uint8_t)
1695 * Notes: ng6 is Ng multiplied by 6
1699 **********************************************************/
1701 static uint16_t rgSCHUtlCalcPhichRegs
1707 static uint16_t rgSCHUtlCalcPhichRegs(bw, ng6)
1712 /* ccpu00115330: Corrected the calculation for number of PHICH groups*/
1713 return (RGSCH_CEIL((bw * ng6) ,(8 * 6)) * RGSCH_NUM_REG_PER_PHICH_GRP);
1718 * @brief Calculates total CCEs (N_cce)
1722 * Function: rgSCHUtlCalcNCce
1723 * Purpose: This function calculates and returns total CCEs for a
1724 * cell, given the following: bandwidth, Ng configuration
1725 * (multiplied by six), cfi (actual number of control
1726 * symbols), m factor for PHICH and number of antennas.
1728 * Invoked by: Scheduler
1730 * @param[in] uint8_t bw
1731 * @param[in] uint8_t ng6
1732 * @param[in] uint8_t cfi
1733 * @param[in] uint8_t mPhich
1734 * @param[in] uint8_t numAntna
1735 * @param[in] Bool isEcp
1736 * @return N_cce (uint8_t)
1740 uint8_t rgSCHUtlCalcNCce
1750 uint8_t rgSCHUtlCalcNCce(bw, ng, cfi, mPhich, numAntna, isEcp)
1764 /*ccpu00116757- removed check for (ERRCLASS & ERRCLS_DEBUG)*/
1768 case RGR_NG_ONESIXTH:
1783 totalRegs = rgSCHUtlCalcTotalRegs(bw, cfi, numAntna, isEcp);
1784 phichRegs = rgSCHUtlCalcPhichRegs(bw, ng6);
1785 cceRegs = totalRegs - mPhich*phichRegs - RGSCH_NUM_PCFICH_REG;
1787 return ((uint8_t)(cceRegs/RGSCH_NUM_REG_PER_CCE));
1792 * @brief Calculates total CCEs (N_cce)
1796 * Function: rgSCHUtlCalcNCce
1797 * Purpose: This function calculates and returns total CCEs for a
1798 * cell, given the following: bandwidth, Ng configuration
1799 * (multiplied by six), cfi (actual number of control
1800 * symbols) and number of antennas.
1802 * Invoked by: Scheduler
1804 * @param[in] uint8_t bw
1805 * @param[in] uint8_t ng6
1806 * @param[in] uint8_t cfi
1807 * @param[in] uint8_t numAntna
1808 * @return N_cce (uint8_t)
1812 uint8_t rgSCHUtlCalcNCce
1821 uint8_t rgSCHUtlCalcNCce(bw, ng, cfi, numAntna, isEcp)
1834 /*ccpu00116757- removed check for (ERRCLASS & ERRCLS_DEBUG)*/
1838 case RGR_NG_ONESIXTH:
1853 totalRegs = rgSCHUtlCalcTotalRegs(bw, cfi, numAntna, isEcp);
1854 phichRegs = rgSCHUtlCalcPhichRegs(bw, ng6);
1855 cceRegs = totalRegs - phichRegs - RGSCH_NUM_PCFICH_REG;
1857 return ((uint8_t)(cceRegs/RGSCH_NUM_REG_PER_CCE));
1862 * @brief Returns PHICH info associated with an uplink
1863 * HARQ process allocation
1867 * Function: rgSCHUtlGetPhichInfo
1868 * Purpose: This function returns PHICH info associated with
1869 * an uplink HARQ process allocation. PHICH info
1870 * comprises RB start and N_dmrs.
1872 * @param[in] RgSchUlHqProcCb *hqProc
1873 * @param[out] uint8_t *rbStartRef
1874 * @param[out] uint8_t *nDmrsRef
1879 S16 rgSCHUtlGetPhichInfo
1881 RgSchUlHqProcCb *hqProc,
1882 uint8_t *rbStartRef,
1887 S16 rgSCHUtlGetPhichInfo(hqProc, rbStartRef, nDmrsRef, iPhich)
1888 RgSchUlHqProcCb *hqProc;
1889 uint8_t *rbStartRef;
1895 S16 rgSCHUtlGetPhichInfo
1897 RgSchUlHqProcCb *hqProc,
1898 uint8_t *rbStartRef,
1902 S16 rgSCHUtlGetPhichInfo(hqProc, rbStartRef, nDmrsRef)
1903 RgSchUlHqProcCb *hqProc;
1904 uint8_t *rbStartRef;
1912 if ((hqProc != NULLP) && (hqProc->alloc != NULLP))
1914 *rbStartRef = hqProc->alloc->grnt.rbStart;
1915 *nDmrsRef = hqProc->alloc->grnt.nDmrs;
1917 *iPhich = hqProc->iPhich;
1925 * @brief Returns uplink grant information required to permit
1926 * PHY to receive data
1930 * Function: rgSCHUtlAllocRcptInfo
1931 * Purpose: Given an uplink allocation, this function returns
1932 * uplink grant information which is needed by PHY to
1933 * decode data sent from UE. This information includes:
1938 * @param[in] RgSchUlAlloc *alloc
1939 * @param[out] uint8_t *rbStartRef
1940 * @param[out] uint8_t *numRbRef
1941 * @param[out] uint8_t *rvRef
1942 * @param[out] uint16_t *size
1943 * @param[out] TfuModScheme *modType
1944 * @param[out] Bool *isRtx
1945 * @param[out] uint8_t *nDmrs
1946 * @param[out] Bool *ndi
1947 * @param[out] uint8_t *hqPId
1951 S16 rgSCHUtlAllocRcptInfo
1953 RgSchUlAlloc *alloc,
1956 uint8_t *rbStartRef,
1960 TfuModScheme *modType,
1967 S16 rgSCHUtlAllocRcptInfo(alloc, rnti, iMcsRef, rbStartRef, numRbRef,
1968 rvRef, size, modType, isRtx, nDmrs, ndi,
1970 RgSchUlAlloc *alloc;
1973 uint8_t *rbStartRef;
1977 TfuModScheme *modType;
1984 /* Modulation order for 16qam UEs would be
1985 * min(4,modulation order in grant). Please refer to 36.213-8.6.1*/
1986 CmLteUeCategory ueCtgy;
1988 #if (ERRCLASS & ERRCLS_DEBUG)
1989 if ((alloc == NULLP) || (alloc->hqProc == NULLP))
1995 if ( !alloc->forMsg3 )
1997 if ( ((alloc->ue) == NULLP) || (RG_SCH_CMN_GET_UE(alloc->ue, alloc->ue->cell) == NULLP))
1999 RLOG_ARG2(L_ERROR,DBG_CELLID,alloc->ue->cell->cellId,
2000 "Failed: ue->sch is null RNTI:%d,isRetx=%d",
2001 alloc->rnti, alloc->grnt.isRtx);
2004 ueCtgy = (RG_SCH_CMN_GET_UE_CTGY(alloc->ue));
2007 *iMcsRef = alloc->grnt.iMcs;
2008 *rbStartRef = alloc->grnt.rbStart;
2009 *numRbRef = alloc->grnt.numRb;
2010 *rvRef = rgRvTable[alloc->hqProc->rvIdx];
2011 *rnti = alloc->rnti;
2012 *size = alloc->grnt.datSz;
2013 *modType = (alloc->forMsg3)? alloc->grnt.modOdr:
2014 ((ueCtgy == CM_LTE_UE_CAT_5)?
2016 (RGSCH_MIN(RGSCH_QM_QPSK,alloc->grnt.modOdr)));
2017 *isRtx = alloc->grnt.isRtx;
2018 *nDmrs = alloc->grnt.nDmrs;
2019 *ndi = alloc->hqProc->ndi;
2020 *hqPId = alloc->hqProc->procId;
2026 * @brief Returns uplink grant information required to permit
2027 * PHY to receive data
2031 * Function: rgSCHUtlAllocRcptInfo
2032 * Purpose: Given an uplink allocation, this function returns
2033 * uplink grant information which is needed by PHY to
2034 * decode data sent from UE. This information includes:
2039 * @param[in] RgSchUlAlloc *alloc
2040 * @param[out] uint8_t *rbStartRef
2041 * @param[out] uint8_t *numRbRef
2042 * @param[out] uint8_t *rvRef
2043 * @param[out] uint16_t *size
2044 * @param[out] TfuModScheme *modType
2048 S16 rgSCHUtlAllocRcptInfo
2051 RgSchUlAlloc *alloc,
2052 CmLteTimingInfo *timeInfo,
2053 TfuUeUlSchRecpInfo *recpReq
2056 S16 rgSCHUtlAllocRcptInfo(cell, alloc, timeInfo, recpReq)
2058 RgSchUlAlloc *alloc;
2059 CmLteTimingInfo *timeInfo;
2060 TfuUeUlSchRecpInfo *recpReq;
2063 #if (ERRCLASS & ERRCLS_DEBUG)
2064 if ((alloc == NULLP) || (alloc->hqProc == NULLP))
2069 recpReq->size = alloc->grnt.datSz;
2070 recpReq->rbStart = alloc->grnt.rbStart;
2071 recpReq->numRb = alloc->grnt.numRb;
2072 /* Modulation order min(4,mod in grant) for 16 qam UEs.
2073 * Please refer to 36.213-8.6.1*/
2074 #ifdef FOUR_TX_ANTENNA
2075 recpReq->modType = (TfuModScheme)((alloc->forMsg3)?alloc->grnt.modOdr:
2076 (/*(alloc->ue->ueCatEnum == CM_LTE_UE_CAT_5)?
2077 alloc->grnt.modOdr: *//* Chandra:TmpFx-TM500 Cat5 with Only16QAM */
2078 (RGSCH_MIN(RGSCH_QM_QPSK,alloc->grnt.modOdr))));
2080 recpReq->modType = (TfuModScheme)((alloc->forMsg3)?alloc->grnt.modOdr:
2081 ((alloc->ue->ueCatEnum == CM_LTE_UE_CAT_5)?
2083 (RGSCH_MIN(RGSCH_QM_QPSK,alloc->grnt.modOdr))));
2085 recpReq->nDmrs = alloc->grnt.nDmrs;
2086 recpReq->hoppingEnbld = FALSE;
2087 recpReq->hoppingBits = 0;
2088 recpReq->isRtx = alloc->grnt.isRtx;
2089 recpReq->ndi = alloc->hqProc->ndi;
2090 recpReq->rv = rgRvTable[alloc->hqProc->rvIdx];
2092 recpReq->harqProcId = alloc->hqProc->procId;
2094 recpReq->harqProcId = rgSCHCmnGetUlHqProcIdx(timeInfo, cell);
2096 /* Transmission mode is SISO till Uplink MIMO is implemented. */
2097 recpReq->txMode = 0;
2098 /* This value needs to filled in in the case of frequency hopping. */
2099 recpReq->crntTxNb = 0;
2101 recpReq->mcs = alloc->grnt.iMcs;
2103 recpReq->rbgStart = alloc->grnt.vrbgStart;
2104 recpReq->numRbg = alloc->grnt.numVrbg;
2105 recpReq->xPUSCHRange = alloc->grnt.xPUSCHRange;
2106 //TODO_SID Need to check
2107 recpReq->nAntPortLayer = 0;
2108 recpReq->SCID = alloc->grnt.SCID;
2109 recpReq->PMI = alloc->grnt.PMI;
2110 recpReq->uciWoTBFlag = alloc->grnt.uciOnxPUSCH;
2113 recpReq->beamIndex = alloc->ue->ue5gtfCb.BeamId;
2118 if (!alloc->forMsg3)
2120 if (alloc->grnt.isRtx)
2122 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulRetxOccns++;
2126 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulTxOccns++;
2127 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulSumiTbs += \
2128 rgSCHCmnUlGetITbsFrmIMcs(alloc->grnt.iMcs);
2129 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulNumiTbs ++;
2130 cell->tenbStats->sch.ulSumiTbs += \
2131 rgSCHCmnUlGetITbsFrmIMcs(alloc->grnt.iMcs);
2132 cell->tenbStats->sch.ulNumiTbs ++;
2134 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulPrbUsg += alloc->grnt.numRb;
2135 cell->tenbStats->sch.ulPrbUsage[0] += alloc->grnt.numRb;
2138 /* ccpu00117050 - DEL - nSrs setting at rgSCHUtlAllocRcptInfo */
2145 * @brief This function initialises the PRACH slot occasions
2149 * Function: rgSCHUtlUpdPrachOcc
2150 * Purpose: This function updates the PRACH slots based on
2151 * RGR configuration.
2153 * Invoked by: Scheduler
2155 * @param[in] RgSchCellCb *cell
2156 * @param[in] RgrTddPrachInfo *cellCfg
2161 static Void rgSCHUtlUpdPrachOcc
2164 RgrTddPrachInfo *cellCfg
2167 static Void rgSCHUtlUpdPrachOcc(cell, cellCfg)
2169 RgrTddPrachInfo *cellCfg;
2178 /* In the 1st half frame */
2179 if(cellCfg->halfFrm == 0)
2184 /* In the 2nd half frame */
2190 for(idx = startIdx; idx < endIdx; idx++)
2192 if(rgSchTddUlDlSubfrmTbl[cell->ulDlCfgIdx][idx]
2193 == RG_SCH_TDD_UL_slot)
2195 if(cellCfg->ulStartSfIdx == count)
2197 size = cell->rachCfg.raOccasion.size;
2198 cell->rachCfg.raOccasion.slotNum[size] = idx;
2199 cell->rachCfg.raOccasion.size++;
2209 * @brief This function initialises the PRACH occasions
2213 * Function: rgSCHUtlPrachCfgInit
2214 * Purpose: This function initialises the PRACH occasions based on
2215 * RGR configuration.
2217 * Invoked by: Scheduler
2219 * @param[in] RgSchCellCb *cell
2220 * @param[in] RgrCellCfg *cellCfg
2225 Void rgSCHUtlPrachCfgInit
2231 Void rgSCHUtlPrachCfgInit(cell, cellCfg)
2233 RgrCellCfg *cellCfg;
2240 if(cellCfg->prachRscInfo.numRsc <= 0)
2242 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId, "Invalid"
2243 "PRACH resources Configuration ");
2247 /* Update SFN occasions */
2248 cell->rachCfg.raOccasion.sfnEnum =
2249 cellCfg->prachRscInfo.prachInfo[0].sfn;
2251 cell->rachCfg.raOccasion.size = 0;
2253 /* Update slot occasions */
2254 for(idx = 0; idx < cellCfg->prachRscInfo.numRsc; idx++)
2256 if(cellCfg->prachRscInfo.prachInfo[idx].freqIdx == 0)
2258 if(cellCfg->prachRscInfo.prachInfo[idx].halfFrm == 0)
2266 if(cellCfg->prachRscInfo.prachInfo[idx].ulStartSfIdx ==
2269 subfrmIdx = cell->rachCfg.raOccasion.size;
2270 cell->rachCfg.raOccasion.slotNum[subfrmIdx] = splFrm;
2271 cell->rachCfg.raOccasion.size++;
2275 rgSCHUtlUpdPrachOcc(cell,
2276 &cellCfg->prachRscInfo.prachInfo[idx]);
2284 * @brief This function performs RGR cell initialization
2288 * Function: rgSCHUtlRgrCellCfg
2289 * Purpose: This function initialises the cell with RGR configuration
2290 * and slot related initialization.
2292 * Invoked by: Scheduler
2294 * @param[in] RgSchCellCb *cell
2295 * @param[in] RgrCellCfg *cellCfg
2296 * @param[in] RgSchErrInfo *errInfo
2301 S16 rgSCHUtlRgrCellCfg
2304 RgrCellCfg *cellCfg,
2305 RgSchErrInfo *errInfo
2308 S16 rgSCHUtlRgrCellCfg(cell, cellCfg, errInfo)
2310 RgrCellCfg *cellCfg;
2311 RgSchErrInfo *errInfo;
2318 CmLteTimingInfo frm;
2319 uint8_t ulDlCfgIdx = cellCfg->ulDlCfgIdx;
2323 uint16_t bw; /*!< Number of RBs in the cell */
2325 memset(&frm,0,sizeof(CmLteTimingInfo));
2327 /* ccpu00132657-MOD- Determining DLSF array size independent of DELTAS */
2328 maxDlslots = rgSchTddNumDlSubfrmTbl[ulDlCfgIdx][RGSCH_NUM_SUB_FRAMES-1];
2329 maxslots = 2 * maxDlslots;
2330 cell->numDlSubfrms = maxslots;
2331 /* ACC-TDD <ccpu00130639> */
2332 cell->tddHqSfnCycle = -1;
2333 cell->ulDlCfgIdx = ulDlCfgIdx;
2335 /* PRACH Occasions Initialization */
2336 rgSCHUtlPrachCfgInit(cell, cellCfg);
2338 /* ccpu00132658- Moved out of below for loop since the updating rbgSize and
2339 * bw are independent of sfNum*/
2340 /* determine the RBG size and no of RBGs for the configured
2342 if (cell->bwCfg.dlTotalBw > 63)
2346 else if (cell->bwCfg.dlTotalBw > 26)
2350 else if (cell->bwCfg.dlTotalBw > 10)
2358 cell->noOfRbgs = RGSCH_CEIL(cell->bwCfg.dlTotalBw, cell->rbgSize);
2360 bw = cell->bwCfg.dlTotalBw;
2362 rgSCHUtlAllocSBuf(cell->instIdx,
2363 (Data **)&cell->subFrms, sizeof(RgSchDlSf *) * maxslots);
2364 if (cell->subFrms == NULLP)
2369 /* Create memory for each frame. */
2370 for(i = 0; i < maxslots; i++)
2372 while(rgSchTddUlDlSubfrmTbl[ulDlCfgIdx][sfNum] ==
2375 sfNum = (sfNum+1) % RGSCH_NUM_SUB_FRAMES;
2378 rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&sf, sizeof(RgSchDlSf));
2383 memset(sf, 0, sizeof(*sf));
2386 if (ROK != rgSCHLaaInitDlSfCb(cell, sf))
2394 /* Mark SPS bandwidth to be occupied */
2395 sf->bwAlloced = ((cellCfg->spsCfg.maxSpsDlBw +
2396 cell->rbgSize - 1)/cell->rbgSize) * cell->rbgSize;
2397 sf->spsAllocdBw = 0;
2398 sf->type2End = sf->bwAlloced/cell->rbgSize;
2401 /* Fix for ccpu00123918*/
2403 #endif /* LTEMAC_SPS */
2404 /* Initialize the ackNakRepQ here */
2405 #ifdef RG_MAC_MEASGAP
2406 cmLListInit (&(sf->ackNakRepQ));
2408 cell->subFrms[i] = sf;
2409 sfNum = (sfNum+1) % RGSCH_NUM_SUB_FRAMES;
2415 /* ccpu00117052 - MOD - Passing double pointer
2416 for proper NULLP assignment*/
2417 rgSCHUtlFreeSBuf(cell->instIdx,
2418 (Data **)(&(cell->subFrms[i-1])), sizeof(RgSchDlSf));
2420 rgSCHLaaDeInitDlSfCb(cell, sf);
2423 /* ccpu00117052 - MOD - Passing double pointer
2424 for proper NULLP assignment*/
2425 rgSCHUtlFreeSBuf(cell->instIdx,
2426 (Data **)(&(cell->subFrms)), sizeof(RgSchDlSf *) * maxslots);
2431 if (cell->sc.apis == NULLP)
2433 cell->sc.apis = &rgSchCmnApis;
2435 ret = cell->sc.apis->rgSCHRgrCellCfg(cell, cellCfg, errInfo);
2439 /* ccpu00132286- Removed deletion of sf nodes as the deletion will be
2440 * happening during CellDelete. Added return handling to provide negative
2445 /* Release the slots and thereby perform the initialization */
2446 for (i = 0; i < maxslots; i++)
2448 if((i > 0) && (i%maxDlslots == 0))
2453 frm.slot = cell->subFrms[i]->sfNum;
2454 rgSCHUtlDlRlsSubFrm(cell, frm);
2463 * @brief This function performs scheduler related cell creation
2467 * Function: rgSCHUtlRgrCellCfg
2468 * Purpose: This function creates the slots needed for the
2469 * cell. It then peforms init of the scheduler by calling
2470 * scheduler specific cell init function.
2472 * Invoked by: Scheduler
2474 * @param[in] RgSchCellCb *cell
2475 * @param[in] RgrCellCfg *cellCfg
2476 * @param[in] RgSchErrInfo *errInfo
2481 S16 rgSCHUtlRgrCellCfg
2484 RgrCellCfg *cellCfg,
2485 RgSchErrInfo *errInfo
2488 S16 rgSCHUtlRgrCellCfg(cell, cellCfg, errInfo)
2490 RgrCellCfg *cellCfg;
2491 RgSchErrInfo *errInfo;
2496 CmLteTimingInfo frm;
2498 Inst inst = cell->instIdx;
2499 /* LTE_ADV_FLAG_REMOVED_START */
2501 len = (uint16_t)((cell->bwCfg.dlTotalBw % 8 == 0) ? (cell->bwCfg.dlTotalBw/8) : (cell->bwCfg.dlTotalBw/8 + 1)); /*KW fix for LTE_ADV */
2502 /* LTE_ADV_FLAG_REMOVED_END */
2504 memset(&frm,0,sizeof(CmLteTimingInfo));
2506 /* determine the RBG size and no of RBGs for the configured
2508 if (cell->bwCfg.dlTotalBw > 63)
2512 else if (cell->bwCfg.dlTotalBw > 26)
2516 else if (cell->bwCfg.dlTotalBw > 10)
2524 cell->noOfRbgs = RGSCH_CEIL(cell->bwCfg.dlTotalBw, cell->rbgSize);
2525 /* Create memory for each frame. */
2526 /* Changing loop limit from
2527 RGSCH_NUM_SUB_FRAMES to RGSCH_NUM_DL_slotS */
2528 for(i = 0; i < RGSCH_NUM_DL_slotS; i++)
2530 rgSCHUtlAllocSBuf(inst, (Data **)&sf, sizeof(RgSchDlSf));
2535 memset(sf, 0, sizeof(*sf));
2538 if (ROK != rgSCHLaaInitDlSfCb(cell, sf))
2543 /* Doing MOD operation before assigning value of i */
2544 sf->sfNum = i % RGSCH_NUM_SUB_FRAMES;
2545 sf->bw = cell->bwCfg.dlTotalBw;
2546 /* Initialize the ackNakRepQ here */
2547 #ifdef RG_MAC_MEASGAP
2548 cmLListInit (&(sf->ackNakRepQ));
2550 cell->subFrms[i] = sf;
2551 /* LTE_ADV_FLAG_REMOVED_START */
2552 if (cell->lteAdvCb.dsfrCfg.status == RGR_ENABLE)
2554 /*initialize the RNTP Buffer*/
2555 if(rgSchDSFRRntpInfoInit(&sf->rntpInfo, cell, sf->bw))
2561 if (cell->lteAdvCb.sfrCfg.status == RGR_ENABLE)
2563 /*initialise the pools of CC and CE*/
2564 if(rgSchSFRTotalPoolInit(cell, sf))
2569 /* LTE_ADV_FLAG_REMOVED_END */
2572 /* LTE_ADV_FLAG_REMOVED_START */
2573 /* Allocate memory for "scheduled UE" Info */
2574 if (cell->lteAdvCb.dsfrCfg.status == RGR_ENABLE)
2576 if((rgSCHUtlAllocSBuf(inst, (Data**)&(cell->rntpAggrInfo.val),
2577 (len * sizeof(uint8_t)))) != ROK)
2579 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,"Memory allocation FAILED for RNTP Alloc");
2582 cell->rntpAggrInfo.pres = PRSNT_NODEF;
2583 cell->rntpAggrInfo.len = len;
2585 /* LTE_ADV_FLAG_REMOVED_END */
2587 /* Changing loop limit from
2588 RGSCH_NUM_SUB_FRAMES to RGSCH_NUM_DL_slotS */
2589 if (i != RGSCH_NUM_DL_slotS)
2593 /* ccpu00117052 - MOD - Passing double pointer
2594 for proper NULLP assignment*/
2595 rgSCHUtlFreeSBuf(inst, (Data **)(&(cell->subFrms[i-1])),
2598 rgSCHLaaDeInitDlSfCb(cell, sf);
2604 if (cell->sc.apis == NULLP)
2606 cell->sc.apis = &rgSchCmnApis;
2609 /* Release the slots and thereby perform the initialization */
2610 for (i = 0; i < RGSCH_NUM_DL_slotS; i++)
2612 if (i >= RGSCH_NUM_SUB_FRAMES)
2614 /* [ccpu00123828]-MOD-The below statement sfn += 1incorrectly modified
2615 * the value of sfn for i>=10 thru 19. Correct way is to assign
2619 frm.slot = i % RGSCH_NUM_SUB_FRAMES;
2620 rgSCHUtlDlRlsSubFrm(cell, frm);
2623 ret = cell->sc.apis->rgSCHRgrCellCfg(cell, cellCfg, errInfo);
2626 errInfo->errCause = RGSCHERR_SCH_CFG;
2630 if(cell->emtcEnable)
2632 /* TODO: Repetition framework in RGR and APP */
2633 if (rgSCHUtlEmtcResMngmtInit(
2635 RGSCH_IOT_PDSCH_POOLSZ, RGSCH_IOT_PDSCH_DELTA, cellCfg->bwCfg.dlTotalBw,
2636 RGSCH_IOT_PUSCH_POOLSZ, RGSCH_IOT_PUSCH_DELTA, RGSCH_IOT_PUSCH_MAXFREQSZ,
2637 RGSCH_IOT_PUCCH_POOLSZ, RGSCH_IOT_PUCCH_DELTA, RGSCH_IOT_PUCCH_MAXFREQSZ) != ROK)
2639 errInfo->errCause = RGSCHERR_SCH_CFG;
2651 * @brief This function performs the cell reconfiguration at RGR interface
2655 * Function: rgSCHUtlRgrCellRecfg
2656 * Purpose: This function updates the reconfigurable parameters
2657 * on the cell control block for the scheduler.
2659 * Invoked by: Scheduler
2661 * @param[in] RgSchCellCb *cell
2662 * @param[in] RgrCellCfg *cellCfg
2663 * @param[in] RgSchErrInfo *errInfo
2668 S16 rgSCHUtlRgrCellRecfg
2671 RgrCellRecfg *recfg,
2675 S16 rgSCHUtlRgrCellRecfg(cell, recfg, err)
2677 RgrCellRecfg *recfg;
2681 return (cell->sc.apis->rgSCHRgrCellRecfg(cell, recfg, err));
2687 * @brief This function returns the Y value of UE for a sub frame
2691 * Function: rgSCHUtlFreeCell
2692 * Purpose: This function updates the value of Y stored in the
2693 * UE control block. It uses the previously computed
2694 * value for computing for this slot.
2696 * Invoked by: Scheduler
2698 * @param[in] RgSchCellCb *cell
2703 S16 rgSCHUtlFreeCell
2708 S16 rgSCHUtlFreeCell(cell)
2715 RgSchPdcchInfo *pdcchInfo;
2716 RgSchPhichInfo *phichInfo;
2718 Inst inst = cell->instIdx;
2721 RgSchRaReqInfo *raReqInfo;
2726 maxslots = cell->numDlSubfrms;
2728 maxslots = RGSCH_NUM_DL_slotS;
2732 /* Invoke the index for scheduler, cell deletion */
2733 cell->sc.apis->rgSCHFreeCell(cell);
2735 /* Release the slots allocated */
2736 for (i = 0; i < maxslots; i++)
2739 rgSCHLaaDeInitDlSfCb(cell, cell->subFrms[i]);
2741 pdcchInfo = &cell->subFrms[i]->pdcchInfo;
2742 /* ccpu00117052 - MOD - Passing double pointer
2743 for proper NULLP assignment*/
2744 rgSCHUtlFreeSBuf(inst, (Data **)(&(pdcchInfo->map)),
2745 (pdcchInfo->nCce + 7) >> 3);
2746 while (pdcchInfo->pdcchs.first != NULLP)
2748 pdcch = (RgSchPdcch *)pdcchInfo->pdcchs.first->node;
2749 cmLListDelFrm(&pdcchInfo->pdcchs, pdcchInfo->pdcchs.first);
2750 /* ccpu00117052 - MOD - Passing double pointer
2751 for proper NULLP assignment*/
2752 rgSCHUtlFreeSBuf(inst, (Data **)&pdcch, sizeof(RgSchPdcch));
2755 phichInfo = &cell->subFrms[i]->phichInfo;
2756 while(phichInfo->phichs.first != NULLP)
2758 phich = (RgSchPhich *)phichInfo->phichs.first->node;
2759 cmLListDelFrm(&phichInfo->phichs, phichInfo->phichs.first);
2760 RGSCH_PHICH_FREE(inst, phich, sizeof(RgSchPhich));
2763 /* LTE_ADV_FLAG_REMOVED_START */
2764 /*releasing SFR pool entries*/
2765 rgSchSFRTotalPoolFree(&cell->subFrms[i]->sfrTotalPoolInfo, cell);
2767 /*releasing dsfr rntp pattern info*/
2768 rgSchDSFRRntpInfoFree(&cell->subFrms[i]->rntpInfo, cell,
2769 cell->bwCfg.dlTotalBw);
2770 /* LTE_ADV_FLAG_REMOVED_END */
2772 /* ccpu00117052 - MOD - Passing double pointer
2773 for proper NULLP assignment*/
2774 rgSCHUtlFreeSBuf(inst, (Data **)(&(cell->subFrms[i])), sizeof(RgSchDlSf));
2777 /* Release the slot pointers */
2778 /* ccpu00117052 - MOD - Passing double pointer
2779 for proper NULLP assignment*/
2780 rgSCHUtlFreeSBuf(inst,
2781 (Data **) (&(cell->subFrms)), sizeof(RgSchDlSf *) * maxslots);
2783 for(idx=0; idx < cell->raInfo.lstSize; idx++)
2785 lst = &cell->raInfo.raReqLst[idx];
2786 while (lst->first != NULLP)
2788 raReqInfo = (RgSchRaReqInfo *)lst->first->node;
2789 cmLListDelFrm(lst, &raReqInfo->raReqLstEnt);
2790 /* ccpu00117052 - MOD - Passing double pointer
2791 for proper NULLP assignment*/
2792 rgSCHUtlFreeSBuf(inst,(Data **)&raReqInfo, sizeof(RgSchRaReqInfo));
2795 /* ccpu00117052 - MOD - Passing double pointer
2796 for proper NULLP assignment*/
2797 rgSCHUtlFreeSBuf(inst,
2798 (Data **)(&(cell->raInfo.raReqLst)),
2799 sizeof(CmLListCp) * (cell->raInfo.lstSize));
2802 /* Release allocated pdcchs */
2803 lst = &cell->pdcchLst;
2804 while (lst->first != NULLP)
2806 pdcch = (RgSchPdcch *)lst->first->node;
2807 cmLListDelFrm(lst, &pdcch->lnk);
2809 if(cell->emtcEnable)
2811 rgSCHEmtcPdcchFree(cell, pdcch);
2812 rgSCHUtlEmtcResMngmtDeinit(cell);
2815 /* ccpu00117052 - MOD - Passing double pointer
2816 for proper NULLP assignment*/
2817 rgSCHUtlFreeSBuf(inst,(Data **)&pdcch, sizeof(RgSchPdcch));
2820 rgSCHLaaFreeLists(cell);
2823 /* LTE_ADV_FLAG_REMOVED_START */
2824 /* releasing RNTP Aggregation Info from CellCb*/
2825 rgSchDSFRRntpInfoFree(&cell->rntpAggrInfo, cell, cell->bwCfg.dlTotalBw);
2826 /* LTE_ADV_FLAG_REMOVED_END */
2833 * @brief This function adds the UE to scheduler
2837 * Function: rgSCHUtlRgrUeCfg
2838 * Purpose: This function performs addition of UE to scheduler
2839 * 1. First, it updates the Y table in the UE
2840 * 2. Then, it calls the scheduler's handler for UE addition
2842 * Invoked by: Scheduler
2844 * @param[in] RgSchCellCb *cell
2845 * @param[in] RgSchUeCb *ue
2846 * @param[in] RgrUeCfg *cfg
2847 * @param[in] RgSchErrInfo *err
2852 S16 rgSCHUtlRgrUeCfg
2860 S16 rgSCHUtlRgrUeCfg(cell, ue, cfg, err)
2868 /* Assign TM 1 as UE's default TM */
2869 ue->mimoInfo.txMode = RGR_UE_TM_1;
2870 ue->txModeTransCmplt = TRUE;
2871 cmInitTimers(&ue->txModeTransTmr, 1);
2872 if (cfg->txMode.pres == PRSNT_NODEF)
2874 /* DL MU-MIMO not supported */
2875 if (cfg->txMode.txModeEnum == RGR_UE_TM_5)
2877 err->errCause = RGSCHERR_SCH_CFG;
2880 ue->mimoInfo.txMode = cfg->txMode.txModeEnum;
2882 ue->ul.ulTxAntSel = cfg->ulTxAntSel;
2883 ue->mimoInfo.cdbkSbstRstrctn = cfg->ueCodeBookRstCfg;
2885 ue->ueCatEnum = cfg->ueCatEnum;
2886 if ((cfg->puschDedCfg.bACKIdx > 15) ||
2887 (cfg->puschDedCfg.bCQIIdx > 15) ||
2888 (cfg->puschDedCfg.bRIIdx > 15))
2890 err->errCause = RGSCHERR_SCH_CFG;
2893 ue->ul.betaHqOffst = cfg->puschDedCfg.bACKIdx;
2894 ue->ul.betaCqiOffst = cfg->puschDedCfg.bCQIIdx;
2895 ue->ul.betaRiOffst = cfg->puschDedCfg.bRIIdx;
2897 ue->csgMmbrSta = cfg->csgMmbrSta;
2899 memset(&ue->pfsStats, 0, sizeof(RgSchPfsStats));
2901 /* Call the handler of the scheduler based on cell configuration */
2902 return (cell->sc.apis->rgSCHRgrUeCfg(cell, ue, cfg, err));
2904 /* Start : LTEMAC_2.1_DEV_CFG */
2907 * @brief This function adds a service to scheduler
2911 * Function: rgSCHUtlRgrLcCfg
2912 * Purpose: This function performs addition of service to scheduler
2913 * The addition is performed for each direction based
2914 * the direction field of the configuration
2916 * Invoked by: Scheduler
2918 * @param[in] RgSchCellCb *cell
2919 * @param[in] RgSchUeCb *ue
2920 * @param[in] RgSchDlLcCb *dlLc
2921 * @param[in] RgrLchCfg *cfg
2922 * @param[in] RgSchErrInfo *err
2927 S16 rgSCHUtlRgrLcCfg
2933 RgSchErrInfo *errInfo
2936 S16 rgSCHUtlRgrLcCfg(cell, ue, dlLc, cfg, errInfo)
2941 RgSchErrInfo *errInfo;
2944 return (cell->sc.apis->rgSCHRgrLchCfg(cell, ue, dlLc, cfg, errInfo));
2949 * @brief This function modifies a service to scheduler
2953 * Function: rgSCHUtlRgrLcRecfg
2954 * Purpose: This function performs modification of a service in
2955 * scheduler. The modification is performed for each direction
2956 * based the direction field of the configuration
2958 * Invoked by: Scheduler
2960 * @param[in] RgSchCellCb *cell
2961 * @param[in] RgSchUeCb *ue
2962 * @param[in] RgSchDlLcCb *dlLc
2963 * @param[in] RgrLchRecfg *recfg
2964 * @param[in] RgSchErrInfo *err
2969 S16 rgSCHUtlRgrLcRecfg
2978 S16 rgSCHUtlRgrLcRecfg(cell, ue, dlLc, recfg, err)
2986 return (cell->sc.apis->rgSCHRgrLchRecfg(cell, ue, dlLc, recfg, err));
2990 * @brief This function deletes a Lc in scheduler
2994 * Function: rgSCHUtlRgrLcDel
2995 * Purpose: This function performs deletion of Lc in scheduler
2997 * Invoked by: Scheduler
2999 * @param[in] RgSchCellCb *cell
3000 * @param[in] RgSchUeCb *ue
3001 * @param[in] CmLteLcId lcId
3002 * @param[in] uint8_t lcgId
3007 S16 rgSCHUtlRgrLcDel
3015 S16 rgSCHUtlRgrLcDel(cell, ue, lcId, lcgId)
3022 cell->sc.apis->rgSCHRgrLchDel(cell, ue, lcId, lcgId);
3025 } /* rgSCHUtlRgrLcDel */
3028 * @brief This function adds a service to scheduler
3032 * Function: rgSCHUtlRgrLcgCfg
3033 * Purpose: This function performs addition of service to scheduler
3034 * The addition is performed for each direction based
3035 * the direction field of the configuration
3037 * Invoked by: Scheduler
3039 * @param[in] RgSchCellCb *cell
3040 * @param[in] RgSchUeCb *ue
3041 * @param[in] RgrLchCfg *cfg
3042 * @param[in] RgSchErrInfo *err
3047 S16 rgSCHUtlRgrLcgCfg
3052 RgSchErrInfo *errInfo
3055 S16 rgSCHUtlRgrLcgCfg(cell, ue, cfg, errInfo)
3059 RgSchErrInfo *errInfo;
3062 return (cell->sc.apis->rgSCHRgrLcgCfg(cell, ue, &(ue->ul.lcgArr[cfg->ulInfo.lcgId]), cfg, errInfo));
3067 * @brief This function modifies a service to scheduler
3071 * Function: rgSCHUtlRgrLcgRecfg
3072 * Purpose: This function performs modification of a service in
3073 * scheduler. The modification is performed for each direction
3074 * based the direction field of the configuration
3076 * Invoked by: Scheduler
3078 * @param[in] RgSchCellCb *cell
3079 * @param[in] RgSchUeCb *ue
3080 * @param[in] RgrLcgRecfg *recfg
3081 * @param[in] RgSchErrInfo *err
3086 S16 rgSCHUtlRgrLcgRecfg
3094 S16 rgSCHUtlRgrLcgRecfg(cell, ue, recfg, err)
3101 return (cell->sc.apis->rgSCHRgrLcgRecfg(cell, ue, &(ue->ul.lcgArr[recfg->ulRecfg.lcgId]), recfg, err));
3102 } /* rgSCHUtlRgrLcRecfg */
3105 * @brief This function modifies a service to scheduler
3109 * Function: rgSCHUtlRgrLcgDel
3110 * Purpose: This function performs modification of a service in
3111 * scheduler. The modification is performed for each direction
3112 * based the direction field of the configuration
3114 * Invoked by: Scheduler
3116 * @param[in] RgSchCellCb *cell
3117 * @param[in] RgSchUeCb *ue
3118 * @param[in] RgrDel *lcDelInfo
3123 Void rgSCHUtlRgrLcgDel
3130 Void rgSCHUtlRgrLcgDel(cell, ue, lcgId)
3136 cell->sc.apis->rgSCHFreeLcg(cell, ue, &ue->ul.lcgArr[lcgId]);
3138 /* Stack Crash problem for TRACE5 changes. added the return below . */
3141 } /* rgSCHUtlRgrLcgDel */
3144 /* End: LTEMAC_2.1_DEV_CFG */
3147 * @brief This function is a wrapper to call scheduler specific API.
3151 * Function: rgSCHUtlDoaInd
3152 * Purpose: Updates the DOA for the UE
3156 * @param[in] RgSchCellCb *cell
3157 * @param[in] RgSchUeCb *ue
3158 * @param[in] TfuDoaRpt *doaRpt
3170 Void rgSCHUtlDoaInd(cell, ue, doaRpt)
3176 ue->mimoInfo.doa.pres = PRSNT_NODEF;
3177 ue->mimoInfo.doa.val = doaRpt->doa;
3182 * @brief This function is a wrapper to call scheduler specific API.
3186 * Function: rgSCHUtlDlCqiInd
3187 * Purpose: Updates the DL CQI for the UE
3191 * @param[in] RgSchCellCb *cell
3192 * @param[in] RgSchUeCb *ue
3193 * @param[in] TfuDlCqiRpt *dlCqiRpt
3194 * @param[in] CmLteTimingInfo timingInfo
3199 Void rgSCHUtlDlCqiInd
3203 TfuDlCqiRpt *dlCqiRpt,
3204 CmLteTimingInfo timingInfo
3207 Void rgSCHUtlDlCqiInd(cell, ue, dlCqiRpt, timingInfo)
3210 TfuDlCqiRpt *dlCqiRpt;
3211 CmLteTimingInfo timingInfo;
3214 RgSchCellCb *sCellCb = NULLP;
3215 if (dlCqiRpt->isPucchInfo)
3217 sCellCb = ue->cellInfo[dlCqiRpt->dlCqiInfo.pucchCqi.cellIdx]->cell;
3218 sCellCb->sc.apis->rgSCHDlCqiInd(sCellCb, ue, dlCqiRpt->isPucchInfo, \
3219 (Void *)&dlCqiRpt->dlCqiInfo.pucchCqi, timingInfo);
3224 for (idx = 0; idx < dlCqiRpt->dlCqiInfo.pusch.numOfCells; idx++)
3226 sCellCb = ue->cellInfo[dlCqiRpt->dlCqiInfo.pusch.puschCqi[idx].cellIdx]->cell;
3227 sCellCb->sc.apis->rgSCHDlCqiInd(sCellCb, ue, dlCqiRpt->isPucchInfo, \
3228 (Void *)&dlCqiRpt->dlCqiInfo.pusch.puschCqi[idx], timingInfo);
3237 * @brief This function is a wrapper to call scheduler specific API.
3241 * Function: rgSCHUtlSrsInd
3242 * Purpose: Updates the UL SRS for the UE
3246 * @param[in] RgSchCellCb *cell
3247 * @param[in] RgSchUeCb *ue
3248 * @param[in] TfuSrsRpt* srsRpt
3249 * @param[in] CmLteTimingInfo timingInfo
3259 CmLteTimingInfo timingInfo
3262 Void rgSCHUtlSrsInd(cell, ue, srsRpt, timingInfo)
3266 CmLteTimingInfo timingInfo;
3269 cell->sc.apis->rgSCHSrsInd(cell, ue, srsRpt, timingInfo);
3275 * @brief This function is a wrapper to call scheduler specific API.
3279 * Function: rgSCHUtlDlTARpt
3280 * Purpose: Reports PHY TA for a UE.
3284 * @param[in] RgSchCellCb *cell
3285 * @param[in] RgSchUeCb *ue
3290 Void rgSCHUtlDlTARpt
3296 Void rgSCHUtlDlTARpt(cell, ue)
3301 cell->sc.apis->rgSCHDlTARpt(cell, ue);
3307 * @brief This function is a wrapper to call scheduler specific API.
3311 * Function: rgSCHUtlDlRlsSubFrm
3312 * Purpose: Releases scheduler Information from DL SubFrm.
3316 * @param[in] RgSchCellCb *cell
3317 * @param[out] CmLteTimingInfo subFrm
3322 Void rgSCHUtlDlRlsSubFrm
3325 CmLteTimingInfo subFrm
3328 Void rgSCHUtlDlRlsSubFrm(cell, subFrm)
3330 CmLteTimingInfo subFrm;
3333 cell->sc.apis->rgSCHDlRlsSubFrm(cell, subFrm);
3339 * @brief This API is invoked to update the AperCQI trigger
3344 * Function : rgSCHUtlUpdACqiTrigWt
3345 * - If HqFdbk is ACK then add up weight corresponding
3346 * to ACK to the AcqiTrigWt.
3347 * - If HqFdbk is NACK then add up weight corresponding
3348 * to NACK to the AcqiTrigWt.
3349 * - If AcqiTrigWt crosses threshold then trigger
3350 * grant req for APERCQI to SCH.
3352 * @param[in] RgSchUeCb *ue
3353 * @param[in] uint8_t isAck
3358 Void rgSCHUtlUpdACqiTrigWt
3361 RgSchUeCellInfo *cellInfo,
3365 Void rgSCHUtlUpdACqiTrigWt(ue,cellInfo, isAck)
3367 RgSchUeCellInfo *cellInfo;
3372 uint8_t triggerSet = 0;
3376 if (isAck == TFU_HQFDB_ACK)
3378 cellInfo->acqiCb.aCqiTrigWt += RG_APER_CQI_ACK_WGT;
3382 cellInfo->acqiCb.aCqiTrigWt += RG_APER_CQI_NACK_WGT;
3385 if (cellInfo->acqiCb.aCqiTrigWt > RG_APER_CQI_THRESHOLD_WGT)
3387 RgSchCellCb *cell = ue->cell;
3388 RgSchErrInfo unUsed;
3390 if(ue->dl.reqForCqi)
3392 /* Already one ACQI trigger procedure is going on
3393 * which is not yet satisfied. Delaying this request till
3394 * the previous is getting satisfied*/
3398 ue->dl.reqForCqi = TRUE;
3400 rgSchCmnSetCqiReqField(cellInfo,ue,&ue->dl.reqForCqi);
3401 //Reset aCqiTrigWt for all the serving cells for which we have triggered ACQI
3402 rgSCHTomUtlGetTrigSet(cell, ue, ue->dl.reqForCqi, &triggerSet);
3403 for (sIdx = 0; sIdx < CM_LTE_MAX_CELLS; sIdx++)
3405 /* The Aperiodic requested for SCell index sIdx */
3406 if ((triggerSet >> (7 - sIdx)) & 0x01)
3408 /* The Aperiodic request for SCell index sIdx */
3409 ue->cellInfo[sIdx]->acqiCb.aCqiTrigWt = 0;
3414 /* Force SCH to send UL grant by indicating fake SR.
3415 * If this UE already in UL SCH Qs this SR Ind will
3417 rgSCHUtlSrRcvd(cell, ue, cell->crntTime, &unUsed);
3425 * @brief This API is invoked to indicate scheduler of a CRC indication.
3429 * Function : rgSCHUtlHdlUlTransInd
3430 * This API is invoked to indicate scheduler of a CRC indication.
3432 * @param[in] RgSchCellCb *cell
3433 * @param[in] RgSchUeCb *ue
3434 * @param[in] CmLteTimingInfo timingInfo
3439 Void rgSCHUtlHdlUlTransInd
3443 CmLteTimingInfo timingInfo
3446 Void rgSCHUtlHdlUlTransInd(cell, ue, timingInfo)
3449 CmLteTimingInfo timingInfo;
3452 cell->sc.apis->rgSCHHdlUlTransInd(cell, ue, timingInfo);
3457 * @brief This API is invoked to indicate scheduler of a CRC failure.
3461 * Function : rgSCHUtlHdlCrcInd
3462 * This API is invoked to indicate CRC to scheduler.
3464 * @param[in] RgSchCellCb *cell
3465 * @param[in] RgSchUeCb *ue
3466 * @param[in] CmLteTimingInfo timingInfo
3471 Void rgSCHUtlHdlCrcInd
3475 CmLteTimingInfo timingInfo
3478 Void rgSCHUtlHdlCrcInd(cell, ue, timingInfo)
3481 CmLteTimingInfo timingInfo;
3484 cell->sc.apis->rgSCHUlCrcInd(cell, ue, timingInfo);
3486 } /* end of rgSCHUtlHdlCrcFailInd */
3489 * @brief This API is invoked to indicate scheduler of a CRC failure.
3493 * Function : rgSCHUtlHdlCrcFailInd
3494 * This API is invoked to indicate CRC failure to scheduler.
3496 * @param[in] RgSchCellCb *cell
3497 * @param[in] RgSchUeCb *ue
3498 * @param[in] CmLteTimingInfo timingInfo
3503 Void rgSCHUtlHdlCrcFailInd
3507 CmLteTimingInfo timingInfo
3510 Void rgSCHUtlHdlCrcFailInd(cell, ue, timingInfo)
3513 CmLteTimingInfo timingInfo;
3516 cell->sc.apis->rgSCHUlCrcFailInd(cell, ue, timingInfo);
3518 } /* end of rgSCHUtlHdlCrcFailInd */
3519 #endif /* LTEMAC_SPS */
3523 * @brief This function is a wrapper to call scheduler specific API.
3527 * Function: rgSCHUtlDlProcAddToRetx
3528 * Purpose: This function adds a HARQ process to retransmission
3529 * queue. This may be performed when a HARQ ack is
3532 * Invoked by: HARQ feedback processing
3534 * @param[in] RgSchCellCb* cell
3535 * @param[in] RgSchDlHqProc* hqP
3540 Void rgSCHUtlDlProcAddToRetx
3543 RgSchDlHqProcCb *hqP
3546 Void rgSCHUtlDlProcAddToRetx(cell, hqP)
3548 RgSchDlHqProcCb *hqP;
3551 cell->sc.apis->rgSCHDlProcAddToRetx(cell, hqP);
3557 * @brief This function adds a HARQ process TB to transmission
3561 * Function: rgSCHUtlDlHqPTbAddToTx
3562 * Purpose: This function a HarqProcess TB to the slot
3565 * Invoked by: Scheduler
3567 * @param[in] RgSubFrm* subFrm
3568 * @param[in] RgDlHqProc* hqP
3569 * @param[in] uint8_t tbIdx
3574 Void rgSCHUtlDlHqPTbAddToTx
3577 RgSchDlHqProcCb *hqP,
3581 Void rgSCHUtlDlHqPTbAddToTx(subFrm, hqP, tbIdx)
3583 RgSchDlHqProcCb *hqP;
3587 RgSchUeCb *ue = NULLP;
3588 RgSchCellCb *cell = hqP->hqE->cell;
3590 /* Addition of UE to dlSf->ueLst shall be done only to UE's PCell */
3591 /* ue->cell will always hold PCell information */
3592 if (NULLP == hqP->hqPSfLnk.node)
3597 if(NULLP == ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk.node)
3599 ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk.node = (PTR)ue;
3600 cmLListAdd2Tail(&cell->subFrms[subFrm->dlIdx]->ueLst,
3601 &ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk);
3603 ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].isPuschHarqRecpPres = FALSE;
3607 /* Add Hq proc in particular dlIdx List for this UE
3608 This list will be used while processing feedback*/
3609 hqP->hqPSfLnk.node = (PTR)hqP;
3610 cmLListAdd2Tail(&ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].hqPLst,&hqP->hqPSfLnk);
3613 uint32_t gSCellSchedCount,gPrimarySchedCount;
3614 if(RG_SCH_IS_CELL_SEC(hqP->hqE->ue,hqP->hqE->cell))
3618 gPrimarySchedCount++;
3622 else if (hqP->hqE->msg4Proc == hqP)
3624 /* Msg4 will be scheduled on PCELL only hence add directly to subFrm msg4HqpList */
3625 hqP->hqPSfLnk.node = (PTR)hqP;
3626 cmLListAdd2Tail(&subFrm->msg4HqPLst, &hqP->hqPSfLnk);
3633 if((ue) && (HQ_TB_WAITING == hqP->tbInfo[tbIdx].state))
3636 ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].totalTbCnt++;
3638 /*totalTbCnt will hold the total number of TBs across all harq Proc from all
3641 hqP->subFrm = subFrm;
3650 * @brief This function removes a HARQ process TB from transmission
3654 * Function: rgSCHUtlDlHqPTbRmvFrmTx
3655 * Purpose: This function removes a HarqProcess TB to the slot
3658 * Invoked by: Scheduler
3660 * @param[in] RgSubFrm* subFrm
3661 * @param[in] RgDlHqProc* hqP
3662 * @param[in] uint8_t tbIdx
3663 * @param[in] Bool isRepeting
3668 Void rgSCHUtlDlHqPTbRmvFrmTx
3671 RgSchDlHqProcCb *hqP,
3676 Void rgSCHUtlDlHqPTbRmvFrmTx(subFrm, hqP, tbIdx, isRepeting)
3678 RgSchDlHqProcCb *hqP;
3683 RgSchCellCb *cell = NULLP;
3684 /* Check with TDD */
3686 (hqP->hqE->ue->ackNakRepCb.cfgRepCnt !=
3687 hqP->tbInfo[tbIdx].fbkRepCntr))
3689 cmLListDelFrm(&subFrm->ackNakRepQ,
3690 &hqP->tbInfo[tbIdx].anRepLnk[hqP->tbInfo[tbIdx].fbkRepCntr]);
3694 if (NULLP != hqP->hqPSfLnk.node)
3697 if (hqP->hqE->msg4Proc == hqP)
3699 /* Msg4 will be scheduled on PCELL only hence delete directly from subFrm msg4HqpList */
3700 cmLListDelFrm(&subFrm->msg4HqPLst, &hqP->hqPSfLnk);
3704 cell = hqP->hqE->cell;
3705 /* Addition of UE to dlSf->ueLst shall be done only to UE's PCell */
3706 /* ue->cell will always hold PCell information */
3707 cmLListDelFrm(&hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].hqPLst,&hqP->hqPSfLnk);
3708 if (0 == hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].hqPLst.count)
3711 cmLListDelFrm(&cell->subFrms[subFrm->dlIdx]->ueLst,
3712 &hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk);
3713 hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk.node = (PTR)NULLP;
3714 hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].totalTbCnt = 0;
3717 hqP->hqPSfLnk.node = NULLP;
3719 hqP->subFrm = NULLP;
3726 * @brief Handler for accessing the existing SCellCb identified by the key
3727 * SCellId under the CellCb.
3731 * Function : rgSchUtlGetCellCb
3734 * @param[in] *cellCb
3736 * @return RgSchUeCb*
3739 RgSchCellCb* rgSchUtlGetCellCb
3745 RgSchCellCb* rgSchUtlGetCellCb(inst, cellId)
3750 RgSchCellCb *cellCb = NULLP;
3753 strtCellId = rgSchCb[inst].genCfg.startCellId;
3754 cellCb = rgSchCb[inst].cells[cellId - strtCellId];
3758 } /* rgSchUtlGetCellCb */
3761 * @brief Handler for deriving the servCellidx
3765 * Function : rgSchUtlGetServCellIdx
3768 * @param[in] *cellId
3769 * @param[in] RgSchUeCb *ue
3770 * @return uint8_t servCellIdx
3773 uint8_t rgSchUtlGetServCellIdx
3780 uint8_t rgSchUtlGetServCellIdx(inst,cellId,ue)
3786 uint8_t servCellIdx;
3787 uint16_t strtCellId;
3789 strtCellId = rgSchCb[inst].genCfg.startCellId;
3791 servCellIdx = ue->cellIdToCellIdxMap[cellId - strtCellId];
3793 return (servCellIdx);
3795 } /* rgSchUtlGetCellCb */
3798 * @brief Handler for validating the Cell Id received secondary Cell Addition
3802 * Function : rgSchUtlGetCellId
3805 * @param[in] *cellCb
3807 * @return RgSchUeCb*
3810 S16 rgSchUtlVldtCellId
3816 S16 rgSchUtlVldtCellId(inst, cellId)
3823 strtCellId = rgSchCb[inst].genCfg.startCellId;
3824 if((cellId >= strtCellId) && ((cellId - strtCellId) < CM_LTE_MAX_CELLS))
3829 } /* rgSchUtlVldtCellId */
3833 * @brief UE reconfiguration for scheduler
3837 * Function : rgSCHUtlRgrUeRecfg
3839 * This functions updates UE specific scheduler
3840 * information upon UE reconfiguration
3842 * @param[in] RgSchCellCb *cell
3843 * @param[in] RgSchUeCb *ue
3844 * @param[int] RgrUeRecfg *ueRecfg
3845 * @param[out] RgSchErrInfo *err
3851 S16 rgSCHUtlRgrUeRecfg
3855 RgrUeRecfg *ueRecfg,
3859 S16 rgSCHUtlRgrUeRecfg(cell, ue, ueRecfg, err)
3862 RgrUeRecfg *ueRecfg;
3866 /* Changes for UE Category Reconfiguration feature addition */
3867 RgSchCmnUe *ueSch = RG_SCH_CMN_GET_UE(ue, cell);
3869 /* Changes for UE Category Reconfiguration feature addition */
3870 if (ueRecfg->ueRecfgTypes & RGR_UE_UECAT_RECFG)
3872 ueSch->cmn.ueCat = ueRecfg->ueCatEnum-1;
3874 ue->ueCatEnum = ueRecfg->ueCatEnum;
3878 /* DL MU-MIMO not supported */
3879 if (ueRecfg->ueRecfgTypes & RGR_UE_TXMODE_RECFG)
3882 if (ueRecfg->txMode.pres == PRSNT_NODEF)
3884 if (ueRecfg->txMode.txModeEnum == RGR_UE_TM_5)
3886 err->errCause = RGSCHERR_SCH_CFG;
3890 if(ue->mimoInfo.txMode != ueRecfg->txMode.txModeEnum)
3892 /* Decremnt the previos A value for this cell */
3893 ue->f1bCsAVal -= rgSCHUtlGetMaxTbSupp(ue->mimoInfo.txMode);
3894 /* Update A value with the new TM Mode */
3895 ue->f1bCsAVal += rgSCHUtlGetMaxTbSupp(ueRecfg->txMode.txModeEnum);
3898 RLOG1(L_INFO,"UeReCfg A valie is %d\n",ue->f1bCsAVal);
3901 ue->mimoInfo.txMode = ueRecfg->txMode.txModeEnum;
3905 /* [ccpu00123958]-ADD- Check for PUSCH related Reconfig from the bit mask */
3906 if(ueRecfg->ueRecfgTypes & RGR_UE_PUSCH_RECFG)
3908 /* Fix: ccpu00124012 */
3909 /* TODO:: Need to check if this is
3910 mandatory to be re-configured on UE category re-configuration */
3911 /* ue->ul.betaHqOffst = ueRecfg->puschDedCfg.bACKIdx;
3912 ue->ul.betaCqiOffst = ueRecfg->puschDedCfg.bCQIIdx;
3913 ue->ul.betaRiOffst = ueRecfg->puschDedCfg.bRIIdx;*/
3916 if (ueRecfg->ueRecfgTypes & RGR_UE_ULTXANTSEL_RECFG)
3918 ue->ul.ulTxAntSel = ueRecfg->ulTxAntSel;
3920 if (ueRecfg->ueRecfgTypes & RGR_UE_CDBKSBST_RECFG)
3922 ue->mimoInfo.cdbkSbstRstrctn = ueRecfg->ueCodeBookRstRecfg;
3925 /* Commenting here to assign garbage value when it is not set in APP. */
3926 //ue->accessStratumRls = ueRecfg->accessStratumRls;
3927 return (cell->sc.apis->rgSCHRgrUeRecfg(cell, ue, ueRecfg, err));
3928 } /* rgSCHUtlRgrUeRecfg */
3931 * @brief This function deletes a service from scheduler
3935 * Function: rgSCHUtlFreeDlLc
3936 * Purpose: This function is made available through a FP for
3937 * making scheduler aware of a service being deleted from UE
3939 * Invoked by: BO and Scheduler
3941 * @param[in] RgSchCellCb* cell
3942 * @param[in] RgSchUeCb* ue
3943 * @param[in] RgSchDlLcCb* svc
3947 Void rgSCHUtlFreeDlLc
3954 Void rgSCHUtlFreeDlLc(cell, ue, svc)
3960 cell->sc.apis->rgSCHFreeDlLc(cell, ue, svc);
3962 /* Stack Crash problem for TRACE5 changes. added the return below . */
3968 * @brief UE deletion for scheduler
3972 * Function : rgSCHUtlFreeUe
3974 * This functions deletes all scheduler information
3975 * pertaining to a UE
3977 * @param[in] RgSchCellCb *cell
3978 * @param[in] RgSchUeCb *ue
3988 Void rgSCHUtlFreeUe(cell, ue)
3994 rgSCHUtlDelUeANFdbkInfo(ue,RGSCH_PCELL_INDEX);
3996 cell->sc.apis->rgSCHFreeUe(cell, ue);
3998 /* Stack Crash problem for TRACE5 changes. added the return below . */
4001 } /* rgSCHUtlFreeUe */
4004 * @brief This function updates the scheduler with service for a UE
4008 * Function: rgSCHUtlDlDedBoUpd
4009 * Purpose: This function should be called whenever there is a
4010 * change BO for a service.
4012 * Invoked by: BO and Scheduler
4014 * @param[in] RgSchCellCb* cell
4015 * @param[in] RgSchUeCb* ue
4016 * @param[in] RgSchDlLcCb* lc
4020 Void rgSCHUtlDlDedBoUpd
4027 Void rgSCHUtlDlDedBoUpd(cell, ue, lc)
4033 cell->sc.apis->rgSCHDlDedBoUpd(cell, ue, lc);
4037 * @brief Record MSG3 allocation into the UE
4041 * Function : rgSCHUtlRecMsg3Alloc
4043 * This function is invoked to update record msg3 allocation information
4044 * in the UE when UE is detected for RaCb
4046 * @param[in] RgSchCellCb *cell
4047 * @param[in] RgSchUeCb *ue
4048 * @param[in] RgSchRaCb *raCb
4052 Void rgSCHUtlRecMsg3Alloc
4059 Void rgSCHUtlRecMsg3Alloc(cell, ue, raCb)
4065 cell->sc.apis->rgSCHUlRecMsg3Alloc(cell, ue, raCb);
4068 } /* rgSCHRecMsg3Alloc */
4072 * @brief Update harq process for allocation
4076 * Function : rgSCHUtlUpdUlHqProc
4078 * This function is invoked when harq process
4079 * control block is now in a new memory location
4080 * thus requiring a pointer/reference update.
4082 * @param[in] RgSchCellCb *cell
4083 * @param[in] RgSchUlHqProcCb *curProc
4084 * @param[in] RgSchUlHqProcCb *oldProc
4090 S16 rgSCHUtlUpdUlHqProc
4093 RgSchUlHqProcCb *curProc,
4094 RgSchUlHqProcCb *oldProc
4097 S16 rgSCHUtlUpdUlHqProc(cell, curProc, oldProc)
4099 RgSchUlHqProcCb *curProc;
4100 RgSchUlHqProcCb *oldProc;
4103 return (cell->sc.apis->rgSCHUpdUlHqProc(cell, curProc, oldProc));
4104 } /* rgSCHUtlUpdUlHqProc */
4107 * @brief UL grant for contention resolution
4111 * Function : rgSCHUtlContResUlGrant
4113 * Add UE to another queue specifically for CRNTI based contention
4116 * @param[in] RgSchCellCb *cell
4117 * @param[in] RgSchUeCb *ue
4118 * @param[out] RgSchErrInfo *err
4124 S16 rgSCHUtlContResUlGrant
4131 S16 rgSCHUtlContResUlGrant(cell, ue, err)
4138 ue->isMsg4PdcchWithCrnti = TRUE;
4140 return (cell->sc.apis->rgSCHContResUlGrant(cell, ue, err));
4141 } /* rgSCHUtlContResUlGrant */
4144 * @brief SR reception handling
4148 * Function : rgSCHUtlSrRcvd
4150 * - Handles SR reception for UE
4152 * @param[in] RgSchCellCb *cell
4153 * @param[in] RgSchUeCb *ue
4154 * @param[out] RgSchErrInfo *err
4164 CmLteTimingInfo frm,
4168 S16 rgSCHUtlSrRcvd(cell, ue, frm, err)
4171 CmLteTimingInfo frm;
4175 return (cell->sc.apis->rgSCHSrRcvd(cell, ue, frm, err));
4176 } /* rgSCHUtlSrRcvd */
4179 * @brief Short BSR update
4183 * Function : rgSCHUtlUpdBsrShort
4185 * This functions does requisite updates to handle short BSR reporting
4187 * @param[in] RgSchCellCb *cell
4188 * @param[in] RgSchUeCb *ue
4189 * @param[in] uint8_t lcgId
4190 * @param[in] uint8_t bsr
4191 * @param[out] RgSchErrInfo *err
4197 Void rgSCHUtlUpdBsrShort
4206 Void rgSCHUtlUpdBsrShort(cell, ue, lcgId, bsr, err)
4214 cell->sc.apis->rgSCHUpdBsrShort(cell, ue, &ue->ul.lcgArr[lcgId], bsr, err);
4216 } /* rgSCHUtlUpdBsrShort */
4220 * @brief Truncated BSR update
4224 * Function : rgSCHUtlUpdBsrTrunc
4226 * This functions does required updates to handle truncated BSR report
4229 * @param[in] RgSchCellCb *cell
4230 * @param[in] RgSchUeCb *ue
4231 * @param[in] uint8_t lcgId
4232 * @param[in] uint8_t bsr
4233 * @param[out] RgSchErrInfo *err
4239 Void rgSCHUtlUpdBsrTrunc
4248 Void rgSCHUtlUpdBsrTrunc(cell, ue, lcgId, bsr, err)
4256 cell->sc.apis->rgSCHUpdBsrTrunc(cell, ue, &ue->ul.lcgArr[lcgId], bsr, err);
4258 } /* rgSCHUtlUpdBsrTrunc */
4262 * @brief Long BSR update
4266 * Function : rgSCHUtlUpdBsrLong
4268 * - Update BSRs for all configured LCGs
4269 * - Update priority of LCGs if needed
4270 * - Update UE's position within/across uplink scheduling queues
4273 * @param[in] RgSchCellCb *cell
4274 * @param[in] RgSchUeCb *ue
4275 * @param[in] uint8_t bsr0
4276 * @param[in] uint8_t bsr1
4277 * @param[in] uint8_t bsr2
4278 * @param[in] uint8_t bsr3
4279 * @param[out] RgSchErrInfo *err
4285 Void rgSCHUtlUpdBsrLong
4296 Void rgSCHUtlUpdBsrLong(cell, ue, bsr0, bsr1, bsr2, bsr3, err)
4312 cell->sc.apis->rgSCHUpdBsrLong(cell, ue, bsArr, err);
4314 } /* rgSCHUtlUpdBsrLong */
4317 * @brief EXT PHR update
4321 * Function : rgSCHUtlUpdExtPhr
4323 * Updates extended power headroom info for a UE
4325 * @param[in] RgSchCellCb *cell
4326 * @param[in] RgSchUeCb *ue
4327 * @param[in] uint8_t phr
4328 * @param[out] RgSchErrInfo *err
4334 S16 rgSCHUtlUpdExtPhr
4338 RgInfExtPhrCEInfo * extPhr,
4342 S16 rgSCHUtlUpdExtPhr(cell, ue, extPhr, err)
4345 RgInfExtPhrCEInfo * extPhr;
4349 return (cell->sc.apis->rgSCHUpdExtPhr(cell, ue, extPhr, err));
4350 } /* rgSCHUtlUpdExtPhr */
4359 * Function : rgSCHUtlUpdPhr
4361 * Updates power headroom info for a UE
4363 * @param[in] RgSchCellCb *cell
4364 * @param[in] RgSchUeCb *ue
4365 * @param[in] uint8_t phr
4366 * @param[out] RgSchErrInfo *err
4380 S16 rgSCHUtlUpdPhr(cell, ue, phr, err)
4387 return (cell->sc.apis->rgSCHUpdPhr(cell, ue, phr, err));
4388 } /* rgSCHUtlUpdPhr */
4392 * @brief Indication of UL CQI
4396 * Function : rgSCHUtlUlCqiInd
4398 * - Updates uplink CQI information for the UE. Computes and
4399 * stores the lowest CQI of CQIs reported in all subbands
4401 * @param[in] RgSchCellCb *cell
4402 * @param[in] RgSchUeCb *ue
4403 * @param[in] TfuUlCqiRpt *ulCqiInfo
4407 Void rgSCHUtlUlCqiInd
4411 TfuUlCqiRpt *ulCqiInfo
4414 Void rgSCHUtlUlCqiInd(cell, ue, ulCqiInfo)
4417 TfuUlCqiRpt *ulCqiInfo;
4420 cell->sc.apis->rgSCHUlCqiInd(cell, ue, ulCqiInfo);
4422 } /* rgSCHUtlUlCqiInd */
4425 * @brief Indication of PUCCH power adjustment
4429 * Function : rgSCHUtlPucchDeltaPwrInd
4431 * - Updates uplink CQI information for the UE. Computes and
4432 * stores the lowest CQI of CQIs reported in all subbands
4434 * @param[in] RgSchCellCb *cell
4435 * @param[in] RgSchUeCb *ue
4436 * @param[in] uint8_t delta
4440 Void rgSCHUtlPucchDeltaPwrInd
4447 Void rgSCHUtlPucchDeltaPwrInd(cell, ue, delta)
4453 cell->sc.apis->rgSCHPucchDeltaPwrInd(cell, ue, delta);
4455 } /* rgSCHUtlPucchDeltaPwrInd */
4457 /* Start: LTEMAC_2.1_DEV_CFG */
4459 * @brief Ue Reset Request
4463 * Function : rgSCHUtlUeReset
4466 * @param[in] RgSchCellCb *cell
4467 * @param[in] RgSchUeCb *ue
4471 Void rgSCHUtlUeReset
4477 Void rgSCHUtlUeReset(cell, ue)
4483 cell->sc.apis->rgSCHUeReset(cell, ue);
4485 } /* rgSCHUtlUeReset */
4486 /* End: LTEMAC_2.1_DEV_CFG */
4489 * @brief Returns HARQ proc for which data expected now
4493 * Function: rgSCHUtlUlHqProcForUe
4494 * Purpose: This function returns the harq process for
4495 * which data is expected in the current slot.
4496 * It does not validate if the HARQ process
4497 * has an allocation.
4501 * @param[in] RgSchCellCb *cell
4502 * @param[in] CmLteTimingInfo frm
4503 * @param[in] RgSchUeCb *ue
4504 * @param[out] RgSchUlHqProcCb **procRef
4508 Void rgSCHUtlUlHqProcForUe
4511 CmLteTimingInfo frm,
4513 RgSchUlHqProcCb **procRef
4516 Void rgSCHUtlUlHqProcForUe(cell, frm, ue, procRef)
4518 CmLteTimingInfo frm;
4520 RgSchUlHqProcCb **procRef;
4523 cell->sc.apis->rgSCHUlHqProcForUe(cell, frm, ue, procRef);
4525 /* Stack Crash problems for TRACE5 changes. added the return below */
4531 * @brief Returns first uplink allocation to send reception
4536 * Function: rgSCHUtlFirstRcptnReq(cell)
4537 * Purpose: This function returns the first uplink allocation
4538 * (or NULLP if there is none) in the slot
4539 * in which is expected to prepare and send reception
4544 * @param[in] RgSchCellCb *cell
4545 * @return RgSchUlAlloc*
4548 RgSchUlAlloc *rgSCHUtlFirstRcptnReq
4553 RgSchUlAlloc *rgSCHUtlFirstRcptnReq(cell)
4557 return (cell->sc.apis->rgSCHFirstRcptnReq(cell));
4561 * @brief Returns first uplink allocation to send reception
4566 * Function: rgSCHUtlNextRcptnReq(cell)
4567 * Purpose: This function returns the next uplink allocation
4568 * (or NULLP if there is none) in the slot
4569 * in which is expected to prepare and send reception
4574 * @param[in] RgSchCellCb *cell
4575 * @return RgSchUlAlloc*
4578 RgSchUlAlloc *rgSCHUtlNextRcptnReq
4584 RgSchUlAlloc *rgSCHUtlNextRcptnReq(cell, alloc)
4586 RgSchUlAlloc *alloc;
4589 return (cell->sc.apis->rgSCHNextRcptnReq(cell, alloc));
4593 * @brief Returns first uplink allocation to send HARQ feedback
4598 * Function: rgSCHUtlFirstHqFdbkAlloc
4599 * Purpose: This function returns the first uplink allocation
4600 * (or NULLP if there is none) in the slot
4601 * in which it is expected to prepare and send HARQ
4606 * @param[in] RgSchCellCb *cell
4607 * @param[in] uint8_t idx
4608 * @return RgSchUlAlloc*
4611 RgSchUlAlloc *rgSCHUtlFirstHqFdbkAlloc
4617 RgSchUlAlloc *rgSCHUtlFirstHqFdbkAlloc(cell, idx)
4622 return (cell->sc.apis->rgSCHFirstHqFdbkAlloc(cell, idx));
4627 * @brief Returns next allocation to send HARQ feedback for
4631 * Function: rgSCHUtlNextHqFdbkAlloc(cell)
4632 * Purpose: This function returns the next uplink allocation
4633 * (or NULLP if there is none) in the slot
4634 * for which HARQ feedback needs to be sent.
4638 * @param[in] RgSchCellCb *cell
4639 * @return RgSchUlAlloc*
4642 RgSchUlAlloc *rgSCHUtlNextHqFdbkAlloc
4645 RgSchUlAlloc *alloc,
4649 RgSchUlAlloc *rgSCHUtlNextHqFdbkAlloc(cell, alloc, idx)
4651 RgSchUlAlloc *alloc;
4655 return (cell->sc.apis->rgSCHNextHqFdbkAlloc(cell, alloc, idx));
4658 /***********************************************************
4660 * Func : rgSCHUtlResetSfAlloc
4662 * Desc : Utility Function to Reset slot allocation information.
4671 **********************************************************/
4673 S16 rgSCHUtlResetSfAlloc
4675 RgInfSfAlloc *sfAlloc,
4676 Bool resetCmnLcInfo,
4680 S16 rgSCHUtlResetSfAlloc(sfAlloc,resetCmnLcInfo,restAlloc)
4681 RgInfSfAlloc *sfAlloc;
4682 Bool resetCmnLcInfo;
4686 if(TRUE == restAlloc)
4688 if(sfAlloc->ueInfo.numUes)
4690 memset(sfAlloc->ueInfo.allocInfo,0x00,
4691 (sizeof(RgInfUeAlloc)*sfAlloc->ueInfo.numUes));
4693 sfAlloc->ueInfo.numUes = 0;
4694 sfAlloc->rarInfo.numRaRntis = 0;
4695 sfAlloc->flowCntrlInfo.numUes = 0;
4697 if(TRUE == resetCmnLcInfo)
4699 sfAlloc->cmnLcInfo.bitMask = 0;
4704 /***********************************************************
4706 * Func : rgSCHUtlGetRlsHqAlloc
4708 * Desc : Utility Function to Allocate slot allocation information.
4717 **********************************************************/
4719 S16 rgSCHUtlGetRlsHqAlloc
4724 S16 rgSCHUtlGetRlsHqAlloc(cell)
4729 Inst inst = cell->instIdx;
4730 for(idx=0; idx < RGSCH_NUM_SUB_FRAMES; idx++)
4732 cell->rlsHqArr[idx].cellId = cell->cellId;
4734 /* Allocating with additional location, to accommodate
4735 TA scheduling along with maximum no of UEs per SF */
4737 /* Allocate memory for "scheduled UE" Info */
4738 if((rgSCHUtlAllocSBuf(inst,
4739 (Data**)&(cell->rlsHqArr[idx].ueHqInfo),
4740 (sizeof(RgInfUeHqInfo)*RGSCH_MAX_UE_PER_DL_SF))) != ROK)
4742 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,"Memory allocation FAILED for "
4752 /***********************************************************
4754 * Func : rgSCHUtlPutRlsHqAlloc
4756 * Desc : Utility Function to deallocate slot allocation information.
4765 **********************************************************/
4767 S16 rgSCHUtlPutRlsHqAlloc
4772 S16 rgSCHUtlPutRlsHqAlloc(cell)
4777 Inst inst = cell->instIdx;
4779 for(idx=0; idx < RGSCH_NUM_SUB_FRAMES; idx++)
4781 /* Deallocate memory for "scheduled UE" Info */
4782 if (cell->rlsHqArr[idx].ueHqInfo != NULLP)
4784 /* Freeing with additional location, to accommodate TA
4785 scheduling along with maximum no of UEs per SF */
4786 /* ccpu00117052 - MOD - Passing double pointer
4787 for proper NULLP assignment*/
4788 rgSCHUtlFreeSBuf(inst,
4789 (Data **)(&(cell->rlsHqArr[idx].ueHqInfo)),
4790 (sizeof(RgInfUeHqInfo)*RGSCH_MAX_UE_PER_DL_SF));
4799 /***********************************************************
4801 * Func : rgSCHUtlGetSfAlloc
4803 * Desc : Utility Function to Allocate slot allocation information.
4812 **********************************************************/
4814 S16 rgSCHUtlGetSfAlloc
4819 S16 rgSCHUtlGetSfAlloc(cell)
4825 Inst inst = cell->instIdx;
4826 RgSchCmnUlCell *cellUl = RG_SCH_CMN_GET_UL_CELL(cell);
4829 for(idx=0; idx < RGSCH_SF_ALLOC_SIZE; idx++)
4831 for(idx=0; idx < RGSCH_NUM_SUB_FRAMES; idx++)
4834 cell->sfAllocArr[idx].cellId = cell->cellId;
4836 /* Allocating with additional location, to accommodate
4837 TA scheduling along with maximum no of UEs per SF */
4839 /* Allocate memory for "scheduled UE" Info */
4840 if((rgSCHUtlAllocSBuf(inst,
4841 (Data**)&(cell->sfAllocArr[idx].ueInfo.allocInfo),
4842 (sizeof(RgInfUeAlloc)*RGSCH_MAX_UE_PER_DL_SF))) != ROK)
4844 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,"Memory allocation FAILED for "
4849 /* Allocate memory for "scheduled RAR" Info */
4850 if((rgSCHUtlAllocSBuf(inst,
4851 (Data**)&(cell->sfAllocArr[idx].rarInfo.raRntiInfo),
4852 (sizeof(RgInfRaRntiInfo)*RGSCH_MAX_RARNTI_PER_DL_SF))) != ROK)
4854 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,"Memory allocation FAILED for "
4858 for(indx = 0; indx < RGSCH_MAX_RARNTI_PER_DL_SF; indx++)
4860 if((rgSCHUtlAllocSBuf(inst,
4861 (Data**)&(cell->sfAllocArr[idx].rarInfo.raRntiInfo[indx].crntiInfo),
4862 (sizeof(RgInfCrntiInfo)* (cellUl->maxMsg3PerUlSf)))) != ROK)
4864 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,"Memory allocation FAILED for "
4873 rgSCHEmtcUtlGetSfAlloc(cell);
4880 /***********************************************************
4882 * Func : rgSCHUtlPutSfAlloc
4884 * Desc : Utility Function to deallocate slot allocation information.
4893 **********************************************************/
4895 S16 rgSCHUtlPutSfAlloc
4900 S16 rgSCHUtlPutSfAlloc(cell)
4906 Inst inst = cell->instIdx;
4907 RgSchCmnUlCell *cellUl = RG_SCH_CMN_GET_UL_CELL(cell);
4910 for(idx=0; idx < RGSCH_SF_ALLOC_SIZE; idx++)
4912 for(idx=0; idx < RGSCH_NUM_SUB_FRAMES; idx++)
4915 if (cell->sfAllocArr[idx].rarInfo.raRntiInfo != NULLP)
4917 for(indx = 0; indx < RGSCH_MAX_RARNTI_PER_DL_SF; indx++)
4919 if (cell->sfAllocArr[idx].rarInfo.raRntiInfo[indx].crntiInfo != NULLP)
4920 /* ccpu00117052 - MOD - Passing double pointer
4921 for proper NULLP assignment*/
4922 rgSCHUtlFreeSBuf(inst,
4923 (Data**)(&(cell->sfAllocArr[idx].rarInfo.raRntiInfo[indx].\
4925 (sizeof(RgInfCrntiInfo)* (cellUl->maxMsg3PerUlSf)));
4927 /* Deallocate memory for "scheduled RAR" Info */
4928 /* ccpu00117052 - MOD - Passing double pointer
4929 for proper NULLP assignment*/
4930 rgSCHUtlFreeSBuf(inst,
4931 (Data**)(&(cell->sfAllocArr[idx].rarInfo.raRntiInfo)),
4932 (sizeof(RgInfRaRntiInfo)*RGSCH_MAX_RARNTI_PER_DL_SF));
4934 /* Deallocate memory for "scheduled UE" Info */
4935 if (cell->sfAllocArr[idx].ueInfo.allocInfo != NULLP)
4937 /* Freeing with additional location, to accommodate TA
4938 scheduling along with maximum no of UEs per SF */
4939 /* ccpu00117052 - MOD - Passing double pointer
4940 for proper NULLP assignment*/
4941 rgSCHUtlFreeSBuf(inst,
4942 (Data**)(&(cell->sfAllocArr[idx].ueInfo.allocInfo)),
4943 (sizeof(RgInfUeAlloc)*RGSCH_MAX_UE_PER_DL_SF));
4948 rgSCHEmtcUtlPutSfAlloc(cell);
4954 /***********************************************************
4956 * Func : rgSCHUtlAllocSBuf
4958 * Desc : Utility Function to Allocate static buffer.
4959 * Memory allocated is assumed contiguous.
4965 * Notes: Caller doesnt need to raise the alarm in case of memory
4966 * allocation gets failed.
4970 **********************************************************/
4972 S16 rgSCHUtlAllocSBuf
4974 Inst inst, /* Instance of the invoking scheduler */
4975 Data **pData, /* Pointer of the data to be returned */
4976 Size size /* size */
4979 S16 rgSCHUtlAllocSBuf(inst, pData, size)
4980 Inst inst; /* Instance of the invoking scheduler */
4981 Data **pData; /* Pointer of the data to be returned */
4982 Size size; /* size */
4985 /* Moving alarm diagnostics to available scope */
4987 /* Initialize the param to NULLP */
4990 /* May not be necessary for data performance path */
4998 /* allocate buffer */
4999 #ifdef MS_MBUF_CORRUPTION /* Should be enabled when debugging mbuf corruption */
5000 MS_BUF_ADD_ALLOC_CALLER();
5002 if (SGetSBuf(rgSchCb[inst].rgSchInit.region, rgSchCb[inst].rgSchInit.pool,
5003 pData, size) != ROK)
5005 RgUstaDgn dgn; /* Alarm diagnostics structure */
5006 dgn.type = LRG_USTA_DGNVAL_MEM;
5007 dgn.u.mem.region = rgSchCb[inst].rgSchInit.region;
5008 dgn.u.mem.pool = rgSchCb[inst].rgSchInit.pool;
5009 /* Send an alarm to Layer Manager */
5010 rgSCHLmmStaInd(inst, LCM_CATEGORY_RESOURCE, LCM_EVENT_SMEM_ALLOC_FAIL,
5011 LCM_CAUSE_MEM_ALLOC_FAIL, &dgn);
5012 RGSCHLOGERROR(inst, ERRCLS_DEBUG, ERG015, 0, "Unable to Allocate Buffer");
5013 RLOG_ARG0(L_ERROR,DBG_INSTID,inst, "Unable to Allocate the Buffer");
5018 /* zero out the allocated memory */
5019 memset(*pData, 0x00, size);
5023 } /* end of rgSCHUtlAllocSBuf */
5028 * Fun: rgSCHUtlFreeSBuf
5030 * Desc: The argument to rgSCHUtlFreeSBuf() is a pointer to a block
5031 * previously allocated by rgSCHUtlAllocSBuf() and size. It
5032 * deallocates the memory.
5040 Void rgSCHUtlFreeSBuf
5042 Inst inst, /* Instance of the invoking scheduler */
5043 Data **data, /* pointer to data */
5044 Size size /* size */
5047 Void rgSCHUtlFreeSBuf(inst, data, size)
5048 Inst inst; /* Instance of the invoking scheduler */
5049 Data **data; /* pointer to data */
5050 Size size; /* size */
5056 if ((data == NULLP) || (*data == NULLP) || (size == 0))
5062 #ifdef MS_MBUF_CORRUPTION /* Should be enabled when debugging mbuf corruption */
5063 MS_BUF_ADD_CALLER();
5065 /* Deallocate buffer */
5066 ret = SPutSBuf(rgSchCb[inst].rgSchInit.region,
5067 rgSchCb[inst].rgSchInit.pool, (*data), size);
5071 RGSCHLOGERROR(inst, ERRCLS_DEBUG, ERG016, (ErrVal) 0,
5072 "rgSCHUtlFreeSBuf failed.\n");
5073 RLOG_ARG0(L_ERROR,DBG_INSTID,inst, "rgSCHUtlFreeSBuf failed");
5077 /* ccpu00117052 - ADD - Assigning the pointer to NULLP */
5081 } /* end of rgSCHUtlFreeSBuf */
5087 * Fun: rgSCHUtlFreeWarningSiSeg
5089 * Desc: This is used to deallocate Warning SI Seg.
5098 Void rgSCHUtlFreeWarningSiSeg
5105 Void rgSCHUtlFreeWarningSiSeg(reg, pool, siPduLst)
5108 CmLListCp *siPduLst;
5114 while (siPduLst->first != NULLP)
5116 node = siPduLst->first;
5117 pdu = (Buffer *)node->node;
5118 cmLListDelFrm(siPduLst, node);
5119 RGSCH_FREE_MSG(pdu);
5120 SPutSBuf(reg, pool, (Data *)node,sizeof(CmLList));
5125 } /* end of rgSCHUtlFreeWarningSiSeg */
5130 * Fun: rgSCHUtlFreeWarningSiPdu
5132 * Desc: This is used to deallocate Warning SI PDU.
5141 Void rgSCHUtlFreeWarningSiPdu
5146 Void rgSCHUtlFreeWarningSiPdu(cell)
5152 RgSchWarningSiInfo *warningSi;
5153 RgSchWarningSiPdu *warningSiPdu;
5155 warningSi = (RgSchWarningSiInfo *) cell->siCb.\
5156 siArray[cell->siCb.siCtx.siId-1].si;
5157 /* ccpu00136659: CMAS ETWS design changes */
5158 CM_LLIST_FIRST_NODE(&warningSi->warningSiMsg.segLstCp, node);
5164 warningSiPdu = (RgSchWarningSiPdu *)node->node;
5165 pdu = warningSiPdu->pdu;
5166 /* ccpu00136659: CMAS ETWS design changes */
5167 cmLListDelFrm(&warningSi->warningSiMsg.segLstCp, node);
5168 RGSCH_FREE_MSG(pdu);
5169 if(warningSi->warningSiMsg.segLstCp.count == 0)
5171 /* ccpu00136659: CMAS ETWS design changes */
5172 cell->siCb.siArray[cell->siCb.siCtx.siId-1].si = NULLP;
5173 rgSCHUtlRgrWarningSiCfgCfm(cell->instIdx,
5174 rgSchCb[cell->instIdx].rgrSap->sapCfg.spId,
5175 cell->siCb.warningSi[warningSi->idx].siId,
5176 warningSi->warningSiMsg.transId, RGR_CFG_CFM_TX_COMPLETE);
5181 } /* end of rgSCHUtlFreeWarningSiPdu */
5186 * Fun: rgSCHUtlGetWarningSiPdu
5188 * Desc: This is used to get Warning SI PDU for Scheduling.
5197 Buffer *rgSCHUtlGetWarningSiPdu
5202 Buffer *rgSCHUtlGetWarningSiPdu(cell)
5206 RgSchWarningSiInfo *warningSi;
5207 RgSchWarningSiPdu *warningSiPdu;
5211 warningSi = (RgSchWarningSiInfo *) cell->siCb.
5212 siArray[cell->siCb.siCtx.siId-1].si;
5213 /* ccpu00136659: CMAS ETWS design changes */
5214 CM_LLIST_FIRST_NODE(&warningSi->warningSiMsg.segLstCp, node);
5217 warningSiPdu = (RgSchWarningSiPdu *)node->node;
5218 pdu = warningSiPdu->pdu;
5225 } /* rgSCHUtlGetWarningSiPdu */
5230 * Fun: rgSCHUtlGetMcsAndNPrb
5232 * Desc: This is used to get mcs and nPrb value.
5241 S16 rgSCHUtlGetMcsAndNPrb
5249 S16 rgSCHUtlGetMcsAndNPrb(cell, nPrb, mcs, msgLen)
5256 RgSchWarningSiInfo *warningSi;
5257 RgSchWarningSiPdu *warningSiPdu;
5260 if(cell->siCb.siCtx.warningSiFlag == FALSE)
5262 *mcs = cell->siCb.crntSiInfo.siInfo[cell->siCb.siCtx.siId-1].mcs;
5263 *nPrb = cell->siCb.crntSiInfo.siInfo[cell->siCb.siCtx.siId-1].nPrb;
5264 *msgLen = cell->siCb.crntSiInfo.siInfo[cell->siCb.siCtx.siId-1].msgLen;
5268 warningSi = (RgSchWarningSiInfo *) cell->siCb.
5269 siArray[cell->siCb.siCtx.siId-1].si;
5270 /* ccpu00136659: CMAS ETWS design changes */
5271 CM_LLIST_FIRST_NODE(&warningSi->warningSiMsg.segLstCp, node);
5277 warningSiPdu = (RgSchWarningSiPdu *)node->node;
5278 *mcs = warningSiPdu->mcs;
5279 *nPrb = warningSiPdu->nPrb;
5280 *msgLen = warningSiPdu->msgLen;
5285 } /* rgSCHUtlGetMcsAndNPrb */
5289 * Fun: rgSCHUtlCalMacAndPrb
5291 * Desc: This is used to Calculate mcs and nPrb value for SIB1 and SIs.
5300 S16 rgSCHUtlCalMcsAndNPrb
5308 S16 rgSCHUtlCalMcsAndNPrb(cell, nPrb, mcs, msgLen)
5318 /*Get the nPrb and mcs parametr values */
5319 if (rgSCHUtlGetAllwdCchTbSz(msgLen*8, &nPrb, &mcs) != (msgLen*8))
5321 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId, "msgLen does "
5322 "not match any valid TB Size");
5327 if(cfgType == RGR_SI_CFG_TYPE_SIB1 || cfgType == RGR_SI_CFG_TYPE_SIB1_PWS)
5330 if(cell->siCb.crntSiInfo.sib1Info.sib1 == NULLP)
5332 cell->siCb.crntSiInfo.sib1Info.mcs = mcs;
5333 cell->siCb.crntSiInfo.sib1Info.nPrb = nPrb;
5334 cell->siCb.crntSiInfo.sib1Info.msgLen = msgLen;
5338 cell->siCb.newSiInfo.sib1Info.mcs = mcs;
5339 cell->siCb.newSiInfo.sib1Info.nPrb= nPrb;
5340 cell->siCb.newSiInfo.sib1Info.msgLen = msgLen;
5345 if(cfgType == RGR_SI_CFG_TYPE_SI)
5347 if(cell->siCb.crntSiInfo.siInfo[siId-1].si == NULLP &&
5348 !(cell->siCb.siBitMask & RGSCH_SI_SICFG_UPD))
5350 cell->siCb.crntSiInfo.siInfo[siId-1].mcs = mcs;
5351 cell->siCb.crntSiInfo.siInfo[siId-1].nPrb = nPrb;
5352 cell->siCb.crntSiInfo.siInfo[siId-1].msgLen = msgLen;
5356 cell->siCb.newSiInfo.siInfo[siId-1].mcs = mcs;
5357 cell->siCb.newSiInfo.siInfo[siId-1].nPrb= nPrb;
5358 cell->siCb.newSiInfo.siInfo[siId-1].msgLen = msgLen;
5362 if(cfgType == RGR_SI_CFG_TYPE_SIB8_CDMA)
5364 cell->siCb.crntSiInfo.siInfo[siId-1].mcs = mcs;
5365 cell->siCb.crntSiInfo.siInfo[siId-1].nPrb = nPrb;
5366 cell->siCb.crntSiInfo.siInfo[siId-1].msgLen = msgLen;
5373 /***********************************************************
5375 * Func : rgSCHUtlFillDgnParams
5377 * Desc : Utility Function to Fill Diagonostic params.
5385 **********************************************************/
5387 Void rgSCHUtlFillDgnParams
5394 Void rgSCHUtlFillDgnParams(inst, dgn, dgnType)
5403 case LRG_USTA_DGNVAL_MEM:
5404 dgn->type = (uint8_t) LRG_USTA_DGNVAL_MEM;
5405 dgn->u.mem.region = rgSchCb[inst].rgSchInit.region;
5406 dgn->u.mem.pool = rgSchCb[inst].rgSchInit.pool;
5414 } /* end of rgSCHUtlFillDgnParams */
5416 /***********************************************************
5418 * Func : rgSCHUtlGetPstToLyr
5420 * Desc : Utility Function to get the pst structure to post a message to MAC
5426 * Notes: This function should be called while sending a msg from
5427 * scheduler instance to MAC
5431 **********************************************************/
5433 Void rgSCHUtlGetPstToLyr
5440 Void rgSCHUtlGetPstToLyr (pst, schCb, macInst)
5447 /* Only the needed params are filled */
5448 pst->region = schCb->rgSchInit.region;
5449 pst->pool = schCb->rgSchInit.pool;
5450 pst->srcInst = schCb->rgSchInit.inst+SCH_INST_START;
5451 pst->srcProcId = schCb->rgSchInit.procId;
5452 pst->dstProcId = schCb->rgSchInit.procId;
5454 pst->dstInst = macInst;
5455 pst->dstEnt = ENTMAC;
5456 pst->srcEnt = ENTMAC;
5458 pst->prior = PRIOR0;
5460 pst->route = RTESPEC;
5463 } /* end of rgSCHUtlGetPstToLyr */
5465 /** @brief This function fills in the common lc information to be sent to MAC
5469 * Function: rgSCHUtlFillRgInfCmnLcInfo
5470 * @param RgSchDlSf *sf,
5471 * @param RgInfSfAlloc *sfAlloc,
5472 * @param CmLteLcId lcId,
5473 * @param Bool sendInd
5480 S16 rgSCHUtlFillRgInfCmnLcInfo
5483 RgInfSfAlloc *sfAlloc,
5488 S16 rgSCHUtlFillRgInfCmnLcInfo(sf, sfAlloc, lcId, sendInd)
5490 RgInfSfAlloc *sfAlloc;
5496 if((sf->bch.tbSize)&&
5497 !(sfAlloc->cmnLcInfo.bitMask & RGINF_BCH_INFO))
5500 sfAlloc->cmnLcInfo.bchInfo.lcId = lcId;
5502 sfAlloc->cmnLcInfo.bitMask |= RGINF_BCH_INFO;
5504 else if((sf->bcch.pdcch != NULLP)&&
5505 !(sfAlloc->cmnLcInfo.bitMask & RGINF_BCCH_INFO))
5507 sfAlloc->cmnLcInfo.bcchInfo.rnti = RGSCH_SI_RNTI;
5508 rgSCHUtlFillPdschDciInfo(&(sfAlloc->cmnLcInfo.bcchInfo.dciInfo),
5509 &(sf->bcch.pdcch->dci));
5511 sfAlloc->cmnLcInfo.bcchInfo.lcId = lcId;
5512 sfAlloc->cmnLcInfo.bcchInfo.sndStatInd = sendInd;
5514 sfAlloc->cmnLcInfo.bitMask |= RGINF_BCCH_INFO;
5516 else if((sf->pcch.pdcch != NULLP) &&
5517 !(sfAlloc->cmnLcInfo.bitMask & RGINF_PCCH_INFO))
5519 sfAlloc->cmnLcInfo.pcchInfo.rnti = RGSCH_P_RNTI;
5520 rgSCHUtlFillPdschDciInfo(&(sfAlloc->cmnLcInfo.pcchInfo.dciInfo),
5521 &(sf->pcch.pdcch->dci));
5522 sfAlloc->cmnLcInfo.pcchInfo.lcId = lcId;
5523 sfAlloc->cmnLcInfo.bitMask |= RGINF_PCCH_INFO;
5528 /** @brief This function fills in the RAR information to be sent to MAC
5532 * Function: rgSCHUtlFillRgInfRarInfo
5534 * @param RgSchCellCb *cell
5535 * @param RgSchDlSf *sf
5536 * @param RgInfSfAlloc *sfAlloc
5542 S16 rgSCHUtlFillRgInfRarInfo
5545 RgInfSfAlloc *sfAlloc,
5549 S16 rgSCHUtlFillRgInfRarInfo(sf, sfAlloc, cell)
5551 RgInfSfAlloc *sfAlloc;
5560 RgInfRaRntiInfo *raRntiAlloc;
5562 RgSchCmnDlCell *cellDl = RG_SCH_CMN_GET_DL_CELL(cell);
5565 noRaRsps = RGSCH_MAX_TDD_RA_RSP_ALLOC;
5567 noRaRsps = RGSCH_MAX_RA_RSP_ALLOC;
5570 for(idx =0; idx < noRaRsps; idx++)
5572 if (sf->raRsp[idx].pdcch == NULLP)
5574 /* No further raResp Allocations. */
5577 /* Added Dl TB count for RACH Response transmission*/
5579 cell->dlUlTbCnt.tbTransDlTotalCnt++;
5581 raRntiAlloc = &(sfAlloc->rarInfo.raRntiInfo[idx]);
5582 raRntiAlloc->raRnti = sf->raRsp[idx].raRnti;
5583 raRntiAlloc->schdTbSz = sf->raRsp[idx].tbSz;
5584 raRntiAlloc->numCrnti = 0;
5585 rgSCHUtlFillPdschDciInfo(&(raRntiAlloc->dciInfo),
5586 &(sf->raRsp[idx].pdcch->dci));
5587 /* RACHO : fill backoff indicator information */
5588 raRntiAlloc->backOffInd = sf->raRsp[idx].backOffInd;
5590 /* Fill for contention free UEs*/
5591 lnkLst = &(sf->raRsp[idx].contFreeUeLst);
5592 CM_LLIST_FIRST_NODE(lnkLst, tmp);
5595 ue = (RgSchUeCb *)tmp->node;
5597 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].tmpCrnti = ue->ueId;
5598 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].isContFree = TRUE;
5599 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].rapId = ue->ul.rarGrnt.rapId;
5600 #ifndef MAC_5GTF_UPDATE
5601 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.hop =
5603 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.cqiBit =
5604 ue->ul.rarGrnt.cqiReqBit;
5606 /* SHASHAHNK ADD RIV CALC */
5607 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.rbStart =
5608 ue->ul.rarGrnt.rbStart;
5609 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.numRb =
5610 ue->ul.rarGrnt.numRb;
5611 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.tpc =
5613 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.iMcsCrnt =
5614 ue->ul.rarGrnt.iMcsCrnt;
5615 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].ta = ue->ul.rarGrnt.ta;
5616 raRntiAlloc->numCrnti++;
5617 cmLListDelFrm(lnkLst, &ue->ul.rarGrnt.raRspLnk);
5618 ue->ul.rarGrnt.raRspLnk.node = (PTR)NULLP;
5620 /* Fill for contention based UEs*/
5621 lnkLst = &(sf->raRsp[idx].raRspLst);
5623 CM_LLIST_FIRST_NODE(lnkLst, tmp);
5625 while((NULLP != tmp) && ((RgSchRaCb *)tmp->node != NULLP))
5627 raCb = (RgSchRaCb *)tmp->node;
5629 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].tmpCrnti = raCb->tmpCrnti;
5630 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].isContFree = FALSE;
5631 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].rapId = raCb->rapId;
5632 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].ta.pres = TRUE;
5633 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].ta.val = raCb->ta.val;
5634 #ifndef MAC_5GTF_UPDATE
5635 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.hop =
5637 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.cqiBit = FALSE;
5639 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.rbStart =
5640 raCb->msg3Grnt.rbStart;
5641 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.numRb =
5642 raCb->msg3Grnt.numRb;
5643 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.tpc =
5645 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.iMcsCrnt =
5646 raCb->msg3Grnt.iMcsCrnt;
5647 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.delayBit =
5648 raCb->msg3Grnt.delayBit;
5649 /* For initial attaching UEs Aperiodic CQI need not be triggered */
5650 raRntiAlloc->numCrnti++;
5651 /* Search the next node */
5652 CM_LLIST_NEXT_NODE(lnkLst, tmp);
5655 sfAlloc->rarInfo.numRaRntis = idx;
5656 /* ccpu00132314-ADD-Update the tx power allocation info
5657 TODO-Need to add a check for max tx power per symbol */
5658 sfAlloc->rarInfo.txPwrOffset = cellDl->rarTxPwrOffset;
5661 } /* end of rgSCHUtlFillRgInfRarInfo */
5663 /** @brief This function fills in the pdsch data related allocation Info
5664 * from the pdcch DCI info.
5669 * Function: rgSCHUtlFillPdschDciInfo
5672 * - Depending upon the DCI Format, fill the appropriate fields.
5674 * @param [out] TfuPdschDciInfo *pdschDci
5675 * @param [in] TfuDciInfo *pdcchDci
5681 S16 rgSCHUtlFillPdschDciInfo
5683 TfuPdschDciInfo *pdsch,
5684 TfuDciInfo *pdcchDci
5687 S16 rgSCHUtlFillPdschDciInfo(pdsch, pdcchDci)
5688 TfuPdschDciInfo *pdsch;
5689 TfuDciInfo *pdcchDci;
5696 pdsch->format = pdcchDci->dciFormat;
5697 switch(pdcchDci->dciFormat)
5699 case TFU_DCI_FORMAT_1:
5700 pdsch->u.format1AllocInfo = pdcchDci->u.format1Info.allocInfo;
5702 case TFU_DCI_FORMAT_1A:
5703 if (pdcchDci->u.format1aInfo.isPdcchOrder == FALSE)
5705 pdsch->u.format1aAllocInfo = pdcchDci->u.format1aInfo.t.pdschInfo.allocInfo;
5708 case TFU_DCI_FORMAT_1B:
5709 pdsch->u.format1bAllocInfo = pdcchDci->u.format1bInfo.allocInfo;
5711 case TFU_DCI_FORMAT_1C:
5712 pdsch->u.format1cAllocInfo = pdcchDci->u.format1cInfo;
5714 case TFU_DCI_FORMAT_1D:
5715 pdsch->u.format1dAllocInfo = pdcchDci->u.format1dInfo.allocInfo;
5717 case TFU_DCI_FORMAT_2:
5718 pdsch->u.format2AllocInfo = pdcchDci->u.format2Info.allocInfo;
5720 case TFU_DCI_FORMAT_2A:
5721 pdsch->u.format2AAllocInfo = pdcchDci->u.format2AInfo.allocInfo;
5724 case TFU_DCI_FORMAT_B1:
5725 pdsch->u.formatB1Info = pdcchDci->u.formatB1Info;
5727 case TFU_DCI_FORMAT_B2:
5728 pdsch->u.formatB2Info = pdcchDci->u.formatB2Info;
5733 ret = rgSCHEmtcUtlFillPdschDciInfo(pdsch, pdcchDci);
5745 /* LTE_ADV_FLAG_REMOVED_START */
5747 * @brief This function resets temporary variables in Pool
5750 * Function: rgSchSFRResetPoolVariables
5752 * Invoked by: rgSCHSFRUtlTotalPoolInit
5754 * @param[in] RgSchCellCb* cell
5755 * @param[in] RgSubFrm* subFrm
5760 Void rgSchDSFRPwrCheck
5763 Bool *isAllUePwrHigh
5766 static Void rgSchDSFRPwrCheck(sf, isAllUePwrHigh)
5768 Bool *isAllUePwrHigh;
5772 RgSchSFRPoolInfo *sfrCCPool;
5777 l = &sf->sfrTotalPoolInfo.ccPool;
5778 n = cmLListFirst(l);
5781 sfrCCPool = (RgSchSFRPoolInfo*)n->node;
5782 if((sfrCCPool->poolstartRB == sfrCCPool->pwrHiCCRange.startRb) &&
5783 (sfrCCPool->poolendRB == sfrCCPool->pwrHiCCRange.endRb))
5790 *isAllUePwrHigh = TRUE;
5797 /* LTE_ADV_FLAG_REMOVED_END */
5798 /***********************************************************
5800 * Func : rgSCHUtlFillRgInfTbInfo
5802 * Desc : Utility Function to fill the allocation info of each Tb
5808 * Notes: This function should be called while sending a msg from
5809 * scheduler instance to MAC
5813 **********************************************************/
5815 static Void rgSCHUtlFillRgInfTbInfo
5817 RgSchDlHqProcCb *hqP,
5818 RgInfUeAlloc *allocInfo,
5822 static Void rgSCHUtlFillRgInfTbInfo (hqP, allocInfo, cell)
5823 RgSchDlHqProcCb *hqP;
5824 RgInfUeAlloc *allocInfo;
5830 RgInfUeTbInfo *tbInfo;
5832 /* LTE_ADV_FLAG_REMOVED_START */
5834 static uint32_t tmpCnt = 0;
5835 Bool isAllUePwrHigh = FALSE;
5837 /* LTE_ADV_FLAG_REMOVED_END */
5838 RgSchDlLcCb *dlLcCb = NULLP;
5839 uint16_t rlcHdrEstmt;
5843 uint8_t prbUsed = 0;
5847 CmLteTimingInfo frm;
5849 /* Get Downlink slot */
5850 frm = cell->crntTime;
5851 RGSCH_INCR_SUB_FRAME(frm, RG_SCH_CMN_DL_DELTA);
5852 sf = rgSCHUtlSubFrmGet(cell, frm);
5853 /* Setting of fillCtrlPdu flag
5854 If both P-cell and S-cell are present,
5855 make TRUE for P-cell and FALSE for all s-cells
5856 For all other cases set TRUE */
5858 if ((rgSchCb[cell->instIdx].genCfg.forceCntrlSrbBoOnPCel) &&
5859 !RG_SCH_CMN_IS_PCELL_HQP(hqP))
5861 allocInfo->fillCtrlPdu = FALSE;
5865 allocInfo->fillCtrlPdu = TRUE;
5869 allocInfo->tbStrtIdx = -1;
5873 allocInfo->tbReqInfo.sCellHqPId = 0xff;
5874 rgSCHLaaHndlFillRgInfTbInfo(cell, hqP, allocInfo);
5877 /*TODO:REEMA: Check and fill the isRetx */
5878 for(tbCnt = 0; tbCnt < 2; tbCnt++)
5880 RgSchUeCb *ue = NULLP;
5881 /*Changed as a result of CR timer*/
5882 if ((hqP->hqE->ue != NULLP)/* &&
5883 ((hqP->tbInfo[tbCnt].lchSchdData[0].lcId != 0) || \
5884 (hqP->tbInfo[tbCnt].schdTa.pres == PRSNT_NODEF))*/)
5887 allocInfo->rnti = ue->ueId;
5888 allocInfo->doa = hqP->hqE->ue->mimoInfo.doa;
5889 allocInfo->txMode = (TfuTxMode)(hqP->hqE->ue->mimoInfo.txMode);
5890 allocInfo->puschRptUsd = hqP->hqE->ue->mimoInfo.puschFdbkVld;
5891 allocInfo->puschPmiInfo = hqP->hqE->ue->mimoInfo.puschPmiInfo;
5892 if(hqP->tbInfo[tbCnt].schdTa.pres == PRSNT_NODEF)
5894 hqP->tbInfo[tbCnt].taSnt = TRUE;
5897 if (RG_SCH_IS_PAPRSNT(ue,hqP->hqE->cell))
5899 /*update pA value */
5900 allocInfo->pa = (RG_SCH_CMN_GET_PA(ue,hqP->hqE->cell)).val;
5904 /* LTE_ADV_FLAG_REMOVED_START */
5905 /* If ABS is enabled, calculate resource used */
5906 if((0 == tbCnt) && (RGR_ENABLE == ue->cell->lteAdvCb.absCfg.status))
5908 /* For Macro count number resource used in Non-ABS SF */
5909 if(RGR_ABS_MUTE == ue->cell->lteAdvCb.absCfg.absPatternType)
5911 if(RG_SCH_ABS_ENABLED_NONABS_SF == ue->cell->lteAdvCb.absDlSfInfo)
5913 ue->cell->lteAdvCb.absLoadInfo[ue->cell->lteAdvCb.absPatternDlIdx]+=
5914 hqP->tbInfo[tbCnt].dlGrnt.numRb;
5917 /* For pico count number resource used in ABS SF for ABS UE */
5918 else if(RGR_ABS_TRANSMIT == ue->cell->lteAdvCb.absCfg.absPatternType)
5920 if(RG_SCH_ABS_ENABLED_ABS_SF == ue->cell->lteAdvCb.absDlSfInfo)
5922 if(TRUE == ue->lteAdvUeCb.rgrLteAdvUeCfg.isAbsUe)
5924 ue->cell->lteAdvCb.absLoadInfo[ue->cell->lteAdvCb.absPatternDlIdx]+=
5925 hqP->tbInfo[tbCnt].dlGrnt.numRb;
5932 /*if SFR is enabled*/
5933 allocInfo->isEnbSFR = (uint8_t)RG_SCH_CMN_IS_SFR_ENB(ue->cell); /* KW fix for LTE_ADV */
5934 if((ue->cell->lteAdvCb.dsfrCfg.status == RGR_ENABLE) &&
5935 (ue->lteAdvUeCb.rgrLteAdvUeCfg.isUeCellEdge == FALSE))
5937 rgSchDSFRPwrCheck(sf, &isAllUePwrHigh);
5941 allocInfo->pa = (uint8_t)ue->cell->lteAdvCb.sfrCfg.pwrThreshold.pHigh; /* KW fix for LTE_ADV */
5942 if(tmpCnt++ == 100000)
5944 RLOG_ARG2(L_DEBUG,DBG_CELLID,ue->cell->cellId,
5945 "DSFR::ll UEs can go HIGH, PHigh(%d) for UE(%d)",allocInfo->pa, ue->ueId);
5951 if (allocInfo->isEnbSFR)
5953 /*Update pA to Plow if it is cell-centred ,else pA will be pHigh*/
5954 if (ue->lteAdvUeCb.rgrLteAdvUeCfg.isUeCellEdge == TRUE)
5956 allocInfo->pa = ue->cell->lteAdvCb.sfrCfg.pwrThreshold.pHigh;
5957 if(tmpCnt++ == 100000)
5959 RLOG_ARG2(L_DEBUG,DBG_CELLID,ue->cell->cellId,
5960 "SFR::UE is CELL EDGE, PHigh(%d) for UE(%d)",allocInfo->pa, ue->ueId);
5967 if(TRUE == ue->lteAdvUeCb.isCCUePHigh)
5969 allocInfo->pa = ue->cell->lteAdvCb.sfrCfg.pwrThreshold.pHigh;
5970 ue->lteAdvUeCb.isCCUePHigh = FALSE;
5974 allocInfo->pa = ue->cell->lteAdvCb.sfrCfg.pwrThreshold.pLow;
5975 if(tmpCnt++ == 100000)
5977 RLOG_ARG2(L_DEBUG,DBG_CELLID,ue->cell->cellId,
5978 "SFR::UE is CELL CENTRE, PLow(%d) for UE(%d)\n",allocInfo->pa, ue->ueId);
5985 /* LTE_ADV_FLAG_REMOVED_END */
5993 RgSchCmnDlCell *cellDl = RG_SCH_CMN_GET_DL_CELL(cell);
5996 allocInfo->pdcchRnti = hqP->hqE->raCb->tmpCrnti;
5998 allocInfo->rnti = hqP->hqE->raCb->tmpCrnti;
6000 /*ccpu00132314-ADD-Use a default pA value
6002 allocInfo->pa = cellDl->msg4pAVal;
6006 /* If TB Is scheduled for this SF */
6007 if(hqP->tbInfo[tbCnt].state == HQ_TB_WAITING)
6009 if (allocInfo->tbStrtIdx == -1){
6010 allocInfo->tbStrtIdx = tbCnt;
6012 rgSCHUtlFillPdschDciInfo(&(allocInfo->dciInfo),
6013 &(hqP->pdcch->dci));
6017 rgSCHUtlFillPdschDciInfo(&(allocInfo->dciInfo),
6018 &(hqP->pdcch->dci));
6020 else if ((ue) && (ue->dl.spsOccPdcch.rnti == ue->spsRnti))
6022 rgSCHUtlFillPdschDciInfo(&(allocInfo->dciInfo),
6023 &(ue->dl.spsOccPdcch.dci));
6025 #endif /* ifndef LTEMAC_SPS */
6030 allocInfo->pdcchRnti = hqP->pdcch->rnti;
6034 allocInfo->pdcchRnti = ue->spsRnti;
6037 tbInfo = &(allocInfo->tbInfo[tbCnt]);
6038 allocInfo->nmbOfTBs++;
6039 allocInfo->hqProcId = hqP->procId;
6040 allocInfo->tbInfo[tbCnt].schdTbSz = hqP->tbInfo[tbCnt].tbSz;
6042 tbInfo->disTb = FALSE;
6043 if(!(hqP->tbInfo[tbCnt].txCntr))
6046 if(!((rgSCHLaaCheckIfLAAProc(hqP)) && (TRUE ==
6047 rgSCHLaaSCellEnabled(cell))))
6050 hqP->tbInfo[tbCnt].txCntr++;
6052 for(idx = 0; idx < hqP->tbInfo[tbCnt].numLch; idx++)
6054 tbInfo->schdDat[idx].lcId =\
6055 hqP->tbInfo[tbCnt].lchSchdData[idx].lcId;
6056 tbInfo->schdDat[idx].numBytes =\
6057 hqP->tbInfo[tbCnt].lchSchdData[idx].schdData;
6060 lcId = hqP->tbInfo[tbCnt].lchSchdData[idx].lcId;
6063 dlLcCb = hqP->hqE->ue->dl.lcCb[lcId-1];
6066 RG_SCH_CMN_DL_GET_HDR_EST(dlLcCb, rlcHdrEstmt);
6067 /* Update the totalBo with the scheduled bo */
6068 (hqP->hqE->ue->totalBo <= tbInfo->schdDat[idx].numBytes - rlcHdrEstmt)?\
6069 (hqP->hqE->ue->totalBo = 0):\
6070 (hqP->hqE->ue->totalBo -= tbInfo->schdDat[idx].numBytes-rlcHdrEstmt);
6074 prbUsed = ((hqP->tbInfo[tbCnt].\
6075 lchSchdData[idx].schdData *
6076 hqP->tbInfo[tbCnt].dlGrnt.numRb) /
6077 (hqP->tbInfo[0].tbSz + hqP->tbInfo[1].tbSz));
6078 dlLcCb->qciCb->dlPrbCount += prbUsed;
6079 if(dlLcCb->qciCb->qci > 0)
6081 RG_SCH_CALC_GBR_UTILIZATION(cell, dlLcCb, prbUsed);
6083 #endif /* RRM_RBC_Y */
6086 //if(!(hqP->hqE->ue->pfsStats.lcStats[lcId-1].isLcCntSet))
6090 if (hqP->hqE->ue->cell == hqP->hqE->cell)
6092 idx = RGSCH_PCELL_INDEX;
6096 idx = RG_SCH_GET_SCELL_INDEX((hqP->hqE->ue), (hqP->hqE->cell));
6098 hqP->hqE->ue->pfsStats.lcStats[lcId-1].ueSchdOcc[idx]++;
6099 hqP->hqE->ue->pfsStats.lcStats[lcId-1].perRefresh[ue->pfsStats.lcStats[lcId-1].lastIdx].lcSchdOcc++;
6106 /* Added Dl TB count for SRB/DRB data transmission*/
6108 cell->dlUlTbCnt.tbTransDlTotalCnt++;
6110 tbInfo->ta.pres = hqP->tbInfo[tbCnt].schdTa.pres;
6111 tbInfo->ta.val = hqP->tbInfo[tbCnt].schdTa.val;
6113 tbInfo->sCellActCe = hqP->tbInfo[tbCnt].schdSCellActCe;
6115 tbInfo->numSchLch = hqP->tbInfo[tbCnt].numLch;
6116 if(!(hqP->tbInfo[tbCnt].numLch))
6118 tbInfo->schdDat[tbInfo->numSchLch].numBytes= hqP->tbInfo[tbCnt].tbSz;
6119 /* Fix: If only TA is scheduled, use some dummy LCID */
6120 if (tbInfo->ta.pres)
6121 tbInfo->schdDat[tbInfo->numSchLch].lcId = RG_TA_LCID;
6124 tbInfo->contResCe = hqP->tbInfo[tbCnt].contResCe;
6125 tbInfo->isReTx = FALSE;
6130 if(!((rgSCHLaaCheckIfLAAProc(hqP)) && (TRUE ==
6131 rgSCHLaaSCellEnabled(cell))))
6134 hqP->tbInfo[tbCnt].txCntr++;
6136 tbInfo->isReTx = TRUE;
6138 /* As per 36.314, harq retransmission also considered for
6139 * prb utilization calculation*/
6140 for(idx = 0; idx < hqP->tbInfo[tbCnt].numLch; idx++)
6145 lcId = hqP->tbInfo[tbCnt].lchSchdData[idx].lcId;
6148 dlLcCb = hqP->hqE->ue->dl.lcCb[lcId-1];
6151 prbUsed = ((hqP->tbInfo[tbCnt].\
6152 lchSchdData[idx].schdData *
6153 hqP->tbInfo[tbCnt].dlGrnt.numRb) /
6154 (hqP->tbInfo[0].tbSz + hqP->tbInfo[1].tbSz));
6155 if(dlLcCb->qciCb->qci > 0)
6157 RG_SCH_CALC_GBR_UTILIZATION(cell, dlLcCb, prbUsed);
6169 rgSCHLaaResetDlHqProcCb(hqP);
6174 /***********************************************************
6176 * Func : rgSCHUtlFillRgInfUeInfo
6178 * Desc : Utility Function to fill the allocation info of Ue
6179 * : MIMO : Filling 2TB's of each UE
6184 * Notes: This function should be called while sending a msg from
6185 * scheduler instance to MAC
6189 **********************************************************/
6192 Void rgSCHUtlFillRgInfUeInfo
6196 CmLListCp *dlDrxInactvTmrLst,
6197 CmLListCp *dlInActvLst,
6198 CmLListCp *ulInActvLst
6201 Void rgSCHUtlFillRgInfUeInfo (sf,cell, dlDrxInactvTmrLst, dlInActvLst, ulInActvLst)
6205 CmLListCp *dlDrxInactvTmrLst;
6206 CmLListCp *dlInActvLst;
6207 CmLListCp *ulInActvLst;
6210 RgInfSfAlloc *sfAlloc;
6211 CmLListCp *lnkLst; /* lnkLst assignment */
6214 RgSchUeCb *ue = NULLP;
6215 RgInfUeInfo *ueInfo = NULLP;
6216 RgInfUeAlloc *ueAlloc = NULLP;
6217 RgSchDlHqProcCb *hqCb = NULLP;
6219 /* Since Msg4 is sched only on PCELL, use cell arg's sfAllocArr */
6220 sfAlloc = &(cell->sfAllocArr[cell->crntSfIdx]);
6221 ueInfo = &(sfAlloc->ueInfo);
6222 ueAlloc = sfAlloc->ueInfo.allocInfo;
6224 lnkLst = &(sf->msg4HqPLst);
6225 CM_LLIST_FIRST_NODE(lnkLst, tmp);
6228 printf("5GTF_ERROR MSG4 Consolidation\n");
6229 hqCb = (RgSchDlHqProcCb *)(tmp->node);
6230 CM_LLIST_NEXT_NODE(lnkLst, tmp);
6232 rgSCHUtlFillRgInfTbInfo(hqCb, &ueAlloc[ueInfo->numUes], cell);
6238 if((!(ue->dl.dlInactvMask & RG_HQENT_INACTIVE)) && (ue->isDrxEnabled))
6240 rgSCHUtlGetDrxSchdUesInDl(cell, ue, hqCb, &ueAlloc[ueInfo->numUes],
6241 dlDrxInactvTmrLst, dlInActvLst, ulInActvLst);
6247 lnkLst = &(sf->ueLst);
6248 CM_LLIST_FIRST_NODE(lnkLst, tmp);
6251 #if defined (TENB_STATS) && defined (RG_5GTF)
6252 cell->tenbStats->sch.dl5gtfPdschCons++;
6254 ue = (RgSchUeCb *)(tmp->node);
6255 CM_LLIST_NEXT_NODE(lnkLst, tmp);
6257 hqPNode = ue->dl.dlSfHqInfo[cell->cellId][sf->dlIdx].hqPLst.first;
6260 hqCb = (RgSchDlHqProcCb *)hqPNode->node;
6261 hqPNode = hqPNode->next;
6263 sfAlloc = &(hqCb->hqE->cell->sfAllocArr[hqCb->hqE->cell->crntSfIdx]);
6264 ueInfo = &(sfAlloc->ueInfo);
6265 ueAlloc = sfAlloc->ueInfo.allocInfo;
6267 rgSCHUtlFillRgInfTbInfo(hqCb, &ueAlloc[ueInfo->numUes],
6270 if(ue->isDrxEnabled)
6272 rgSCHUtlGetDrxSchdUesInDl(cell, ue, hqCb, &ueAlloc[ueInfo->numUes],
6273 dlDrxInactvTmrLst, dlInActvLst, ulInActvLst);
6278 if (rgSchCb[cell->instIdx].genCfg.isSCellActDeactAlgoEnable == TRUE)
6280 /*If remaining BO is left then increment the count*/
6284 /* Check if trigger for Activation is met or not */
6285 if(rgSCHIsActvReqd(cell, ue))
6288 /*Passing primary cell*/
6289 rgSCHSCellSelectAndActDeAct(ue->cell, ue, RGR_SCELL_ACT);
6294 /*If remaining BO is 0 then reset the count*/
6302 } /* end of rgSCHUtlFillRgInfUeInfo */
6306 /** @brief This function shall update the scheduler with the CEs and data rcvd
6310 * Function: rgSCHUtlUpdSch
6313 * - Collate the information of all the SDUs received and inform the
6314 * scheduler rgSCHDataRcvd
6315 * - Send Data indication to the higher layer with the dedicated data
6316 * (rgUIMSndDedDatInd)
6317 * - Inform scheduler with any MAC CEs if present.
6319 * @param [in] RgCellCb *cellCb
6320 * @param [in] RgUeCb *ueCb
6321 * @param [in] RgMacPdu *pdu
6322 * @param [in] RgSchErrInfo *err
6330 RgInfSfDatInd *subfrmInfo,
6331 RgSchCellCb *cellCb,
6337 S16 rgSCHUtlUpdSch (subfrmInfo, cellCb, ueCb, pdu, err)
6338 RgInfSfDatInd *subfrmInfo;
6339 RgSchCellCb *cellCb;
6349 if (RGSCH_UL_SPS_ACT_PRSENT & pdu->ceInfo.bitMask)
6351 /* SPS to be activated due to data on SPS LCG ID*/
6352 rgSCHUtlSpsActInd(cellCb, ueCb, pdu->ceInfo.spsSduSize);
6355 /* TODO : Temp Fix for crash due to UL SDU corruption*/
6356 if (RGSCH_PHR_CE_PRSNT & pdu->ceInfo.bitMask)
6359 RGSCHCPYTIMEINFO(subfrmInfo->timingInfo, ueCb->macCeRptTime);
6360 if ((ret = rgSCHUtlUpdPhr(cellCb, ueCb, pdu->ceInfo.ces.phr, err)) != ROK)
6363 /* Note: Order of indication to Sch now is
6364 * 1st Indicate the DataInd info for each LCG's
6365 * 2nd Update the BSR reports received along with data
6366 * this is to make sure the effBsr is updated to the latest BSR
6369 cellCb->sc.apis->rgSCHUpdUeDataIndLcg(cellCb, ueCb, pdu);
6371 #ifndef MAC_5GTF_UPDATE
6372 if (RGSCH_TRUNC_BSR_CE_PRSNT & pdu->ceInfo.bitMask)
6374 RGSCHCPYTIMEINFO(subfrmInfo->timingInfo, ueCb->macCeRptTime);
6375 /*ccpu00129922 - MOD - Deleted return value
6376 * checking since it returns void*/
6377 rgSCHUtlUpdBsrTrunc (cellCb, ueCb,
6378 (uint8_t)(pdu->ceInfo.ces.bsr.truncBsr >> 6),
6379 (uint8_t)(pdu->ceInfo.ces.bsr.truncBsr & 0x3F), err);
6383 if (RGSCH_SHORT_BSR_CE_PRSNT & pdu->ceInfo.bitMask)
6385 RGSCHCPYTIMEINFO(subfrmInfo->timingInfo, ueCb->macCeRptTime);
6386 /*ccpu00129922 - MOD - Deleted return value
6387 checking since it returns void*/
6388 rgSCHUtlUpdBsrShort (cellCb, ueCb,
6389 (uint8_t)(pdu->ceInfo.ces.bsr.shortBsr >> 6),
6390 (uint8_t)(pdu->ceInfo.ces.bsr.shortBsr & 0x3F), err);
6394 if (RGSCH_LONG_BSR_CE_PRSNT & pdu->ceInfo.bitMask)
6396 if (RGSCH_BSR_CE_PRSNT & pdu->ceInfo.bitMask)
6399 RGSCHCPYTIMEINFO(subfrmInfo->timingInfo, ueCb->macCeRptTime);
6400 /*ccpu00129922 - MOD - Deleted return value
6401 checking since it returns void*/
6402 rgSCHUtlUpdBsrLong (cellCb, ueCb,
6403 pdu->ceInfo.ces.bsr.longBsr.bs1,
6404 pdu->ceInfo.ces.bsr.longBsr.bs2,
6405 pdu->ceInfo.ces.bsr.longBsr.bs3,
6406 pdu->ceInfo.ces.bsr.longBsr.bs4,
6409 #ifndef MAC_5GTF_UPDATE
6416 } /* end of rgSCHUtlUpdSch */
6419 * @brief Handler for Updating Bo received in StaRsp
6423 * Function : rgSCHUtlAddUeToCcchSduLst
6425 * This function shall be invoked once it receives staRsp on CCCH
6427 * @param[in] RgSchCellCb *cell
6428 * @param[in] RgSchUeCb *ueCb
6433 S16 rgSCHUtlAddUeToCcchSduLst
6439 S16 rgSCHUtlAddUeToCcchSduLst(cell, ueCb)
6444 RgSchCmnDlUe *ueDl = RG_SCH_CMN_GET_DL_UE(ueCb, cell);
6445 RgSchDlHqProcCb *hqP = (RgSchDlHqProcCb *)ueDl->proc;
6447 /* Temp Guard: For back to back CCCH SDU BO
6448 * twice. Hence an extra guard. If already added to scheduling
6449 * queue or if scheduled and waiting for HQ FDBK, ignore */
6450 if ((ueCb->ccchSduLnk.node) ||
6451 ((!(ueCb->dl.dlInactvMask & RG_HQENT_INACTIVE)) &&
6452 ((hqP != NULLP) && (hqP->hqE->ccchSduProc))))
6454 RLOG_ARG1(L_ERROR,DBG_CELLID,cell->cellId,"RNTI:%d Unexpected CCCH SDU BO",
6459 ueCb->ccchSduLnk.node = (PTR)(ueCb);
6460 cmLListAdd2Tail(&(cell->ccchSduUeLst), &(ueCb->ccchSduLnk));
6468 * Function : rgSCHUtlUpdtBo
6470 * This function shall be invoked once it receives staRsp on CCCH
6472 * @param[in] RgSchCellCb *cell
6473 * @param[in] RgRguCmnStaRsp *staRsp
6481 RgInfCmnBoRpt *staRsp
6484 S16 rgSCHUtlUpdtBo(cell, staRsp)
6486 RgInfCmnBoRpt *staRsp;
6491 if ((ueCb = rgSCHDbmGetUeCb(cell, staRsp->u.rnti)) == NULLP)
6493 /* Handle Ue fetch failure */
6494 RLOG_ARG1(L_ERROR,DBG_CELLID,cell->cellId,"Invalid UEID:%d",staRsp->u.rnti);
6497 /* Update Bo in ueCb */
6498 ueCb->dlCcchInfo.bo = (uint32_t)(staRsp->bo);
6502 rgSCHUtlAddUeToEmtcCcchSduLst(cell,ueCb);
6507 rgSCHUtlAddUeToCcchSduLst(cell, ueCb);
6511 } /* rgSCHUtlUpdtBo */
6517 * Function : rgSCHUtlHndlCcchBoUpdt
6519 * This function shall fetch the raCb with the given rnti and ask RAM to
6523 * @param[in] RgSchCellCb *cell
6524 * @param[in] RgInfCmnBoRpt *boRpt
6530 S16 rgSCHUtlHndlCcchBoUpdt
6533 RgInfCmnBoRpt *boRpt
6536 S16 rgSCHUtlHndlCcchBoUpdt(cell, boRpt)
6538 RgInfCmnBoRpt *boRpt;
6544 if ((raCb = rgSCHDbmGetRaCb(cell, boRpt->u.rnti)) == NULLP)
6547 /* CR timer implementation changes*/
6548 /*If no raCb, schedule ueCb, ueCb is extracted in rgSCHUtlUpdtBo*/
6549 return (rgSCHUtlUpdtBo(cell, boRpt));
6551 /* Handle RaCb fetch failure */
6552 RLOG_ARG1(L_ERROR,DBG_CELLID,cell->cellId,
6553 "Invalid RNTI:%d to fetch raCb",boRpt->u.rnti);
6560 /*Fix: If RaCb exists, then MSG4 is not completed yet*/
6561 /*Check if guard timer has expired, if not CR CE + CCCH SDU will be scheduled*/
6562 if((raCb->contResTmrLnk.node != NULLP) && \
6563 (raCb->schdLnk.node == NULLP) && (raCb->dlHqE->msg4Proc == NULLP))
6566 /*if contention resolution timer left ,Stop the Contention Resolution Guard Timer ,
6567 add in toBeSchduled list and update the Bo */
6568 if(TRUE == raCb->isEmtcRaCb)
6570 rgSCHRamEmtcUpdtBo(cell, raCb, boRpt);
6575 cmLListDelFrm(&cell->contResGrdTmrLst, &(raCb->contResTmrLnk));
6576 raCb->contResTmrLnk.node=NULLP;
6577 rgSCHRamUpdtBo(cell, raCb, boRpt);
6582 /*Fix:Guard timer has expired */
6583 /*Update the BO in UE CB but dont add it to the scheduling list.
6584 *Should be added to the list after MSG4 completion*/
6585 if ((ueCb = rgSCHDbmGetUeCb(cell, boRpt->u.rnti)) == NULLP)
6587 /* Handle Ue fetch failure */
6588 RLOG_ARG1(L_ERROR,DBG_CELLID,cell->cellId,"Invalid RNTI:%d",boRpt->u.rnti);
6591 /* Update Bo in ueCb */
6592 ueCb->dlCcchInfo.bo = (uint32_t)(boRpt->bo);
6596 rgSCHRamUpdtBo(cell, raCb, boRpt);
6600 } /* rgSCHUtlHndlCcchBoUpdt */
6603 * @brief Validates BO received for BCCH or PCCH.
6607 * Function : rgSCHUtlGetAllwdCchTbSz
6609 * This function shall return the tbSz equal to or
6610 * the nearest greater value for a given bo.
6611 * If no such value found return -1. The nPrb value is
6615 * @param[in] uint32_t bo
6616 * @param[out] uint8_t *nPrb
6622 S32 rgSCHUtlGetAllwdCchTbSz
6629 S32 rgSCHUtlGetAllwdCchTbSz(bo, nPrb, mcs)
6639 for (lt = 0, rt = 43; lt <= rt;)
6642 if (rgSchUtlBcchPcchTbSzTbl[cn].tbSz == bo)
6644 *nPrb = rgSchUtlBcchPcchTbSzTbl[cn].rbIndex;
6645 *mcs = rgSchUtlBcchPcchTbSzTbl[cn].mcs;
6646 return (rgSchUtlBcchPcchTbSzTbl[cn].tbSz);
6648 else if (rgSchUtlBcchPcchTbSzTbl[cn].tbSz < bo)
6657 *nPrb = rgSchUtlBcchPcchTbSzTbl[lt].rbIndex;
6658 *mcs = rgSchUtlBcchPcchTbSzTbl[lt].mcs;
6659 return (rgSchUtlBcchPcchTbSzTbl[lt].tbSz);
6663 * @brief Handler for BO Updt received for BCCH or PCCH.
6667 * Function : rgSCHUtlHndlBcchPcchBoUpdt
6669 * This function shall store the buffer and time to transmit in lcCb
6672 * @param[in] RgSchCellCb *cell
6673 * @param[in] RgInfCmnBoRpt *boRpt
6679 S16 rgSCHUtlHndlBcchPcchBoUpdt
6682 RgInfCmnBoRpt *boUpdt
6685 S16 rgSCHUtlHndlBcchPcchBoUpdt(cell, boUpdt)
6687 RgInfCmnBoRpt *boUpdt;
6690 RgSchClcDlLcCb *dlLc;
6691 RgSchClcBoRpt *boRpt;
6692 Inst inst = cell->instIdx;
6696 dlLc = rgSCHDbmGetBcchOnBch(cell);
6699 RLOG_ARG2(L_ERROR,DBG_CELLID,cell->cellId,
6700 "No Logical Channel dlLc is NULLP for RNTI:%d LCID:%d",boUpdt->u.rnti,boUpdt->lcId);
6703 if (boUpdt->lcId != dlLc->lcId)
6705 /* Added for dropping paging Message*/
6707 if ((rgSCHChkBoUpdate(cell,boUpdt))== ROK) /* Checking if received BO falls within the window of 5120 slots*/
6709 if (rgSCHUtlGetAllwdCchTbSz(boUpdt->bo*8, &nPrb, &mcs)
6712 RLOG_ARG3(L_ERROR,DBG_CELLID,cell->cellId,"[%ld]BO: does not match any "
6713 "valid TB Size RNTI:%d LCID:%d", boUpdt->bo,boUpdt->u.rnti,boUpdt->lcId);
6716 }/*end of rgSCHChkBoUpdate*/
6722 if ((dlLc = rgSCHDbmGetCmnLcCb(cell, boUpdt->lcId)) == NULLP)
6724 /* Handle lcCb fetch failure */
6725 RLOG_ARG2(L_ERROR,DBG_CELLID,cell->cellId,
6726 "LCID:%d Invalid for RNTI:%d",boUpdt->lcId,boUpdt->u.rnti);
6729 if (((rgSCHUtlAllocSBuf(inst, (Data **)(&boRpt), sizeof(RgSchClcBoRpt))) ==RFAILED) ||
6732 RLOG_ARG3(L_ERROR,DBG_CELLID,cell->cellId, "Allocation of common bo %dreport "
6733 "failed RNTI:%d LCID:%d", boUpdt->bo,boUpdt->u.rnti,boUpdt->lcId);
6737 boRpt->bo = boUpdt->bo;
6739 boRpt->timeToTx = boUpdt->u.timeToTx;
6742 if(cell->emtcEnable)
6744 boRpt->emtcDIReason = boUpdt->emtcDIReason;
6745 boRpt->pnb = boUpdt->pnb;
6748 RG_SCH_ADD_TO_CRNT_TIME(boRpt->timeToTx,
6749 boRpt->maxTimeToTx, cell->siCfg.siWinSize)
6750 if((NULLP != dlLc) && (dlLc->si))
6752 boRpt->retxCnt = cell->siCfg.retxCnt;
6758 rgSCHDbmInsCmnLcBoRpt(dlLc, boRpt);
6761 } /* rgSCHUtlHndlBcchPcchBoUpdt */
6764 * @brief API for sending bind confirm from Scheduler instance to RRM
6768 * Function: rgSCHUtlRgrBndCfm
6770 * This API is invoked to send bind confirm from Scheduler instance to RRM.
6771 * This API fills in Pst structure and SAP Ids and invokes
6772 * bind confirm API towards RRM.
6774 * @param[in] SuId suId
6775 * @param[in] uint8_t status
6781 S16 rgSCHUtlRgrBndCfm
6788 S16 rgSCHUtlRgrBndCfm(instId, suId, status)
6796 ret = RgUiRgrBndCfm(&rgSchCb[instId].rgrSap[suId].sapCfg.sapPst, rgSchCb[instId].rgrSap[suId].sapCfg.suId, status);
6799 RLOG_ARG0(L_ERROR,DBG_INSTID,instId,"rgSCHUtlRgrBndCfm: RgUiRgrBndCfm Failed ");
6803 } /* rgSCHUtlRgrBndCfm*/
6806 * @brief API for sending bind confirm from Scheduler instance to RRM via RGM
6811 * Function: rgSCHUtlRgmBndCfm
6813 * This API is invoked to send bind confirm from Scheduler instance to RRM.
6814 * This API fills in Pst structure and SAP Ids and invokes
6816 * @param[in] SuId suId
6817 * @param[in] uint8_t status
6823 S16 rgSCHUtlRgmBndCfm
6830 S16 rgSCHUtlRgmBndCfm(instId, suId, status)
6838 ret = RgUiRgmBndCfm(&rgSchCb[instId].rgmSap[suId].sapCfg.sapPst, rgSchCb[instId].rgmSap[suId].sapCfg.suId, status);
6841 RLOG_ARG0(L_ERROR,DBG_INSTID,instId,"rgSCHUtlRgmBndCfm: RgUiRgrBndCfm Failed ");
6845 } /* rgSCHUtlRgmBndCfm*/
6850 * @brief API for sending configuration confirm from Scheduler to DU APP
6854 * Function: schSendCfgCfm
6856 * This API is invoked to send configuration confirm from Scheduler to DU
6859 * @param[in] Pst pst
6860 * @param[in] RgrCfgTransId transId
6861 * @param[in] uint8_t status
6871 RgrCfgTransId transId,
6875 S16 schSendCfgCfm(reg, pool, transId, status)
6878 RgrCfgTransId transId;
6885 memset((&cfmPst), 0, sizeof(Pst));
6887 cfmPst.srcEnt = (Ent)ENTDUAPP;
6888 cfmPst.srcInst = (Inst) 0;
6889 cfmPst.srcProcId = SFndProcId();
6890 cfmPst.dstEnt = (Ent)ENTMAC;
6891 cfmPst.dstInst = (Inst) 0;
6892 cfmPst.dstProcId = SFndProcId();
6893 cfmPst.selector = ODU_SELECTOR_LC;
6894 cfmPst.region = reg;
6897 if(RgUiRgrCfgCfm(&cfmPst,transId, status) != ROK)
6899 RLOG_ARG0(L_ERROR,DBG_INSTID,inst,"schSendCfgCfm: RgUiRgrCfgCfm Failed");
6900 printf("\nschSendCfgCfm: RgUiRgrCfgCfm Failed ");
6904 } /* schSendCfgCfm*/
6907 * @brief API for sending TTI indication from Scheduler to RRM.
6911 * Function: rgSCHUtlRgrTtiInd
6913 * This API is invoked to send TTI indication from Scheduler instance to RRM.
6914 * This API fills in Pst structure and RgrTtiIndInfo
6916 * @param[in] cell RgSchCellCb
6917 * @param[in] CmLteTimingInfo status
6923 S16 rgSCHUtlRgrTtiInd
6926 RgrTtiIndInfo *rgrTti
6929 S16 rgSCHUtlRgrTtiInd(cell, rgrTti)
6931 RgrTtiIndInfo *rgrTti;
6935 RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
6938 Void mtTmrHdlrPublic(void);
6941 rgrSap = cell->rgrSap;
6942 if (rgrSap->sapSta.sapState != LRG_BND)
6944 RLOG_ARG1(L_ERROR,DBG_CELLID,cell->cellId,
6945 "rgSCHUtlRgrTtiInd() Upper SAP not bound (%d) ",
6946 rgrSap->sapSta.sapState);
6949 RgUiRgrTtiInd(&(cell->rgrSap->sapCfg.sapPst),
6950 cell->rgrSap->sapCfg.suId, rgrTti);
6958 } /* rgSCHUtlRgrTtiInd*/
6960 /** @brief This function is called by rgMacSchSfRecpInd. This function invokes the
6961 * scheduler with the information of the received Data and any Control Elements
6969 * - Retrieves the RaCb with the rnti provided, if it doesnt exist
6971 * - If UE exists then update the Schduler with any MAC CEs if present.
6972 * - Invoke RAM module to do Msg3 related processing rgSCHRamProcMsg3
6974 * @param [in] RgSchCellCb *cellCb
6975 * @param [in] RgSchUeCb *ueCb
6976 * @param [in] CmLteRnti rnti
6977 * @param [in] RgMacPdu *pdu
6978 * @param [in] RgSchErrInfo *err
6985 S16 rgSCHUtlProcMsg3
6987 RgInfSfDatInd *subfrmInfo,
6988 RgSchCellCb *cellCb,
6995 S16 rgSCHUtlProcMsg3 (subfrmInfo, cellCb, ueCb, rnti, pdu, err)
6996 RgInfSfDatInd *subfrmInfo;
6997 RgSchCellCb *cellCb;
7007 /* must have an raCb for this case */
7008 raCb = rgSCHDbmGetRaCb (cellCb, rnti);
7011 RLOG_ARG1(L_ERROR,DBG_CELLID,cellCb->cellId, "RNTI:%d Received MSG3, unable to "
7016 /* ccpu00130982: Processing CRNTI MAC CE before Short BSR, if any, such that
7017 * effBsr of current case only will be considered in scheduling of ContResLst*/
7018 ret = rgSCHRamProcMsg3 (cellCb, ueCb, raCb, pdu, err);
7021 RLOG_ARG1(L_ERROR,DBG_CELLID,cellCb->cellId,"Processing failed in the RAM "
7025 /* if ueCb is present */
7028 rgSCHUtlUpdSch (subfrmInfo, cellCb, ueCb, pdu, err);
7034 /** @brief This function is called by RgMacSchSpsRelInd. This function invokes the
7035 * scheduler with the information of the received Data.
7039 * Function: rgSCHUtlSpsRelInd
7044 * @param [in] RgSchCellCb *cellCb
7045 * @param [in] RgSchUeCb *ueCb
7046 * @param [in] Bool *isExplRel
7053 S16 rgSCHUtlSpsRelInd
7055 RgSchCellCb *cellCb,
7060 S16 rgSCHUtlSpsRelInd (cellCb, ueCb, isExplRel)
7061 RgSchCellCb *cellCb;
7066 cellCb->sc.apis->rgSCHUlSpsRelInd(cellCb, ueCb, isExplRel);
7068 } /* end of rgSCHUtlSpsRelInd */
7071 /** @brief This function is called by RgMacSchSpsRelInd. This function invokes the
7072 * scheduler with the information of the received Data.
7076 * Function: rgSCHUtlSpsActInd
7081 * @param [in] RgSchCellCb *cellCb
7082 * @param [in] RgSchUeCb *ueCb
7083 * @param [in] uint16_t spsSduSize
7090 S16 rgSCHUtlSpsActInd
7092 RgSchCellCb *cellCb,
7097 S16 rgSCHUtlSpsActInd (cellCb, ueCb, spsSduSize)
7098 RgSchCellCb *cellCb;
7100 uint16_t spsSduSize;
7103 cellCb->sc.apis->rgSCHUlSpsActInd(cellCb, ueCb, spsSduSize);
7105 } /* end of rgSCHUtlSpsActInd */
7108 #endif /* LTEMAC_SPS */
7112 * @brief This API is invoked to send uplink group power control request to PHY.
7116 * Function : rgSCHUtlTfuGrpPwrCntrlReq
7118 * This API is invoked to send uplink group power control request to PHY.
7119 * It fills in the Pst structure, spId value and invokes group power
7120 * control request primitive at TFU.
7122 * @param[in] TfuGrpPwrCntrlReqInfo *grpPwrCntrlReq
7128 S16 rgSCHUtlTfuGrpPwrCntrlReq
7132 TfuGrpPwrCntrlReqInfo *grpPwrCntrlReq
7135 S16 rgSCHUtlTfuGrpPwrCntrlReq(inst, sapId, grpPwrCntrlReq)
7138 TfuGrpPwrCntrlReqInfo *grpPwrCntrlReq;
7142 RgSchLowSapCb *tfuSap;
7146 /* Get the lower SAP control block from the layer control block. */
7147 tfuSap = &(rgSchCb[inst].tfuSap[sapId]);
7148 if (tfuSap->sapSta.sapState != LRG_BND)
7150 RLOG_ARG1(L_ERROR,DBG_CELLID,grpPwrCntrlReq->cellId,
7151 "rgSCHUtlTfuGrpPwrCntrlReq() Lower SAP not bound (%d) ",tfuSap->sapSta.sapState);
7154 memcpy (&pst, &(tfuSap->sapCfg.sapPst), sizeof(Pst));
7155 if((ret = RgLiTfuGrpPwrCntrlReq (&pst, tfuSap->sapCfg.spId, grpPwrCntrlReq)) != ROK)
7157 RLOG_ARG0(L_ERROR,DBG_CELLID,grpPwrCntrlReq->cellId,
7158 "rgSCHUtlTfuGrpPwrCntrlReq() Call to RgLiTfuGrpPwrCntrlReq() failed");
7161 } /* rgSCHUtlTfuGrpPwrCntrlReq */
7164 /* FOR ACK NACK REP */
7167 * @brief This API is invoked to tell the DL Scheduler to add the UE back into
7168 * its scheduling queues.
7172 * Function : rgSCHUtlDlActvtUe
7174 * This API is invoked from Measurement gap moduled.
7176 * @param[in] RgSchCellCb *cell
7177 * @param[in] RgSchUeCb *ueCb
7184 S16 rgSCHUtlDlActvtUe
7190 S16 rgSCHUtlDlActvtUe(cell, ue)
7195 cell->sc.apis->rgSCHActvtDlUe(cell, ue);
7200 * @brief This API is invoked to tell the UL Scheduler to add the UE back into
7201 * its scheduling queues.
7205 * Function : rgSCHUtlUlActvtUe
7207 * This API is invoked from Measurement gap moduled.
7209 * @param[in] RgSchCellCb *cell
7210 * @param[in] RgSchUeCb *ueCb
7217 S16 rgSCHUtlUlActvtUe
7223 S16 rgSCHUtlUlActvtUe(cell, ue)
7228 cell->sc.apis->rgSCHActvtUlUe(cell, ue);
7232 /** @brief This function Validates the SAP information received along with the
7233 * primitive from the lower layer.
7235 * Function: rgSCHUtlValidateTfuSap
7237 * Validates SAP information.
7238 * @param suId The SAP Id
7244 S16 rgSCHUtlValidateTfuSap
7250 S16 rgSCHUtlValidateTfuSap(inst, suId)
7255 RgSchLowSapCb *tfuSap;
7257 if(suId >= rgSchCb[inst].numSaps)
7259 RLOG_ARG0(L_ERROR,DBG_INSTID,inst, "Incorrect SuId");
7262 tfuSap = &(rgSchCb[inst].tfuSap[suId]);
7264 /* First lets check the suId */
7265 if( suId != tfuSap->sapCfg.suId)
7267 RLOG_ARG2(L_ERROR,DBG_INSTID,inst,"Incorrect SuId. Configured (%d) Recieved (%d)",
7268 tfuSap->sapCfg.suId, suId);
7271 if (tfuSap->sapSta.sapState != LRG_BND)
7273 RLOG_ARG1(L_ERROR,DBG_INSTID,inst,"Lower SAP not enabled SuId (%d)",
7274 tfuSap->sapCfg.suId);
7278 } /* end of rgSCHUtlValidateTfuSap */
7282 * Fun: rgSCHUtlAllocEventMem
7284 * Desc: This function allocates event memory
7286 * Ret: ROK - on success
7287 * RFAILED - on failure
7295 S16 rgSCHUtlAllocEventMem
7302 S16 rgSCHUtlAllocEventMem(inst, memPtr, memSize)
7309 volatile uint32_t startTime=0;
7312 sMem.region = rgSchCb[inst].rgSchInit.region;
7313 sMem.pool = rgSchCb[inst].rgSchInit.pool;
7315 #if (ERRCLASS & ERRCLS_DEBUG)
7318 RGSCHLOGERROR(inst, ERRCLS_INT_PAR, ERG022, memSize,
7319 "rgAllocEventMem(): memSize invalid\n");
7322 #endif /* ERRCLASS & ERRCLS_DEBUG */
7324 SStartTask(&startTime, PID_SCHUTL_CMALLCEVT);
7326 #ifdef MS_MBUF_CORRUPTION /* Should be enabled when debugging mbuf corruption */
7327 MS_BUF_ADD_ALLOC_CALLER();
7329 #ifdef TFU_ALLOC_EVENT_NO_INIT
7330 if(ROK != cmAllocEvntNoInit(memSize, TFU_MAX_MEMBLK_SIZE, &sMem, memPtr))
7332 if(ROK != cmAllocEvnt(memSize, TFU_MAX_MEMBLK_SIZE, &sMem, memPtr))
7335 RLOG_ARG0(L_ERROR,DBG_INSTID,inst,"cmAllocEvnt Failed.");
7339 SStopTask(startTime, PID_SCHUTL_CMALLCEVT);
7341 } /* end of rgSCHUtlAllocEventMem*/
7345 * Fun: rgGetEventMem
7347 * Desc: This function allocates event memory
7349 * Ret: ROK - on success
7350 * RFAILED - on failure
7358 S16 rgSCHUtlGetEventMem
7365 S16 rgSCHUtlGetEventMem(ptr, len, memCp)
7373 #ifdef TFU_ALLOC_EVENT_NO_INIT
7374 ret = cmGetMemNoInit(memCp, len, (Ptr *)ptr);
7376 ret = cmGetMem(memCp, len, (Ptr *)ptr);
7379 } /* end of rgSCHUtlGetEventMem*/
7385 * @brief Handler to allocate memory for ACK/NACk feedback information
7389 * Function : rgSCHUtlAllocUeANFdbkInfo
7391 * It allocates memory for the UE related ACK NACK information.
7393 * @param[in] RgSchUeCb *ue
7397 S16 rgSCHUtlAllocUeANFdbkInfo
7403 S16 rgSCHUtlAllocUeANFdbkInfo(ue,servCellIdx)
7405 uint8_t servCellIdx;
7410 if (rgSCHUtlAllocSBuf(ue->cell->instIdx,
7411 (Data **) &(ue->cellInfo[servCellIdx]->anInfo), sizeof(RgSchTddANInfo) * \
7412 ue->cell->ackNackFdbkArrSize) != ROK)
7417 for(idx=0; idx < ue->cell->ackNackFdbkArrSize; idx++)
7419 rgSCHUtlInitUeANFdbkInfo(&ue->cellInfo[servCellIdx]->anInfo[idx]);
7422 /* Set it to the first index */
7423 ue->cellInfo[servCellIdx]->nextFreeANIdx = 0;
7425 } /* rgSCHUtlAllocUeANFdbkInfo */
7428 * @brief Handler to release memory for ACK/NACk feedback information
7432 * Function : rgSCHUtlDelUeANFdbkInfo
7434 * It releases memory for the UE related ACK NACK information.
7436 * @param[in] RgSchUeCb *ue
7440 Void rgSCHUtlDelUeANFdbkInfo
7446 Void rgSCHUtlDelUeANFdbkInfo(ue,servCellIdx)
7448 uint8_t servCellIdx;
7452 /* ccpu00117052 - MOD - Passing double pointer
7453 for proper NULLP assignment*/
7454 rgSCHUtlFreeSBuf(ue->cell->instIdx,
7455 (Data **)(&( ue->cellInfo[servCellIdx]->anInfo)), sizeof(RgSchTddANInfo) * \
7456 ue->cell->ackNackFdbkArrSize);
7459 } /* rgSCHUtlDelUeANFdbkInfo */
7462 * @brief Handler to initialise UE ACK/NACk feedback information
7466 * Function : rgSCHUtlInitUeANFdbkInfo
7468 * It initialises UE related ACK NACK information.
7470 * @param[in] RgSchTddANInfo *anFdInfo
7474 S16 rgSCHUtlInitUeANFdbkInfo
7476 RgSchTddANInfo *anFdInfo
7479 S16 rgSCHUtlInitUeANFdbkInfo(anFdInfo)
7480 RgSchTddANInfo *anFdInfo;
7484 anFdInfo->sfn = RGSCH_MAX_SFN+1; /* defensively setting invalid sfn */
7486 anFdInfo->ulDai = RG_SCH_INVALID_DAI_VAL;
7487 anFdInfo->dlDai = RG_SCH_INVALID_DAI_VAL;
7488 anFdInfo->latestMIdx = RG_SCH_INVALID_M_VAL;
7491 } /* rgSCHUtlInitUeANFdbkInfo */
7494 * @brief Handler to get UE related ACK NACK feedback information
7498 * Function : rgSCHUtlGetUeANFdbkInfo
7500 * It gets the UE related ACK NACK information based on
7501 * SFN and slot number.
7503 * @param[in] RgSchUeCb *ueCb
7504 * @param[in] CmLteTimingInfo *time
7505 * @return RgSchTddANInfo*
7508 RgSchTddANInfo* rgSCHUtlGetUeANFdbkInfo
7511 CmLteTimingInfo *timeInfo,
7515 RgSchTddANInfo* rgSCHUtlGetUeANFdbkInfo(ueCb, timeInfo,servCellIdx)
7517 CmLteTimingInfo *timeInfo;
7518 uint8_t servCellIdx;
7523 for (idx = 0; idx < ueCb->cell->ackNackFdbkArrSize; ++idx)
7525 if( (timeInfo->sfn == ueCb->cellInfo[servCellIdx]->anInfo[idx].sfn) &&
7526 (timeInfo->slot == ueCb->cellInfo[servCellIdx]->anInfo[idx].slot))
7528 return (&ueCb->cellInfo[servCellIdx]->anInfo[idx]);
7533 } /* rgSCHUtlGetUeANFdbkInfo */
7536 * @brief To get downlink slot index
7540 * Function: rgSCHUtlGetDlSfIdx
7541 * Purpose: Gets downlink slot index based on SFN and slot no
7543 * @param[in] CmLteTimingInfo *timeInfo
7544 * @param[in] RgSchCellCb *cell
7549 uint8_t rgSCHUtlGetDlSfIdx
7552 CmLteTimingInfo *timeInfo
7555 uint8_t rgSCHUtlGetDlSfIdx(cell, timeInfo)
7557 CmLteTimingInfo *timeInfo;
7562 idx = RGSCH_NUM_SUB_FRAMES - \
7563 rgSchTddNumUlSubfrmTbl[cell->ulDlCfgIdx][RGSCH_NUM_SUB_FRAMES-1];
7564 idx = ((idx * timeInfo->sfn) + \
7565 rgSchTddNumDlSubfrmTbl[cell->ulDlCfgIdx][timeInfo->slot]) - 1;
7566 idx = idx % cell->numDlSubfrms;
7568 return ((uint8_t)idx);
7572 * @brief To get the next downlink slot
7576 * Function: rgSCHUtlGetNxtDlSfInfo
7577 * Purpose: Gets next downlink slot based on current DL slot
7579 * @param[in] CmLteTimingInfo curDlTime
7580 * @param[in] RgSchCellCb *cell
7581 * @param[in] RgSchDlSf *dlSf
7582 * @param[in] RgSchDlSf **nxtDlsf
7583 * @param[in] CmLteTimingInfo *nxtDlTime
7588 Void rgSCHUtlGetNxtDlSfInfo
7590 CmLteTimingInfo curDlTime,
7593 RgSchDlSf **nxtDlsf,
7594 CmLteTimingInfo *nxtDlTime
7597 Void rgSCHUtlGetNxtDlSfInfo(curDlTime, cell, dlSf, nxtDlsf, nxtDlTime)
7598 CmLteTimingInfo curDlTime;
7601 RgSchDlSf **nxtDlsf;
7602 CmLteTimingInfo *nxtDlTime;
7605 uint16_t idx = curDlTime.slot;
7612 idx = (idx + 1) % RGSCH_NUM_SUB_FRAMES;
7614 }while(rgSchTddUlDlSubfrmTbl[cell->ulDlCfgIdx][idx]
7615 != RG_SCH_TDD_DL_slot);
7616 RG_SCH_ADD_TO_CRNT_TIME(curDlTime, (*nxtDlTime), count);
7617 *nxtDlsf = rgSCHUtlSubFrmGet(cell, *nxtDlTime);
7618 if(dlSf->dlFdbkInfo.slot != (*nxtDlsf)->dlFdbkInfo.slot)
7627 * @brief To get the previous downlink slot
7631 * Function: rgSCHUtlGetPrevDlSfInfo
7632 * Purpose: Gets previous downlink slot based on current DL slot
7634 * @param[in] RgSchCellCb *cell
7635 * @param[in] CmLteTimingInfo curDlTime
7636 * @param[in] CmLteTimingInfo *prevDlTime
7637 * @param[in] uint8_t *numSubfrm
7642 Void rgSCHUtlGetPrevDlSfInfo
7645 CmLteTimingInfo curDlTime,
7646 CmLteTimingInfo *prevDlTime,
7650 Void rgSCHUtlGetPrevDlSfInfo(cell, curDlTime, prevDlTime, numSubfrm)
7652 CmLteTimingInfo curDlTime;
7653 CmLteTimingInfo *prevDlTime;
7657 S16 idx = curDlTime.slot;
7665 idx = RGSCH_NUM_SUB_FRAMES-1;
7668 }while(rgSchTddUlDlSubfrmTbl[cell->ulDlCfgIdx][idx]
7669 != RG_SCH_TDD_DL_slot);
7671 RGSCHDECRFRMCRNTTIME(curDlTime, (*prevDlTime), count);
7676 /* Added Holes Management functions for Adaptive Re transmission */
7677 /******* </AllocHolesMemMgmnt>: START *****/
7678 /***********************************************************
7680 * Func : rgSCHUtlUlSfInit
7682 * Desc : UL slot init.
7690 **********************************************************/
7692 S16 rgSCHUtlUlSfInit
7700 S16 rgSCHUtlUlSfInit(cell, sf, idx, maxUePerSf)
7715 if(cell->ulDlCfgIdx == 0)
7717 /* Store the Uplink slot number corresponding to the idx */
7718 sf->ulSfIdx = rgSchTddCfg0UlSfTbl[idx%6];
7721 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&sf->allocDb,
7722 sizeof(RgSchUlAllocDb));
7727 ret = rgSCHUtlUlAllocDbInit(cell, sf->allocDb, maxUePerSf);
7730 /* ccpu00117052 - MOD - Passing double pointer
7731 for proper NULLP assignment*/
7732 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->allocDb)),
7733 sizeof(RgSchUlAllocDb));
7736 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&sf->holeDb,
7737 sizeof(RgSchUlHoleDb));
7740 rgSCHUtlUlAllocDbDeinit(cell, sf->allocDb);
7741 /* ccpu00117052 - MOD - Passing double pointer
7742 for proper NULLP assignment*/
7743 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->allocDb)),
7744 sizeof(RgSchUlAllocDb));
7747 /* Initialize the hole with CFI 1 Pusch Bw Info */
7748 ret = rgSCHUtlUlHoleDbInit(cell, sf->holeDb, (uint8_t)(maxUePerSf + 2), \
7749 0, cell->dynCfiCb.bwInfo[1].numSb);
7753 rgSCHUtlUlAllocDbDeinit(cell, sf->allocDb);
7754 /* ccpu00117052 - MOD - Passing double pointer
7755 for proper NULLP assignment*/
7756 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->allocDb)),
7757 sizeof(RgSchUlAllocDb));
7758 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->holeDb)),
7759 sizeof(RgSchUlHoleDb));
7762 cmLListInit(&sf->reTxLst);
7764 /* Fix ccpu00120610*/
7765 sf->allocCountRef = &sf->allocDb->count;
7767 /* initialize UL available subbands for current sub-frame */
7768 sf->availSubbands = cell->dynCfiCb.bwInfo[1].numSb;
7770 sf->numGrpPerTti = cell->cell5gtfCb.ueGrpPerTti;
7771 sf->numUePerGrp = cell->cell5gtfCb.uePerGrpPerTti;
7772 for(index = 0; index < MAX_5GTF_BEAMS; index++)
7774 sf->sfBeamInfo[index].totVrbgAllocated = 0;
7775 sf->sfBeamInfo[index].totVrbgRequired = 0;
7776 sf->sfBeamInfo[index].vrbgStart = 0;
7784 /***********************************************************
7786 * Func : rgSCHUtlUlSfDeinit
7788 * Desc : Deinitialises a slot
7796 **********************************************************/
7798 Void rgSCHUtlUlSfDeinit
7804 Void rgSCHUtlUlSfDeinit(cell, sf)
7811 rgSCHUtlUlAllocDbDeinit(cell, sf->allocDb);
7812 /* ccpu00117052 - MOD - Passing double pointer
7813 for proper NULLP assignment*/
7814 /* ccpu00117052 - MOD - Passing double pointer
7815 for proper NULLP assignment*/
7816 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->allocDb)),
7817 sizeof(RgSchUlAllocDb));
7821 rgSCHUtlUlHoleDbDeinit(cell, sf->holeDb);
7822 /* ccpu00117052 - MOD - Passing double pointer
7823 for proper NULLP assignment*/
7824 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->holeDb)),
7825 sizeof(RgSchUlHoleDb));
7830 /***********************************************************
7832 * Func : rgSCHUtlUlAllocDbInit
7834 * Desc : Initialise allocation DB
7836 * Ret : S16 (ROK/RFAILED)
7842 **********************************************************/
7844 static S16 rgSCHUtlUlAllocDbInit
7847 RgSchUlAllocDb *allocDb,
7851 static S16 rgSCHUtlUlAllocDbInit(cell, allocDb, maxAllocs)
7853 RgSchUlAllocDb *allocDb;
7857 S16 ret = rgSCHUtlUlAllocMemInit(cell, &allocDb->mem, maxAllocs);
7863 allocDb->first = NULLP;
7867 /***********************************************************
7869 * Func : rgSCHUtlUlAllocDbDeinit
7871 * Desc : Deinitialises allocation DB
7872 * sent to UE, for a UE with accumulation disabled
7880 **********************************************************/
7882 static Void rgSCHUtlUlAllocDbDeinit
7885 RgSchUlAllocDb *allocDb
7888 static Void rgSCHUtlUlAllocDbDeinit(cell, allocDb)
7890 RgSchUlAllocDb *allocDb;
7893 rgSCHUtlUlAllocMemDeinit(cell, &allocDb->mem);
7895 allocDb->first = NULLP;
7899 /***********************************************************
7901 * Func : rgSCHUtlUlHoleDbInit
7903 * Desc : Initialise hole DB
7905 * Ret : S16 (ROK/RFAILED)
7911 **********************************************************/
7913 static S16 rgSCHUtlUlHoleDbInit
7916 RgSchUlHoleDb *holeDb,
7922 static S16 rgSCHUtlUlHoleDbInit(cell, holeDb, maxHoles, start, num)
7924 RgSchUlHoleDb *holeDb;
7931 RgSchUlHole *hole = NULLP;
7933 ret = rgSCHUtlUlHoleMemInit(cell, &holeDb->mem, maxHoles, &hole);
7939 holeDb->first = hole;
7940 hole->start = start;
7942 hole->prv = hole->nxt = NULLP;
7946 /***********************************************************
7948 * Func : rgSCHUtlUlHoleDbDeinit
7950 * Desc : Deinitialises hole DB
7958 **********************************************************/
7960 static Void rgSCHUtlUlHoleDbDeinit
7963 RgSchUlHoleDb *holeDb
7966 static Void rgSCHUtlUlHoleDbDeinit(cell, holeDb)
7968 RgSchUlHoleDb *holeDb;
7971 rgSCHUtlUlHoleMemDeinit(cell, &holeDb->mem);
7973 holeDb->first = NULLP;
7978 /***********************************************************
7980 * Func : rgSCHUtlUlAllocGetHole
7982 * Desc : Get allocation from hole
7984 * Ret : RgSchUlAlloc *
7990 **********************************************************/
7992 RgSchUlAlloc *rgSCHUtlUlAllocGetHole
7999 RgSchUlAlloc *rgSCHUtlUlAllocGetHole(sf, numSb, hole)
8005 if (numSb < hole->num)
8007 return (rgSCHUtlUlAllocGetPartHole(sf, numSb, hole));
8011 return (rgSCHUtlUlAllocGetCompHole(sf, hole));
8016 /***********************************************************
8018 * Func : rgSCHUtlUlAllocGetCompHole
8020 * Desc : Get an allocation corresponding to an entire hole
8022 * Ret : RgSchUlAlloc *
8028 **********************************************************/
8030 RgSchUlAlloc *rgSCHUtlUlAllocGetCompHole
8036 RgSchUlAlloc *rgSCHUtlUlAllocGetCompHole(sf, hole)
8041 RgSchUlAlloc *alloc;
8042 /* alloc = rgSCHUtlUlAllocGetAndIns(sf->allocDb, hole->prvAlloc, hole->nxtAlloc); */
8043 /* Calling rgSchCmnUlAllocGetAndIns is ok, but prv alloc needs to have nxtHole
8044 * updated, causing another check for prv */
8045 RgSchUlAlloc *prv = hole->prvAlloc;
8046 RgSchUlAlloc *nxt = hole->nxtAlloc;
8050 if (hole->start == prv->nxtHole->start)
8052 prv->nxtHole = NULLP;
8054 alloc = rgSCHUtlUlAllocGetAdjNxt(sf->allocDb, prv);
8058 alloc = rgSCHUtlUlAllocGetFirst(sf->allocDb);
8061 RGSCH_NULL_CHECK( 0, alloc);
8062 alloc->prvHole = NULLP;
8063 alloc->nxtHole = NULLP;
8065 alloc->sbStart = hole->start;
8066 alloc->numSb = hole->num;
8070 nxt->prvHole = NULLP;
8073 rgSCHUtlUlHoleRls(sf->holeDb, hole);
8075 /* UL_ALLOC_CHANGES*/
8076 alloc->allocDbRef = (void*)sf->allocDb;
8077 alloc->holeDbRef = (void*)sf->holeDb;
8081 /***********************************************************
8083 * Func : rgSCHUtlUlAllocGetPartHole
8085 * Desc : Get an allocation corresponding to a part of a hole.
8086 * The initial 'numSb' part of the hole shall be taken
8087 * away for this alloc.
8089 * Ret : RgSchUlAlloc *
8095 **********************************************************/
8097 RgSchUlAlloc *rgSCHUtlUlAllocGetPartHole
8104 RgSchUlAlloc *rgSCHUtlUlAllocGetPartHole(sf, numSb, hole)
8110 RgSchUlAlloc *alloc;
8111 /* alloc = rgSCHUtlUlAllocGetAndIns(sf->allocDb, hole->prvAlloc, hole->nxtAlloc); */
8112 /* Calling rgSchCmnUlAllocGetAndIns is ok, but prv alloc needs to have nxtHole
8113 * updated, causing another check for prv */
8114 RgSchUlAlloc *prv = hole->prvAlloc;
8118 if (hole->start == prv->nxtHole->start)
8120 prv->nxtHole = NULLP;
8122 alloc = rgSCHUtlUlAllocGetAdjNxt(sf->allocDb, prv);
8126 alloc = rgSCHUtlUlAllocGetFirst(sf->allocDb);
8129 RGSCH_NULL_CHECK( 0, alloc);
8130 alloc->prvHole = NULLP;
8131 alloc->nxtHole = hole;
8132 hole->prvAlloc = alloc;
8134 alloc->sbStart = hole->start;
8135 alloc->numSb = numSb;
8136 hole->start += numSb;
8139 rgSCHUtlUlHoleDecr(sf->holeDb, hole);
8141 /* UL_ALLOC_CHANGES*/
8142 alloc->allocDbRef = (void*)sf->allocDb;
8143 alloc->holeDbRef = (void*)sf->holeDb;
8148 /***********************************************************
8150 * Func : rgSCHUtlUlAllocFirst
8152 * Desc : Get first alloc in slot
8154 * Ret : RgSchUlAlloc *
8160 **********************************************************/
8162 RgSchUlAlloc *rgSCHUtlUlAllocFirst
8167 RgSchUlAlloc *rgSCHUtlUlAllocFirst(sf)
8171 return (sf->allocDb->first);
8174 /***********************************************************
8176 * Func : rgSCHUtlUlAllocNxt
8178 * Desc : Get next alloc
8180 * Ret : RgSchUlAlloc *
8186 **********************************************************/
8188 RgSchUlAlloc *rgSCHUtlUlAllocNxt
8194 RgSchUlAlloc *rgSCHUtlUlAllocNxt(sf, alloc)
8196 RgSchUlAlloc *alloc;
8200 return (alloc->nxt);
8203 /***********************************************************
8205 * Func : rgSCHUtlUlAllocGetAdjNxt
8207 * Desc : Get alloc which is immediately after the passed one.
8208 * 1. Gets alloc from mem.
8209 * 2. Inserts alloc into list (between prv and
8210 * prv->nxt, prv is not NULLP).
8211 * 3. Increments alloc count.
8212 * Note 1: Holes are not dealt with here.
8213 * Note 2: Assumes prv to be NULL.
8215 * Ret : RgSchUlAlloc *
8221 **********************************************************/
8223 RgSchUlAlloc *rgSCHUtlUlAllocGetAdjNxt
8229 RgSchUlAlloc *rgSCHUtlUlAllocGetAdjNxt(db, prv)
8234 RgSchUlAlloc *alloc = rgSCHUtlUlAllocMemGet(&db->mem);
8235 RgSchUlAlloc *nxt = prv->nxt;
8237 #if (ERRCLASS & ERRCLS_DEBUG)
8238 if ( alloc == NULLP )
8256 /***********************************************************
8258 * Func : rgSCHUtlUlAllocGetFirst
8260 * Desc : Get alloc which is to be the first one in the alloc list
8261 * 1. Gets alloc from mem.
8262 * 2. Inserts alloc as first element into list.
8263 * 3. Increments alloc count.
8264 * Note 1: Holes are not dealt with here.
8265 * Note 2: prv to necessarily NULLP.
8267 * Ret : RgSchUlAlloc *
8273 **********************************************************/
8275 RgSchUlAlloc *rgSCHUtlUlAllocGetFirst
8280 RgSchUlAlloc *rgSCHUtlUlAllocGetFirst(db)
8284 RgSchUlAlloc *alloc = rgSCHUtlUlAllocMemGet(&db->mem);
8285 RgSchUlAlloc *nxt = db->first;
8287 #if (ERRCLASS & ERRCLS_DEBUG)
8288 if ( alloc == NULLP )
8307 /* UL_ALLOC_ENHANCEMENT */
8308 /***********************************************************
8310 * Func : rgSCHUtlUlHoleAddAllocation
8312 * Desc : On freeing an alloc, add to hole
8320 **********************************************************/
8322 Void rgSCHUtlUlHoleAddAllocation
8327 Void rgSCHUtlUlHoleAddAllocation(alloc)
8328 RgSchUlAlloc *alloc;
8331 /* Note: rgSchCmnUlHoleUpdAllocLnks function that is used should not exist as
8332 * one, if such excessive branching is done (AllocNone, AllocNoPrv etc).
8333 * The excessive branching is meant to utilise the knowledge of whether prv
8334 * and nxt allocs exist or not. Hence for each kind (none, noprv, nonxt,
8335 * both), there should be a rgSchCmnUlHoleUpdAllocLnks... function (such as
8336 * rgSchCmnUlHoleUpdAllocLnksNone/NoPrv etc. */
8337 RgSchUlHoleDb *db = alloc->holeDbRef;
8338 RgSchUlHole *prv = alloc->prvHole;
8339 RgSchUlHole *nxt = alloc->nxtHole;
8345 rgSCHUtlUlHoleJoin(db, prv, nxt, alloc);
8348 rgSCHUtlUlHoleExtndRight(db, prv, alloc);
8354 rgSCHUtlUlHoleExtndLeft(db, nxt, alloc);
8357 rgSCHUtlUlHoleNew(db, alloc);
8363 /***********************************************************
8365 * Func : rgSCHUtlUlAllocRelease
8367 * Desc : Releases an uplink allocation, only take alloc ptr
8375 **********************************************************/
8377 Void rgSCHUtlUlAllocRelease
8382 Void rgSCHUtlUlAllocRelease(alloc)
8383 RgSchUlAlloc *alloc;
8386 RgSchUlAllocDb *allocDb = alloc->allocDbRef;
8387 RgSchUlAlloc *prv = alloc->prv;
8388 RgSchUlAlloc *nxt = alloc->nxt;
8391 alloc->raCb = NULLP;
8392 alloc->isAdaptive = FALSE;
8397 if (nxt) /* general case: this allocation lies btw two */
8404 allocDb->first = nxt;
8411 rgSCHUtlUlHoleAddAllocation(alloc);
8412 rgSCHUtlUlAllocMemRls(&allocDb->mem, alloc);
8418 /***********************************************************
8420 * Func : rgSCHUtlUlAllocRls
8422 * Desc : Releases an uplink allocation
8430 **********************************************************/
8432 Void rgSCHUtlUlAllocRls
8438 Void rgSCHUtlUlAllocRls(sf, alloc)
8440 RgSchUlAlloc *alloc;
8443 RgSchUlAllocDb *allocDb = sf->allocDb;
8444 RgSchUlAlloc *prv = alloc->prv;
8445 RgSchUlAlloc *nxt = alloc->nxt;
8448 alloc->raCb = NULLP;
8449 alloc->isAdaptive = FALSE;
8456 if (nxt) /* general case: this allocation lies btw two */
8463 allocDb->first = nxt;
8470 rgSCHUtlUlHoleAddAlloc(sf, alloc);
8471 rgSCHUtlUlAllocMemRls(&allocDb->mem, alloc);
8476 printf("\nError: allocDb->count is ZERO ====\n");
8479 //printf("\nallocDb->count:%u\n",allocDb->count);
8484 /***********************************************************
8486 * Func : rgSCHUtlUlHoleFirst
8488 * Desc : Get first (largest) hole
8490 * Ret : RgSchUlHole *
8496 **********************************************************/
8498 RgSchUlHole *rgSCHUtlUlHoleFirst
8503 RgSchUlHole *rgSCHUtlUlHoleFirst(sf)
8507 return (sf->holeDb->first);
8510 /***********************************************************
8512 * Func : rgSCHUtlUlHoleNxt
8514 * Desc : Get next largest hole
8516 * Ret : RgSchUlHole *
8522 **********************************************************/
8524 RgSchUlHole *rgSCHUtlUlHoleNxt
8530 RgSchUlHole *rgSCHUtlUlHoleNxt(sf, hole)
8539 /***********************************************************
8541 * Func : rgSCHUtlUlHoleAddAlloc
8543 * Desc : On freeing an alloc, add to hole
8551 **********************************************************/
8553 Void rgSCHUtlUlHoleAddAlloc
8559 Void rgSCHUtlUlHoleAddAlloc(sf, alloc)
8561 RgSchUlAlloc *alloc;
8564 /* Note: rgSchCmnUlHoleUpdAllocLnks function that is used should not exist as
8565 * one, if such excessive branching is done (AllocNone, AllocNoPrv etc).
8566 * The excessive branching is meant to utilise the knowledge of whether prv
8567 * and nxt allocs exist or not. Hence for each kind (none, noprv, nonxt,
8568 * both), there should be a rgSchCmnUlHoleUpdAllocLnks... function (such as
8569 * rgSchCmnUlHoleUpdAllocLnksNone/NoPrv etc. */
8570 RgSchUlHoleDb *db = sf->holeDb;
8571 RgSchUlHole *prv = alloc->prvHole;
8572 RgSchUlHole *nxt = alloc->nxtHole;
8578 rgSCHUtlUlHoleJoin(db, prv, nxt, alloc);
8581 rgSCHUtlUlHoleExtndRight(db, prv, alloc);
8587 rgSCHUtlUlHoleExtndLeft(db, nxt, alloc);
8590 rgSCHUtlUlHoleNew(db, alloc);
8593 /* increment the number of subbands getting freed to total available list */
8594 sf->availSubbands += alloc->numSb;
8599 /***********************************************************
8601 * Func : rgSCHUtlUlHoleJoin
8603 * Desc : Join two holes (due to alloc being deleted)
8611 **********************************************************/
8613 Void rgSCHUtlUlHoleJoin
8621 Void rgSCHUtlUlHoleJoin(db, prv, nxt, alloc)
8625 RgSchUlAlloc *alloc;
8628 prv->num += alloc->numSb + nxt->num;
8629 rgSCHUtlUlHoleRls(db, nxt);
8630 rgSCHUtlUlHoleIncr(db, prv);
8631 rgSCHUtlUlHoleUpdAllocLnks(prv, alloc->prv, alloc->nxt);
8636 /***********************************************************
8638 * Func : rgSCHUtlUlHoleExtndRight
8640 * Desc : Extend hole due to alloc coming 'after' the hole
8649 **********************************************************/
8651 Void rgSCHUtlUlHoleExtndRight
8658 Void rgSCHUtlUlHoleExtndRight(db, prv, alloc)
8661 RgSchUlAlloc *alloc;
8664 prv->num += alloc->numSb;
8665 rgSCHUtlUlHoleIncr(db, prv);
8666 rgSCHUtlUlHoleUpdAllocLnks(prv, alloc->prv, alloc->nxt);
8670 /***********************************************************
8672 * Func : rgSCHUtlUlHoleExtndLeft
8674 * Desc : Extend hole due to alloc coming 'before' the hole
8683 **********************************************************/
8685 Void rgSCHUtlUlHoleExtndLeft
8692 Void rgSCHUtlUlHoleExtndLeft(db, nxt, alloc)
8695 RgSchUlAlloc *alloc;
8698 nxt->num += alloc->numSb;
8699 nxt->start = alloc->sbStart;
8700 rgSCHUtlUlHoleIncr(db, nxt);
8701 rgSCHUtlUlHoleUpdAllocLnks(nxt, alloc->prv, alloc->nxt);
8705 /***********************************************************
8707 * Func : rgSCHUtlUlHoleNew
8709 * Desc : Create new hole due to alloc being deleted
8717 **********************************************************/
8719 Void rgSCHUtlUlHoleNew
8725 Void rgSCHUtlUlHoleNew(db, alloc)
8727 RgSchUlAlloc *alloc;
8730 RgSchUlHole *hole = rgSCHUtlUlHoleMemGet(&db->mem);
8731 #if (ERRCLASS & ERRCLS_DEBUG)
8732 if ( hole == NULLP )
8737 hole->start = alloc->sbStart;
8738 hole->num = alloc->numSb;
8740 rgSCHUtlUlHoleIns(db, hole);
8741 rgSCHUtlUlHoleUpdAllocLnks(hole, alloc->prv, alloc->nxt);
8745 /***********************************************************
8747 * Func : rgSCHUtlUlHoleUpdAllocLnks
8749 * Desc : Update alloc links in hole
8757 **********************************************************/
8759 Void rgSCHUtlUlHoleUpdAllocLnks
8762 RgSchUlAlloc *prvAlloc,
8763 RgSchUlAlloc *nxtAlloc
8766 Void rgSCHUtlUlHoleUpdAllocLnks(hole, prvAlloc, nxtAlloc)
8768 RgSchUlAlloc *prvAlloc;
8769 RgSchUlAlloc *nxtAlloc;
8774 prvAlloc->nxtHole = hole;
8778 nxtAlloc->prvHole = hole;
8780 hole->prvAlloc = prvAlloc;
8781 hole->nxtAlloc = nxtAlloc;
8786 /***********************************************************
8788 * Func : rgSCHUtlUlHoleIns
8790 * Desc : Insert (newly created) hole in sorted list of holes.
8791 * Searches linearly, beginning with the largest hole.
8799 **********************************************************/
8801 Void rgSCHUtlUlHoleIns
8807 Void rgSCHUtlUlHoleIns(db, hole)
8814 if ((cur = db->first) != NULLP)
8817 if (cur->num < hole->num)
8827 for (nxt = cur->nxt; nxt; cur = nxt, nxt = nxt->nxt)
8829 if (nxt->num < hole->num)
8831 /* Insert hole: cur <-> hole <-> nxt */
8847 /* This is the first hole */
8849 hole->prv = NULLP; /* may not be needed */
8855 /***********************************************************
8857 * Func : rgSCHUtlUlHoleIncr
8859 * Desc : hole->num has increeased, reposition in sorted
8868 **********************************************************/
8870 Void rgSCHUtlUlHoleIncr
8876 Void rgSCHUtlUlHoleIncr(db, hole)
8883 if ((cur = hole->prv) != NULLP)
8887 if (cur->num > hole->num)
8892 /* Remove hole from current position */
8893 cur->nxt = hole->nxt;
8896 hole->nxt->prv = cur;
8899 for (prv = cur->prv; prv; cur = prv, prv = prv->prv)
8901 if (prv->num > hole->num)
8903 /* Insert hole: prv <-> hole <-> cur */
8922 /***********************************************************
8924 * Func : rgSCHUtlUlHoleDecr
8926 * Desc : hole->num has decreeased, reposition in sorted
8935 **********************************************************/
8937 Void rgSCHUtlUlHoleDecr
8943 Void rgSCHUtlUlHoleDecr(db, hole)
8950 if ((cur = hole->nxt) != NULLP)
8954 if (cur->num < hole->num)
8959 /* Remove hole from current position */
8960 cur->prv = hole->prv;
8963 hole->prv->nxt = cur;
8965 else /* no prv, so cur to replace hole as first in list */
8970 for (nxt = cur->nxt; nxt; cur = nxt, nxt = nxt->nxt)
8972 if (nxt->num < hole->num)
8974 /* Insert hole: cur <-> hole <-> nxt */
8992 /***********************************************************
8994 * Func : rgSCHUtlUlHoleRls
8996 * Desc : Releases hole.
8997 * 1. Decrements hole count.
8998 * 2. Deletes hole from list.
8999 * 3. Frees hole (hole memory release).
9007 **********************************************************/
9009 Void rgSCHUtlUlHoleRls
9015 Void rgSCHUtlUlHoleRls(db, hole)
9020 RgSchUlHole *prv = hole->prv;
9021 RgSchUlHole *nxt = hole->nxt;
9041 rgSCHUtlUlHoleMemRls(&db->mem, hole);
9046 /***********************************************************
9048 * Func : rgSCHUtlUlAllocMemInit
9050 * Desc : Initialises alloc free pool
9052 * Ret : S16 (ROK/RFAILED)
9058 **********************************************************/
9060 S16 rgSCHUtlUlAllocMemInit
9063 RgSchUlAllocMem *mem,
9067 S16 rgSCHUtlUlAllocMemInit(cell, mem, maxAllocs)
9069 RgSchUlAllocMem *mem;
9074 RgSchUlAlloc *allocs;
9076 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&allocs,
9077 maxAllocs * sizeof(*allocs));
9082 mem->allocs = allocs;
9083 mem->maxAllocs = maxAllocs;
9084 if (mem->maxAllocs == 1)
9086 allocs[0].prv = NULLP;
9087 allocs[0].nxt = NULLP;
9092 allocs[0].prv = NULLP;
9093 allocs[0].nxt = &allocs[1];
9094 for (i = 1; i < mem->maxAllocs - 1; ++i)
9096 allocs[i].prv = &allocs[i-1];
9097 allocs[i].nxt = &allocs[i+1];
9099 allocs[i].prv = &allocs[i-1];
9100 allocs[i].nxt = NULLP;
9102 mem->firstFree = &allocs[0];
9106 /***********************************************************
9108 * Func : rgSCHUtlUlAllocMemDeinit
9110 * Desc : Deinitialises alloc free pool
9118 **********************************************************/
9120 Void rgSCHUtlUlAllocMemDeinit
9123 RgSchUlAllocMem *mem
9126 Void rgSCHUtlUlAllocMemDeinit(cell, mem)
9128 RgSchUlAllocMem *mem;
9131 /* ccpu00117052 - MOD - Passing double pointer
9132 for proper NULLP assignment*/
9133 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(mem->allocs)),
9134 mem->maxAllocs * sizeof(*mem->allocs));
9136 mem->firstFree = NULLP;
9140 /***********************************************************
9142 * Func : rgSCHUtlUlHoleMemInit
9144 * Desc : Initialises hole free pool. Assumes maxHoles
9147 * Ret : S16 (ROK/RFAILED)
9153 **********************************************************/
9155 S16 rgSCHUtlUlHoleMemInit
9158 RgSchUlHoleMem *mem,
9160 RgSchUlHole **holeRef
9163 S16 rgSCHUtlUlHoleMemInit(cell, mem, maxHoles, holeRef)
9165 RgSchUlHoleMem *mem;
9167 RgSchUlHole **holeRef;
9173 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&holes,
9174 maxHoles * sizeof(*holes));
9181 mem->maxHoles = maxHoles;
9183 /* first hole is taken up */
9184 holes[0].prv = NULLP; /* not needed */
9185 holes[0].nxt = NULLP; /* not needed */
9186 *holeRef = &holes[0];
9188 if (mem->maxHoles == 2)
9190 holes[1].prv = NULLP; /* may not be needed */
9191 holes[1].nxt = NULLP; /* may not be needed */
9196 holes[1].prv = NULLP;
9197 holes[0].nxt = &holes[1];
9198 for (i = 1; i < mem->maxHoles - 1; ++i)
9200 holes[i].prv = &holes[i-1];
9201 holes[i].nxt = &holes[i+1];
9203 holes[i].prv = &holes[i-1];
9204 holes[i].nxt = NULLP;
9206 mem->firstFree = &holes[1];
9211 /***********************************************************
9213 * Func : rgSCHUtlUlHoleMemDeinit
9215 * Desc : Deinitialises hole free pool
9223 **********************************************************/
9225 Void rgSCHUtlUlHoleMemDeinit
9231 Void rgSCHUtlUlHoleMemDeinit(cell, mem)
9233 RgSchUlHoleMem *mem;
9236 /* ccpu00117052 - MOD - Passing double pointer
9237 for proper NULLP assignment*/
9238 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(mem->holes)),
9239 mem->maxHoles * sizeof(*mem->holes));
9241 mem->firstFree = NULLP;
9245 /***********************************************************
9247 * Func : rgSCHUtlUlAllocMemGet
9249 * Desc : Gets an 'alloc' from the free pool
9251 * Ret : RgSchUlAlloc *
9257 **********************************************************/
9259 RgSchUlAlloc *rgSCHUtlUlAllocMemGet
9261 RgSchUlAllocMem *mem
9264 RgSchUlAlloc *rgSCHUtlUlAllocMemGet(mem)
9265 RgSchUlAllocMem *mem;
9268 RgSchUlAlloc *alloc;
9270 #if (ERRCLASS & ERRCLS_DEBUG)
9271 if (mem->firstFree == NULLP)
9277 alloc = mem->firstFree;
9278 mem->firstFree = alloc->nxt;
9279 alloc->nxt = NULLP; /* probably not needed */
9280 /* alloc->prv might already be NULLP, in case was needed to set it to NULLP */
9285 /***********************************************************
9287 * Func : rgSCHUtlUlAllocMemRls
9289 * Desc : Returns an 'alloc' to the free pool
9297 **********************************************************/
9299 Void rgSCHUtlUlAllocMemRls
9301 RgSchUlAllocMem *mem,
9305 Void rgSCHUtlUlAllocMemRls(mem, alloc)
9306 RgSchUlAllocMem *mem;
9307 RgSchUlAlloc *alloc;
9312 alloc->nxt = mem->firstFree;
9313 if (mem->firstFree != NULLP)
9315 mem->firstFree->prv = alloc;
9317 mem->firstFree = alloc;
9321 /***********************************************************
9323 * Func : rgSCHUtlUlHoleMemGet
9325 * Desc : Gets a 'hole' from the free pool
9327 * Ret : RgSchUlHole *
9333 **********************************************************/
9335 RgSchUlHole *rgSCHUtlUlHoleMemGet
9340 RgSchUlHole *rgSCHUtlUlHoleMemGet(mem)
9341 RgSchUlHoleMem *mem;
9346 #if (ERRCLASS & ERRCLS_DEBUG)
9347 if (mem->firstFree == NULLP)
9353 hole = mem->firstFree;
9354 mem->firstFree = hole->nxt;
9355 mem->firstFree->prv = NULLP; /* may not be needed, under error class */
9356 hole->nxt = NULLP; /* probably not needed */
9357 /* hole->prv is might already be NULLP, in case was needed to set it to NULLP */
9362 /***********************************************************
9364 * Func : rgSCHUtlUlHoleMemRls
9366 * Desc : Returns a 'hole' to the free pool
9374 **********************************************************/
9376 Void rgSCHUtlUlHoleMemRls
9378 RgSchUlHoleMem *mem,
9382 Void rgSCHUtlUlHoleMemRls(mem, hole)
9383 RgSchUlHoleMem *mem;
9389 hole->nxt = mem->firstFree;
9390 if (mem->firstFree != NULLP)
9392 mem->firstFree->prv = hole;
9394 mem->firstFree = hole;
9399 * @brief Get an alloc from the specified position in the BW.
9403 * Function : rgSCHUtlUlGetSpfcAlloc
9405 * - Return an alloc from the specified position in the BW.
9406 * Note: This function assumes there is always a hole
9407 * Existing which completely has the specified
9408 * allocation. The reason for such an assumption is
9409 * the function's usage as of now guarantees that there
9410 * will always be such hole. And also for efficiency.
9412 * @param[in] RgSchUlSf *sf
9413 * @param[in] uint8_t startSb
9414 * @param[in] uint8_t numSb
9415 * @return RgSchUlAlloc*
9418 RgSchUlAlloc *rgSCHUtlUlGetSpfcAlloc
9425 RgSchUlAlloc *rgSCHUtlUlGetSpfcAlloc(sf, startSb, numSb)
9431 RgSchUlHole *hole, *nxtHole;
9432 RgSchUlAlloc *alloc = NULLP;
9434 if ((hole = rgSCHUtlUlHoleFirst(sf)) == NULLP)
9440 nxtHole = rgSCHUtlUlHoleNxt(sf, hole);
9441 if ((startSb >= hole->start) &&
9442 (startSb+numSb <= hole->start+hole->num))
9444 if (startSb != hole->start)
9446 /* Create a new hole to accomodate Subbands between
9447 * hole start and req alloc start */
9448 RgSchUlHole *newHole = rgSCHUtlUlHoleMemGet(&(sf->holeDb->mem));
9450 #if (ERRCLASS & ERRCLS_DEBUG)
9451 if ( newHole == NULLP )
9456 newHole->start = hole->start;
9457 newHole->num = startSb - hole->start;
9458 hole->start = startSb;
9459 /* [ccpu00122847]-MOD- Correctly updating the hole->num */
9460 hole->num -= newHole->num;
9461 ++(sf->holeDb->count);
9462 rgSCHUtlUlHoleIns(sf->holeDb, newHole);
9463 newHole->prvAlloc = hole->prvAlloc;
9464 if (newHole->prvAlloc)
9466 newHole->prvAlloc->nxtHole = newHole;
9468 if (numSb == hole->num)
9470 alloc = rgSCHUtlUlAllocGetCompHole(sf, hole);
9474 alloc = rgSCHUtlUlAllocGetPartHole(sf, numSb, hole);
9476 alloc->prvHole = newHole;
9477 newHole->nxtAlloc = alloc;
9479 else /* Hole start and req alloc start are same */
9481 if (numSb == hole->num)
9483 alloc = rgSCHUtlUlAllocGetCompHole(sf, hole);
9487 alloc = rgSCHUtlUlAllocGetPartHole(sf, numSb, hole);
9492 } while ((hole = nxtHole) != NULLP);
9497 * @brief Validates the qci values
9501 * Function :rgSCHUtlValidateQci
9503 * @param[in] RgSchCellCb *cellCb
9504 * @param[in] uint8_t numQci
9505 * @param[out] uint8_t *qci
9511 static S16 rgSCHUtlValidateQci
9513 RgSchCellCb *cellCb,
9518 static S16 rgSCHUtlValidateQci(cellCb, numQci, qci)
9519 RgSchCellCb *cellCb;
9528 for(qciIdx = 0; qciIdx < numQci; qciIdx++)
9530 qciVal = qci[qciIdx];
9531 if(qciVal == 0 || qciVal > 9)
9535 if(qciVal != cellCb->qciArray[qciVal].qci)
9542 }/* rgSCHUtlValidateQci */
9544 * @brief Validates the measurement request parameters.
9548 * Function :rgSCHUtlValidateMeasReq
9550 * @param[in] RgSchCellCb *cellCb
9551 * @param[in] LrgSchMeasReqInfo *schL2MeasInfo
9552 * @param[out] RgSchErrInfo *err
9553 * @return RgSchUlAlloc*
9556 S16 rgSCHUtlValidateMeasReq
9558 RgSchCellCb *cellCb,
9559 LrgSchMeasReqInfo *schL2MeasInfo,
9563 S16 rgSCHUtlValidateMeasReq(cellCb, schL2MeasInfo, err)
9564 RgSchCellCb *cellCb;
9565 LrgSchMeasReqInfo *schL2MeasInfo;
9573 measType = schL2MeasInfo->measType;
9575 if((measType == 0) ||
9578 err->errType = RGSCHERR_SCH_INVALID_MEAS_TYPE;
9579 err->errCause = RGSCHERR_SCH_L2MEAS;
9582 if((schL2MeasInfo->timePrd !=0) &&
9583 (measType & LRG_L2MEAS_AVG_PRB_PER_QCI_DL) &&
9584 ((schL2MeasInfo->avgPrbQciDl.numQci > LRG_MAX_QCI_PER_REQ)||
9585 (schL2MeasInfo->avgPrbQciDl.numQci == 0)))
9587 err->errType = RGSCHERR_SCH_INVALID_PARAM_RANGE;
9588 err->errCause = RGSCHERR_SCH_L2MEAS;
9591 if((schL2MeasInfo->timePrd !=0) &&
9592 (measType & LRG_L2MEAS_AVG_PRB_PER_QCI_UL) &&
9593 (schL2MeasInfo->avgPrbQciUl.numQci > LRG_MAX_QCI_PER_REQ))
9595 err->errType = RGSCHERR_SCH_INVALID_PARAM_RANGE;
9596 err->errCause = RGSCHERR_SCH_L2MEAS;
9599 if((measType & LRG_L2MEAS_NMB_ACTV_UE_PER_QCI_DL) &&
9600 ((schL2MeasInfo->nmbActvUeQciDl.numQci > LRG_MAX_QCI_PER_REQ) ||
9601 (schL2MeasInfo->nmbActvUeQciDl.sampPrd == 0)||
9602 ((schL2MeasInfo->timePrd !=0)&&
9603 (schL2MeasInfo->timePrd < schL2MeasInfo->nmbActvUeQciDl.sampPrd)) ||
9604 (schL2MeasInfo->nmbActvUeQciDl.sampPrd > LRG_MAX_SAMP_PRD)))
9606 err->errType = RGSCHERR_SCH_INVALID_PARAM_RANGE;
9607 err->errCause = RGSCHERR_SCH_L2MEAS;
9610 if((measType & LRG_L2MEAS_NMB_ACTV_UE_PER_QCI_UL) &&
9611 ((schL2MeasInfo->nmbActvUeQciUl.numQci > LRG_MAX_QCI_PER_REQ) ||
9612 (schL2MeasInfo->nmbActvUeQciUl.sampPrd == 0)||
9613 ((schL2MeasInfo->timePrd !=0) &&
9614 (schL2MeasInfo->timePrd < schL2MeasInfo->nmbActvUeQciUl.sampPrd)) ||
9615 (schL2MeasInfo->nmbActvUeQciUl.sampPrd > LRG_MAX_SAMP_PRD)))
9617 err->errType = RGSCHERR_SCH_INVALID_PARAM_RANGE;
9618 err->errCause = RGSCHERR_SCH_L2MEAS;
9621 if((schL2MeasInfo->timePrd !=0) &&
9622 (measType & LRG_L2MEAS_AVG_PRB_PER_QCI_DL))
9624 RGSCH_ARRAY_BOUND_CHECK(cellCb->instIdx, schL2MeasInfo->avgPrbQciDl.qci, \
9625 (schL2MeasInfo->avgPrbQciDl.numQci));
9626 ret = rgSCHUtlValidateQci(cellCb, schL2MeasInfo->avgPrbQciDl.numQci,
9627 schL2MeasInfo->avgPrbQciDl.qci);
9630 err->errType = RGSCHERR_SCH_INVALID_QCI_VAL;
9631 err->errCause = RGSCHERR_SCH_L2MEAS;
9636 }/* rgSCHUtlValidateMeasReq */
9637 #endif /* LTE_L2_MEAS */
9638 /******* </AllocHolesMemMgmnt>: END *****/
9641 * @brief API for sending SI configuration confirm from Scheduler to RRM
9645 * Function: rgSCHUtlRgrSiCfgCfm
9647 * This API is invoked to send SI configuration confirm from Scheduler
9649 * This API fills in Pst structure and SAP Ids and invokes
9650 * config confirm API towards RRM.
9652 * @param[in] RgrCfgTransId transId
9653 * @param[in] uint8_t status
9659 S16 rgSCHUtlRgrSiCfgCfm
9663 RgrCfgTransId transId,
9667 S16 rgSCHUtlRgrSiCfgCfm(instId, spId, transId, status)
9670 RgrCfgTransId transId;
9674 uint8_t prntTrans[RGR_CFG_TRANSID_SIZE+1];
9677 memcpy(prntTrans, transId.trans, RGR_CFG_TRANSID_SIZE);
9678 prntTrans[RGR_CFG_TRANSID_SIZE] = '\0';
9681 if(RgUiRgrSiCfgCfm(&rgSchCb[instId].rgrSap[spId].sapCfg.sapPst,
9682 rgSchCb[instId].rgrSap[spId].sapCfg.suId,
9683 transId, status) != ROK)
9685 RLOG_ARG0(L_ERROR,DBG_INSTID,instId,"rgSCHUtlRgrSiCfgCfm: "
9686 "RgUiRgrSiCfgCfm Failed ");
9691 } /* rgSCHUtlRgrSiCfgCfm */
9695 * @brief API for sending Warning SI configuration confirm from
9701 * This API is invoked to send Warning SI configuration confirm
9702 * from Scheduler to RRM.
9703 * This API fills in Pst structure and SAP Ids and invokes
9704 * config confirm API towards RRM.
9706 * @param[in] RgrCfgTransId transId
9707 * @param[in] uint8_t status
9713 S16 rgSCHUtlRgrWarningSiCfgCfm
9718 RgrCfgTransId transId,
9722 S16 rgSCHUtlRgrWarningSiCfgCfm(instId, spId, siId, transId, status)
9726 RgrCfgTransId transId;
9730 uint8_t prntTrans[RGR_CFG_TRANSID_SIZE+1];
9733 memcpy(prntTrans, transId.trans, RGR_CFG_TRANSID_SIZE);
9734 prntTrans[RGR_CFG_TRANSID_SIZE] = '\0';
9737 if(RgUiRgrWarningSiCfgCfm(&rgSchCb[instId].rgrSap[spId].sapCfg.sapPst,
9738 rgSchCb[instId].rgrSap[spId].sapCfg.suId,
9739 transId, siId, status) != ROK)
9741 RLOG_ARG0(L_ERROR,DBG_INSTID,instId,"rgSCHUtlRgrSiCfgCfm: "
9742 "RgUiRgrSiCfgCfm Failed ");
9747 } /* rgSCHUtlRgrWarningSiCfgCfm */
9749 /***********************************************************
9751 * Func : rgSCHUtlPutSiInfo
9753 * Desc : Utility Function to deallocate SI information
9761 **********************************************************/
9763 Void rgSCHUtlPutSiInfo
9768 Void rgSCHUtlPutSiInfo(cell)
9773 uint32_t sizeOfSiInfo = 0;
9774 /*Free the buffers in crntSiInfo*/
9775 RGSCH_FREE_MSG(cell->siCb.crntSiInfo.mib)
9776 RGSCH_FREE_MSG(cell->siCb.crntSiInfo.sib1Info.sib1)
9778 sizeOfSiInfo = sizeof(cell->siCb.crntSiInfo.siInfo)/sizeof(cell->siCb.crntSiInfo.siInfo[0]);
9780 for(idx=0; idx < sizeOfSiInfo; idx++)
9782 RGSCH_FREE_MSG(cell->siCb.crntSiInfo.siInfo[idx].si)
9785 /*Free the buffers in newSiInfo */
9786 RGSCH_FREE_MSG(cell->siCb.newSiInfo.mib)
9787 RGSCH_FREE_MSG(cell->siCb.newSiInfo.sib1Info.sib1)
9789 sizeOfSiInfo = sizeof(cell->siCb.newSiInfo.siInfo)/sizeof(cell->siCb.newSiInfo.siInfo[0]);
9791 for(idx=0; idx < sizeOfSiInfo; idx++)
9793 RGSCH_FREE_MSG(cell->siCb.newSiInfo.siInfo[idx].si)
9798 #endif /*RGR_SI_SCH */
9802 /***********************************************************
9804 * Func : rgSCHUtlGetDrxSchdUesInDl
9806 * Desc : Utility Function to fill the get the list of
9807 * scheduled UEs. On these UE's, drx-inactivity
9808 * timer will be started/restarted.
9817 **********************************************************/
9819 S16 rgSCHUtlGetDrxSchdUesInDl
9821 RgSchCellCb *cellCb,
9823 RgSchDlHqProcCb *dlHq,
9824 RgInfUeAlloc *allocInfo,
9825 CmLListCp *dlDrxInactvTmrLst,
9826 CmLListCp *dlInActvLst,
9827 CmLListCp *ulInActvLst
9830 S16 rgSCHUtlGetDrxSchdUesInDl(cellCb, ueCb, dlHq, allocInfo, dlDrxInactvTmrLst, dlInActvLst, ulInActvLst)
9831 RgSchCellCb *cellCb;
9833 RgSchDlHqProcCb *dlHq;
9834 RgInfUeAlloc *allocInfo;
9835 CmLListCp *dlDrxInactvTmrLst;
9836 CmLListCp *dlInActvLst;
9837 CmLListCp *ulInActvLst;
9840 Bool isNewTx = FALSE;
9842 RgSchDrxDlHqProcCb *drxHq;
9843 RgSchDRXCellCb *drxCell = cellCb->drxCb;
9844 RgSchDrxUeCb *drxUe;
9846 Inst inst = cellCb->instIdx;
9848 uint8_t cellIdx = ueCb->cellIdToCellIdxMap[RG_SCH_CELLINDEX(dlHq->hqE->cell)];
9849 uint32_t dlInactvMask;
9850 uint32_t ulInactvMask;
9852 for(idx = 0; idx < allocInfo->nmbOfTBs; idx++)
9854 if(allocInfo->tbInfo[idx].isReTx == FALSE)
9857 /* Removing break here, since in 2 TB case if 2nd TB is proceeding with
9858 retx then drxretx timer should be stopped.*/
9862 /*Stop the DRX retransmission timer as UE scheduled for retx. Here
9863 * we stop the timer and inactivate the UE for both UL and DL.
9864 * This may result in loss of one slot for UL but this trade
9865 * off is taken to avoid the overhead of maintaining a list of UEs
9866 * to be inactivated in the next slot.*/
9867 drxHq = RG_SCH_DRX_GET_DL_HQ(dlHq);
9868 drxUe = RG_SCH_DRX_GET_UE(ueCb);
9869 if(drxHq->reTxIndx != DRX_INVALID)
9871 /* This condition should never occur */
9872 if(drxHq->reTxIndx >= RG_SCH_MAX_DRXQ_SIZE)
9874 RGSCHDBGERRNEW(inst,(rgSchPBuf(inst),"[%d]UE:DRXUE RETX IDX[%d]"
9875 "is out of bound,dlInactvMask %d,procId %d\n", ueCb->ueId,
9876 drxHq->reTxIndx,ueCb->dl.dlInactvMask, dlHq->procId));
9879 drxUe->drxDlInactvMaskPerCell[cellIdx] |= (RG_SCH_DRX_DLHQ_BITMASK << dlHq->procId);
9880 drxUe->drxUlInactvMaskPerCell[cellIdx] |= (RG_SCH_DRX_DLHQ_BITMASK << dlHq->procId);
9882 dlInactvMask = RG_SCH_DRX_DLHQ_BITMASK << dlHq->procId;
9883 ulInactvMask = RG_SCH_DRX_DLHQ_BITMASK << dlHq->procId;
9885 for(cellIdx = 0; cellIdx < CM_LTE_MAX_CELLS; cellIdx++)
9887 dlInactvMask &= drxUe->drxDlInactvMaskPerCell[cellIdx];
9888 ulInactvMask &= drxUe->drxUlInactvMaskPerCell[cellIdx];
9891 drxUe->drxDlInactvMask |= dlInactvMask;
9892 drxUe->drxUlInactvMask |= ulInactvMask;
9894 /* if no other condition is keeping ue active,
9897 if(!RG_SCH_DRX_DL_IS_UE_ACTIVE(drxUe))
9899 /* BUG 2 : HARQ_RTT, changed for consistency */
9900 ueCb->dl.dlInactvMask |= (RG_DRX_INACTIVE);
9902 /* Add to DL inactive list */
9903 cmLListAdd2Tail(dlInActvLst,&(ueCb->dlDrxInactvLnk));
9904 ueCb->dlDrxInactvLnk.node = (PTR)ueCb;
9907 if(!RG_SCH_DRX_UL_IS_UE_ACTIVE(drxUe))
9909 /*BUG 2: HARQ_RTT changed for consistency */
9910 ueCb->ul.ulInactvMask |= (RG_DRX_INACTIVE);
9912 cmLListAdd2Tail(ulInActvLst,&(ueCb->ulDrxInactvLnk));
9913 ueCb->ulDrxInactvLnk.node = (PTR)ueCb;
9916 /* Deleting entry from HARQ RTT queue for the same HARQ proc,
9917 * if exist. This is the special case which can happen iF UL
9918 * scheduling is done later. */
9919 if(drxHq->rttIndx != DRX_INVALID)
9921 cmLListDelFrm (&(cellCb->drxCb->drxQ[drxHq->rttIndx].harqRTTQ),
9922 &(drxHq->harqRTTEnt));
9924 drxHq->rttIndx = DRX_INVALID;
9927 cmLListDelFrm (&(drxCell->drxQ[drxHq->reTxIndx].harqRetxQ),
9928 &(drxHq->harqRetxEnt));
9929 drxHq->reTxIndx = DRX_INVALID;
9936 if(ueCb->drxCb->raRcvd == TRUE)
9938 ueCb->drxCb->raRcvd = FALSE;
9940 /* mark the ra bit */
9941 ueCb->drxCb->drxUlInactvMask |= RG_SCH_DRX_RA_BITMASK;
9942 ueCb->drxCb->drxDlInactvMask |= RG_SCH_DRX_RA_BITMASK;
9944 }/*if(ra->rcvd) == TRUE */
9946 if(ueCb->dlDrxInactvTmrLnk.node == NULLP)
9948 cmLListAdd2Tail(dlDrxInactvTmrLst,&(ueCb->dlDrxInactvTmrLnk));
9949 ueCb->dlDrxInactvTmrLnk.node = (PTR)ueCb;
9951 }/*if(isNewTx == TRUE) */
9954 }/* rgSCHUtlGetSchdUes*/
9956 /* ccpu00117452 - MOD - Changed macro name from
9957 RGR_RRM_DLPWR_CNTRL to RGR_CQI_REPT */
9960 * @brief This function fills StaInd struct
9964 * Function: rgSCHUtlFillSndStaInd
9965 * Purpose: Fills StaInd struct and sends the
9968 * @param[in] RgSchCellCb *cell pointer to Cell Control block
9969 * @param[in] RgSchUeCb *ue pointer to Ue Control block
9970 * @param[in] RgrStaIndInfo *staInfo Sta Ind struct to be filled
9971 * @param[in] uint8_t numCqiRept NUmber of reports to be filled
9976 S16 rgSCHUtlFillSndStaInd
9980 RgrStaIndInfo *staInfo,
9984 S16 rgSCHUtlFillSndStaInd(cell, ue, staInfo, numCqiRept)
9987 RgrStaIndInfo *staInfo;
9993 /* Fill StaInd for sending collated Latest N CQI rpeorts */
9994 /* Find index in the array from where Latest N
9995 reports needs to be fetched. Use this value to index in the array
9996 and copy the reports into staInfo */
9998 /* Fill the Cell Id of PCC of the UE */
9999 staInfo->cellId = ue->cell->cellId;
10000 staInfo->crnti = ue->ueId;
10002 idxStart = ue->schCqiInfo.cqiCount - numCqiRept;
10004 memcpy (&(staInfo->ueCqiInfo.cqiRept),
10005 &(ue->schCqiInfo.cqiRept[idxStart]),
10006 numCqiRept * sizeof(RgrUeCqiRept));
10008 staInfo->ueCqiInfo.numCqiRept = numCqiRept;
10010 ue->schCqiInfo.cqiCount = 0;
10012 /* Call utility function (rgSCHUtlRgrStaInd) to send rpts to RRM */
10013 if(rgSCHUtlRgrStaInd(cell, staInfo) != ROK)
10015 RLOG_ARG1(L_ERROR,DBG_CELLID,cell->cellId,"Could not send "
10016 "CQI reports for RNTI:%d",ue->ueId);
10022 }/* End of rgSCHUtlFillSndStaInd */
10027 * @brief API for sending STA indication from Scheduler to RRM.
10031 * Function: rgSCHUtlRgrStaInd
10033 * This API is invoked to send STA indication from Scheduler instance to RRM.
10034 * This API fills in Pst structure and RgrStaIndInfo
10035 * and calls the Sta primitive API towards RRM.
10037 * @param[in] cell RgSchCellCb
10038 * @param[in] RgrStsIndInfo *rgrSta
10044 S16 rgSCHUtlRgrStaInd
10047 RgrStaIndInfo *rgrSta
10050 S16 rgSCHUtlRgrStaInd(cell, rgrSta)
10052 RgrStaIndInfo *rgrSta;
10056 RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
10060 rgrSap = cell->rgrSap;
10061 if (rgrSap->sapSta.sapState != LRG_BND)
10063 RLOG_ARG1(L_ERROR,DBG_CELLID,cell->cellId,
10064 "rgSCHUtlRgrStaInd() Upper SAP not bound (%d) ",
10065 rgrSap->sapSta.sapState);
10068 RgUiRgrStaInd(&(cell->rgrSap->sapCfg.sapPst),
10069 cell->rgrSap->sapCfg.suId, rgrSta);
10071 } /* rgSCHUtlRgrStaInd*/
10072 #endif /* End of RGR_CQI_REPT */
10074 /* Fix : syed HO UE does not have a valid ue->rntiLnk */
10076 * @brief Indicates MAC to release any rnti context it has.
10079 * Function : rgSCHUtlIndRntiRls2Mac
10080 * This function indicates MAC for this rnti release.
10081 * In case of ueId change it will indicate MAC
10082 * about the new rnti to be updated.
10083 * It will post a release RNTI indication to MAC.
10087 * @param[in] RgSchCellCb *cell
10088 * @param[in] CmLteRnti rnti
10089 * @param[in] Bool ueIdChng
10090 * @param[in] CmLteRnti newRnti
10095 Void rgSCHUtlIndRntiRls2Mac
10103 Void rgSCHUtlIndRntiRls2Mac(cell, rnti, ueIdChng, newRnti)
10111 Inst inst = cell->instIdx;
10112 RgInfRlsRnti rntiInfo;
10115 /* Copy the info to rntiInfo */
10116 rntiInfo.cellId = cell->cellId;
10117 rntiInfo.rnti = rnti;
10118 /* Fix : syed ueId change as part of reestablishment.
10119 * Now SCH to trigger this. CRG ueRecfg for ueId change
10121 rntiInfo.ueIdChng = ueIdChng;
10122 rntiInfo.newRnti = newRnti;
10124 rntiInfo.isUeSCellDel = FALSE;
10126 /* Invoke MAC to release the rnti */
10127 rgSCHUtlGetPstToLyr(&pst, &rgSchCb[inst], cell->macInst);
10128 RgSchMacRlsRnti(&pst, &rntiInfo);
10132 /* LTE_ADV_FLAG_REMOVED_START */
10134 * @brief API for sending LOAD INF indication from Scheduler to RRM.
10137 * Function: rgSCHUtlRgrLoadInfInd
10139 * This API is invoked to send LOAD INF indication from Scheduler instance to RRM.
10140 * This API fills in Pst structure and RgrLoadInfIndInfo
10141 * and calls the Sta primitive API towards RRM.
10143 * @param[in] cell RgSchCellCb
10144 * @param[in] RgrLoadInfIndInfo *rgrLoadInf
10150 S16 rgSCHUtlRgrLoadInfInd
10153 RgrLoadInfIndInfo *rgrLoadInf
10156 S16 rgSCHUtlRgrLoadInfInd(cell, rgrLoadInf)
10158 RgrLoadInfIndInfo *rgrLoadInf;
10162 RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
10164 rgrSap = cell->rgrSap;
10165 if (rgrSap->sapSta.sapState != LRG_BND)
10167 RLOG_ARG1(L_ERROR,DBG_CELLID,cell->cellId,
10168 "rgSCHUtlRgrLoadInfInd() Upper SAP not bound (%d) ",
10169 rgrSap->sapSta.sapState);
10172 RgUiRgrLoadInfInd(&(cell->rgrSap->sapCfg.sapPst),
10173 cell->rgrSap->sapCfg.suId, rgrLoadInf);
10175 } /* rgSCHUtlRgrLoadInfInd*/
10176 /* LTE_ADV_FLAG_REMOVED_END */
10178 /* MS_FIX : syed SCH to act as MASTER in maintaining
10179 * rnti related context. Trigger to rnti del/Chng at SCH
10180 * will result in a Indication to MAC to release its
10181 * RNTI context. MAC inturn indicates the context cleared
10182 * indication to SCH, upon which SCH would set this
10184 * @brief API for sending STA indication from Scheduler to RRM.
10188 * Function: rgSCHUtlRlsRnti
10190 * This API is invoked to indicate MAC to release rnti
10192 * @param[in] RgSchCellCb *cellCb
10193 * @param[in] RgSchRntiLnk *rntiLnk,
10194 * @param[in] Bool ueIdChngd,
10195 * @param[in] CmLteRnti newRnti
10200 Void rgSCHUtlRlsRnti
10203 RgSchRntiLnk *rntiLnk,
10208 Void rgSCHUtlRlsRnti(cell, rntiLnk, ueIdChngd, newRnti)
10210 RgSchRntiLnk *rntiLnk;
10216 uint8_t isLegacy = 0;
10218 if(cell->emtcEnable)
10220 rgSCHEmtcUtlRlsRnti(cell, rntiLnk, &isLegacy);
10225 /*Add to Guard Pool*/
10226 cmLListAdd2Tail(&cell->rntiDb.rntiGuardPool, &rntiLnk->rntiGrdPoolLnk);
10227 rntiLnk->rntiGrdPoolLnk.node = (PTR)rntiLnk;
10229 /* Fix: syed Explicitly Inidcate MAC to release RNTI */
10230 rgSCHUtlIndRntiRls2Mac(cell, rntiLnk->rnti, ueIdChngd, newRnti);
10237 * @brief This function fills StaInd struct
10241 * Function: rgSCHUtlFillSndUeStaInd
10242 * Purpose: Fills StaInd struct and sends the
10245 * @param[in] RgSchCellCb *cell pointer to Cell Control block
10246 * @param[in] RgSchUeCb *ue pointer to Ue Control block
10247 * @param[in] uint8_t numCqiRept NUmber of reports to be filled
10252 S16 rgSCHUtlFillSndUeStaInd
10256 RgrUeStaIndInfo *ueStaInfo
10259 S16 rgSCHUtlFillSndUeStaInd(cell, ue, ueStaInfo)
10262 RgrUeStaIndInfo *ueStaInfo;
10266 ueStaInfo->cellId = cell->cellId;
10267 ueStaInfo->crnti = ue->ueId;
10269 /* Call utility function (rgSCHUtlRgrUeStaInd) to send rpts to RRM */
10270 if(rgSCHUtlRgrUeStaInd(cell, ueStaInfo) != ROK)
10272 RLOG_ARG1(L_ERROR,DBG_CELLID,cell->cellId,"Could not send "
10273 "UE Sta reports CRNTI:%d",ue->ueId);
10279 }/* End of rgSCHUtlFillSndStaInd */
10284 * @brief API for sending STA indication from Scheduler to RRM.
10288 * Function: rgSCHUtlRgrStaInd
10290 * This API is invoked to send STA indication from Scheduler instance to RRM.
10291 * This API fills in Pst structure and RgrStaIndInfo
10292 * and calls the Sta primitive API towards RRM.
10294 * @param[in] cell RgSchCellCb
10295 * @param[in] RgrStsIndInfo *rgrSta
10301 S16 rgSCHUtlRgrUeStaInd
10304 RgrUeStaIndInfo *rgrUeSta
10307 S16 rgSCHUtlRgrUeStaInd(cell, rgrUeSta)
10309 RgrUeStaIndInfo *rgrUeSta;
10313 RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
10315 rgrSap = cell->rgrSap;
10316 if (rgrSap->sapSta.sapState != LRG_BND)
10318 RLOG_ARG1(L_ERROR,DBG_CELLID,cell->cellId,
10319 "rgSCHUtlRgrUeStaInd() Upper SAP not bound (%d) ",
10320 rgrSap->sapSta.sapState);
10323 RgUiRgrUeStaInd(&(cell->rgrSap->sapCfg.sapPst),
10324 cell->rgrSap->sapCfg.suId, rgrUeSta);
10326 } /* rgSCHUtlRgrStaInd*/
10330 * @brief function to report DL and UL PRB usage to RRM.
10333 * Function: rgSCHUtlUpdAvgPrbUsage
10334 * This function sends the PRB usage report to
10335 * RRM with the interval configured by RRM.
10337 * @param[in] cell *RgSchCellCb
10343 S16 rgSCHUtlUpdAvgPrbUsage
10348 S16 rgSCHUtlUpdAvgPrbUsage(cell)
10352 CmLteTimingInfo frm;
10353 RgmPrbRprtInd *prbRprtInd;
10356 #ifdef DBG_MAC_RRM_PRB_PRINT
10357 static uint32_t count = 0;
10358 const uint32_t reprotForEvery20Sec = 20000/cell->prbUsage.rprtPeriod;
10363 frm = cell->crntTime;
10364 RGSCH_INCR_SUB_FRAME(frm, RG_SCH_CMN_DL_DELTA);
10370 if(cell->prbUsage.rprtPeriod >= RGSCH_NUM_SUB_FRAMES)
10372 /* Get the total number of DL and UL slots within the reporting period*/
10373 numDlSf = (cell->prbUsage.rprtPeriod *
10374 rgSchTddNumDlSubfrmTbl[cell->ulDlCfgIdx][RGSCH_NUM_SUB_FRAMES-1])
10375 / RGSCH_NUM_SUB_FRAMES;
10376 numUlSf = (cell->prbUsage.rprtPeriod *
10377 rgSchTddNumUlSubfrmTbl[cell->ulDlCfgIdx][RGSCH_NUM_SUB_FRAMES-1])
10378 / RGSCH_NUM_SUB_FRAMES;
10382 /* Get the total number of DL and UL slots < 10 ms interval */
10383 numDlSf = rgSchTddNumDlSubfrmTbl[cell->ulDlCfgIdx][frm.slot];
10384 numUlSf = rgSchTddNumUlSubfrmTbl[cell->ulDlCfgIdx][frm.slot];
10387 numDlSf = cell->prbUsage.rprtPeriod;
10388 numUlSf = cell->prbUsage.rprtPeriod;
10391 if(SGetSBuf(cell->rgmSap->sapCfg.sapPst.region,
10392 cell->rgmSap->sapCfg.sapPst.pool, (Data**)&prbRprtInd,
10393 sizeof(RgmPrbRprtInd)) != ROK)
10398 memset(&prbRprtInd->stQciPrbRpts[0],
10400 (RGM_MAX_QCI_REPORTS * sizeof(RgmPrbRptPerQci)));
10402 prbRprtInd->bCellId = cell->cellId;
10406 prbRprtInd->bPrbUsageMask |= RGM_PRB_USAGE_DL;
10407 for (idx = 0; idx < RGM_MAX_QCI_REPORTS; idx++ )
10409 prbRprtInd->stQciPrbRpts[idx].bAvgPrbDlUsage =
10410 RGSCH_DIV_ROUND((cell->prbUsage.qciPrbRpts[idx].dlTotPrbUsed*100),
10411 (numDlSf * cell->bwCfg.dlTotalBw));
10412 prbRprtInd->stQciPrbRpts[idx].bQci = cell->prbUsage.qciPrbRpts[idx].qci;
10413 cell->prbUsage.qciPrbRpts[idx].dlTotPrbUsed = 0;
10419 prbRprtInd->bPrbUsageMask |= RGM_PRB_USAGE_UL;
10420 for (idx = 0; idx < RGM_MAX_QCI_REPORTS; idx++ )
10422 prbRprtInd->stQciPrbRpts[idx].bAvgPrbUlUsage =
10423 RGSCH_DIV_ROUND((cell->prbUsage.qciPrbRpts[idx].ulTotPrbUsed*100),
10424 (numUlSf * cell->ulAvailBw));
10425 prbRprtInd->stQciPrbRpts[idx].bQci = cell->prbUsage.qciPrbRpts[idx].qci;
10426 cell->prbUsage.qciPrbRpts[idx].ulTotPrbUsed = 0;
10430 #ifdef DBG_MAC_RRM_PRB_PRINT
10431 if((count % reprotForEvery20Sec) == 0 )
10433 printf("\n====================================================================");
10434 printf("\nMAC: QCI-1[DL:UL] | QCI-2[DL:UL] | QCI-3[DL:UL] | QCI-4[DL:UL] \n");
10435 printf("======================================================================\n");
10436 printf(" [%d: %d]\t | [%d: %d]\t | [%d: %d]\t| [%d: %d]\t\n",
10437 prbRprtInd->stQciPrbRpts[0].bAvgPrbDlUsage,
10438 prbRprtInd->stQciPrbRpts[0].bAvgPrbUlUsage,
10439 prbRprtInd->stQciPrbRpts[1].bAvgPrbDlUsage,
10440 prbRprtInd->stQciPrbRpts[1].bAvgPrbUlUsage,
10441 prbRprtInd->stQciPrbRpts[2].bAvgPrbDlUsage,
10442 prbRprtInd->stQciPrbRpts[2].bAvgPrbUlUsage,
10443 prbRprtInd->stQciPrbRpts[3].bAvgPrbDlUsage,
10444 prbRprtInd->stQciPrbRpts[3].bAvgPrbUlUsage);
10447 RgUiRgmSendPrbRprtInd(&(cell->rgmSap->sapCfg.sapPst),
10448 cell->rgmSap->sapCfg.suId, prbRprtInd);
10456 * @brief This function resends the Ta in case of
10457 * max retx failure or DTX for the Ta transmitted
10461 * Function: rgSCHUtlReTxTa
10464 * @param[in] RgSchCellCb *cell
10465 * @param[in] RgSchUeCb *ue
10470 Void rgSCHUtlReTxTa
10472 RgSchCellCb *cellCb,
10476 Void rgSCHUtlReTxTa(cellCb, ueCb)
10477 RgSchCellCb *cellCb;
10482 /* If TA Timer is running. Stop it */
10483 if (ueCb->taTmr.tmrEvnt != TMR_NONE)
10485 rgSCHTmrStopTmr(cellCb, ueCb->taTmr.tmrEvnt, ueCb);
10487 /*[ccpu00121813]-ADD-If maxretx is reached then
10488 * use outstanding TA val for scheduling again */
10489 if(ueCb->dl.taCb.outStndngTa == TRUE)
10491 ueCb->dl.taCb.ta = ueCb->dl.taCb.outStndngTaval;
10492 ueCb->dl.taCb.outStndngTaval = RGSCH_NO_TA_RQD;
10493 ueCb->dl.taCb.outStndngTa = FALSE;
10496 /* Fix : syed TA state updation missing */
10497 ueCb->dl.taCb.state = RGSCH_TA_TOBE_SCHEDULED;
10498 rgSCHUtlDlTARpt(cellCb, ueCb);
10503 /* Added function for dropping Paging Message*/
10505 * @brief Handler for BO Updt received for BCCH or PCCH.
10509 * Function : rgSCHChkBoUpdate
10511 * This function shall check for BO received falls within the scheduling window or not
10514 * @param[in] RgSchCellCb *cell
10520 static S16 rgSCHChkBoUpdate
10523 RgInfCmnBoRpt *boUpdt
10526 static S16 rgSCHChkBoUpdate (cell, boUpdt)
10528 RgInfCmnBoRpt *boUpdt;
10532 uint32_t crntTimeInSubFrms = 0;
10533 uint32_t boUpdTimeInSubFrms = 0;
10534 uint32_t distance = 0;
10536 crntTimeInSubFrms = (cell->crntTime.sfn * RGSCH_NUM_SUB_FRAMES_5G) + cell->crntTime.slot +
10537 RG_SCH_CMN_DL_DELTA + 2; /* As bo received will scheduled in next TTI
10538 so incrementing with +1 more */
10539 boUpdTimeInSubFrms = (boUpdt->u.timeToTx.sfn * RGSCH_NUM_SUB_FRAMES_5G)+ boUpdt->u.timeToTx.slot;
10542 distance = boUpdTimeInSubFrms > crntTimeInSubFrms ? \
10543 boUpdTimeInSubFrms - crntTimeInSubFrms : \
10544 (RGSCH_MAX_SUBFRM_5G - crntTimeInSubFrms + boUpdTimeInSubFrms);
10546 if (distance > RGSCH_PCCHBCCH_WIN)
10552 }/*rgSCHChkBoUpdate*/
10557 * @brief Utility function to calculate the UL reTxIdx in TDD cfg0
10561 * Function : rgSchUtlCfg0ReTxIdx
10563 * Update the reTxIdx according to the rules mentioned
10564 * in 3GPP TS 36.213 section 8 for TDD Cfg0
10566 * @param[in] RgSchCellCb *cell
10567 * @param[in] CmLteTimingInfo phichTime
10568 * @param[in] uint8_t hqFdbkIdx
10572 uint8_t rgSchUtlCfg0ReTxIdx
10575 CmLteTimingInfo phichTime,
10579 uint8_t rgSchUtlCfg0ReTxIdx (cell, phichTime, hqFdbkIdx)
10581 CmLteTimingInfo phichTime;
10585 uint8_t reTxIdx = RGSCH_INVALID_INFO;
10586 uint8_t iPhich = 0;
10587 RgSchCmnUlCell *cellUl = RG_SCH_CMN_GET_UL_CELL(cell);
10589 uint8_t ulSF; /* UL SF in the TDD frame */
10591 ulSf = &cellUl->ulSfArr[hqFdbkIdx];
10592 ulSF = ulSf->ulSfIdx;
10594 /* Check for the UL SF 4 or 9 */
10595 if(ulSF == 9 || ulSF == 4)
10599 if(phichTime.slot == 0 || phichTime.slot == 5)
10603 /* Retx will happen according to the Pusch k table */
10604 reTxIdx = cellUl->schdIdx;
10608 /* Retx will happen at n+7 */
10609 RGSCHCMNADDTOCRNTTIME(phichTime, phichTime, 7);
10610 /* Fetch the corresponding UL slot Idx in UL sf array */
10611 reTxIdx = rgSCHCmnGetUlSfIdx(&phichTime, cell);
10614 else if(phichTime.slot == 1 || phichTime.slot == 6)
10616 /* Retx will happen at n+7 */
10617 RGSCHCMNADDTOCRNTTIME(phichTime, phichTime, 7);
10618 /* Fetch the corresponding UL slot Idx in UL sf array */
10619 reTxIdx = rgSCHCmnGetUlSfIdx(&phichTime, cell);
10626 * @brief Utility function to calculate total num of PRBs required to
10627 * satisfy DL BO for TM1/TM2/TM6/TM7
10631 * Function : rgSchUtlDlCalc1CwPrb
10633 * Calculate PRBs required for UE to satisfy BO in DL
10635 * Note : Total calculated PRBs will be assigned to *prbReqrd
10638 * @param[in] RgSchCellCb *cell
10639 * @param[in] RgSchUeCb *ue
10640 * @param[in] uint32_t bo
10641 * @param[out] uint32_t *prbReqrd
10645 Void rgSchUtlDlCalc1CwPrb
10653 Void rgSchUtlDlCalc1CwPrb(cell, ue, bo, prbReqrd)
10657 uint32_t *prbReqrd;
10660 RgSchCmnDlCell *dlCell = RG_SCH_CMN_GET_DL_CELL(cell);
10661 RgSchCmnDlUe *dlUe = RG_SCH_CMN_GET_DL_UE(ue, cell);
10665 uint8_t cfi = dlCell->currCfi;
10667 iTbs = dlUe->mimoInfo.cwInfo[0].iTbs[0];
10668 eff = (*(RgSchCmnTbSzEff *)(dlCell->cqiToEffTbl[0][cfi]))[iTbs];
10670 /* Optimization to convert totalBo (which is in-terms of bytes) to bits
10671 * i.e, << 3 and multiply with 1024 i.e, << 10 */
10672 noRes = ((uint64_t)((bo << 3) << 10)) / (eff);
10673 /* Get the number of RBs needed for this transmission */
10674 /* Number of RBs = No of REs / No of REs per RB */
10675 *prbReqrd = RGSCH_CEIL(noRes, dlCell->noResPerRb[cfi]);
10678 } /* rgSchUtlDlCalc1CwPrb*/
10681 * @brief Utility function to calculate total num of PRBs required to
10682 * satisfy DL BO(BO sum of all logical channels for that UE or an LC BO)
10687 * Function : rgSchUtlDlCalc2CwPrb
10689 * Calculate PRBs required for UE to satisfy BO in DL
10691 * Note : Total calculated PRBs will be assigned to *prbReqrd
10694 * @param[in] RgSchCellCb *cell
10695 * @param[in] RgSchUeCb *ue
10696 * @param[in] uint32_t bo
10697 * @param[out] uint32_t *prbReqrd
10701 Void rgSchUtlDlCalc2CwPrb
10709 Void rgSchUtlDlCalc2CwPrb(cell, ue, bo, prbReqrd)
10713 uint32_t *prbReqrd;
10716 RgSchCmnDlCell *dlCell = RG_SCH_CMN_GET_DL_CELL(cell);
10717 RgSchCmnDlUe *dlUe = RG_SCH_CMN_GET_DL_UE(ue, cell);
10718 uint32_t eff1, eff2;
10720 uint8_t noLyr1, noLyr2;
10721 uint8_t iTbs1, iTbs2;
10722 uint8_t cfi = dlCell->currCfi;
10724 if ((dlUe->mimoInfo.forceTD) ||/* Transmit Diversity (TD) */
10725 (dlUe->mimoInfo.ri < 2))/* 1 layer precoding */
10727 iTbs1 = dlUe->mimoInfo.cwInfo[0].iTbs[0];
10728 eff1 = (*(RgSchCmnTbSzEff *)(dlCell->cqiToEffTbl[0][cfi]))[iTbs1];
10730 /* Optimization to convert totalBo (which is in-terms of bytes) to bits
10731 * i.e, << 3 and multiply with 1024 i.e, << 10 */
10732 noRes = ((uint64_t)((bo << 3) << 10)) / (eff1);
10733 /* Get the number of RBs needed for this transmission */
10734 /* Number of RBs = No of REs / No of REs per RB */
10735 *prbReqrd = RGSCH_CEIL(noRes, dlCell->noResPerRb[cfi]);
10739 noLyr1 = dlUe->mimoInfo.cwInfo[0].noLyr;
10740 noLyr2 = dlUe->mimoInfo.cwInfo[1].noLyr;
10741 iTbs1 = dlUe->mimoInfo.cwInfo[0].iTbs[noLyr1 - 1];
10742 iTbs2 = dlUe->mimoInfo.cwInfo[1].iTbs[noLyr2 - 1];
10743 eff1 = (*(RgSchCmnTbSzEff *)(dlCell->cqiToEffTbl[noLyr1 - 1][cfi]))[iTbs1];
10744 eff2 = (*(RgSchCmnTbSzEff *)(dlCell->cqiToEffTbl[noLyr2 - 1][cfi]))[iTbs2];
10746 /* Optimization to convert totalBo (which is in-terms of bytes) to bits
10747 * i.e, << 3 and multiply with 1024 i.e, << 10 */
10748 noRes = ((uint64_t)((bo << 3) << 10)) / (eff1 + eff2);
10749 /* Get the number of RBs needed for this transmission */
10750 /* Number of RBs = No of REs / No of REs per RB */
10751 *prbReqrd = RGSCH_CEIL(noRes, dlCell->noResPerRb[cfi]);
10754 } /* rgSchUtlDlCalc2CwPrb */
10757 * @brief Utility function to calculate total num of PRBs required to
10758 * satisfy DL BO(BO sum of all logical channels for that UE or an LC BO)
10762 * Function : rgSchUtlCalcTotalPrbReq
10764 * This function calls TM specific routine to calculate PRB
10767 * @param[in] RgSchCellCb *cell
10768 * @param[in] RgSchUeCb *ue
10769 * @param[in] uint32_t bo
10770 * @param[out] uint32_t *prbReqrd
10774 Void rgSchUtlCalcTotalPrbReq
10782 Void rgSchUtlCalcTotalPrbReq(cell, ue, bo, prbReqrd)
10786 uint32_t *prbReqrd;
10789 /* Call TM specific Prb calculation routine */
10790 (dlCalcPrbFunc[ue->mimoInfo.txMode - 1])(cell, ue, bo, prbReqrd);
10793 } /* rgSchUtlCalcTotalPrbReq */
10796 /***********************************************************
10798 * Func : rgSCHUtlFetchPcqiBitSz
10801 * Desc : Fetch the CQI/PMI bits for a UE based on the mode, periodicity.
10810 **********************************************************/
10812 static uint8_t rgSCHUtlFetchPcqiBitSz
10819 static uint8_t rgSCHUtlFetchPcqiBitSz (cell, ueCb, numTxAnt)
10825 uint8_t confRepMode;
10828 RgSchUePCqiCb *cqiCb = RG_SCH_GET_UE_CELL_CQI_CB(ueCb,cell);
10830 confRepMode = cqiCb->cqiCfg.cqiSetup.prdModeEnum;
10831 if((ueCb->mimoInfo.txMode != RGR_UE_TM_3) &&
10832 (ueCb->mimoInfo.txMode != RGR_UE_TM_4))
10838 ri = cqiCb->perRiVal;
10840 switch(confRepMode)
10842 case RGR_PRD_CQI_MOD10:
10848 case RGR_PRD_CQI_MOD11:
10861 else if(numTxAnt == 4)
10874 /* This is number of antenna case 1.
10875 * This is not applicable for Mode 1-1.
10876 * So setting it to invalid value */
10882 case RGR_PRD_CQI_MOD20:
10890 pcqiSz = 4 + cqiCb->label;
10895 case RGR_PRD_CQI_MOD21:
10910 else if(numTxAnt == 4)
10923 /* This might be number of antenna case 1.
10924 * For mode 2-1 wideband case only antenna port 2 or 4 is supported.
10925 * So setting invalid value.*/
10933 pcqiSz = 4 + cqiCb->label;
10937 pcqiSz = 7 + cqiCb->label;
10953 * @brief Utility function to returns the number of subbands based on the
10958 * Function : rgSchUtlGetNumSbs
10960 * Calculate the number of PRBs
10961 * Update the subbandRequired based on the nPrbs and subband size
10963 * @param[in] RgSchCellCb *cell
10964 * @param[in] RgSchUeCb *ue
10965 * @param[in] uint32_t *numSbs
10969 uint8_t rgSchUtlGetNumSbs
10976 uint8_t rgSchUtlGetNumSbs (cell, ue, numSbs)
10983 //Currently hardcoding MAX prb for each UE
10984 nPrb = ue->ue5gtfCb.maxPrb;
10985 (*numSbs) = RGSCH_CEIL(nPrb, MAX_5GTF_VRBG_SIZE);
10990 * @brief Utility function to insert the UE node into UE Lst based on the
10991 * number of subbands allocated for the UE for the current TTI.
10995 * Function : rgSchUtlSortInsUeLst
10997 * If subbandRequired < Min, then insert at head
10998 * Else If subbandRequired > Max, then insert at tail
10999 * Else, traverse the list and place the node at the appropriate place
11001 * @param[in] RgSchCellCb *cell
11002 * @param[in] RgSchUeCb *ue
11006 uint8_t rgSchUtlSortInsUeLst
11011 uint8_t vrbgRequired
11014 uint8_t rgSchUtlSortInsUeLst (cell, ueLst, node, vrbgRequired)
11018 uint8_t vrbgRequired;
11022 CmLList *firstUeInLst;
11023 CmLList *lastUeInLst;
11025 RgSchCmnUlUe *ueUl;
11027 //firstUeInLst = cmLListFirst(ueLst);
11028 CM_LLIST_FIRST_NODE(ueLst,firstUeInLst);
11029 if(NULLP == firstUeInLst)
11031 /* first node to be added to the list */
11032 cmLListAdd2Tail(ueLst, node);
11036 /* Sb Required for the UE is less than the first node in the list */
11037 tempUe = (RgSchUeCb *)(firstUeInLst->node);
11038 ueUl = RG_SCH_CMN_GET_UL_UE(tempUe, cell);
11040 if(vrbgRequired <= ueUl->vrbgRequired)
11042 cmLListInsCrnt(ueLst, (node));
11046 /* Sb Required for this UE is higher than the UEs in the list */
11047 lastUeInLst = cmLListLast(ueLst);
11048 tempUe = (RgSchUeCb *)(lastUeInLst->node);
11049 if(vrbgRequired >= ueUl->vrbgRequired)
11051 cmLListAdd2Tail(ueLst, (node));
11055 /* This UE needs to be in the middle. Search and insert the UE */
11056 ueInLst = cmLListFirst(ueLst);
11059 tempUe = (RgSchUeCb *)(ueInLst->node);
11061 if(vrbgRequired <= ueUl->vrbgRequired)
11063 cmLListInsCrnt(ueLst, (node));
11067 ueInLst = cmLListNext(ueLst);
11069 } while(NULLP != ueInLst && ueInLst != firstUeInLst);
11078 * @brief Function to Send LCG GBR register to MAC
11082 * Function: rgSCHUtlBuildNSendLcgReg
11084 * Handler for sending LCG GBR registration
11089 * Processing Steps:
11091 * @param[in] RgSchCellCb *cell
11092 * @param[in] CmLteRnti crnti
11093 * @param[in] uint8_t lcgId
11094 * @param[in] Bool isGbr
11099 S16 rgSCHUtlBuildNSendLcgReg
11107 S16 rgSCHUtlBuildNSendLcgReg(cell, crnti, lcgId, isGbr)
11115 RgInfLcgRegReq lcgRegReq;
11117 memset(&pst, 0, sizeof(Pst));
11118 lcgRegReq.isGbr = isGbr;
11119 lcgRegReq.cellId = cell->cellId;
11120 lcgRegReq.crnti = crnti;
11121 lcgRegReq.lcgId = lcgId;
11122 rgSCHUtlGetPstToLyr(&pst, &rgSchCb[cell->instIdx], cell->macInst);
11123 /* code Coverage portion of the test case */
11124 RgSchMacLcgReg(&pst, &lcgRegReq);
11133 * @brief Function to map RGR pucch type to TFU type
11137 * Function: rgSchUtlGetFdbkMode
11143 * Processing Steps:
11145 * @param[in] RgrSchFrmt1b3TypEnum
11146 * @return TfuAckNackMode
11150 TfuAckNackMode rgSchUtlGetFdbkMode
11152 RgrSchFrmt1b3TypEnum fdbkType
11155 TfuAckNackMode rgSchUtlGetFdbkMode(fdbkType)
11156 RgrSchFrmt1b3TypEnum fdbkType;
11160 TfuAckNackMode mode = TFU_UCI_FORMAT_1A_1B;
11164 case RG_SCH_UCI_FORMAT_NON_CA:
11165 case RG_SCH_UCI_FORMAT1A_1B:
11167 mode = TFU_UCI_FORMAT_1A_1B;
11170 case RG_SCH_UCI_FORMAT1B_CS:
11172 mode = TFU_UCI_FORMAT_1B_CS;
11175 case RG_SCH_UCI_FORMAT3:
11177 mode = TFU_UCI_FORMAT_3;
11183 #endif /* TFU_TDD */
11184 #endif /* LTE_ADV */
11185 #endif /*TFU_UPGRADE */
11189 * @brief Send Ue SCell delete to SMAC.
11193 * Function : rgSCHUtlSndUeSCellDel2Mac
11194 * This function populates the struct RgInfRlsRnti and
11195 * get the pst for SMac and mark field isUeSCellDel to TRUE which
11196 * indicates that it is a Ue SCell delete.
11200 * @param[in] RgSchCellCb *cell
11201 * @param[in] CmLteRnti rnti
11206 Void rgSCHUtlSndUeSCellDel2Mac
11212 Void rgSCHUtlSndUeSCellDel2Mac(cell, rnti)
11218 Inst inst = cell->instIdx;
11219 RgInfRlsRnti rntiInfo;
11221 RGSCHDBGINFONEW(inst,(rgSchPBuf(inst),"RNTI Release IND for UE(%d)\n", rnti));
11222 /* Copy the info to rntiInfo */
11223 rntiInfo.cellId = cell->cellId;
11224 rntiInfo.rnti = rnti;
11225 /* Fix : syed ueId change as part of reestablishment.
11226 * Now SCH to trigger this. CRG ueRecfg for ueId change
11228 rntiInfo.ueIdChng = FALSE;
11229 rntiInfo.newRnti = rnti;
11230 rntiInfo.isUeSCellDel = TRUE;
11231 /* Invoke MAC to release the rnti */
11232 rgSCHUtlGetPstToLyr(&pst, &rgSchCb[inst], cell->macInst);
11233 RgSchMacRlsRnti(&pst, &rntiInfo);
11238 * @brief Returns max TB supported by a given txMode
11242 * Function : rgSCHUtlGetMaxTbSupp
11243 * Max TB supported for TM Modes (1,2,5,6 and 7) is 1
11247 * @param[in] RgrTxMode txMode
11248 * @return uint8_t maxTbCount;
11252 uint8_t rgSCHUtlGetMaxTbSupp
11257 uint8_t rgSCHUtlGetMaxTbSupp(txMode)
11261 uint8_t maxTbCount;
11285 return (maxTbCount);
11289 * @brief Send Ue SCell delete to SMAC.
11293 * Function : rgSCHTomUtlGetTrigSet
11294 * This function gets the triggerset based on cqiReq
11296 * @param[in] RgSchCellCb *cell
11297 * @param[in] RgSchUeCb ueCb
11298 * @param[in] uint8_t cqiReq,
11299 * @param[out] uint8_t *triggerSet
11305 Void rgSCHTomUtlGetTrigSet
11310 uint8_t *triggerSet
11313 static S16 rgSCHTomUtlGetTrigSet(cell, ueCb, cqiReq, triggerSet)
11317 uint8_t *triggerSet;
11320 RgSchUeCellInfo *pCellInfo = RG_SCH_CMN_GET_PCELL_INFO(ueCb);
11323 case RG_SCH_APCQI_SERVING_CC:
11325 /* APeriodic CQI request for Current Carrier.*/
11326 uint8_t sCellIdx = ueCb->cellIdToCellIdxMap[RG_SCH_CELLINDEX(cell)];
11327 *triggerSet = 1 << (7 - sCellIdx);
11330 case RG_SCH_APCQI_1ST_SERVING_CCS_SET:
11332 *triggerSet = pCellInfo->acqiCb.aCqiCfg.triggerSet1;
11335 case RG_SCH_APCQI_2ND_SERVING_CCS_SET:
11337 *triggerSet = pCellInfo->acqiCb.aCqiCfg.triggerSet2;
11350 * @brief This function updates the value of UE specific DCI sizes
11354 * Function: rgSCHUtlUpdUeDciSize
11355 * Purpose: This function calculates and updates DCI Sizes in bits.
11357 * Invoked by: Scheduler
11359 * @param[in] RgSchCellCb *cell
11360 * @param[in] RgSchUeCb *ueCb
11361 * @param[in] isCsi2Bit *isCsi2Bit: is 1 bit or 2 bit CSI
11366 Void rgSCHUtlUpdUeDciSize
11373 Void rgSCHUtlUpdUeDciSize(cell, ueCb, isCsi2Bit)
11379 uint8_t dci01aCmnSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_0];
11380 uint8_t dci01aDedSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_0];
11381 if ((ueCb->accessStratumRls >= RGR_REL_10) && (cell->bwCfg.dlTotalBw >= cell->bwCfg.ulTotalBw))
11383 dci01aCmnSize += 1; /* Resource Allocation Type DCI 0 */
11384 dci01aDedSize += 1; /* Resource Allocation Type DCI 0 */
11386 if (isCsi2Bit == TRUE)
11388 dci01aDedSize += 2; /* 2 bit CSI DCI 0 */
11392 dci01aDedSize += 1; /* 1 bit CSI DCI 0 */
11395 /* Common CSI is always 1 bit DCI 0 */
11396 dci01aCmnSize += 1; /* 1 bit CSI DCI 0 */
11398 /* Compare the sizes of DCI 0 with DCI 1A and consider the greater */
11399 if (dci01aCmnSize < cell->dciSize.baseSize[TFU_DCI_FORMAT_1A])
11401 dci01aCmnSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_1A];
11403 if (dci01aDedSize < cell->dciSize.baseSize[TFU_DCI_FORMAT_1A])
11405 dci01aDedSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_1A];
11408 /* Remove the Ambiguous Sizes as mentioned in table Table 5.3.3.1.2-1 Spec 36.212-a80 Sec 5.3.3.1.3 */
11409 dci01aCmnSize += rgSchDciAmbigSizeTbl[dci01aCmnSize];
11410 dci01aDedSize += rgSchDciAmbigSizeTbl[dci01aDedSize];
11412 ueCb->dciSize.cmnSize[TFU_DCI_FORMAT_0] = dci01aCmnSize;
11413 ueCb->dciSize.cmnSize[TFU_DCI_FORMAT_1A] = dci01aCmnSize;
11415 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_0] = dci01aDedSize;
11416 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1A] = dci01aDedSize;
11418 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] = cell->dciSize.baseSize[TFU_DCI_FORMAT_1];
11420 /* Spec 36.212-a80 Sec 5.3.3.1.2: If the UE is configured to decode PDCCH with CRC scrambled
11421 * by the C-RNTI and the number of information bits in format 1 is equal to that for format 0/1A
11422 * for scheduling the same serving cell and mapped onto the UE specific search space given by the
11423 * C-RNTI as defined in [3], one bit of value zero shall be appended to format 1. */
11424 if (ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] == ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1A])
11426 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] += 1;
11429 /* Spec 36.212-a80 Sec 5.3.3.1.2: If the number of information bits in format 1 belongs
11430 * to one of the sizes in Table 5.3.3.1.2-1, one or more zero bit(s) shall be appended
11431 * to format 1 until the payload size of format 1 does not belong to one of the sizes in
11432 * Table 5.3.3.1.2-1 and is not equal to that of format 0/1A mapped onto the same search space. */
11433 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] += rgSchDciAmbigSizeTbl[ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1]];
11434 } while (ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] == ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1A]);
11436 /* Just copying the value of 2/2A to avoid multiple checks at PDCCH allocations. This values never change.*/
11437 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_2] = cell->dciSize.size[TFU_DCI_FORMAT_2];
11438 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_2A] = cell->dciSize.size[TFU_DCI_FORMAT_2A];
11439 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_2] = cell->dciSize.size[TFU_DCI_FORMAT_2];
11440 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_2A] = cell->dciSize.size[TFU_DCI_FORMAT_2A];
11442 /* Spec 36.212-a80 Sec 5.3.3.1.3: except when format 1A assigns downlink resource
11443 * on a secondary cell without an uplink configuration associated with the secondary cell */
11444 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A] = cell->dciSize.baseSize[TFU_DCI_FORMAT_1A];
11445 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A] += rgSchDciAmbigSizeTbl[ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A]];
11446 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] = cell->dciSize.baseSize[TFU_DCI_FORMAT_1];
11448 /* Spec 36.212-a80 Sec 5.3.3.1.2: If the UE is configured to decode PDCCH with CRC scrambled
11449 * by the C-RNTI and the number of information bits in format 1 is equal to that for format 0/1A
11450 * for scheduling the same serving cell and mapped onto the UE specific search space given by the
11451 * C-RNTI as defined in [3], one bit of value zero shall be appended to format 1. */
11452 if (ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] == ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A])
11454 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] += 1;
11457 /* Spec 36.212-a80 Sec 5.3.3.1.2: If the number of information bits in format 1 belongs
11458 * to one of the sizes in Table 5.3.3.1.2-1, one or more zero bit(s) shall be appended
11459 * to format 1 until the payload size of format 1 does not belong to one of the sizes in
11460 * Table 5.3.3.1.2-1 and is not equal to that of format 0/1A mapped onto the same search space. */
11461 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] += rgSchDciAmbigSizeTbl[ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1]];
11462 } while (ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] == ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A]);
11464 rgSCHEmtcUtlUpdUeDciSize(cell, ueCb);
11469 * @brief This function initialises the DCI Size table
11473 * Function: rgSCHUtlCalcDciSizes
11474 * Purpose: This function calculates and initialises DCI Sizes in bits.
11476 * Invoked by: Scheduler
11478 * @param[in] RgSchCellCb *cell
11483 Void rgSCHUtlCalcDciSizes
11488 Void rgSCHUtlCalcDciSizes(cell)
11492 uint8_t dciSize = 0;
11493 uint8_t dci01aSize = 0;
11494 uint32_t bits = 0, idx = 0;
11496 switch(TFU_DCI_FORMAT_0) /* Switch case for the purpose of readability */
11498 case TFU_DCI_FORMAT_0:
11500 /* DCI 0: Spec 36.212 Section 5.3.3.1.1 */
11502 /*-- Calculate resource block assignment bits need to be set
11503 Which is ln(N(N+1)/2) 36.212 5.3.3.1 --*/
11504 bits = (cell->bwCfg.ulTotalBw * (cell->bwCfg.ulTotalBw + 1) / 2);
11505 while ((bits & 0x8000) == 0)
11512 dciSize = 1 /* DCI 0 bit indicator */ + \
11513 1 /* Frequency hoping enable bit field */ + \
11514 (uint8_t)bits /* For frequency Hopping */ + \
11521 2 /* UL Index Config 0 or DAI Config 1-6 */
11525 cell->dciSize.baseSize[TFU_DCI_FORMAT_0] = dciSize;
11527 /* If hoping flag is enabled */
11528 if (cell->bwCfg.ulTotalBw <= 49) /* Spec 36.213 Table 8.4-1, N UL_hop, if hopping is enabled */
11530 cell->dciSize.dci0HopSize = 1;
11534 cell->dciSize.dci0HopSize = 2;
11537 /* Update common non-CRNTI scrambled DCI 0/1A flag */
11538 dci01aSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_0] + 1; /* 1 bit CSI */
11540 case TFU_DCI_FORMAT_1A:
11542 /* DCI 1A: Spec 36.212 Section 5.3.3.1.3 */
11545 /* Calculate resource block assignment bits need to be set
11546 Which is ln(N(N+1)/2) */
11547 bits = (cell->bwCfg.dlTotalBw * (cell->bwCfg.dlTotalBw + 1) / 2);
11548 while ((bits & 0x8000) == 0)
11555 dciSize += 1 /* Format 1A */ + \
11556 1 /* Local or Distributed */ + \
11557 (uint8_t)bits /* Resource block Assignment */ + \
11560 4 /* HARQ Proc Id */ +
11562 3 /* HARQ Proc Id */ +
11572 cell->dciSize.baseSize[TFU_DCI_FORMAT_1A] = dciSize;
11574 /* If the UE is not configured to decode PDCCH with CRC scrambled by the C-RNTI,
11575 * and the number of information bits in format 1A is less than that of format 0,
11576 * zeros shall be appended to format 1A until the payload size equals that of format 0. */
11577 /* Compare the size with DCI 1A and DCI 0 and consider the greater one */
11578 if (dci01aSize < cell->dciSize.baseSize[TFU_DCI_FORMAT_1A])
11580 dci01aSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_1A];
11582 /* If the number of information bits in format 1A belongs to one of the sizes in
11583 * Table 5.3.3.1.2-1, one zero bit shall be appended to format 1A. */
11584 dci01aSize += rgSchDciAmbigSizeTbl[dci01aSize];
11585 cell->dciSize.size[TFU_DCI_FORMAT_1A] = cell->dciSize.size[TFU_DCI_FORMAT_0] = dci01aSize;
11587 case TFU_DCI_FORMAT_1:
11589 /* DCI 1: Spec 36.212 Section 5.3.3.1.2 */
11591 if (cell->bwCfg.dlTotalBw > 10)
11593 dciSize = 1; /* Resource Allocation header bit */
11596 /* Resouce allocation bits Type 0 and Type 1 */
11597 bits = (cell->bwCfg.dlTotalBw/cell->rbgSize);
11598 if ((cell->bwCfg.dlTotalBw % cell->rbgSize) != 0)
11603 dciSize += (uint8_t)bits /* Resource Allocation bits */ + \
11611 2 /* Redunancy Version */ + \
11620 cell->dciSize.baseSize[TFU_DCI_FORMAT_1] = dciSize;
11622 cell->dciSize.size[TFU_DCI_FORMAT_1] = dciSize;
11625 /* If the UE is not configured to decode PDCCH with CRC
11626 * scrambled by the C-RNTI and the number of information bits in format 1
11627 * is equal to that for format 0/1A, one bit of value zero shall be appended
11629 if (dci01aSize == cell->dciSize.size[TFU_DCI_FORMAT_1])
11631 cell->dciSize.size[TFU_DCI_FORMAT_1] += 1;
11634 /* If the number of information bits in format 1 belongs to one of the sizes in
11635 * Table 5.3.3.1.2-1, one or more zero bit(s) shall be appended to format 1 until
11636 * the payload size of format 1 does not belong to one of the sizes in Table 5.3.3.1.2-1
11637 * and is not equal to that of format 0/1A mapped onto the same search space. */
11638 cell->dciSize.size[TFU_DCI_FORMAT_1] += rgSchDciAmbigSizeTbl[cell->dciSize.size[TFU_DCI_FORMAT_1]];
11639 } while (cell->dciSize.size[TFU_DCI_FORMAT_1] == dci01aSize);
11641 case TFU_DCI_FORMAT_2:
11643 /* DCI 2: Spec 36.212 Section 5.3.3.1.5 */
11645 if (cell->bwCfg.dlTotalBw > 10)
11647 dciSize = 1; /* Resource Allocation bit */
11650 dciSize += (uint8_t)bits /* Resource Allocation bits */ + \
11658 1 /* CW Swap Flag */ + \
11659 5 /* MCS for TB1 */+ \
11660 1 /* NDI for TB1 */+ \
11661 2 /* RV for TB1 */ + \
11662 5 /* MCS for TB2 */+ \
11663 1 /* NDI for TB2 */+ \
11664 2 /* RV for TB2 */;
11665 if (cell->numTxAntPorts == 2)
11669 else if (cell->numTxAntPorts == 4)
11673 cell->dciSize.size[TFU_DCI_FORMAT_2] = dciSize;
11674 cell->dciSize.size[TFU_DCI_FORMAT_2] += rgSchDciAmbigSizeTbl[cell->dciSize.size[TFU_DCI_FORMAT_2]];
11676 case TFU_DCI_FORMAT_2A:
11678 /* DCI 2A: Spec 36.212 Section 5.3.3.1.5A */
11680 if (cell->bwCfg.dlTotalBw > 10)
11682 dciSize = 1; /* Resource Allocation bit */
11685 dciSize += (uint8_t)bits /* Resource Allocation bits */ + \
11693 1 /* CW Swap Flag */ + \
11694 5 /* MCS for TB1 */+ \
11695 1 /* NDI for TB1 */+ \
11696 2 /* RV for TB1 */ + \
11697 5 /* MCS for TB2 */+ \
11698 1 /* NDI for TB2 */+ \
11699 2 /* RV for TB2 */;
11700 if (cell->numTxAntPorts == 4)
11704 cell->dciSize.size[TFU_DCI_FORMAT_2A] = dciSize;
11705 cell->dciSize.size[TFU_DCI_FORMAT_2A] += \
11706 rgSchDciAmbigSizeTbl[cell->dciSize.size[TFU_DCI_FORMAT_2A]]; /* Spec 39.212 Table 5.3.3.1.2-1 */
11708 case TFU_DCI_FORMAT_3:
11710 /* DCI 3: Spec 36.212 Section 5.3.3.1.6 */
11711 cell->dciSize.size[TFU_DCI_FORMAT_3] = cell->dciSize.size[TFU_DCI_FORMAT_1A] / 2;
11712 if (cell->dciSize.size[TFU_DCI_FORMAT_3] % 2)
11714 cell->dciSize.size[TFU_DCI_FORMAT_3]++;
11717 case TFU_DCI_FORMAT_3A:
11719 /* DCI 3A: Spec 36.212 Section 5.3.3.1.7 */
11720 cell->dciSize.size[TFU_DCI_FORMAT_3A] = cell->dciSize.size[TFU_DCI_FORMAT_1A];
11723 case TFU_DCI_FORMAT_6_0A:
11725 rgSCHEmtcGetDciFrmt60ASize(cell);
11727 case TFU_DCI_FORMAT_6_1A:
11729 rgSCHEmtcGetDciFrmt61ASize(cell);
11734 /* DCI format not supported */
11741 * @brief Handler for the CPU OvrLd related state adjustment.
11745 * Function : rgSCHUtlCpuOvrLdAdjItbsCap
11747 * Processing Steps:
11748 * - Record dl/ulTpts
11749 * - Adjust maxItbs to acheive target throughputs
11751 * @param[in] RgSchCellCb *cell
11755 Void rgSCHUtlCpuOvrLdAdjItbsCap
11760 Void rgSCHUtlCpuOvrLdAdjItbsCap(cell)
11766 if ((cell->cpuOvrLdCntrl.cpuOvrLdIns) & (RGR_CPU_OVRLD_DL_TPT_UP |
11767 RGR_CPU_OVRLD_DL_TPT_DOWN))
11769 /* Regulate DL Tpt for CPU overload */
11770 if (cell->measurements.dlTpt > cell->cpuOvrLdCntrl.tgtDlTpt)
11772 tptDelta = cell->measurements.dlTpt - cell->cpuOvrLdCntrl.tgtDlTpt;
11773 /* Upto 0.5% drift in measured vs target tpt is ignored */
11774 if (((tptDelta*1000)/cell->cpuOvrLdCntrl.tgtDlTpt) > 5)
11776 cell->thresholds.maxDlItbs = RGSCH_MAX((cell->thresholds.maxDlItbs-1), 1);
11781 tptDelta = cell->cpuOvrLdCntrl.tgtDlTpt - cell->measurements.dlTpt;
11782 /* Upto 0.5% drift in measured vs target tpt is ignored */
11783 if (((tptDelta*1000)/cell->cpuOvrLdCntrl.tgtDlTpt) > 5)
11785 cell->thresholds.maxDlItbs = RGSCH_MIN((cell->thresholds.maxDlItbs+1), RG_SCH_DL_MAX_ITBS);
11788 #ifdef CPU_OL_DBG_PRINTS
11789 printf("\n DL CPU OL ADJ = %lu, %lu, %d\n", cell->measurements.dlTpt, cell->cpuOvrLdCntrl.tgtDlTpt,
11790 cell->thresholds.maxDlItbs);
11794 if ((cell->cpuOvrLdCntrl.cpuOvrLdIns) & (RGR_CPU_OVRLD_UL_TPT_UP |
11795 RGR_CPU_OVRLD_UL_TPT_DOWN))
11797 /* Regualte DL Tpt for CPU overload */
11798 if (cell->measurements.ulTpt > cell->cpuOvrLdCntrl.tgtUlTpt)
11800 tptDelta = cell->measurements.ulTpt - cell->cpuOvrLdCntrl.tgtUlTpt;
11801 /* Upto 1% drift in measured vs target tpt is ignored */
11802 if (((tptDelta*1000)/cell->cpuOvrLdCntrl.tgtUlTpt) > 10)
11804 cell->thresholds.maxUlItbs = RGSCH_MAX((cell->thresholds.maxUlItbs-1), 1);
11809 tptDelta = cell->cpuOvrLdCntrl.tgtUlTpt - cell->measurements.ulTpt;
11810 /* Upto 1% drift in measured vs target tpt is ignored */
11811 if (((tptDelta*1000)/cell->cpuOvrLdCntrl.tgtUlTpt) > 10)
11813 cell->thresholds.maxUlItbs = RGSCH_MIN((cell->thresholds.maxUlItbs+1), RG_SCH_UL_MAX_ITBS);
11816 #ifdef CPU_OL_DBG_PRINTS
11817 printf("\n UL CPU OL ADJ = %lu, %lu, %d\n", cell->measurements.ulTpt, cell->cpuOvrLdCntrl.tgtUlTpt,
11818 cell->thresholds.maxUlItbs);
11825 * @brief Handler for the num UE per TTI based CPU OvrLd instr updating
11829 * Function : rgSCHUtlChkAndUpdNumUePerTtiCpuOvInstr
11831 * Processing Steps:
11832 * - Validate the config params.
11833 * - Update numUEperTTi CPU OL related information.
11834 * - If successful, return ROK else RFAILED.
11836 * @param[in] RgSchCellCb *cell
11837 * @param[in] uint8_t cnrtCpuOvrLdIns
11841 static Void rgSCHUtlChkAndUpdNumUePerTtiCpuOvInstr
11844 uint8_t crntCpuOvrLdIns
11847 static S16 rgSCHUtlChkAndUpdNumUePerTtiCpuOvInstr(cell, crntCpuOvrLdIns)
11849 uint8_t crntCpuOvrLdIns;
11852 RgSchCpuOvrLdCntrlCb *cpuInstr = &(cell->cpuOvrLdCntrl);
11853 RgSchCmnCell *cellSch;
11854 uint8_t maxUeNewDlTxPerTti;
11855 uint8_t maxUeNewUlTxPerTti;
11856 uint8_t tmpslot = 0;
11857 #ifdef CPU_OL_DBG_PRINTS
11860 uint8_t maxDlDecCnt;
11861 uint8_t maxUlDecCnt;
11863 cellSch = RG_SCH_CMN_GET_CELL(cell);
11865 maxUeNewDlTxPerTti = cellSch->dl.maxUeNewTxPerTti;
11866 maxUeNewUlTxPerTti = cellSch->ul.maxUeNewTxPerTti;
11868 /* Calculate Maximum Decremen */
11869 maxDlDecCnt = (10*(maxUeNewDlTxPerTti - 1))-(10-RGR_MAX_PERC_NUM_UE_PER_TTI_RED);
11870 maxUlDecCnt = (10*(maxUeNewUlTxPerTti - 1))-(10-RGR_MAX_PERC_NUM_UE_PER_TTI_RED);
11872 /* Check for DL CPU Commands */
11873 if ( crntCpuOvrLdIns & RGR_CPU_OVRLD_DL_DEC_NUM_UE_PER_TTI )
11875 /* Decrement till 90% of maxUeNewDlTxPerTti */
11876 if ( cpuInstr->dlNxtIndxDecNumUeTti < maxDlDecCnt )
11878 tmpslot = (cpuInstr->dlNxtIndxDecNumUeTti) % 10;
11879 cpuInstr->dlNxtIndxDecNumUeTti++;
11880 if ( cpuInstr->maxUeNewTxPerTti[tmpslot] > 1 )
11882 cpuInstr->maxUeNewTxPerTti[tmpslot]--;
11886 #ifdef CPU_OL_DBG_PRINTS
11887 printf("CPU_OL_TTI__ERROR\n");
11889 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,"Invalid CPU OL");
11892 #ifdef CPU_OL_DBG_PRINTS
11893 printf("dlNxtIndxDecNumUeTti = %d\n", cpuInstr->dlNxtIndxDecNumUeTti);
11895 RLOG_ARG1(L_DEBUG,DBG_CELLID,cell->cellId,"dlNxtIndxDecNumUeTti = %d",
11896 cpuInstr->dlNxtIndxDecNumUeTti);
11898 else if ( crntCpuOvrLdIns & RGR_CPU_OVRLD_DL_INC_NUM_UE_PER_TTI )
11900 if ( cpuInstr->dlNxtIndxDecNumUeTti > 0)
11902 cpuInstr->dlNxtIndxDecNumUeTti--;
11903 tmpslot = (cpuInstr->dlNxtIndxDecNumUeTti) % 10;
11904 if ( cpuInstr->maxUeNewTxPerTti[tmpslot] < maxUeNewDlTxPerTti )
11906 cpuInstr->maxUeNewTxPerTti[tmpslot]++;
11910 #ifdef CPU_OL_DBG_PRINTS
11911 printf("CPU_OL_TTI__ERROR\n");
11913 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,"Invalid CPU OL");
11916 #ifdef CPU_OL_DBG_PRINTS
11917 printf("dlNxtIndxDecNumUeTti = %d\n", cpuInstr->dlNxtIndxDecNumUeTti);
11919 RLOG_ARG1(L_DEBUG,DBG_CELLID,cell->cellId,"dlNxtIndxDecNumUeTti = %d",
11920 cpuInstr->dlNxtIndxDecNumUeTti);
11922 /* Check for UL CPU commands */
11923 if ( crntCpuOvrLdIns & RGR_CPU_OVRLD_UL_DEC_NUM_UE_PER_TTI )
11925 /* Decrement till 90% of maxUeNewDlTxPerTti */
11926 if ( cpuInstr->ulNxtIndxDecNumUeTti < maxUlDecCnt )
11928 tmpslot = (cpuInstr->ulNxtIndxDecNumUeTti) % 10;
11929 cpuInstr->ulNxtIndxDecNumUeTti++;
11930 if ( cpuInstr->maxUeNewRxPerTti[tmpslot] > 1 )
11932 cpuInstr->maxUeNewRxPerTti[tmpslot]--;
11936 #ifdef CPU_OL_DBG_PRINTS
11937 printf("CPU_OL_TTI__ERROR\n");
11939 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,"Invalid CPU OL");
11942 #ifdef CPU_OL_DBG_PRINTS
11943 printf("ulNxtIndxDecNumUeTti = %d\n", cpuInstr->ulNxtIndxDecNumUeTti);
11945 RLOG_ARG1(L_DEBUG,DBG_CELLID,cell->cellId,"dlNxtIndxDecNumUeTti = %d",
11946 cpuInstr->dlNxtIndxDecNumUeTti);
11948 else if ( crntCpuOvrLdIns & RGR_CPU_OVRLD_UL_INC_NUM_UE_PER_TTI )
11950 if ( cpuInstr->ulNxtIndxDecNumUeTti > 0)
11952 cpuInstr->ulNxtIndxDecNumUeTti--;
11953 tmpslot = (cpuInstr->ulNxtIndxDecNumUeTti) % 10;
11954 if ( cpuInstr->maxUeNewRxPerTti[tmpslot] < maxUeNewUlTxPerTti )
11956 cpuInstr->maxUeNewRxPerTti[tmpslot]++;
11960 #ifdef CPU_OL_DBG_PRINTS
11961 printf("CPU_OL_TTI__ERROR\n");
11963 RLOG_ARG0(L_ERROR,DBG_CELLID,cell->cellId,"Invalid CPU OL");
11966 #ifdef CPU_OL_DBG_PRINTS
11967 printf("ulNxtIndxDecNumUeTti = %d\n", cpuInstr->ulNxtIndxDecNumUeTti);
11969 RLOG_ARG1(L_DEBUG,DBG_CELLID,cell->cellId,"dlNxtIndxDecNumUeTti = %d",
11970 cpuInstr->dlNxtIndxDecNumUeTti);
11972 #ifdef CPU_OL_DBG_PRINTS
11973 /* TODO: Debug Information - Shall be moved under CPU_OL_DBG_PRINTS */
11974 printf("maxUeNewDlTxPerTti = %d, maxUeNewUlTxPerTti = %d\n", maxUeNewDlTxPerTti, maxUeNewUlTxPerTti);
11975 printf("DL Sf numUePerTti:");
11976 for ( idx = 0; idx < 10 ; idx ++ )
11978 printf(" %d", cpuInstr->maxUeNewTxPerTti[idx]);
11980 printf("\nUL Sf numUePerTti:");
11981 for ( idx = 0; idx < 10 ; idx ++ )
11983 printf(" %d", cpuInstr->maxUeNewRxPerTti[idx]);
11989 } /* rgSCHUtlChkAndUpdNumUePerTtiCpuOvInstr */
11992 * @brief Handler for the CPU OvrLd related cell Recfg.
11996 * Function : rgSCHUtlResetCpuOvrLdState
11998 * Processing Steps:
11999 * - Validate the config params.
12000 * - Update CPU OL related state information.
12001 * - If successful, return ROK else RFAILED.
12003 * @param[in] RgSchCellCb *cell
12004 * @param[in] uint8_t cnrtCpuOvrLdIns
12010 S16 rgSCHUtlResetCpuOvrLdState
12013 uint8_t crntCpuOvrLdIns
12016 S16 rgSCHUtlResetCpuOvrLdState(cell, crntCpuOvrLdIns)
12018 uint8_t crntCpuOvrLdIns;
12021 uint8_t crntDlCpuOL=0;
12022 uint8_t crntUlCpuOL=0;
12023 RgSchCmnCell *schCmnCell = (RgSchCmnCell *)(cell->sc.sch);
12026 #ifdef CPU_OL_DBG_PRINTS
12027 printf("\n CPU OVR LD Ins Rcvd = %d\n", (int)crntCpuOvrLdIns);
12029 RLOG_ARG0(L_INFO,DBG_CELLID,cell->cellId,"CPU OVR LD Ins Rcvd");
12031 if ( RGR_CPU_OVRLD_RESET == crntCpuOvrLdIns )
12033 /* The CPU OL instruction received with RESET (0), hence reset it */
12034 #ifdef CPU_OL_DBG_PRINTS
12035 printf("rgSCHUtlResetCpuOvrLdState: RESET CPU OL instr\n");
12037 RLOG_ARG0(L_INFO,DBG_CELLID,cell->cellId,"RESET CPU OVR LD");
12038 cell->cpuOvrLdCntrl.cpuOvrLdIns = 0;
12039 /* Reset the max UL and DL itbs to 26 */
12040 cell->thresholds.maxUlItbs = RG_SCH_UL_MAX_ITBS;
12041 cell->thresholds.maxDlItbs = RG_SCH_DL_MAX_ITBS;
12042 /* Reset the num UE per TTI intructions */
12043 cell->cpuOvrLdCntrl.dlNxtIndxDecNumUeTti = 0;
12044 cell->cpuOvrLdCntrl.ulNxtIndxDecNumUeTti = 0;
12045 for ( idx = 0; idx < 10; idx++ )
12047 cell->cpuOvrLdCntrl.maxUeNewTxPerTti[idx] =
12048 schCmnCell->dl.maxUeNewTxPerTti;
12049 cell->cpuOvrLdCntrl.maxUeNewRxPerTti[idx] =
12050 schCmnCell->ul.maxUeNewTxPerTti;
12055 /* Check and Update numUEPer TTI based CPU overload instruction before
12056 * going for TP based CPU OL
12057 * TTI based intrcuctions shall be > 0xF */
12058 if ( crntCpuOvrLdIns > 0xF )
12060 rgSCHUtlChkAndUpdNumUePerTtiCpuOvInstr(cell, crntCpuOvrLdIns);
12061 /* If need to have both TP and numUePerTti instrcution together in
12062 * one command then dont return from here */
12066 crntDlCpuOL = (crntCpuOvrLdIns & RGR_CPU_OVRLD_DL_TPT_UP) +\
12067 (crntCpuOvrLdIns & RGR_CPU_OVRLD_DL_TPT_DOWN);
12068 if ((crntDlCpuOL) && (crntDlCpuOL != RGR_CPU_OVRLD_DL_TPT_UP) &&
12069 (crntDlCpuOL != RGR_CPU_OVRLD_DL_TPT_DOWN))
12071 /* Cfg validation failed. Invalid Command. Either UP/DOWN is allowed */
12074 crntUlCpuOL = (crntCpuOvrLdIns & RGR_CPU_OVRLD_UL_TPT_UP) +\
12075 (crntCpuOvrLdIns & RGR_CPU_OVRLD_UL_TPT_DOWN);
12076 if ((crntUlCpuOL) && (crntUlCpuOL != RGR_CPU_OVRLD_UL_TPT_UP) &&
12077 (crntUlCpuOL != RGR_CPU_OVRLD_UL_TPT_DOWN))
12079 /* Cfg validation failed. Invalid Command. Either UP/DOWN is allowed */
12082 if ((crntDlCpuOL == 0) && (crntUlCpuOL == 0))
12084 /* Cfg validation failed. Invalid Command. Either UP/DOWN is allowed */
12088 cell->cpuOvrLdCntrl.cpuOvrLdIns = crntCpuOvrLdIns;
12092 if (crntUlCpuOL == RGR_CPU_OVRLD_UL_TPT_DOWN)
12094 cell->cpuOvrLdCntrl.tgtUlTpt = cell->measurements.ulTpt - \
12095 (cell->measurements.ulTpt * 3 )/100;
12099 cell->cpuOvrLdCntrl.tgtUlTpt = cell->measurements.ulTpt + \
12100 (cell->measurements.ulTpt * 2 )/100;
12102 RLOG_ARG3(L_DEBUG,DBG_CELLID,cell->cellId,"CPU OVR LD UL Reset to "
12103 "%d, %lu, %lu", (int)crntUlCpuOL, cell->cpuOvrLdCntrl.tgtUlTpt,cell->measurements.ulTpt);
12104 #ifdef CPU_OL_DBG_PRINTS
12105 printf("\n CPU OVR LD UL Reset to= %d, %lu, %lu\n", (int)crntUlCpuOL, cell->cpuOvrLdCntrl.tgtUlTpt,
12106 cell->measurements.ulTpt);
12112 if (crntDlCpuOL == RGR_CPU_OVRLD_DL_TPT_DOWN)
12114 cell->cpuOvrLdCntrl.tgtDlTpt = cell->measurements.dlTpt - \
12115 (cell->measurements.dlTpt * 1 )/100;
12119 cell->cpuOvrLdCntrl.tgtDlTpt = cell->measurements.dlTpt + \
12120 (cell->measurements.dlTpt * 1 )/100;
12122 RLOG_ARG3(L_DEBUG,DBG_CELLID,cell->cellId,"CPU OVR LD DL Reset to "
12123 "%d, %lu, %lu", (int)crntDlCpuOL, cell->cpuOvrLdCntrl.tgtDlTpt,cell->measurements.dlTpt);
12125 #ifdef CPU_OL_DBG_PRINTS
12126 printf("\n CPU OVR LD DL Reset to= %d, %lu, %lu\n", (int)crntDlCpuOL, cell->cpuOvrLdCntrl.tgtDlTpt,
12127 cell->measurements.dlTpt);
12130 rgSCHUtlCpuOvrLdAdjItbsCap(cell);
12134 S16 rgSCHUtlAddToResLst
12137 RgSchIotRes *iotRes
12140 cmLListAdd2Tail(cp, &iotRes->resLnk);
12141 iotRes->resLnk.node = (PTR)iotRes;
12144 S16 rgSCHUtlDelFrmResLst
12147 RgSchIotRes *iotRes
12150 CmLListCp *cp = NULLP;
12151 RgSchEmtcUeInfo *emtcUe = NULLP;
12152 emtcUe = RG_GET_EMTC_UE_CB(ue);
12153 if(iotRes->resType == RG_SCH_EMTC_PUCCH_RES)
12155 cp = &emtcUe->ulResLst;
12156 }else if(iotRes->resType == RG_SCH_EMTC_PDSCH_RES)
12158 cp = &emtcUe->dlResLst;
12161 RLOG0(L_INFO, "*****restype mismatch");
12167 RLOG0(L_INFO,"****error count*****\n");
12171 cmLListDelFrm(cp, &iotRes->resLnk);
12172 iotRes->resLnk.node = NULLP;
12176 /**********************************************************************
12179 **********************************************************************/