1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for Entry point fucntions
29 **********************************************************************/
31 /** @file rg_sch_utl.c
32 @brief This file implements the schedulers main access to MAC layer code.
36 /* header include files -- defines (.h) */
37 #include "common_def.h"
41 #include "sch_utils.h"
43 #include "rg_sch_err.h"
44 #include "rg_sch_inf.h"
46 #include "rg_sch_cmn.h"
49 /* header/extern include files (.x) */
50 #include "tfu.x" /* TFU types */
51 #include "lrg.x" /* layer management typedefs for MAC */
52 #include "rgr.x" /* layer management typedefs for MAC */
54 #include "rg_sch_inf.x" /* typedefs for Scheduler */
55 #include "rg_sch.x" /* typedefs for Scheduler */
56 #include "rg_sch_cmn.x" /* typedefs for Scheduler */
58 #include "rg_sch_emtc_ext.x"
63 uint32_t rgNumPrachRecvd =0; /* Num of Rach Req received including dedicated preambles */
64 uint32_t rgNumRarSched =0; /* Num of RARs sent */
65 uint32_t rgNumBI =0; /* Num of BackOff Ind sent */
66 uint32_t rgNumMsg3CrcPassed =0; /* Num of CRC success for Msg3 */
67 uint32_t rgNumMsg3CrcFailed =0; /* Num of CRC fail for Msg 3 */
68 uint32_t rgNumMsg3FailMaxRetx =0; /* Num of Msg3 fail after Max Retx attempts */
69 uint32_t rgNumMsg4Ack =0; /* Num of Acks for Msg4 Tx */
70 uint32_t rgNumMsg4Nack =0;
71 /* Num of Nacks for Msg4 Tx */
72 uint32_t rgNumMsg4FailMaxRetx =0; /* Num of Msg4 Tx failed after Max Retx attempts */
73 uint32_t rgNumSrRecvd =0; /* Num of Sched Req received */
74 uint32_t rgNumSrGrant =0; /* Num of Sched Req Grants sent */
75 uint32_t rgNumMsg3CrntiCE =0; /* Num of Msg 3 CRNTI CE received */
76 uint32_t rgNumDedPream =0; /* Num of Dedicated Preambles recvd */
77 uint32_t rgNumMsg3CCCHSdu =0; /* Num of Msg 3 CCCH Sdus recvd */
78 uint32_t rgNumCCCHSduCrntiNotFound =0; /*UE Ctx not found for CCCH SDU Msg 3 */
79 uint32_t rgNumCrntiCeCrntiNotFound =0; /*UE Ctx not found for CRNTI CE Msg 3 */
80 uint32_t rgNumMsg4WithCCCHSdu =0; /* Num of Msg4 with CCCH Sdu */
81 uint32_t rgNumMsg4WoCCCHSdu =0; /* Num of Msg4 without CCCH Sdu */
82 uint32_t rgNumMsg4Dtx =0; /* Num of DTX received for Msg 4 */
83 uint32_t rgNumMsg3AckSent =0; /* Num of PHICH Ack sent for Msg 3 */
84 uint32_t rgNumMsg3NackSent =0; /* Num of PHICH Nack sent for Msg 3 */
85 uint32_t rgNumMsg4PdcchWithCrnti =0; /* Num of PDCCH for CRNTI based contention resolution */
86 uint32_t rgNumRarFailDuetoRntiExhaustion =0; /* Num of RACH Failures due to RNTI pool exhaution */
87 uint32_t rgNumTAModified =0; /* Num of times TA received is different from prev value */
88 uint32_t rgNumTASent =0; /* Num of TA Command sent */
89 uint32_t rgNumMsg4ToBeTx =0; /* Num of times MSG4 that should be sent */
90 uint32_t rgNumMsg4Txed =0; /* Num of MSG4 actually sent *//* ysNumMsg4ToBeTx -ysNumMsg4Txed == Failed MSG4 TX */
91 uint32_t rgNumMsg3DtxRcvd =0; /* CRC Fail with SINR < 0 */
93 uint32_t rgNumDedPreamUECtxtFound =0; /* Num of Dedicated Preambles recvd */
95 static uint8_t rgSchDciAmbigSizeTbl[61] = {0,0,0,0,0,0,0,0,0,0,0,
96 0,1,0,1,0,1,0,0,0,1,
97 0,0,0,1,0,1,0,0,0,0,
98 0,1,0,0,0,0,0,0,0,1,
99 0,0,0,1,0,0,0,0,0,0,
100 0,0,0,0,0,1,0,0,0,0};
104 uint32_t rgSchCmnBetaCqiOffstTbl[16];
105 uint32_t rgSchCmnBetaRiOffstTbl[16];
106 RgSchdApis rgSchCmnApis;
107 S16 RgUiRgmSendPrbRprtInd ARGS((
110 RgmPrbRprtInd *prbRprtInd
113 S16 RgUiRgmSendTmModeChangeInd ARGS((
116 RgmTransModeInd *txModeChngInd
119 S16 rgSCHEmtcUtlGetSfAlloc ARGS((
122 S16 rgSCHEmtcUtlPutSfAlloc ARGS((
125 Void rgSCHEmtcUtlUpdUeDciSize ARGS((
129 Void rgSCHEmtcGetDciFrmt61ASize ARGS((
132 Void rgSCHEmtcGetDciFrmt60ASize ARGS((
135 S16 rgSCHEmtcUtlFillPdschDciInfo ARGS((
136 TfuPdschDciInfo *pdsch,
139 Void rgSCHEmtcUtlRlsRnti ARGS((
141 RgSchRntiLnk *rntiLnk,
144 S16 rgSCHEmtcPdcchAlloc ARGS((
148 Void rgSCHEmtcPdcchFree ARGS((
153 /* Functions specific to TM1/TM2/TM6/TM7 for PRB calculation*/
154 Void rgSchUtlDlCalc1CwPrb ARGS(( RgSchCellCb *cell,
157 uint32_t *prbReqrd));
159 /* Functions specific to TM3/TM4 for PRB calculation*/
160 Void rgSchUtlDlCalc2CwPrb ARGS(( RgSchCellCb *cell,
163 uint32_t *prbReqrd));
166 RgSchCellCb* rgSchUtlGetCellCb ARGS(( Inst inst,
171 typedef Void (*RgSchUtlDlCalcPrbFunc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
172 uint32_t bo, uint32_t *prbRequrd));
174 /* Functions specific to each transmission mode for PRB calculation*/
175 RgSchUtlDlCalcPrbFunc dlCalcPrbFunc[7] = {rgSchUtlDlCalc1CwPrb,
176 rgSchUtlDlCalc1CwPrb, rgSchUtlDlCalc2CwPrb, rgSchUtlDlCalc2CwPrb,
177 NULLP, rgSchUtlDlCalc1CwPrb, rgSchUtlDlCalc1CwPrb};
180 /* Functions specific to each transmission mode for PRB calculation*/
181 RgSchUtlDlCalcPrbFunc dlCalcPrbFunc[9] = {rgSchUtlDlCalc1CwPrb,
182 rgSchUtlDlCalc1CwPrb, rgSchUtlDlCalc2CwPrb, rgSchUtlDlCalc2CwPrb,
183 NULLP, rgSchUtlDlCalc1CwPrb, rgSchUtlDlCalc1CwPrb, NULLP, NULLP};
188 /* The below table will be used to map the UL SF number in a TDD Cfg 0
189 frame to the ul Sf array maintained in cellCb */
190 static uint8_t rgSchTddCfg0UlSfTbl[] = {2, 3, 4, 7, 8, 9};
193 static S16 rgSCHUtlUlAllocDbInit ARGS((
198 static Void rgSCHUtlUlAllocDbDeinit ARGS((
202 static S16 rgSCHUtlUlHoleDbInit ARGS((
209 static Void rgSCHUtlUlHoleDbDeinit ARGS((
214 static S16 rgSCHChkBoUpdate ARGS((
216 RgInfCmnBoRpt *boUpdt
220 static uint8_t rgSCHUtlFetchPcqiBitSz ARGS((
227 /* sorted in ascending order of tbSz */
228 const struct rgSchUtlBcchPcchTbSz
230 uint8_t rbIndex; /* RB index {2,3} */
231 uint16_t tbSz; /* one of the Transport block size in bits of
233 /* Corrected allocation for common channels */
234 uint8_t mcs; /* imcs */
235 } rgSchUtlBcchPcchTbSzTbl[44] = {
236 { 2, 32, 0 }, { 2, 56, 1 }, { 2, 72, 2 }, { 3, 88, 1 },
237 { 2, 104, 3 }, { 2, 120, 4 }, { 2, 144, 5 }, { 2, 176, 6 },
238 { 3, 208, 4 }, { 2, 224, 7 }, { 2, 256, 8 }, { 2, 296, 9 },
239 { 2, 328, 10 }, { 2, 376, 11 }, { 3, 392, 8 }, { 2, 440, 12 },
240 { 3, 456, 9 }, { 2, 488, 13 }, { 3, 504, 10 }, { 2, 552, 14 },
241 { 3, 584, 11 }, { 2, 600, 15 }, { 2, 632, 16 }, { 3, 680, 12 },
242 { 2, 696, 17 }, { 3, 744, 13 }, { 2, 776, 18 }, { 2, 840, 19 },
243 { 2, 904, 20 }, { 3, 968, 16 }, { 2, 1000, 21 }, { 2, 1064, 22 },
244 { 2, 1128, 23 }, { 3, 1160, 18 }, { 2, 1192, 24 }, { 2, 1256, 25 },
245 { 3, 1288, 19 }, { 3, 1384, 20 }, { 2, 1480, 26 }, { 3, 1608, 22 },
246 { 3, 1736, 23 }, { 3, 1800, 24 }, { 3, 1864, 25 }, { 3, 2216, 26 }
253 /* forward references */
255 static Void rgSCHUtlUpdPrachOcc ARGS((
257 RgrTddPrachInfo *cellCfg));
260 #define RGSCH_NUM_PCFICH_REG 4
261 #define RGSCH_NUM_REG_PER_CCE 9
262 #define RGSCH_NUM_REG_PER_PHICH_GRP 3
265 #define RGSCH_INITPHICH(_phich, _hqFeedBack, _nDmrs, _rbStart, _iPhich) {\
266 (_phich)->hqFeedBack = _hqFeedBack; \
267 (_phich)->rbStart = _rbStart; \
268 (_phich)->nDmrs = _nDmrs; \
269 (_phich)->iPhich = _iPhich; \
270 (_phich)->lnk.next = NULLP; \
271 (_phich)->lnk.prev = NULLP; \
272 (_phich)->lnk.node = (PTR)(_phich); \
275 #define RGSCH_INITPHICH(_phich, _hqFeedBack, _nDmrs, _rbStart, _isForMsg3) {\
276 (_phich)->hqFeedBack = _hqFeedBack; \
277 (_phich)->rbStart = _rbStart; \
278 (_phich)->nDmrs = _nDmrs; \
279 (_phich)->isForMsg3 = _isForMsg3; \
280 (_phich)->lnk.next = NULLP; \
281 (_phich)->lnk.prev = NULLP; \
282 (_phich)->lnk.node = (PTR)(_phich); \
286 #define RGSCH_PHICH_ALLOC(_inst,_dataPtr, _size, _ret) {\
287 _ret = rgSCHUtlAllocSBuf(_inst, (Data **)&_dataPtr, _size); \
290 /* ccpu00117052 - MOD - Passing double pointer
291 for proper NULLP assignment*/
292 #define RGSCH_PHICH_FREE(_inst, _dataPtr, _size) {\
293 rgSCHUtlFreeSBuf(_inst, (Data **)(&(_dataPtr)), _size); \
297 #define RGSCH_GETBIT(a, b) ((((uint8_t*)a)[(b)>>3] >> ((7-((b)&7)))) & 1)
303 * Desc: This function finds of the Power of x raised to n
305 * Ret: value of x raised to n
312 F64 rgSCHUtlPower(F64 x,F64 n)
320 return ( x * rgSCHUtlPower( x, n-1 ) );
324 return ( (1/x) * rgSCHUtlPower( x, n+1 ) );
326 } /* end of rgSCHUtlPower*/
332 * Desc: This function parses bits x to y of an array and
333 * returns the integer value out of it.
335 * Ret: integer value of z bits
342 uint32_t rgSCHUtlParse(uint8_t *buff,uint8_t startPos,uint8_t endPos,uint8_t buffSize)
344 uint8_t pointToChar,pointToEnd, loop;
345 uint8_t size = endPos - startPos;
347 pointToEnd = (startPos)%8;
348 for ( loop=0; loop<size; loop++)
350 pointToChar = (((startPos)+loop)/8);
351 if (RGSCH_GETBIT(buff+pointToChar,pointToEnd%8)==1)
353 result=result+(rgSCHUtlPower(2,(size-loop-1)));
357 return ((uint32_t)result);
358 } /* end of rgSCHUtlParse*/
362 * Fun: rgSCHUtlFindDist
364 * Desc: This function calculates the iterations need to cover
365 * before the valid Index can be used for next possible Reception
367 * Ret: integer value of z bits
374 uint8_t rgSCHUtlFindDist(uint16_t crntTime,uint16_t tempIdx)
377 /* ccpu00137113- Distance is not estimated properly if the periodicity is
378 * equal to RG_SCH_PCQI_SRS_SR_TRINS_SIZE.
380 while(crntTime<=tempIdx)
382 crntTime += RG_SCH_PCQI_SRS_SR_TRINS_SIZE;
386 } /* end of rgSCHUtlFindDist*/
391 * @brief This function checks availability of a PDCCH
395 * Function: rgSCHUtlPdcchAvail
396 * Purpose: This function checks if a particular PDCCH is in use.
397 * map field of PDCCH is used to track the CCEs arleady
398 * allocated. Each bit of map represents one CCE and the
399 * LSBit of first byte represents CCE 0.
401 * 1. Locate the set of bits that represent the PDCCH for
402 * the provided location.
403 * 2. If the value of the bits is non-zero one or many CCEs
404 * for the PDCCH are in use and hence the PDCCH is not available.
405 * 3. If pdcch is available, assign it to [out]pdcch.
406 * 4. Set all of the bits to one. There is no check performed
407 * to see if the PDCCH is available.
409 * Invoked by: scheduler
411 * @param[in] RgSchCellCb* cell
412 * @param[in] RgSchPdcchInfo* pdcchInfo
413 * @param[in] uint8_t loc
414 * @param[in] uint8_t aggrLvl
415 * @param[out] RgSchPdcch** pdcch
417 * -# TRUE if available
421 Bool rgSCHUtlPdcchAvail
424 RgSchPdcchInfo *pdcchInfo,
425 CmLteAggrLvl aggrLvl,
433 Inst inst = cell->instIdx;
435 uint16_t offsetStepMask;
439 byte = &pdcchInfo->map[0];
440 initMask = (0xffff >> (16 - aggrLvl));
442 /* if N(symbol, xPDCCH) =2, then xPDCCH will be candidates in
443 * search space of index {0,1,2,3} and {8,9,..14}
445 if ((cell->cell5gtfCb.cfi == 2) && (aggrLvl == CM_LTE_AGGR_LVL2))
447 offsetStepMask = 0xc;
451 offsetStepMask = 0xc0;
454 /* Loop till the number of bytes available in the CCE map */
455 while (offset < ((pdcchInfo->nCce+ 7) >> 3))
457 byte = &pdcchInfo->map[offset];
458 /* Checking for available CCE */
459 if ((*byte & currMask) == 0)
463 /* if the number of CCEs required are not available, move to next offset */
464 if (currMask & offsetStepMask)
471 /* Move to the next available CCE index in the current byte(cce map) */
472 currMask = currMask << aggrLvl;
476 if ((offset >= ((pdcchInfo->nCce + 7) >> 3)) ||
477 ((aggrLvl == CM_LTE_AGGR_LVL16) && (offset > 0)))
482 byte = &pdcchInfo->map[offset];
484 if (cell->pdcchLst.first != NULLP)
486 *pdcch = (RgSchPdcch *)(cell->pdcchLst.first->node);
487 cmLListDelFrm(&cell->pdcchLst, cell->pdcchLst.first);
491 ret = rgSCHUtlAllocSBuf(inst, (Data **)pdcch, sizeof(RgSchPdcch));
501 /* ALL CCEs will be used in case of level 16 */
502 if (aggrLvl == CM_LTE_AGGR_LVL16)
504 *(byte+1) |= currMask;
506 (*pdcch)->aggrLvl = aggrLvl;
507 cmLListAdd2Tail(&pdcchInfo->pdcchs, &((*pdcch)->lnk));
508 (*pdcch)->lnk.node = (PTR)*pdcch;
509 (*pdcch)->nCce = aggrLvl;
510 (*pdcch)->ue = NULLP;
518 * @brief This function releases a PDCCH
522 * Function: rgSCHUtlPdcchPut
523 * Purpose: This function releases a PDCCH.
525 * 1. Locate the set of bits that represent the PDCCH for
526 * the provided location.
527 * 2. Set all of the bits to zero.
528 * 3. Release the memory of PDCCH to the cell free Q
530 * Invoked by: scheduler
532 * @param[in] RgSchPdcchInfo* pdcchInfo
533 * @param[in] uint8_t loc
534 * @param[in] uint8_t aggrLvl
538 Void rgSCHUtlPdcchPut(RgSchCellCb *cell,RgSchPdcchInfo *pdcchInfo,RgSchPdcch *pdcch)
544 switch(pdcch->aggrLvl)
546 case CM_LTE_AGGR_LVL2:
547 offset = (pdcch->nCce >> 1) & 3;
548 mask = 0x3 << (offset * 2); /*ccpu00128826 - Offset Correction */
550 case CM_LTE_AGGR_LVL4:
551 offset = (pdcch->nCce >> 2) & 1;
552 mask = 0xf << (offset * 4);/*ccpu00128826 - Offset Correction */
554 case CM_LTE_AGGR_LVL8:
557 case CM_LTE_AGGR_LVL16:
563 /* Placing common computation of byte from all the cases above here
565 byte = &pdcchInfo->map[pdcch->nCce >> 3];
567 cmLListDelFrm(&pdcchInfo->pdcchs, &pdcch->lnk);
568 cmLListAdd2Tail(&cell->pdcchLst, &pdcch->lnk);
569 pdcch->lnk.node = (PTR)pdcch;
578 * @brief This function initializes PDCCH information for frame
582 * Function: rgSCHUtlPdcchInit
583 * Purpose: This function initializes PDCCH information for
584 * a slot. It removes the list of PDCCHs allocated
585 * in the prior use of this slot structure.
587 * Invoked by: rgSCHUtlSubFrmPut
589 * @param[in] RgSchCellCb* cell
590 * @param[in] RgSubFrm* subFrm
594 Void rgSCHUtlPdcchInit(RgSchCellCb *cell,RgSchDlSf *subFrm,uint16_t nCce)
596 RgSchPdcchInfo *pdcchInfo;
598 Inst inst = cell->instIdx;
602 pdcchInfo = &subFrm->pdcchInfo;
603 while(pdcchInfo->pdcchs.first != NULLP)
605 pdcch = (RgSchPdcch *)pdcchInfo->pdcchs.first->node;
606 cmLListDelFrm(&pdcchInfo->pdcchs, pdcchInfo->pdcchs.first);
607 cmLListAdd2Tail(&cell->pdcchLst, &pdcch->lnk);
610 cmLListInit(&pdcchInfo->pdcchs);
613 subFrm->relPdcch = NULLP;
616 cceMapSz = ((pdcchInfo->nCce + 7) >> 3);
618 /* The bitMap array size is the number of ceiling(CCEs/8) */
619 /* If nCce received is not the same as the one stored in
620 * pdcchInfo, free the pdcchInfo map */
622 if(pdcchInfo->nCce != nCce)
626 rgSCHUtlFreeSBuf(inst, (Data **)(&(pdcchInfo->map)), cceMapSz);
628 pdcchInfo->nCce = nCce;
629 cceMapSz = ((pdcchInfo->nCce + 7) >> 3);
630 rgSCHUtlAllocSBuf(inst, (Data **)&pdcchInfo->map,
632 if (pdcchInfo->map == NULLP)
634 /* Generate log error here */
639 memset(subFrm->pdcchInfo.map, 0, cceMapSz);
640 /* If nCce is not exactly same as the bitMap size(no of bits allocated
641 * to represent the Cce's, then mark the extra bits as unavailable
642 extra bits = (((pdcchInfo->nCce + 7) >> 3)*8) - pdcchInfo->nCce
643 The last byte of bit map = subFrm->pdcchInfo.map[((pdcchInfo->nCce + 7) >> 3) - 1]
644 NOTE : extra bits are most significant of the last byte eg. */
645 extraBits = (cceMapSz)*8 - pdcchInfo->nCce;
646 subFrm->pdcchInfo.map[cceMapSz - 1] |=
647 ((1 << extraBits) - 1) << (8 - extraBits);
651 /* LTE_ADV_FLAG_REMOVED_START */
653 * @brief This function frees Pool
656 * Function: rgSchSFRTotalPoolFree
658 * Invoked by: rgSchSFRTotalPoolInit
660 * @param[in] RgSchCellCb* cell
661 * @param[in] RgSubFrm* subFrm
665 Void rgSchSFRTotalPoolFree(RgSchSFRTotalPoolInfo *sfrTotalPoolInfo,RgSchCellCb *cell)
670 /*Deinitialise if these cc pools and ce pools are already existent*/
671 l = &sfrTotalPoolInfo->ccPool;
675 /*REMOVING Cell Centred POOLS IF ANY*/
676 n = cmLListDelFrm(l, n);
678 /* Deallocate buffer */
679 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(n->node)), sizeof(RgSchSFRPoolInfo));
681 /* Deallocate buffer */
682 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(n)), sizeof(CmLList));
686 /*REMOVING Cell Edged POOLS IF ANY*/
687 l = &sfrTotalPoolInfo->cePool;
691 n = cmLListDelFrm(l, n);
693 /* Deallocate buffer */
694 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(n->node)), sizeof(RgSchSFRPoolInfo));
696 /* Deallocate buffer */
697 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(n)), sizeof(CmLList));
704 * @brief This function resets temporary variables in Pool
707 * Function: rgSchSFRResetPoolVariables
709 * Invoked by: rgSCHSFRUtlTotalPoolInit
711 * @param[in] RgSchCellCb* cell
712 * @param[in] RgSubFrm* subFrm
716 S16 rgSchSFRTotalPoolInit(RgSchCellCb *cell,RgSchDlSf *sf)
718 /* Initialise the variables */
719 RgSchSFRPoolInfo *sfrCCPool;
720 RgSchSFRPoolInfo *sfrCEPool;
723 CmLList *temp = NULLP;
726 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo, cell);
727 sf->sfrTotalPoolInfo.CCPool1BwAvlbl = 0;
728 sf->sfrTotalPoolInfo.CCPool2BwAvlbl = 0;
729 sf->sfrTotalPoolInfo.CEPoolBwAvlbl = 0;
730 sf->sfrTotalPoolInfo.CC1 = FALSE;
731 sf->sfrTotalPoolInfo.CC2 = FALSE;
732 /*Initialise the CE Pools*/
733 cmLListInit (&(sf->sfrTotalPoolInfo.cePool));
735 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp, sizeof(CmLList));
738 DU_LOG("\nERROR --> SCH : CE Pool memory allocation FAILED for cell");
739 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo, cell);
743 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp->node, sizeof(RgSchSFRPoolInfo));
746 DU_LOG("\nERROR --> SCH : CE Pool memory allocation FAILED for cell ");
747 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
751 l = &sf->sfrTotalPoolInfo.cePool;
752 cmLListAdd2Tail(l, temp);
754 /*Initialise Bandwidth and startRB and endRB for each pool*/
757 /* Initialise the CE Pools */
758 sfrCEPool = (RgSchSFRPoolInfo*)n->node;
760 sfrCEPool->poolstartRB = cell->lteAdvCb.sfrCfg.cellEdgeRbRange.startRb;
761 sfrCEPool->poolendRB = cell->lteAdvCb.sfrCfg.cellEdgeRbRange.endRb;
762 sfrCEPool->bw = sfrCEPool->poolendRB - sfrCEPool->poolstartRB + 1;
763 sf->sfrTotalPoolInfo.CEPoolBwAvlbl = sfrCEPool->bw;
765 sfrCEPool->bwAlloced = 0;
766 sfrCEPool->type2Start = sfrCEPool->poolstartRB;
767 sfrCEPool->type2End = RGSCH_CEIL(sfrCEPool->poolstartRB, cell->rbgSize);
768 sfrCEPool->type0End = ((sfrCEPool->poolendRB + 1) / cell->rbgSize) - 1;
769 sfrCEPool->pwrHiCCRange.startRb = 0;
770 sfrCEPool->pwrHiCCRange.endRb = 0;
772 /*Initialise CC Pool*/
773 cmLListInit (&(sf->sfrTotalPoolInfo.ccPool));
775 /*Add memory and Update CCPool*/
776 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp, sizeof(CmLList));
779 DU_LOG("\nERROR --> SCH : CC Pool memory allocation FAILED for cell ");
780 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
784 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp->node, sizeof(RgSchSFRPoolInfo));
787 DU_LOG("\nERROR --> SCH : CC Pool memory allocation FAILED for cell ");
788 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
792 l = &sf->sfrTotalPoolInfo.ccPool;
793 cmLListAdd2Tail(l, temp);
795 /*Initialise Bandwidth and startRB and endRB for each pool*/
796 if(sfrCEPool->poolstartRB)
799 sfrCCPool = (RgSchSFRPoolInfo*)n->node;
801 sfrCCPool->poolstartRB = 0;
802 sfrCCPool->poolendRB = sfrCEPool->poolstartRB - 1;
803 sfrCCPool->bw = sfrCCPool->poolendRB - sfrCCPool->poolstartRB + 1;
804 sf->sfrTotalPoolInfo.CCPool1BwAvlbl = sfrCCPool->bw;
805 sfrCCPool->bwAlloced = 0;
806 sfrCCPool->type2Start = 0;
807 sfrCCPool->type2End = 0;
808 sfrCCPool->type0End = ((sfrCCPool->poolendRB + 1) / cell->rbgSize) - 1;
809 sf->sfrTotalPoolInfo.CC1 = TRUE;
810 sfrCCPool->pwrHiCCRange.startRb = 0;
811 sfrCCPool->pwrHiCCRange.endRb = 0;
816 sfrCCPool = (RgSchSFRPoolInfo*)n->node;
818 sfrCCPool->poolstartRB = sfrCEPool->poolendRB + 1;
819 sfrCCPool->poolendRB = sf->bw - 1;
820 sfrCCPool->bw = sfrCCPool->poolendRB - sfrCCPool->poolstartRB + 1;
821 sf->sfrTotalPoolInfo.CCPool2BwAvlbl = sfrCCPool->bw;
822 sfrCCPool->CCPool2Exists = TRUE;
823 sfrCCPool->bwAlloced = 0;
824 sfrCCPool->type2Start = sfrCCPool->poolstartRB;
825 sfrCCPool->type2End = RGSCH_CEIL(sfrCCPool->poolstartRB, cell->rbgSize);
826 sfrCCPool->type0End = ((sfrCCPool->poolendRB + 1) / cell->rbgSize) - 1;
827 sf->sfrTotalPoolInfo.CC2 = TRUE;
828 sfrCEPool->adjCCPool = sfrCCPool; /* SFR_FIX */
829 sfrCCPool->pwrHiCCRange.startRb = 0;
830 sfrCCPool->pwrHiCCRange.endRb = 0;
833 if((sfrCEPool->poolendRB != sf->bw - 1) && (!sfrCCPool->poolstartRB))
835 /*Add memory and Update CCPool*/
836 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp, sizeof(CmLList));
839 DU_LOG("\nERROR --> SCH : CC Pool memory allocation FAILED for cell ");
840 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
844 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp->node, sizeof(RgSchSFRPoolInfo));
847 DU_LOG("\nERROR --> SCH : CC Pool memory allocation FAILED for cell ");
848 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
852 cmLListAdd2Tail(l, temp);
855 sfrCCPool = (RgSchSFRPoolInfo*)n->node;
857 sfrCCPool->poolstartRB = sfrCEPool->poolendRB + 1;
858 sfrCCPool->poolendRB = sf->bw - 1;
859 sfrCCPool->bw = sfrCCPool->poolendRB - sfrCCPool->poolstartRB + 1;
860 sf->sfrTotalPoolInfo.CCPool2BwAvlbl = sfrCCPool->bw;
861 sfrCCPool->CCPool2Exists = TRUE;
862 sfrCCPool->bwAlloced = 0;
863 sfrCCPool->type2Start = sfrCCPool->poolstartRB;
864 sfrCCPool->type2End = RGSCH_CEIL(sfrCCPool->poolstartRB, cell->rbgSize);
865 sfrCCPool->type0End = ((sfrCCPool->poolendRB + 1) / cell->rbgSize) - 1;
866 sf->sfrTotalPoolInfo.CC2 = TRUE;
867 sfrCEPool->adjCCPool = sfrCCPool; /* SFR_FIX */
868 sfrCCPool->pwrHiCCRange.startRb = 0;
869 sfrCCPool->pwrHiCCRange.endRb = 0;
872 sf->sfrTotalPoolInfo.CCRetx = FALSE;
873 sf->sfrTotalPoolInfo.CERetx = FALSE;
875 sf->sfrTotalPoolInfo.ccBwFull = FALSE;
876 sf->sfrTotalPoolInfo.ceBwFull = FALSE;
877 sf->sfrTotalPoolInfo.isUeCellEdge = FALSE;
881 * @brief This function resets temporary variables in RNTP Prepration
884 * Function: rgSchDSFRRntpInfoInit
886 * Invoked by: rgSCHSFRUtlTotalPoolInit
888 * @param[in] TknStrOSXL* rntpPtr
889 * @param[in] RgSubFrm* subFrm
893 S16 rgSchDSFRRntpInfoInit(TknStrOSXL *rntpPtr,RgSchCellCb *cell,uint16_t bw)
895 Inst inst = cell->instIdx;
898 rntpPtr->pres = PRSNT_NODEF;
900 len = (bw % 8 == 0) ? (bw/8) : (bw/8 + 1);
904 /* Allocate memory for "scheduled UE" Info */
905 if((rgSCHUtlAllocSBuf(inst, (Data**)&(rntpPtr->val),
906 (len * sizeof(uint8_t)))) != ROK)
908 DU_LOG("\nERROR --> SCH : Memory allocation FAILED for RNTP Alloc");
916 * @brief This function release RNTP pattern from slot and Cell
919 * Function: rgSchDSFRRntpInfoFree
921 * Invoked by: rgSCHSFRUtlTotalPoolInit
923 * @param[in] TknStrOSXL* rntpPtr
924 * @param[in] RgSubFrm* subFrm
928 S16 rgSchDSFRRntpInfoFree(TknStrOSXL *rntpPtr,RgSchCellCb *cell,uint16_t bw)
930 Inst inst = cell->instIdx;
933 len = (bw % 8 == 0) ? (bw/8) : (bw/8 + 1);
935 if(rntpPtr->pres == PRSNT_NODEF)
937 rgSCHUtlFreeSBuf(inst, (Data **)(&(rntpPtr->val)),(len * sizeof(uint8_t)));
938 rntpPtr->pres = NOTPRSNT;
946 * @brief This function resets temporary variables in Pool
949 * Function: rgSchSFRResetPoolVariables
950 * Purpose: Initialise the dynamic variables in each pool.
951 * Reset bwAlloced, bwAssigned, type2End, type0End, type2Start
952 * Invoked by: rgSCHSFRUtlTotalPoolReset
954 * @param[in] RgSchCellCb* cell
955 * @param[in] RgSchSFRPoolInfo *pool
959 static Void rgSchSFRResetPoolVariables(RgSchCellCb *cell,RgSchSFRPoolInfo *pool)
964 /*type0end will be the last RBG in pool with all available RBs*/
965 pool->type0End = (((pool->poolendRB + 1)/cell->rbgSize) - 1);
967 /*type2end will be the first RBG in pool with all available RBs*/
968 pool->type2End = RGSCH_CEIL(pool->poolstartRB, cell->rbgSize);
969 pool->type2Start = pool->poolstartRB;
970 pool->bw = pool->poolendRB - pool->poolstartRB + 1;
975 * @brief This function resets SFR Pool information for frame
979 * Function: rgSCHSFRUtlTotalPooReset
980 * Purpose: Update the dynamic variables in each pool as they will be modified in each slot.
981 * Dont modify the static variables like startRB, endRB, BW
982 * Invoked by: rgSCHUtlSubFrmPut
984 * @param[in] RgSchCellCb* cell
985 * @param[in] RgSchDlSf* subFrm
989 static Void rgSCHSFRUtlTotalPoolReset(RgSchCellCb *cell,RgSchDlSf *subFrm)
991 RgSchSFRTotalPoolInfo *totalPoolInfo = &subFrm->sfrTotalPoolInfo;
992 CmLListCp *ccPool = &totalPoolInfo->ccPool;
993 CmLListCp *cePool = &totalPoolInfo->cePool;
994 CmLList *node = NULLP;
995 RgSchSFRPoolInfo *tempPool = NULLP;
997 totalPoolInfo->ccBwFull = FALSE;
998 totalPoolInfo->ceBwFull = FALSE;
999 totalPoolInfo->isUeCellEdge = FALSE;
1000 totalPoolInfo->CCPool1BwAvlbl = 0;
1001 totalPoolInfo->CCPool2BwAvlbl = 0;
1002 totalPoolInfo->CEPoolBwAvlbl = 0;
1003 totalPoolInfo->CCRetx = FALSE;
1004 totalPoolInfo->CERetx = FALSE;
1006 node = ccPool->first;
1009 tempPool = (RgSchSFRPoolInfo *)(node->node);
1011 rgSchSFRResetPoolVariables(cell, tempPool);
1012 if(tempPool->poolstartRB == 0)
1013 totalPoolInfo->CCPool1BwAvlbl = tempPool->bw;
1015 totalPoolInfo->CCPool2BwAvlbl = tempPool->bw;
1018 node = cePool->first;
1021 tempPool = (RgSchSFRPoolInfo *)(node->node);
1023 rgSchSFRResetPoolVariables(cell, tempPool);
1024 totalPoolInfo->CEPoolBwAvlbl = tempPool->bw;
1029 /* LTE_ADV_FLAG_REMOVED_END */
1031 * @brief This function appends PHICH information for frame
1035 * Function: rgSCHUtlAddPhich
1036 * Purpose: This function appends PHICH information for
1041 * @param[in] RgSchCellCb* cell
1042 * @param[in] RgSubFrm* subFrm
1043 * @param[in] uint8_t hqFeedBack
1044 * @param[in] uint8_t nDmrs
1045 * @param[in] uint8_t rbStart
1051 S16 rgSCHUtlAddPhich
1054 CmLteTimingInfo frm,
1061 S16 rgSCHUtlAddPhich
1064 CmLteTimingInfo frm,
1075 Inst inst = cell->instIdx;
1077 dlSf = rgSCHUtlSubFrmGet(cell, frm);
1078 RGSCH_PHICH_ALLOC(inst, phich,sizeof(RgSchPhich), ret);
1082 DU_LOG("\nERROR --> SCH : rgSCHUtlAddPhich(): "
1083 "Allocation of RgSchPhich failed");
1087 RGSCH_INITPHICH(phich, hqFeedBack, nDmrs, rbStart, iPhich);
1089 RGSCH_INITPHICH(phich, hqFeedBack, nDmrs, rbStart, isForMsg3); /*SR_RACH_STATS */
1091 cmLListAdd2Tail(&dlSf->phichInfo.phichs, &phich->lnk);
1093 } /* rgSCHUtlAddPhich */
1096 * @brief This function resets PHICH information for frame
1100 * Function: rgSCHUtlPhichReset
1101 * Purpose: This function initializes PHICH information for
1102 * a slot. It removes the list of PHICHs allocated
1103 * in the prior use of this slot structure.
1105 * Invoked by: rgSCHUtlSubFrmPut
1107 * @param[in] RgSchCellCb* cell
1108 * @param[in] RgSubFrm* subFrm
1112 static Void rgSCHUtlPhichReset(RgSchCellCb *cell,RgSchDlSf *subFrm)
1114 RgSchPhichInfo *phichInfo;
1119 phichInfo = &subFrm->phichInfo;
1120 while(phichInfo->phichs.first != NULLP)
1122 phich = (RgSchPhich *)phichInfo->phichs.first->node;
1123 cmLListDelFrm(&phichInfo->phichs, phichInfo->phichs.first);
1124 RGSCH_PHICH_FREE(cell->instIdx, phich, sizeof(RgSchPhich));
1126 cmLListInit(&phichInfo->phichs);
1128 } /* rgSCHUtlPhichReset */
1132 * @brief This function returns slot data structure for a cell
1136 * Function: rgSCHUtlSubFrmGet
1137 * Purpose: This function resets the slot data structure
1138 * when the slot is released
1140 * Invoked by: scheduler
1142 * @param[in] RgSubFrm subFrm
1146 RgSchDlSf* rgSCHUtlSubFrmGet(RgSchCellCb *cell,CmLteTimingInfo frm)
1152 dlIdx = rgSCHUtlGetDlSfIdx(cell, &frm);
1153 //RGSCH_ARRAY_BOUND_CHECK(cell->instIdx, cell->subFrms, dlIdx);
1154 sf = cell->subFrms[dlIdx];
1156 /* Changing the idexing
1157 so that proper slot is selected */
1158 dlIdx = (((frm.sfn & 1) * RGSCH_NUM_SUB_FRAMES) + (frm.slot % RGSCH_NUM_SUB_FRAMES));
1159 RGSCH_ARRAY_BOUND_CHECK(cell->instIdx, cell->subFrms, dlIdx);
1160 sf = cell->subFrms[dlIdx];
1170 * @brief This function returns slot data structure for a cell
1174 * Function: rgSCHUtlSubFrmPut
1175 * Purpose: This function resets the slot data structure
1176 * when the slot is released
1178 * Invoked by: scheduler
1180 * @param[in] RgSubFrm subFrm
1184 Void rgSCHUtlSubFrmPut(RgSchCellCb *cell,RgSchDlSf *sf)
1190 /* Release all the held PDCCH information */
1191 rgSCHUtlPdcchInit(cell, sf, sf->nCce);
1193 /* Release all the held PDCCH information */
1194 rgSCHUtlPdcchInit(cell, sf, cell->nCce);
1196 rgSCHUtlPhichReset(cell, sf);
1198 /* Reset the bw allocated. */
1201 /* Setting allocated bandwidth to SPS bandwidth for non-SPS RB allocator */
1202 sf->bwAlloced = ((cell->spsCellCfg.maxSpsDlBw +
1203 cell->rbgSize - 1)/cell->rbgSize) * cell->rbgSize;
1204 if (sf->bwAlloced > sf->bw)
1206 sf->bwAlloced = sf->bw;
1208 sf->spsAllocdBw = 0;
1209 sf->type2Start = sf->bwAlloced;
1210 memset( &sf->dlSfAllocInfo, 0, sizeof(RgSchDlSfAllocInfo));
1213 /* Fix for ccpu00123918*/
1215 /* LTE_ADV_FLAG_REMOVED_START */
1216 /* dsfr_pal_fixes ** 21-March-2013 ** SKS */
1217 if (cell->lteAdvCb.dsfrCfg.status == RGR_ENABLE)
1219 memset(sf->rntpInfo.val, 0, sf->rntpInfo.len);
1221 /* LTE_ADV_FLAG_REMOVED_END */
1224 /*[ccpu00138609]-ADD-Reset the CCCH UE counter */
1227 /* Non DLFS scheduling using Type0 RA requires the following
1228 * parameter's tracking */
1229 /* Type 2 localized allocations start from 0th RBG and onwards */
1230 /* Type 0 allocations start from last RBG and backwards*/
1234 sf->type2End = RGSCH_CEIL(sf->bwAlloced,cell->rbgSize);
1236 sf->type0End = cell->noOfRbgs - 1;
1237 /* If last RBG is of incomplete size then special handling */
1238 (sf->bw % cell->rbgSize == 0)? (sf->lstRbgDfct = 0) :
1239 (sf->lstRbgDfct = cell->rbgSize - (sf->bw % cell->rbgSize));
1240 /* This resets the allocation for BCCH and PDCCH */
1242 /* TODO we need to move this reset for emtc functions */
1243 if(!(cell->emtcEnable))
1252 sf->bcch.pdcch = NULLP;
1253 sf->pcch.pdcch = NULLP;
1255 noRaRsps = RGSCH_MAX_TDD_RA_RSP_ALLOC;
1257 noRaRsps = RGSCH_MAX_RA_RSP_ALLOC;
1259 for (i = 0; i < noRaRsps; i++)
1261 sf->raRsp[i].pdcch = NULLP;
1262 cmLListInit(&(sf->raRsp[i].raRspLst));
1264 /* LTE_ADV_FLAG_REMOVED_START */
1265 if (cell->lteAdvCb.sfrCfg.status == RGR_ENABLE)
1267 rgSCHSFRUtlTotalPoolReset(cell, sf);
1269 /* LTE_ADV_FLAG_REMOVED_END */
1271 cmLListInit(&sf->n1PucchResLst);
1275 sf->isCceFailure = FALSE;
1276 sf->dlUlBothCmplt = 0;
1282 * @brief This function computes log N (32 bit Unsigned) to the base 2
1286 * Function: rgSCHUtlLog32bitNbase2
1287 * Purpose: This function computes log N (32 bit Unsigned) to the base 2.
1288 * For n= 0,1 ret = 0.
1290 * Invoked by: Scheduler
1292 * @param[in] uint32_t n
1296 uint8_t rgSCHUtlLog32bitNbase2(uint32_t n)
1298 uint32_t b[] = {0x2, 0xc, 0xf0, 0xff00, 0xffff0000};
1299 uint32_t s[] = {1, 2, 4, 8, 16};
1303 for (i=4; i >= 0; i--)
1317 * @brief This function is a wrapper to call scheduler specific API.
1321 * Function: rgSCHUtlDlRelPdcchFbk
1322 * Purpose: Calls scheduler's handler for SPS release PDCCH feedback
1327 * @param[in] RgSchCellCb *cell
1328 * @param[in] RgSchUeCb *ue
1329 * @param[in] uint8_t isAck
1333 Void rgSCHUtlDlRelPdcchFbk(RgSchCellCb *cell,RgSchUeCb *ue,uint8_t isAck)
1335 cell->sc.apis->rgSCHDlRelPdcchFbk(cell, ue, isAck);
1342 * @brief This function is a wrapper to call scheduler specific API.
1346 * Function: rgSCHUtlDlProcAck
1347 * Purpose: Calls scheduler's handler to process Ack
1352 * @param[in] RgSchCellCb *cell
1353 * @param[in] RgSchDlHqProcCb *hqP
1357 Void rgSCHUtlDlProcAck(RgSchCellCb *cell,RgSchDlHqProcCb *hqP)
1359 cell->sc.apis->rgSCHDlProcAck(cell, hqP);
1364 * @brief CRNTI CE Handler
1368 * Function : rgSCHUtlHdlCrntiCE
1370 * - Call scheduler common API
1373 * @param[in] RgSchCellCb *cell
1374 * @param[in] RgSchUeCb *ue
1375 * @param[out] RgSchErrInfo *err
1378 Void rgSCHUtlHdlCrntiCE(RgSchCellCb *cell,RgSchUeCb *ue)
1381 cell->sc.apis->rgSCHHdlCrntiCE(cell, ue);
1383 } /* rgSCHUtlHdlCrntiCE */
1384 #endif /* LTEMAC_SPS */
1386 /***********************************************************
1388 * Func : rgSCHUtlCalcTotalRegs
1390 * Desc : Calculate total REGs, given a bandwidth, CFI
1391 * and number of antennas.
1393 * Ret : Total REGs (uint16_t)
1395 * Notes: Could optimise if bw values are limited
1396 * (taken from RRC spec) by indexing values from
1398 * Input values are not validated. CFI is assumed
1403 **********************************************************/
1404 static uint16_t rgSCHUtlCalcTotalRegs(uint8_t bw,uint8_t cfi,uint8_t numAntna,Bool isEcp)
1408 /*ccpu00116757- removed check for (ERRCLASS & ERRCLS_DEBUG)*/
1414 /* Refer 36.211 section 6.10.1.2
1415 * For symbols 2 and 4, the REGs per RB will be based on cyclic prefix
1416 * and number of antenna ports.
1417 * For symbol 1, there are 2 REGs per RB always. Similarly symbol 3
1421 /*CR changes [ccpu00124416] - MOD*/
1424 regs = bw * RGSCH_NUM_REGS_4TH_SYM_EXT_CP;
1428 regs = bw * RGSCH_NUM_REGS_4TH_SYM_NOR_CP;
1431 regs += bw * RGSCH_NUM_REGS_3RD_SYM;
1433 /*CR changes [ccpu00124416] - MOD using number of antenna ports*/
1434 regs += (numAntna == RGSCH_NUM_ANT_PORT_FOUR) ? \
1435 (bw * RGSCH_NUM_REGS_2ND_SYM_FOUR_ANT_PORT) : \
1436 (bw * RGSCH_NUM_REGS_2ND_SYM_1OR2_ANT_PORT);
1437 default: /* case 1 */
1438 regs += bw * RGSCH_NUM_REGS_1ST_SYM;
1443 /***********************************************************
1445 * Func : rgSCHUtlCalcPhichRegs
1447 * Desc : Calculates number of PHICH REGs
1449 * Ret : Number of PHICH REGs (uint8_t)
1451 * Notes: ng6 is Ng multiplied by 6
1455 **********************************************************/
1456 static uint16_t rgSCHUtlCalcPhichRegs(uint8_t bw,uint8_t ng6)
1458 /* ccpu00115330: Corrected the calculation for number of PHICH groups*/
1459 return (RGSCH_CEIL((bw * ng6) ,(8 * 6)) * RGSCH_NUM_REG_PER_PHICH_GRP);
1464 * @brief Calculates total CCEs (N_cce)
1468 * Function: rgSCHUtlCalcNCce
1469 * Purpose: This function calculates and returns total CCEs for a
1470 * cell, given the following: bandwidth, Ng configuration
1471 * (multiplied by six), cfi (actual number of control
1472 * symbols), m factor for PHICH and number of antennas.
1474 * Invoked by: Scheduler
1476 * @param[in] uint8_t bw
1477 * @param[in] uint8_t ng6
1478 * @param[in] uint8_t cfi
1479 * @param[in] uint8_t mPhich
1480 * @param[in] uint8_t numAntna
1481 * @param[in] Bool isEcp
1482 * @return N_cce (uint8_t)
1485 uint8_t rgSCHUtlCalcNCce(uint8_t bw,RgrPhichNg ng,uint8_t cfi,uint8_t mPhich,uint8_t numAntna,Bool isEcp)
1492 /*ccpu00116757- removed check for (ERRCLASS & ERRCLS_DEBUG)*/
1496 case RGR_NG_ONESIXTH:
1511 totalRegs = rgSCHUtlCalcTotalRegs(bw, cfi, numAntna, isEcp);
1512 phichRegs = rgSCHUtlCalcPhichRegs(bw, ng6);
1513 cceRegs = totalRegs - mPhich*phichRegs - RGSCH_NUM_PCFICH_REG;
1515 return ((uint8_t)(cceRegs/RGSCH_NUM_REG_PER_CCE));
1520 * @brief Calculates total CCEs (N_cce)
1524 * Function: rgSCHUtlCalcNCce
1525 * Purpose: This function calculates and returns total CCEs for a
1526 * cell, given the following: bandwidth, Ng configuration
1527 * (multiplied by six), cfi (actual number of control
1528 * symbols) and number of antennas.
1530 * Invoked by: Scheduler
1532 * @param[in] uint8_t bw
1533 * @param[in] uint8_t ng6
1534 * @param[in] uint8_t cfi
1535 * @param[in] uint8_t numAntna
1536 * @return N_cce (uint8_t)
1539 uint8_t rgSCHUtlCalcNCce(uint8_t bw,RgrPhichNg ng,uint8_t cfi,uint8_t numAntna,Bool isEcp)
1546 /*ccpu00116757- removed check for (ERRCLASS & ERRCLS_DEBUG)*/
1550 case RGR_NG_ONESIXTH:
1565 totalRegs = rgSCHUtlCalcTotalRegs(bw, cfi, numAntna, isEcp);
1566 phichRegs = rgSCHUtlCalcPhichRegs(bw, ng6);
1567 cceRegs = totalRegs - phichRegs - RGSCH_NUM_PCFICH_REG;
1569 return ((uint8_t)(cceRegs/RGSCH_NUM_REG_PER_CCE));
1574 * @brief Returns PHICH info associated with an uplink
1575 * HARQ process allocation
1579 * Function: rgSCHUtlGetPhichInfo
1580 * Purpose: This function returns PHICH info associated with
1581 * an uplink HARQ process allocation. PHICH info
1582 * comprises RB start and N_dmrs.
1584 * @param[in] RgSchUlHqProcCb *hqProc
1585 * @param[out] uint8_t *rbStartRef
1586 * @param[out] uint8_t *nDmrsRef
1590 S16 rgSCHUtlGetPhichInfo(RgSchUlHqProcCb *hqProc,uint8_t *rbStartRef,uint8_t *nDmrsRef,uint8_t *iPhich)
1592 S16 rgSCHUtlGetPhichInfo(RgSchUlHqProcCb *hqProc,uint8_t *rbStartRef,uint8_t *nDmrsRef)
1598 if ((hqProc != NULLP) && (hqProc->alloc != NULLP))
1600 *rbStartRef = hqProc->alloc->grnt.rbStart;
1601 *nDmrsRef = hqProc->alloc->grnt.nDmrs;
1603 *iPhich = hqProc->iPhich;
1611 * @brief Returns uplink grant information required to permit
1612 * PHY to receive data
1616 * Function: rgSCHUtlAllocRcptInfo
1617 * Purpose: Given an uplink allocation, this function returns
1618 * uplink grant information which is needed by PHY to
1619 * decode data sent from UE. This information includes:
1624 * @param[in] RgSchUlAlloc *alloc
1625 * @param[out] uint8_t *rbStartRef
1626 * @param[out] uint8_t *numRbRef
1627 * @param[out] uint8_t *rvRef
1628 * @param[out] uint16_t *size
1629 * @param[out] TfuModScheme *modType
1630 * @param[out] Bool *isRtx
1631 * @param[out] uint8_t *nDmrs
1632 * @param[out] Bool *ndi
1633 * @param[out] uint8_t *hqPId
1636 S16 rgSCHUtlAllocRcptInfo
1638 RgSchUlAlloc *alloc,
1641 uint8_t *rbStartRef,
1645 TfuModScheme *modType,
1652 /* Modulation order for 16qam UEs would be
1653 * min(4,modulation order in grant). Please refer to 36.213-8.6.1*/
1654 CmLteUeCategory ueCtgy;
1656 #if (ERRCLASS & ERRCLS_DEBUG)
1657 if ((alloc == NULLP) || (alloc->hqProc == NULLP))
1663 if ( !alloc->forMsg3 )
1665 if ( ((alloc->ue) == NULLP) || (RG_SCH_CMN_GET_UE(alloc->ue, alloc->ue->cell) == NULLP))
1667 DU_LOG("\nERROR --> SCH : Failed: ue->sch is null RNTI:%d,isRetx=%d",
1668 alloc->rnti, alloc->grnt.isRtx);
1671 ueCtgy = (RG_SCH_CMN_GET_UE_CTGY(alloc->ue));
1674 *iMcsRef = alloc->grnt.iMcs;
1675 *rbStartRef = alloc->grnt.rbStart;
1676 *numRbRef = alloc->grnt.numRb;
1677 *rvRef = rgRvTable[alloc->hqProc->rvIdx];
1678 *rnti = alloc->rnti;
1679 *size = alloc->grnt.datSz;
1680 *modType = (alloc->forMsg3)? alloc->grnt.modOdr:
1681 ((ueCtgy == CM_LTE_UE_CAT_5)?
1683 (RGSCH_MIN(RGSCH_QM_QPSK,alloc->grnt.modOdr)));
1684 *isRtx = alloc->grnt.isRtx;
1685 *nDmrs = alloc->grnt.nDmrs;
1686 *ndi = alloc->hqProc->ndi;
1687 *hqPId = alloc->hqProc->procId;
1693 * @brief Returns uplink grant information required to permit
1694 * PHY to receive data
1698 * Function: rgSCHUtlAllocRcptInfo
1699 * Purpose: Given an uplink allocation, this function returns
1700 * uplink grant information which is needed by PHY to
1701 * decode data sent from UE. This information includes:
1706 * @param[in] RgSchUlAlloc *alloc
1707 * @param[out] uint8_t *rbStartRef
1708 * @param[out] uint8_t *numRbRef
1709 * @param[out] uint8_t *rvRef
1710 * @param[out] uint16_t *size
1711 * @param[out] TfuModScheme *modType
1714 S16 rgSCHUtlAllocRcptInfo(RgSchCellCb *cell,RgSchUlAlloc *alloc,CmLteTimingInfo *timeInfo,TfuUeUlSchRecpInfo *recpReq)
1716 #if (ERRCLASS & ERRCLS_DEBUG)
1717 if ((alloc == NULLP) || (alloc->hqProc == NULLP))
1722 recpReq->size = alloc->grnt.datSz;
1723 recpReq->rbStart = alloc->grnt.rbStart;
1724 recpReq->numRb = alloc->grnt.numRb;
1725 /* Modulation order min(4,mod in grant) for 16 qam UEs.
1726 * Please refer to 36.213-8.6.1*/
1727 #ifdef FOUR_TX_ANTENNA
1728 recpReq->modType = (TfuModScheme)((alloc->forMsg3)?alloc->grnt.modOdr:
1729 (/*(alloc->ue->ueCatEnum == CM_LTE_UE_CAT_5)?
1730 alloc->grnt.modOdr: *//* Chandra:TmpFx-TM500 Cat5 with Only16QAM */
1731 (RGSCH_MIN(RGSCH_QM_QPSK,alloc->grnt.modOdr))));
1733 recpReq->modType = (TfuModScheme)((alloc->forMsg3)?alloc->grnt.modOdr:
1734 ((alloc->ue->ueCatEnum == CM_LTE_UE_CAT_5)?
1736 (RGSCH_MIN(RGSCH_QM_QPSK,alloc->grnt.modOdr))));
1738 recpReq->nDmrs = alloc->grnt.nDmrs;
1739 recpReq->hoppingEnbld = FALSE;
1740 recpReq->hoppingBits = 0;
1741 recpReq->isRtx = alloc->grnt.isRtx;
1742 recpReq->ndi = alloc->hqProc->ndi;
1743 recpReq->rv = rgRvTable[alloc->hqProc->rvIdx];
1745 recpReq->harqProcId = alloc->hqProc->procId;
1747 recpReq->harqProcId = rgSCHCmnGetUlHqProcIdx(timeInfo, cell);
1749 /* Transmission mode is SISO till Uplink MIMO is implemented. */
1750 recpReq->txMode = 0;
1751 /* This value needs to filled in in the case of frequency hopping. */
1752 recpReq->crntTxNb = 0;
1754 recpReq->mcs = alloc->grnt.iMcs;
1756 recpReq->rbgStart = alloc->grnt.vrbgStart;
1757 recpReq->numRbg = alloc->grnt.numVrbg;
1758 recpReq->xPUSCHRange = alloc->grnt.xPUSCHRange;
1759 //TODO_SID Need to check
1760 recpReq->nAntPortLayer = 0;
1761 recpReq->SCID = alloc->grnt.SCID;
1762 recpReq->PMI = alloc->grnt.PMI;
1763 recpReq->uciWoTBFlag = alloc->grnt.uciOnxPUSCH;
1766 recpReq->beamIndex = alloc->ue->ue5gtfCb.BeamId;
1771 if (!alloc->forMsg3)
1773 if (alloc->grnt.isRtx)
1775 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulRetxOccns++;
1779 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulTxOccns++;
1780 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulSumiTbs += \
1781 rgSCHCmnUlGetITbsFrmIMcs(alloc->grnt.iMcs);
1782 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulNumiTbs ++;
1783 cell->tenbStats->sch.ulSumiTbs += \
1784 rgSCHCmnUlGetITbsFrmIMcs(alloc->grnt.iMcs);
1785 cell->tenbStats->sch.ulNumiTbs ++;
1787 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulPrbUsg += alloc->grnt.numRb;
1788 cell->tenbStats->sch.ulPrbUsage[0] += alloc->grnt.numRb;
1791 /* ccpu00117050 - DEL - nSrs setting at rgSCHUtlAllocRcptInfo */
1798 * @brief This function initialises the PRACH slot occasions
1802 * Function: rgSCHUtlUpdPrachOcc
1803 * Purpose: This function updates the PRACH slots based on
1804 * RGR configuration.
1806 * Invoked by: Scheduler
1808 * @param[in] RgSchCellCb *cell
1809 * @param[in] RgrTddPrachInfo *cellCfg
1813 static Void rgSCHUtlUpdPrachOcc(RgSchCellCb *cell,RgrTddPrachInfo *cellCfg)
1821 /* In the 1st half frame */
1822 if(cellCfg->halfFrm == 0)
1827 /* In the 2nd half frame */
1833 for(idx = startIdx; idx < endIdx; idx++)
1835 if(rgSchTddUlDlSubfrmTbl[cell->ulDlCfgIdx][idx]
1836 == RG_SCH_TDD_UL_slot)
1838 if(cellCfg->ulStartSfIdx == count)
1840 size = cell->rachCfg.raOccasion.size;
1841 cell->rachCfg.raOccasion.slotNum[size] = idx;
1842 cell->rachCfg.raOccasion.size++;
1852 * @brief This function initialises the PRACH occasions
1856 * Function: rgSCHUtlPrachCfgInit
1857 * Purpose: This function initialises the PRACH occasions based on
1858 * RGR configuration.
1860 * Invoked by: Scheduler
1862 * @param[in] RgSchCellCb *cell
1863 * @param[in] RgrCellCfg *cellCfg
1867 Void rgSCHUtlPrachCfgInit(RgSchCellCb *cell,RgrCellCfg *cellCfg)
1873 if(cellCfg->prachRscInfo.numRsc <= 0)
1875 DU_LOG("\nERROR --> SCH : Invalid"
1876 "PRACH resources Configuration ");
1880 /* Update SFN occasions */
1881 cell->rachCfg.raOccasion.sfnEnum =
1882 cellCfg->prachRscInfo.prachInfo[0].sfn;
1884 cell->rachCfg.raOccasion.size = 0;
1886 /* Update slot occasions */
1887 for(idx = 0; idx < cellCfg->prachRscInfo.numRsc; idx++)
1889 if(cellCfg->prachRscInfo.prachInfo[idx].freqIdx == 0)
1891 if(cellCfg->prachRscInfo.prachInfo[idx].halfFrm == 0)
1899 if(cellCfg->prachRscInfo.prachInfo[idx].ulStartSfIdx ==
1902 subfrmIdx = cell->rachCfg.raOccasion.size;
1903 cell->rachCfg.raOccasion.slotNum[subfrmIdx] = splFrm;
1904 cell->rachCfg.raOccasion.size++;
1908 rgSCHUtlUpdPrachOcc(cell,
1909 &cellCfg->prachRscInfo.prachInfo[idx]);
1917 * @brief This function performs RGR cell initialization
1921 * Function: rgSCHUtlRgrCellCfg
1922 * Purpose: This function initialises the cell with RGR configuration
1923 * and slot related initialization.
1925 * Invoked by: Scheduler
1927 * @param[in] RgSchCellCb *cell
1928 * @param[in] RgrCellCfg *cellCfg
1929 * @param[in] RgSchErrInfo *errInfo
1933 S16 rgSCHUtlRgrCellCfg(RgSchCellCb *cell,RgrCellCfg *cellCfg,RgSchErrInfo *errInfo)
1939 CmLteTimingInfo frm;
1940 uint8_t ulDlCfgIdx = cellCfg->ulDlCfgIdx;
1944 uint16_t bw; /*!< Number of RBs in the cell */
1946 memset(&frm,0,sizeof(CmLteTimingInfo));
1948 /* ccpu00132657-MOD- Determining DLSF array size independent of DELTAS */
1949 maxDlslots = rgSchTddNumDlSubfrmTbl[ulDlCfgIdx][RGSCH_NUM_SUB_FRAMES-1];
1950 maxslots = 2 * maxDlslots;
1951 cell->numDlSubfrms = maxslots;
1952 /* ACC-TDD <ccpu00130639> */
1953 cell->tddHqSfnCycle = -1;
1954 cell->ulDlCfgIdx = ulDlCfgIdx;
1956 /* PRACH Occasions Initialization */
1957 rgSCHUtlPrachCfgInit(cell, cellCfg);
1959 /* ccpu00132658- Moved out of below for loop since the updating rbgSize and
1960 * bw are independent of sfNum*/
1961 /* determine the RBG size and no of RBGs for the configured
1963 if (cell->bwCfg.dlTotalBw > 63)
1967 else if (cell->bwCfg.dlTotalBw > 26)
1971 else if (cell->bwCfg.dlTotalBw > 10)
1979 cell->noOfRbgs = RGSCH_CEIL(cell->bwCfg.dlTotalBw, cell->rbgSize);
1981 bw = cell->bwCfg.dlTotalBw;
1983 rgSCHUtlAllocSBuf(cell->instIdx,
1984 (Data **)&cell->subFrms, sizeof(RgSchDlSf *) * maxslots);
1985 if (cell->subFrms == NULLP)
1990 /* Create memory for each frame. */
1991 for(i = 0; i < maxslots; i++)
1993 while(rgSchTddUlDlSubfrmTbl[ulDlCfgIdx][sfNum] ==
1996 sfNum = (sfNum+1) % RGSCH_NUM_SUB_FRAMES;
1999 rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&sf, sizeof(RgSchDlSf));
2004 memset(sf, 0, sizeof(*sf));
2007 if (ROK != rgSCHLaaInitDlSfCb(cell, sf))
2015 /* Mark SPS bandwidth to be occupied */
2016 sf->bwAlloced = ((cellCfg->spsCfg.maxSpsDlBw +
2017 cell->rbgSize - 1)/cell->rbgSize) * cell->rbgSize;
2018 sf->spsAllocdBw = 0;
2019 sf->type2End = sf->bwAlloced/cell->rbgSize;
2022 /* Fix for ccpu00123918*/
2024 #endif /* LTEMAC_SPS */
2025 /* Initialize the ackNakRepQ here */
2026 #ifdef RG_MAC_MEASGAP
2027 cmLListInit (&(sf->ackNakRepQ));
2029 cell->subFrms[i] = sf;
2030 sfNum = (sfNum+1) % RGSCH_NUM_SUB_FRAMES;
2036 /* ccpu00117052 - MOD - Passing double pointer
2037 for proper NULLP assignment*/
2038 rgSCHUtlFreeSBuf(cell->instIdx,
2039 (Data **)(&(cell->subFrms[i-1])), sizeof(RgSchDlSf));
2041 rgSCHLaaDeInitDlSfCb(cell, sf);
2044 /* ccpu00117052 - MOD - Passing double pointer
2045 for proper NULLP assignment*/
2046 rgSCHUtlFreeSBuf(cell->instIdx,
2047 (Data **)(&(cell->subFrms)), sizeof(RgSchDlSf *) * maxslots);
2052 if (cell->sc.apis == NULLP)
2054 cell->sc.apis = &rgSchCmnApis;
2056 ret = cell->sc.apis->rgSCHRgrCellCfg(cell, cellCfg, errInfo);
2060 /* ccpu00132286- Removed deletion of sf nodes as the deletion will be
2061 * happening during CellDelete. Added return handling to provide negative
2066 /* Release the slots and thereby perform the initialization */
2067 for (i = 0; i < maxslots; i++)
2069 if((i > 0) && (i%maxDlslots == 0))
2074 frm.slot = cell->subFrms[i]->sfNum;
2075 rgSCHUtlDlRlsSubFrm(cell, frm);
2084 * @brief This function performs scheduler related cell creation
2088 * Function: rgSCHUtlRgrCellCfg
2089 * Purpose: This function creates the slots needed for the
2090 * cell. It then peforms init of the scheduler by calling
2091 * scheduler specific cell init function.
2093 * Invoked by: Scheduler
2095 * @param[in] RgSchCellCb *cell
2096 * @param[in] RgrCellCfg *cellCfg
2097 * @param[in] RgSchErrInfo *errInfo
2101 S16 rgSCHUtlRgrCellCfg(RgSchCellCb *cell,RgrCellCfg *cellCfg,RgSchErrInfo *errInfo)
2105 CmLteTimingInfo frm;
2107 Inst inst = cell->instIdx;
2108 /* LTE_ADV_FLAG_REMOVED_START */
2110 len = (uint16_t)((cell->bwCfg.dlTotalBw % 8 == 0) ? (cell->bwCfg.dlTotalBw/8) : (cell->bwCfg.dlTotalBw/8 + 1)); /*KW fix for LTE_ADV */
2111 /* LTE_ADV_FLAG_REMOVED_END */
2113 memset(&frm,0,sizeof(CmLteTimingInfo));
2115 /* determine the RBG size and no of RBGs for the configured
2117 if (cell->bwCfg.dlTotalBw > 63)
2121 else if (cell->bwCfg.dlTotalBw > 26)
2125 else if (cell->bwCfg.dlTotalBw > 10)
2133 cell->noOfRbgs = RGSCH_CEIL(cell->bwCfg.dlTotalBw, cell->rbgSize);
2134 /* Create memory for each frame. */
2135 /* Changing loop limit from
2136 RGSCH_NUM_SUB_FRAMES to RGSCH_NUM_DL_slotS */
2137 for(i = 0; i < RGSCH_NUM_DL_slotS; i++)
2139 rgSCHUtlAllocSBuf(inst, (Data **)&sf, sizeof(RgSchDlSf));
2144 memset(sf, 0, sizeof(*sf));
2147 if (ROK != rgSCHLaaInitDlSfCb(cell, sf))
2152 /* Doing MOD operation before assigning value of i */
2153 sf->sfNum = i % RGSCH_NUM_SUB_FRAMES;
2154 sf->bw = cell->bwCfg.dlTotalBw;
2155 /* Initialize the ackNakRepQ here */
2156 #ifdef RG_MAC_MEASGAP
2157 cmLListInit (&(sf->ackNakRepQ));
2159 cell->subFrms[i] = sf;
2160 /* LTE_ADV_FLAG_REMOVED_START */
2161 if (cell->lteAdvCb.dsfrCfg.status == RGR_ENABLE)
2163 /*initialize the RNTP Buffer*/
2164 if(rgSchDSFRRntpInfoInit(&sf->rntpInfo, cell, sf->bw))
2170 if (cell->lteAdvCb.sfrCfg.status == RGR_ENABLE)
2172 /*initialise the pools of CC and CE*/
2173 if(rgSchSFRTotalPoolInit(cell, sf))
2178 /* LTE_ADV_FLAG_REMOVED_END */
2181 /* LTE_ADV_FLAG_REMOVED_START */
2182 /* Allocate memory for "scheduled UE" Info */
2183 if (cell->lteAdvCb.dsfrCfg.status == RGR_ENABLE)
2185 if((rgSCHUtlAllocSBuf(inst, (Data**)&(cell->rntpAggrInfo.val),
2186 (len * sizeof(uint8_t)))) != ROK)
2188 DU_LOG("\nERROR --> SCH : Memory allocation FAILED for RNTP Alloc");
2191 cell->rntpAggrInfo.pres = PRSNT_NODEF;
2192 cell->rntpAggrInfo.len = len;
2194 /* LTE_ADV_FLAG_REMOVED_END */
2196 /* Changing loop limit from
2197 RGSCH_NUM_SUB_FRAMES to RGSCH_NUM_DL_slotS */
2198 if (i != RGSCH_NUM_DL_slotS)
2202 /* ccpu00117052 - MOD - Passing double pointer
2203 for proper NULLP assignment*/
2204 rgSCHUtlFreeSBuf(inst, (Data **)(&(cell->subFrms[i-1])),
2207 rgSCHLaaDeInitDlSfCb(cell, sf);
2213 if (cell->sc.apis == NULLP)
2215 cell->sc.apis = &rgSchCmnApis;
2218 /* Release the slots and thereby perform the initialization */
2219 for (i = 0; i < RGSCH_NUM_DL_slotS; i++)
2221 if (i >= RGSCH_NUM_SUB_FRAMES)
2223 /* [ccpu00123828]-MOD-The below statement sfn += 1incorrectly modified
2224 * the value of sfn for i>=10 thru 19. Correct way is to assign
2228 frm.slot = i % RGSCH_NUM_SUB_FRAMES;
2229 rgSCHUtlDlRlsSubFrm(cell, frm);
2232 ret = cell->sc.apis->rgSCHRgrCellCfg(cell, cellCfg, errInfo);
2235 errInfo->errCause = RGSCHERR_SCH_CFG;
2239 if(cell->emtcEnable)
2241 /* TODO: Repetition framework in RGR and APP */
2242 if (rgSCHUtlEmtcResMngmtInit(
2244 RGSCH_IOT_PDSCH_POOLSZ, RGSCH_IOT_PDSCH_DELTA, cellCfg->bwCfg.dlTotalBw,
2245 RGSCH_IOT_PUSCH_POOLSZ, RGSCH_IOT_PUSCH_DELTA, RGSCH_IOT_PUSCH_MAXFREQSZ,
2246 RGSCH_IOT_PUCCH_POOLSZ, RGSCH_IOT_PUCCH_DELTA, RGSCH_IOT_PUCCH_MAXFREQSZ) != ROK)
2248 errInfo->errCause = RGSCHERR_SCH_CFG;
2260 * @brief This function performs the cell reconfiguration at RGR interface
2264 * Function: rgSCHUtlRgrCellRecfg
2265 * Purpose: This function updates the reconfigurable parameters
2266 * on the cell control block for the scheduler.
2268 * Invoked by: Scheduler
2270 * @param[in] RgSchCellCb *cell
2271 * @param[in] RgrCellCfg *cellCfg
2272 * @param[in] RgSchErrInfo *errInfo
2276 S16 rgSCHUtlRgrCellRecfg(RgSchCellCb *cell,RgrCellRecfg *recfg,RgSchErrInfo *err)
2278 return (cell->sc.apis->rgSCHRgrCellRecfg(cell, recfg, err));
2284 * @brief This function returns the Y value of UE for a sub frame
2288 * Function: rgSCHUtlFreeCell
2289 * Purpose: This function updates the value of Y stored in the
2290 * UE control block. It uses the previously computed
2291 * value for computing for this slot.
2293 * Invoked by: Scheduler
2295 * @param[in] RgSchCellCb *cell
2299 S16 rgSCHUtlFreeCell(RgSchCellCb *cell)
2304 RgSchPdcchInfo *pdcchInfo;
2305 RgSchPhichInfo *phichInfo;
2307 Inst inst = cell->instIdx;
2310 RgSchRaReqInfo *raReqInfo;
2315 maxslots = cell->numDlSubfrms;
2317 maxslots = RGSCH_NUM_DL_slotS;
2321 /* Invoke the index for scheduler, cell deletion */
2322 cell->sc.apis->rgSCHFreeCell(cell);
2324 /* Release the slots allocated */
2325 for (i = 0; i < maxslots; i++)
2328 rgSCHLaaDeInitDlSfCb(cell, cell->subFrms[i]);
2330 pdcchInfo = &cell->subFrms[i]->pdcchInfo;
2331 /* ccpu00117052 - MOD - Passing double pointer
2332 for proper NULLP assignment*/
2333 rgSCHUtlFreeSBuf(inst, (Data **)(&(pdcchInfo->map)),
2334 (pdcchInfo->nCce + 7) >> 3);
2335 while (pdcchInfo->pdcchs.first != NULLP)
2337 pdcch = (RgSchPdcch *)pdcchInfo->pdcchs.first->node;
2338 cmLListDelFrm(&pdcchInfo->pdcchs, pdcchInfo->pdcchs.first);
2339 /* ccpu00117052 - MOD - Passing double pointer
2340 for proper NULLP assignment*/
2341 rgSCHUtlFreeSBuf(inst, (Data **)&pdcch, sizeof(RgSchPdcch));
2344 phichInfo = &cell->subFrms[i]->phichInfo;
2345 while(phichInfo->phichs.first != NULLP)
2347 phich = (RgSchPhich *)phichInfo->phichs.first->node;
2348 cmLListDelFrm(&phichInfo->phichs, phichInfo->phichs.first);
2349 RGSCH_PHICH_FREE(inst, phich, sizeof(RgSchPhich));
2352 /* LTE_ADV_FLAG_REMOVED_START */
2353 /*releasing SFR pool entries*/
2354 rgSchSFRTotalPoolFree(&cell->subFrms[i]->sfrTotalPoolInfo, cell);
2356 /*releasing dsfr rntp pattern info*/
2357 rgSchDSFRRntpInfoFree(&cell->subFrms[i]->rntpInfo, cell,
2358 cell->bwCfg.dlTotalBw);
2359 /* LTE_ADV_FLAG_REMOVED_END */
2361 /* ccpu00117052 - MOD - Passing double pointer
2362 for proper NULLP assignment*/
2363 rgSCHUtlFreeSBuf(inst, (Data **)(&(cell->subFrms[i])), sizeof(RgSchDlSf));
2366 /* Release the slot pointers */
2367 /* ccpu00117052 - MOD - Passing double pointer
2368 for proper NULLP assignment*/
2369 rgSCHUtlFreeSBuf(inst,
2370 (Data **) (&(cell->subFrms)), sizeof(RgSchDlSf *) * maxslots);
2372 for(idx=0; idx < cell->raInfo.lstSize; idx++)
2374 lst = &cell->raInfo.raReqLst[idx];
2375 while (lst->first != NULLP)
2377 raReqInfo = (RgSchRaReqInfo *)lst->first->node;
2378 cmLListDelFrm(lst, &raReqInfo->raReqLstEnt);
2379 /* ccpu00117052 - MOD - Passing double pointer
2380 for proper NULLP assignment*/
2381 rgSCHUtlFreeSBuf(inst,(Data **)&raReqInfo, sizeof(RgSchRaReqInfo));
2384 /* ccpu00117052 - MOD - Passing double pointer
2385 for proper NULLP assignment*/
2386 rgSCHUtlFreeSBuf(inst,
2387 (Data **)(&(cell->raInfo.raReqLst)),
2388 sizeof(CmLListCp) * (cell->raInfo.lstSize));
2391 /* Release allocated pdcchs */
2392 lst = &cell->pdcchLst;
2393 while (lst->first != NULLP)
2395 pdcch = (RgSchPdcch *)lst->first->node;
2396 cmLListDelFrm(lst, &pdcch->lnk);
2398 if(cell->emtcEnable)
2400 rgSCHEmtcPdcchFree(cell, pdcch);
2401 rgSCHUtlEmtcResMngmtDeinit(cell);
2404 /* ccpu00117052 - MOD - Passing double pointer
2405 for proper NULLP assignment*/
2406 rgSCHUtlFreeSBuf(inst,(Data **)&pdcch, sizeof(RgSchPdcch));
2409 rgSCHLaaFreeLists(cell);
2412 /* LTE_ADV_FLAG_REMOVED_START */
2413 /* releasing RNTP Aggregation Info from CellCb*/
2414 rgSchDSFRRntpInfoFree(&cell->rntpAggrInfo, cell, cell->bwCfg.dlTotalBw);
2415 /* LTE_ADV_FLAG_REMOVED_END */
2422 * @brief This function adds the UE to scheduler
2426 * Function: rgSCHUtlRgrUeCfg
2427 * Purpose: This function performs addition of UE to scheduler
2428 * 1. First, it updates the Y table in the UE
2429 * 2. Then, it calls the scheduler's handler for UE addition
2431 * Invoked by: Scheduler
2433 * @param[in] RgSchCellCb *cell
2434 * @param[in] RgSchUeCb *ue
2435 * @param[in] RgrUeCfg *cfg
2436 * @param[in] RgSchErrInfo *err
2440 S16 rgSCHUtlRgrUeCfg(RgSchCellCb *cell,RgSchUeCb *ue,RgrUeCfg *cfg,RgSchErrInfo *err)
2443 /* Assign TM 1 as UE's default TM */
2444 ue->mimoInfo.txMode = RGR_UE_TM_1;
2445 ue->txModeTransCmplt = TRUE;
2446 cmInitTimers(&ue->txModeTransTmr, 1);
2447 if (cfg->txMode.pres == PRSNT_NODEF)
2449 /* DL MU-MIMO not supported */
2450 if (cfg->txMode.txModeEnum == RGR_UE_TM_5)
2452 err->errCause = RGSCHERR_SCH_CFG;
2455 ue->mimoInfo.txMode = cfg->txMode.txModeEnum;
2457 ue->ul.ulTxAntSel = cfg->ulTxAntSel;
2458 ue->mimoInfo.cdbkSbstRstrctn = cfg->ueCodeBookRstCfg;
2460 ue->ueCatEnum = cfg->ueCatEnum;
2461 if ((cfg->puschDedCfg.bACKIdx > 15) ||
2462 (cfg->puschDedCfg.bCQIIdx > 15) ||
2463 (cfg->puschDedCfg.bRIIdx > 15))
2465 err->errCause = RGSCHERR_SCH_CFG;
2468 ue->ul.betaHqOffst = cfg->puschDedCfg.bACKIdx;
2469 ue->ul.betaCqiOffst = cfg->puschDedCfg.bCQIIdx;
2470 ue->ul.betaRiOffst = cfg->puschDedCfg.bRIIdx;
2472 ue->csgMmbrSta = cfg->csgMmbrSta;
2474 memset(&ue->pfsStats, 0, sizeof(RgSchPfsStats));
2476 /* Call the handler of the scheduler based on cell configuration */
2477 return (cell->sc.apis->rgSCHRgrUeCfg(cell, ue, cfg, err));
2479 /* Start : LTEMAC_2.1_DEV_CFG */
2482 * @brief This function adds a service to scheduler
2486 * Function: rgSCHUtlRgrLcCfg
2487 * Purpose: This function performs addition of service to scheduler
2488 * The addition is performed for each direction based
2489 * the direction field of the configuration
2491 * Invoked by: Scheduler
2493 * @param[in] RgSchCellCb *cell
2494 * @param[in] RgSchUeCb *ue
2495 * @param[in] RgSchDlLcCb *dlLc
2496 * @param[in] RgrLchCfg *cfg
2497 * @param[in] RgSchErrInfo *err
2501 S16 rgSCHUtlRgrLcCfg(RgSchCellCb *cell,RgSchUeCb *ue,RgSchDlLcCb *dlLc,RgrLchCfg *cfg,RgSchErrInfo *errInfo)
2503 return (cell->sc.apis->rgSCHRgrLchCfg(cell, ue, dlLc, cfg, errInfo));
2508 * @brief This function modifies a service to scheduler
2512 * Function: rgSCHUtlRgrLcRecfg
2513 * Purpose: This function performs modification of a service in
2514 * scheduler. The modification is performed for each direction
2515 * based the direction field of the configuration
2517 * Invoked by: Scheduler
2519 * @param[in] RgSchCellCb *cell
2520 * @param[in] RgSchUeCb *ue
2521 * @param[in] RgSchDlLcCb *dlLc
2522 * @param[in] RgrLchRecfg *recfg
2523 * @param[in] RgSchErrInfo *err
2527 S16 rgSCHUtlRgrLcRecfg(RgSchCellCb *cell,RgSchUeCb *ue,RgSchDlLcCb *dlLc,RgrLchRecfg *recfg,RgSchErrInfo *err)
2529 return (cell->sc.apis->rgSCHRgrLchRecfg(cell, ue, dlLc, recfg, err));
2533 * @brief This function deletes a Lc in scheduler
2537 * Function: rgSCHUtlRgrLcDel
2538 * Purpose: This function performs deletion of Lc in scheduler
2540 * Invoked by: Scheduler
2542 * @param[in] RgSchCellCb *cell
2543 * @param[in] RgSchUeCb *ue
2544 * @param[in] CmLteLcId lcId
2545 * @param[in] uint8_t lcgId
2549 S16 rgSCHUtlRgrLcDel(RgSchCellCb *cell,RgSchUeCb *ue,CmLteLcId lcId,uint8_t lcgId)
2551 cell->sc.apis->rgSCHRgrLchDel(cell, ue, lcId, lcgId);
2554 } /* rgSCHUtlRgrLcDel */
2557 * @brief This function adds a service to scheduler
2561 * Function: rgSCHUtlRgrLcgCfg
2562 * Purpose: This function performs addition of service to scheduler
2563 * The addition is performed for each direction based
2564 * the direction field of the configuration
2566 * Invoked by: Scheduler
2568 * @param[in] RgSchCellCb *cell
2569 * @param[in] RgSchUeCb *ue
2570 * @param[in] RgrLchCfg *cfg
2571 * @param[in] RgSchErrInfo *err
2575 S16 rgSCHUtlRgrLcgCfg(RgSchCellCb *cell,RgSchUeCb *ue,RgrLcgCfg *cfg,RgSchErrInfo *errInfo)
2577 return (cell->sc.apis->rgSCHRgrLcgCfg(cell, ue, &(ue->ul.lcgArr[cfg->ulInfo.lcgId]), cfg, errInfo));
2582 * @brief This function modifies a service to scheduler
2586 * Function: rgSCHUtlRgrLcgRecfg
2587 * Purpose: This function performs modification of a service in
2588 * scheduler. The modification is performed for each direction
2589 * based the direction field of the configuration
2591 * Invoked by: Scheduler
2593 * @param[in] RgSchCellCb *cell
2594 * @param[in] RgSchUeCb *ue
2595 * @param[in] RgrLcgRecfg *recfg
2596 * @param[in] RgSchErrInfo *err
2600 S16 rgSCHUtlRgrLcgRecfg(RgSchCellCb *cell,RgSchUeCb *ue,RgrLcgRecfg *recfg,RgSchErrInfo *err)
2602 return (cell->sc.apis->rgSCHRgrLcgRecfg(cell, ue, &(ue->ul.lcgArr[recfg->ulRecfg.lcgId]), recfg, err));
2603 } /* rgSCHUtlRgrLcRecfg */
2606 * @brief This function modifies a service to scheduler
2610 * Function: rgSCHUtlRgrLcgDel
2611 * Purpose: This function performs modification of a service in
2612 * scheduler. The modification is performed for each direction
2613 * based the direction field of the configuration
2615 * Invoked by: Scheduler
2617 * @param[in] RgSchCellCb *cell
2618 * @param[in] RgSchUeCb *ue
2619 * @param[in] RgrDel *lcDelInfo
2623 Void rgSCHUtlRgrLcgDel(RgSchCellCb *cell,RgSchUeCb *ue,uint8_t lcgId)
2625 cell->sc.apis->rgSCHFreeLcg(cell, ue, &ue->ul.lcgArr[lcgId]);
2627 /* Stack Crash problem for TRACE5 changes. added the return below . */
2630 } /* rgSCHUtlRgrLcgDel */
2633 /* End: LTEMAC_2.1_DEV_CFG */
2636 * @brief This function is a wrapper to call scheduler specific API.
2640 * Function: rgSCHUtlDoaInd
2641 * Purpose: Updates the DOA for the UE
2645 * @param[in] RgSchCellCb *cell
2646 * @param[in] RgSchUeCb *ue
2647 * @param[in] TfuDoaRpt *doaRpt
2651 Void rgSCHUtlDoaInd(RgSchCellCb *cell,RgSchUeCb *ue,TfuDoaRpt *doaRpt)
2653 ue->mimoInfo.doa.pres = PRSNT_NODEF;
2654 ue->mimoInfo.doa.val = doaRpt->doa;
2659 * @brief This function is a wrapper to call scheduler specific API.
2663 * Function: rgSCHUtlDlCqiInd
2664 * Purpose: Updates the DL CQI for the UE
2668 * @param[in] RgSchCellCb *cell
2669 * @param[in] RgSchUeCb *ue
2670 * @param[in] TfuDlCqiRpt *dlCqiRpt
2671 * @param[in] CmLteTimingInfo timingInfo
2675 Void rgSCHUtlDlCqiInd(RgSchCellCb *cell,RgSchUeCb *ue,TfuDlCqiRpt *dlCqiRpt,CmLteTimingInfo timingInfo)
2677 RgSchCellCb *sCellCb = NULLP;
2678 if (dlCqiRpt->isPucchInfo)
2680 sCellCb = ue->cellInfo[dlCqiRpt->dlCqiInfo.pucchCqi.cellIdx]->cell;
2681 sCellCb->sc.apis->rgSCHDlCqiInd(sCellCb, ue, dlCqiRpt->isPucchInfo, \
2682 (Void *)&dlCqiRpt->dlCqiInfo.pucchCqi, timingInfo);
2687 for (idx = 0; idx < dlCqiRpt->dlCqiInfo.pusch.numOfCells; idx++)
2689 sCellCb = ue->cellInfo[dlCqiRpt->dlCqiInfo.pusch.puschCqi[idx].cellIdx]->cell;
2690 sCellCb->sc.apis->rgSCHDlCqiInd(sCellCb, ue, dlCqiRpt->isPucchInfo, \
2691 (Void *)&dlCqiRpt->dlCqiInfo.pusch.puschCqi[idx], timingInfo);
2700 * @brief This function is a wrapper to call scheduler specific API.
2704 * Function: rgSCHUtlSrsInd
2705 * Purpose: Updates the UL SRS for the UE
2709 * @param[in] RgSchCellCb *cell
2710 * @param[in] RgSchUeCb *ue
2711 * @param[in] TfuSrsRpt* srsRpt
2712 * @param[in] CmLteTimingInfo timingInfo
2716 Void rgSCHUtlSrsInd(RgSchCellCb *cell,RgSchUeCb *ue,TfuSrsRpt *srsRpt,CmLteTimingInfo timingInfo)
2718 cell->sc.apis->rgSCHSrsInd(cell, ue, srsRpt, timingInfo);
2724 * @brief This function is a wrapper to call scheduler specific API.
2728 * Function: rgSCHUtlDlTARpt
2729 * Purpose: Reports PHY TA for a UE.
2733 * @param[in] RgSchCellCb *cell
2734 * @param[in] RgSchUeCb *ue
2738 Void rgSCHUtlDlTARpt(RgSchCellCb *cell,RgSchUeCb *ue)
2740 cell->sc.apis->rgSCHDlTARpt(cell, ue);
2746 * @brief This function is a wrapper to call scheduler specific API.
2750 * Function: rgSCHUtlDlRlsSubFrm
2751 * Purpose: Releases scheduler Information from DL SubFrm.
2755 * @param[in] RgSchCellCb *cell
2756 * @param[out] CmLteTimingInfo subFrm
2760 Void rgSCHUtlDlRlsSubFrm(RgSchCellCb *cell,CmLteTimingInfo subFrm)
2762 cell->sc.apis->rgSCHDlRlsSubFrm(cell, subFrm);
2768 * @brief This API is invoked to update the AperCQI trigger
2773 * Function : rgSCHUtlUpdACqiTrigWt
2774 * - If HqFdbk is ACK then add up weight corresponding
2775 * to ACK to the AcqiTrigWt.
2776 * - If HqFdbk is NACK then add up weight corresponding
2777 * to NACK to the AcqiTrigWt.
2778 * - If AcqiTrigWt crosses threshold then trigger
2779 * grant req for APERCQI to SCH.
2781 * @param[in] RgSchUeCb *ue
2782 * @param[in] uint8_t isAck
2786 Void rgSCHUtlUpdACqiTrigWt(RgSchUeCb *ue,RgSchUeCellInfo *cellInfo,uint8_t isAck )
2789 uint8_t triggerSet = 0;
2793 if (isAck == TFU_HQFDB_ACK)
2795 cellInfo->acqiCb.aCqiTrigWt += RG_APER_CQI_ACK_WGT;
2799 cellInfo->acqiCb.aCqiTrigWt += RG_APER_CQI_NACK_WGT;
2802 if (cellInfo->acqiCb.aCqiTrigWt > RG_APER_CQI_THRESHOLD_WGT)
2804 RgSchCellCb *cell = ue->cell;
2805 RgSchErrInfo unUsed;
2807 if(ue->dl.reqForCqi)
2809 /* Already one ACQI trigger procedure is going on
2810 * which is not yet satisfied. Delaying this request till
2811 * the previous is getting satisfied*/
2815 ue->dl.reqForCqi = TRUE;
2817 rgSchCmnSetCqiReqField(cellInfo,ue,&ue->dl.reqForCqi);
2818 //Reset aCqiTrigWt for all the serving cells for which we have triggered ACQI
2819 rgSCHTomUtlGetTrigSet(cell, ue, ue->dl.reqForCqi, &triggerSet);
2820 for (sIdx = 0; sIdx < CM_LTE_MAX_CELLS; sIdx++)
2822 /* The Aperiodic requested for SCell index sIdx */
2823 if ((triggerSet >> (7 - sIdx)) & 0x01)
2825 /* The Aperiodic request for SCell index sIdx */
2826 ue->cellInfo[sIdx]->acqiCb.aCqiTrigWt = 0;
2831 /* Force SCH to send UL grant by indicating fake SR.
2832 * If this UE already in UL SCH Qs this SR Ind will
2834 rgSCHUtlSrRcvd(cell, ue, cell->crntTime, &unUsed);
2842 * @brief This API is invoked to indicate scheduler of a CRC indication.
2846 * Function : rgSCHUtlHdlUlTransInd
2847 * This API is invoked to indicate scheduler of a CRC indication.
2849 * @param[in] RgSchCellCb *cell
2850 * @param[in] RgSchUeCb *ue
2851 * @param[in] CmLteTimingInfo timingInfo
2855 Void rgSCHUtlHdlUlTransInd(RgSchCellCb *cell,RgSchUeCb *ue,CmLteTimingInfo timingInfo)
2857 cell->sc.apis->rgSCHHdlUlTransInd(cell, ue, timingInfo);
2862 * @brief This API is invoked to indicate scheduler of a CRC failure.
2866 * Function : rgSCHUtlHdlCrcInd
2867 * This API is invoked to indicate CRC to scheduler.
2869 * @param[in] RgSchCellCb *cell
2870 * @param[in] RgSchUeCb *ue
2871 * @param[in] CmLteTimingInfo timingInfo
2875 Void rgSCHUtlHdlCrcInd(RgSchCellCb *cell,RgSchUeCb *ue,CmLteTimingInfo timingInfo)
2877 cell->sc.apis->rgSCHUlCrcInd(cell, ue, timingInfo);
2879 } /* end of rgSCHUtlHdlCrcFailInd */
2882 * @brief This API is invoked to indicate scheduler of a CRC failure.
2886 * Function : rgSCHUtlHdlCrcFailInd
2887 * This API is invoked to indicate CRC failure to scheduler.
2889 * @param[in] RgSchCellCb *cell
2890 * @param[in] RgSchUeCb *ue
2891 * @param[in] CmLteTimingInfo timingInfo
2895 Void rgSCHUtlHdlCrcFailInd(RgSchCellCb *cell,RgSchUeCb *ue,CmLteTimingInfo timingInfo)
2897 cell->sc.apis->rgSCHUlCrcFailInd(cell, ue, timingInfo);
2899 } /* end of rgSCHUtlHdlCrcFailInd */
2900 #endif /* LTEMAC_SPS */
2904 * @brief This function is a wrapper to call scheduler specific API.
2908 * Function: rgSCHUtlDlProcAddToRetx
2909 * Purpose: This function adds a HARQ process to retransmission
2910 * queue. This may be performed when a HARQ ack is
2913 * Invoked by: HARQ feedback processing
2915 * @param[in] RgSchCellCb* cell
2916 * @param[in] RgSchDlHqProc* hqP
2920 Void rgSCHUtlDlProcAddToRetx(RgSchCellCb *cell,RgSchDlHqProcCb *hqP)
2922 cell->sc.apis->rgSCHDlProcAddToRetx(cell, hqP);
2928 * @brief This function adds a HARQ process TB to transmission
2932 * Function: rgSCHUtlDlHqPTbAddToTx
2933 * Purpose: This function a HarqProcess TB to the slot
2936 * Invoked by: Scheduler
2938 * @param[in] RgSubFrm* subFrm
2939 * @param[in] RgDlHqProc* hqP
2940 * @param[in] uint8_t tbIdx
2944 Void rgSCHUtlDlHqPTbAddToTx(RgSchDlSf *subFrm,RgSchDlHqProcCb *hqP,uint8_t tbIdx)
2946 RgSchUeCb *ue = NULLP;
2947 RgSchCellCb *cell = hqP->hqE->cell;
2949 /* Addition of UE to dlSf->ueLst shall be done only to UE's PCell */
2950 /* ue->cell will always hold PCell information */
2951 if (NULLP == hqP->hqPSfLnk.node)
2956 if(NULLP == ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk.node)
2958 ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk.node = (PTR)ue;
2959 cmLListAdd2Tail(&cell->subFrms[subFrm->dlIdx]->ueLst,
2960 &ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk);
2962 ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].isPuschHarqRecpPres = FALSE;
2966 /* Add Hq proc in particular dlIdx List for this UE
2967 This list will be used while processing feedback*/
2968 hqP->hqPSfLnk.node = (PTR)hqP;
2969 cmLListAdd2Tail(&ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].hqPLst,&hqP->hqPSfLnk);
2972 uint32_t gSCellSchedCount,gPrimarySchedCount;
2973 if(RG_SCH_IS_CELL_SEC(hqP->hqE->ue,hqP->hqE->cell))
2977 gPrimarySchedCount++;
2981 else if (hqP->hqE->msg4Proc == hqP)
2983 /* Msg4 will be scheduled on PCELL only hence add directly to subFrm msg4HqpList */
2984 hqP->hqPSfLnk.node = (PTR)hqP;
2985 cmLListAdd2Tail(&subFrm->msg4HqPLst, &hqP->hqPSfLnk);
2992 if((ue) && (HQ_TB_WAITING == hqP->tbInfo[tbIdx].state))
2995 ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].totalTbCnt++;
2997 /*totalTbCnt will hold the total number of TBs across all harq Proc from all
3000 hqP->subFrm = subFrm;
3009 * @brief This function removes a HARQ process TB from transmission
3013 * Function: rgSCHUtlDlHqPTbRmvFrmTx
3014 * Purpose: This function removes a HarqProcess TB to the slot
3017 * Invoked by: Scheduler
3019 * @param[in] RgSubFrm* subFrm
3020 * @param[in] RgDlHqProc* hqP
3021 * @param[in] uint8_t tbIdx
3022 * @param[in] Bool isRepeting
3026 Void rgSCHUtlDlHqPTbRmvFrmTx(RgSchDlSf *subFrm,RgSchDlHqProcCb *hqP,uint8_t tbIdx,Bool isRepeting)
3028 RgSchCellCb *cell = NULLP;
3029 /* Check with TDD */
3031 (hqP->hqE->ue->ackNakRepCb.cfgRepCnt !=
3032 hqP->tbInfo[tbIdx].fbkRepCntr))
3034 cmLListDelFrm(&subFrm->ackNakRepQ,
3035 &hqP->tbInfo[tbIdx].anRepLnk[hqP->tbInfo[tbIdx].fbkRepCntr]);
3039 if (NULLP != hqP->hqPSfLnk.node)
3042 if (hqP->hqE->msg4Proc == hqP)
3044 /* Msg4 will be scheduled on PCELL only hence delete directly from subFrm msg4HqpList */
3045 cmLListDelFrm(&subFrm->msg4HqPLst, &hqP->hqPSfLnk);
3049 cell = hqP->hqE->cell;
3050 /* Addition of UE to dlSf->ueLst shall be done only to UE's PCell */
3051 /* ue->cell will always hold PCell information */
3052 cmLListDelFrm(&hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].hqPLst,&hqP->hqPSfLnk);
3053 if (0 == hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].hqPLst.count)
3056 cmLListDelFrm(&cell->subFrms[subFrm->dlIdx]->ueLst,
3057 &hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk);
3058 hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk.node = (PTR)NULLP;
3059 hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].totalTbCnt = 0;
3062 hqP->hqPSfLnk.node = NULLP;
3064 hqP->subFrm = NULLP;
3071 * @brief Handler for accessing the existing SCellCb identified by the key
3072 * SCellId under the CellCb.
3076 * Function : rgSchUtlGetCellCb
3079 * @param[in] *cellCb
3081 * @return RgSchUeCb*
3083 RgSchCellCb* rgSchUtlGetCellCb(Inst inst,uint16_t cellId)
3085 RgSchCellCb *cellCb = NULLP;
3087 strtCellId = rgSchCb[inst].genCfg.startCellId;
3088 cellCb = rgSchCb[inst].cells[cellId - strtCellId];
3092 } /* rgSchUtlGetCellCb */
3095 * @brief Handler for deriving the servCellidx
3099 * Function : rgSchUtlGetServCellIdx
3102 * @param[in] *cellId
3103 * @param[in] RgSchUeCb *ue
3104 * @return uint8_t servCellIdx
3106 uint8_t rgSchUtlGetServCellIdx(Inst inst, uint16_t cellId, RgSchUeCb *ue)
3108 uint8_t servCellIdx;
3109 uint16_t strtCellId;
3111 strtCellId = rgSchCb[inst].genCfg.startCellId;
3112 servCellIdx = ue->cellIdToCellIdxMap[cellId - strtCellId];
3113 return (servCellIdx);
3115 } /* rgSchUtlGetCellCb */
3118 * @brief Handler for validating the Cell Id received secondary Cell Addition
3122 * Function : rgSchUtlGetCellId
3125 * @param[in] *cellCb
3127 * @return RgSchUeCb*
3129 S16 rgSchUtlVldtCellId(Inst inst,uint16_t cellId)
3133 strtCellId = rgSchCb[inst].genCfg.startCellId;
3134 if((cellId >= strtCellId) && ((cellId - strtCellId) < CM_LTE_MAX_CELLS))
3139 } /* rgSchUtlVldtCellId */
3143 * @brief UE reconfiguration for scheduler
3147 * Function : rgSCHUtlRgrUeRecfg
3149 * This functions updates UE specific scheduler
3150 * information upon UE reconfiguration
3152 * @param[in] RgSchCellCb *cell
3153 * @param[in] RgSchUeCb *ue
3154 * @param[int] RgrUeRecfg *ueRecfg
3155 * @param[out] RgSchErrInfo *err
3160 S16 rgSCHUtlRgrUeRecfg(RgSchCellCb *cell,RgSchUeCb *ue,RgrUeRecfg *ueRecfg,RgSchErrInfo *err)
3162 /* Changes for UE Category Reconfiguration feature addition */
3163 RgSchCmnUe *ueSch = RG_SCH_CMN_GET_UE(ue, cell);
3165 /* Changes for UE Category Reconfiguration feature addition */
3166 if (ueRecfg->ueRecfgTypes & RGR_UE_UECAT_RECFG)
3168 ueSch->cmn.ueCat = ueRecfg->ueCatEnum-1;
3170 ue->ueCatEnum = ueRecfg->ueCatEnum;
3174 /* DL MU-MIMO not supported */
3175 if (ueRecfg->ueRecfgTypes & RGR_UE_TXMODE_RECFG)
3178 if (ueRecfg->txMode.pres == PRSNT_NODEF)
3180 if (ueRecfg->txMode.txModeEnum == RGR_UE_TM_5)
3182 err->errCause = RGSCHERR_SCH_CFG;
3186 if(ue->mimoInfo.txMode != ueRecfg->txMode.txModeEnum)
3188 /* Decremnt the previos A value for this cell */
3189 ue->f1bCsAVal -= rgSCHUtlGetMaxTbSupp(ue->mimoInfo.txMode);
3190 /* Update A value with the new TM Mode */
3191 ue->f1bCsAVal += rgSCHUtlGetMaxTbSupp(ueRecfg->txMode.txModeEnum);
3194 DU_LOG("\nINFO --> SCH : UeReCfg A valie is %d\n",ue->f1bCsAVal);
3197 ue->mimoInfo.txMode = ueRecfg->txMode.txModeEnum;
3201 /* [ccpu00123958]-ADD- Check for PUSCH related Reconfig from the bit mask */
3202 if(ueRecfg->ueRecfgTypes & RGR_UE_PUSCH_RECFG)
3204 /* Fix: ccpu00124012 */
3205 /* TODO:: Need to check if this is
3206 mandatory to be re-configured on UE category re-configuration */
3207 /* ue->ul.betaHqOffst = ueRecfg->puschDedCfg.bACKIdx;
3208 ue->ul.betaCqiOffst = ueRecfg->puschDedCfg.bCQIIdx;
3209 ue->ul.betaRiOffst = ueRecfg->puschDedCfg.bRIIdx;*/
3212 if (ueRecfg->ueRecfgTypes & RGR_UE_ULTXANTSEL_RECFG)
3214 ue->ul.ulTxAntSel = ueRecfg->ulTxAntSel;
3216 if (ueRecfg->ueRecfgTypes & RGR_UE_CDBKSBST_RECFG)
3218 ue->mimoInfo.cdbkSbstRstrctn = ueRecfg->ueCodeBookRstRecfg;
3221 /* Commenting here to assign garbage value when it is not set in APP. */
3222 //ue->accessStratumRls = ueRecfg->accessStratumRls;
3223 return (cell->sc.apis->rgSCHRgrUeRecfg(cell, ue, ueRecfg, err));
3224 } /* rgSCHUtlRgrUeRecfg */
3227 * @brief This function deletes a service from scheduler
3231 * Function: rgSCHUtlFreeDlLc
3232 * Purpose: This function is made available through a FP for
3233 * making scheduler aware of a service being deleted from UE
3235 * Invoked by: BO and Scheduler
3237 * @param[in] RgSchCellCb* cell
3238 * @param[in] RgSchUeCb* ue
3239 * @param[in] RgSchDlLcCb* svc
3242 Void rgSCHUtlFreeDlLc(RgSchCellCb *cell,RgSchUeCb *ue,RgSchDlLcCb *svc)
3244 cell->sc.apis->rgSCHFreeDlLc(cell, ue, svc);
3246 /* Stack Crash problem for TRACE5 changes. added the return below . */
3252 * @brief UE deletion for scheduler
3256 * Function : rgSCHUtlFreeUe
3258 * This functions deletes all scheduler information
3259 * pertaining to a UE
3261 * @param[in] RgSchCellCb *cell
3262 * @param[in] RgSchUeCb *ue
3265 Void rgSCHUtlFreeUe(RgSchCellCb *cell,RgSchUeCb *ue)
3268 rgSCHUtlDelUeANFdbkInfo(ue,RGSCH_PCELL_INDEX);
3270 cell->sc.apis->rgSCHFreeUe(cell, ue);
3272 /* Stack Crash problem for TRACE5 changes. added the return below . */
3275 } /* rgSCHUtlFreeUe */
3278 * @brief This function updates the scheduler with service for a UE
3282 * Function: rgSCHUtlDlDedBoUpd
3283 * Purpose: This function should be called whenever there is a
3284 * change BO for a service.
3286 * Invoked by: BO and Scheduler
3288 * @param[in] RgSchCellCb* cell
3289 * @param[in] RgSchUeCb* ue
3290 * @param[in] RgSchDlLcCb* lc
3293 Void rgSCHUtlDlDedBoUpd(RgSchCellCb *cell,RgSchUeCb *ue,RgSchDlLcCb *lc)
3295 cell->sc.apis->rgSCHDlDedBoUpd(cell, ue, lc);
3299 * @brief Record MSG3 allocation into the UE
3303 * Function : rgSCHUtlRecMsg3Alloc
3305 * This function is invoked to update record msg3 allocation information
3306 * in the UE when UE is detected for RaCb
3308 * @param[in] RgSchCellCb *cell
3309 * @param[in] RgSchUeCb *ue
3310 * @param[in] RgSchRaCb *raCb
3313 Void rgSCHUtlRecMsg3Alloc(RgSchCellCb *cell,RgSchUeCb *ue,RgSchRaCb *raCb)
3315 cell->sc.apis->rgSCHUlRecMsg3Alloc(cell, ue, raCb);
3318 } /* rgSCHRecMsg3Alloc */
3322 * @brief Update harq process for allocation
3326 * Function : rgSCHUtlUpdUlHqProc
3328 * This function is invoked when harq process
3329 * control block is now in a new memory location
3330 * thus requiring a pointer/reference update.
3332 * @param[in] RgSchCellCb *cell
3333 * @param[in] RgSchUlHqProcCb *curProc
3334 * @param[in] RgSchUlHqProcCb *oldProc
3339 S16 rgSCHUtlUpdUlHqProc(RgSchCellCb *cell,RgSchUlHqProcCb *curProc,RgSchUlHqProcCb *oldProc)
3341 return (cell->sc.apis->rgSCHUpdUlHqProc(cell, curProc, oldProc));
3342 } /* rgSCHUtlUpdUlHqProc */
3345 * @brief UL grant for contention resolution
3349 * Function : rgSCHUtlContResUlGrant
3351 * Add UE to another queue specifically for CRNTI based contention
3354 * @param[in] RgSchCellCb *cell
3355 * @param[in] RgSchUeCb *ue
3356 * @param[out] RgSchErrInfo *err
3361 S16 rgSCHUtlContResUlGrant(RgSchCellCb *cell,RgSchUeCb *ue,RgSchErrInfo *err)
3364 ue->isMsg4PdcchWithCrnti = TRUE;
3365 return (cell->sc.apis->rgSCHContResUlGrant(cell, ue, err));
3366 } /* rgSCHUtlContResUlGrant */
3369 * @brief SR reception handling
3373 * Function : rgSCHUtlSrRcvd
3375 * - Handles SR reception for UE
3377 * @param[in] RgSchCellCb *cell
3378 * @param[in] RgSchUeCb *ue
3379 * @param[out] RgSchErrInfo *err
3384 S16 rgSCHUtlSrRcvd(RgSchCellCb *cell,RgSchUeCb *ue,CmLteTimingInfo frm,RgSchErrInfo *err)
3386 return (cell->sc.apis->rgSCHSrRcvd(cell, ue, frm, err));
3387 } /* rgSCHUtlSrRcvd */
3390 * @brief Short BSR update
3394 * Function : rgSCHUtlUpdBsrShort
3396 * This functions does requisite updates to handle short BSR reporting
3398 * @param[in] RgSchCellCb *cell
3399 * @param[in] RgSchUeCb *ue
3400 * @param[in] uint8_t lcgId
3401 * @param[in] uint8_t bsr
3402 * @param[out] RgSchErrInfo *err
3407 Void rgSCHUtlUpdBsrShort(RgSchCellCb *cell,RgSchUeCb *ue,uint8_t lcgId,uint8_t bsr,RgSchErrInfo *err)
3409 cell->sc.apis->rgSCHUpdBsrShort(cell, ue, &ue->ul.lcgArr[lcgId], bsr, err);
3411 } /* rgSCHUtlUpdBsrShort */
3415 * @brief Truncated BSR update
3419 * Function : rgSCHUtlUpdBsrTrunc
3421 * This functions does required updates to handle truncated BSR report
3424 * @param[in] RgSchCellCb *cell
3425 * @param[in] RgSchUeCb *ue
3426 * @param[in] uint8_t lcgId
3427 * @param[in] uint8_t bsr
3428 * @param[out] RgSchErrInfo *err
3433 Void rgSCHUtlUpdBsrTrunc(RgSchCellCb *cell,RgSchUeCb *ue,uint8_t lcgId,uint8_t bsr,RgSchErrInfo *err)
3435 cell->sc.apis->rgSCHUpdBsrTrunc(cell, ue, &ue->ul.lcgArr[lcgId], bsr, err);
3437 } /* rgSCHUtlUpdBsrTrunc */
3441 * @brief Long BSR update
3445 * Function : rgSCHUtlUpdBsrLong
3447 * - Update BSRs for all configured LCGs
3448 * - Update priority of LCGs if needed
3449 * - Update UE's position within/across uplink scheduling queues
3452 * @param[in] RgSchCellCb *cell
3453 * @param[in] RgSchUeCb *ue
3454 * @param[in] uint8_t bsr0
3455 * @param[in] uint8_t bsr1
3456 * @param[in] uint8_t bsr2
3457 * @param[in] uint8_t bsr3
3458 * @param[out] RgSchErrInfo *err
3463 Void rgSCHUtlUpdBsrLong(RgSchCellCb *cell,RgSchUeCb *ue,uint8_t bsr0,uint8_t bsr1,uint8_t bsr2,uint8_t bsr3,RgSchErrInfo *err)
3470 cell->sc.apis->rgSCHUpdBsrLong(cell, ue, bsArr, err);
3472 } /* rgSCHUtlUpdBsrLong */
3475 * @brief EXT PHR update
3479 * Function : rgSCHUtlUpdExtPhr
3481 * Updates extended power headroom info for a UE
3483 * @param[in] RgSchCellCb *cell
3484 * @param[in] RgSchUeCb *ue
3485 * @param[in] uint8_t phr
3486 * @param[out] RgSchErrInfo *err
3491 S16 rgSCHUtlUpdExtPhr(RgSchCellCb *cell,RgSchUeCb *ue,RgInfExtPhrCEInfo *extPhr,RgSchErrInfo *err)
3493 return (cell->sc.apis->rgSCHUpdExtPhr(cell, ue, extPhr, err));
3494 } /* rgSCHUtlUpdExtPhr */
3503 * Function : rgSCHUtlUpdPhr
3505 * Updates power headroom info for a UE
3507 * @param[in] RgSchCellCb *cell
3508 * @param[in] RgSchUeCb *ue
3509 * @param[in] uint8_t phr
3510 * @param[out] RgSchErrInfo *err
3515 S16 rgSCHUtlUpdPhr(RgSchCellCb *cell,RgSchUeCb *ue,uint8_t phr,RgSchErrInfo *err)
3517 return (cell->sc.apis->rgSCHUpdPhr(cell, ue, phr, err));
3518 } /* rgSCHUtlUpdPhr */
3522 * @brief Indication of UL CQI
3526 * Function : rgSCHUtlUlCqiInd
3528 * - Updates uplink CQI information for the UE. Computes and
3529 * stores the lowest CQI of CQIs reported in all subbands
3531 * @param[in] RgSchCellCb *cell
3532 * @param[in] RgSchUeCb *ue
3533 * @param[in] TfuUlCqiRpt *ulCqiInfo
3536 Void rgSCHUtlUlCqiInd(RgSchCellCb *cell,RgSchUeCb *ue,TfuUlCqiRpt *ulCqiInfo)
3538 cell->sc.apis->rgSCHUlCqiInd(cell, ue, ulCqiInfo);
3540 } /* rgSCHUtlUlCqiInd */
3543 * @brief Indication of PUCCH power adjustment
3547 * Function : rgSCHUtlPucchDeltaPwrInd
3549 * - Updates uplink CQI information for the UE. Computes and
3550 * stores the lowest CQI of CQIs reported in all subbands
3552 * @param[in] RgSchCellCb *cell
3553 * @param[in] RgSchUeCb *ue
3554 * @param[in] uint8_t delta
3557 Void rgSCHUtlPucchDeltaPwrInd(RgSchCellCb *cell,RgSchUeCb *ue,S8 delta)
3559 cell->sc.apis->rgSCHPucchDeltaPwrInd(cell, ue, delta);
3561 } /* rgSCHUtlPucchDeltaPwrInd */
3563 /* Start: LTEMAC_2.1_DEV_CFG */
3565 * @brief Ue Reset Request
3569 * Function : rgSCHUtlUeReset
3572 * @param[in] RgSchCellCb *cell
3573 * @param[in] RgSchUeCb *ue
3576 Void rgSCHUtlUeReset(RgSchCellCb *cell,RgSchUeCb *ue)
3579 cell->sc.apis->rgSCHUeReset(cell, ue);
3581 } /* rgSCHUtlUeReset */
3582 /* End: LTEMAC_2.1_DEV_CFG */
3585 * @brief Returns HARQ proc for which data expected now
3589 * Function: rgSCHUtlUlHqProcForUe
3590 * Purpose: This function returns the harq process for
3591 * which data is expected in the current slot.
3592 * It does not validate if the HARQ process
3593 * has an allocation.
3597 * @param[in] RgSchCellCb *cell
3598 * @param[in] CmLteTimingInfo frm
3599 * @param[in] RgSchUeCb *ue
3600 * @param[out] RgSchUlHqProcCb **procRef
3603 Void rgSCHUtlUlHqProcForUe(RgSchCellCb *cell,CmLteTimingInfo frm,RgSchUeCb *ue,RgSchUlHqProcCb **procRef)
3605 cell->sc.apis->rgSCHUlHqProcForUe(cell, frm, ue, procRef);
3607 /* Stack Crash problems for TRACE5 changes. added the return below */
3613 * @brief Returns first uplink allocation to send reception
3618 * Function: rgSCHUtlFirstRcptnReq(cell)
3619 * Purpose: This function returns the first uplink allocation
3620 * (or NULLP if there is none) in the slot
3621 * in which is expected to prepare and send reception
3626 * @param[in] RgSchCellCb *cell
3627 * @return RgSchUlAlloc*
3629 RgSchUlAlloc *rgSCHUtlFirstRcptnReq(RgSchCellCb *cell)
3631 return (cell->sc.apis->rgSCHFirstRcptnReq(cell));
3635 * @brief Returns first uplink allocation to send reception
3640 * Function: rgSCHUtlNextRcptnReq(cell)
3641 * Purpose: This function returns the next uplink allocation
3642 * (or NULLP if there is none) in the slot
3643 * in which is expected to prepare and send reception
3648 * @param[in] RgSchCellCb *cell
3649 * @return RgSchUlAlloc*
3651 RgSchUlAlloc *rgSCHUtlNextRcptnReq(RgSchCellCb *cell,RgSchUlAlloc *alloc)
3653 return (cell->sc.apis->rgSCHNextRcptnReq(cell, alloc));
3657 * @brief Returns first uplink allocation to send HARQ feedback
3662 * Function: rgSCHUtlFirstHqFdbkAlloc
3663 * Purpose: This function returns the first uplink allocation
3664 * (or NULLP if there is none) in the slot
3665 * in which it is expected to prepare and send HARQ
3670 * @param[in] RgSchCellCb *cell
3671 * @param[in] uint8_t idx
3672 * @return RgSchUlAlloc*
3674 RgSchUlAlloc *rgSCHUtlFirstHqFdbkAlloc(RgSchCellCb *cell,uint8_t idx)
3676 return (cell->sc.apis->rgSCHFirstHqFdbkAlloc(cell, idx));
3681 * @brief Returns next allocation to send HARQ feedback for
3685 * Function: rgSCHUtlNextHqFdbkAlloc(cell)
3686 * Purpose: This function returns the next uplink allocation
3687 * (or NULLP if there is none) in the slot
3688 * for which HARQ feedback needs to be sent.
3692 * @param[in] RgSchCellCb *cell
3693 * @return RgSchUlAlloc*
3695 RgSchUlAlloc *rgSCHUtlNextHqFdbkAlloc(RgSchCellCb *cell,RgSchUlAlloc *alloc,uint8_t idx)
3697 return (cell->sc.apis->rgSCHNextHqFdbkAlloc(cell, alloc, idx));
3700 /***********************************************************
3702 * Func : rgSCHUtlResetSfAlloc
3704 * Desc : Utility Function to Reset slot allocation information.
3713 **********************************************************/
3714 S16 rgSCHUtlResetSfAlloc(RgInfSfAlloc *sfAlloc,Bool resetCmnLcInfo,Bool restAlloc)
3716 if(TRUE == restAlloc)
3718 if(sfAlloc->ueInfo.numUes)
3720 memset(sfAlloc->ueInfo.allocInfo,0x00,
3721 (sizeof(RgInfUeAlloc)*sfAlloc->ueInfo.numUes));
3723 sfAlloc->ueInfo.numUes = 0;
3724 sfAlloc->rarInfo.numRaRntis = 0;
3725 sfAlloc->flowCntrlInfo.numUes = 0;
3727 if(TRUE == resetCmnLcInfo)
3729 sfAlloc->cmnLcInfo.bitMask = 0;
3734 /***********************************************************
3736 * Func : rgSCHUtlGetRlsHqAlloc
3738 * Desc : Utility Function to Allocate slot allocation information.
3747 **********************************************************/
3748 S16 rgSCHUtlGetRlsHqAlloc(RgSchCellCb *cell)
3751 Inst inst = cell->instIdx;
3752 for(idx=0; idx < RGSCH_NUM_SUB_FRAMES; idx++)
3754 cell->rlsHqArr[idx].cellId = cell->cellId;
3756 /* Allocating with additional location, to accommodate
3757 TA scheduling along with maximum no of UEs per SF */
3759 /* Allocate memory for "scheduled UE" Info */
3760 if((rgSCHUtlAllocSBuf(inst,
3761 (Data**)&(cell->rlsHqArr[idx].ueHqInfo),
3762 (sizeof(RgInfUeHqInfo)*RGSCH_MAX_UE_PER_DL_SF))) != ROK)
3764 DU_LOG("\nERROR --> SCH : Memory allocation FAILED for "
3774 /***********************************************************
3776 * Func : rgSCHUtlPutRlsHqAlloc
3778 * Desc : Utility Function to deallocate slot allocation information.
3787 **********************************************************/
3788 S16 rgSCHUtlPutRlsHqAlloc(RgSchCellCb *cell)
3791 Inst inst = cell->instIdx;
3793 for(idx=0; idx < RGSCH_NUM_SUB_FRAMES; idx++)
3795 /* Deallocate memory for "scheduled UE" Info */
3796 if (cell->rlsHqArr[idx].ueHqInfo != NULLP)
3798 /* Freeing with additional location, to accommodate TA
3799 scheduling along with maximum no of UEs per SF */
3800 /* ccpu00117052 - MOD - Passing double pointer
3801 for proper NULLP assignment*/
3802 rgSCHUtlFreeSBuf(inst,
3803 (Data **)(&(cell->rlsHqArr[idx].ueHqInfo)),
3804 (sizeof(RgInfUeHqInfo)*RGSCH_MAX_UE_PER_DL_SF));
3813 /***********************************************************
3815 * Func : rgSCHUtlGetSfAlloc
3817 * Desc : Utility Function to Allocate slot allocation information.
3826 **********************************************************/
3827 S16 rgSCHUtlGetSfAlloc(RgSchCellCb *cell)
3831 Inst inst = cell->instIdx;
3832 RgSchCmnUlCell *cellUl = RG_SCH_CMN_GET_UL_CELL(cell);
3835 for(idx=0; idx < RGSCH_SF_ALLOC_SIZE; idx++)
3837 for(idx=0; idx < RGSCH_NUM_SUB_FRAMES; idx++)
3840 cell->sfAllocArr[idx].cellId = cell->cellId;
3842 /* Allocating with additional location, to accommodate
3843 TA scheduling along with maximum no of UEs per SF */
3845 /* Allocate memory for "scheduled UE" Info */
3846 if((rgSCHUtlAllocSBuf(inst,
3847 (Data**)&(cell->sfAllocArr[idx].ueInfo.allocInfo),
3848 (sizeof(RgInfUeAlloc)*RGSCH_MAX_UE_PER_DL_SF))) != ROK)
3850 DU_LOG("\nERROR --> SCH : Memory allocation FAILED for "
3855 /* Allocate memory for "scheduled RAR" Info */
3856 if((rgSCHUtlAllocSBuf(inst,
3857 (Data**)&(cell->sfAllocArr[idx].rarInfo.raRntiInfo),
3858 (sizeof(RgInfRaRntiInfo)*RGSCH_MAX_RARNTI_PER_DL_SF))) != ROK)
3860 DU_LOG("\nERROR --> SCH : Memory allocation FAILED for "
3864 for(indx = 0; indx < RGSCH_MAX_RARNTI_PER_DL_SF; indx++)
3866 if((rgSCHUtlAllocSBuf(inst,
3867 (Data**)&(cell->sfAllocArr[idx].rarInfo.raRntiInfo[indx].crntiInfo),
3868 (sizeof(RgInfCrntiInfo)* (cellUl->maxMsg3PerUlSf)))) != ROK)
3870 DU_LOG("\nERROR --> SCH : Memory allocation FAILED for "
3879 rgSCHEmtcUtlGetSfAlloc(cell);
3886 /***********************************************************
3888 * Func : rgSCHUtlPutSfAlloc
3890 * Desc : Utility Function to deallocate slot allocation information.
3899 **********************************************************/
3900 S16 rgSCHUtlPutSfAlloc(RgSchCellCb *cell)
3904 Inst inst = cell->instIdx;
3905 RgSchCmnUlCell *cellUl = RG_SCH_CMN_GET_UL_CELL(cell);
3908 for(idx=0; idx < RGSCH_SF_ALLOC_SIZE; idx++)
3910 for(idx=0; idx < RGSCH_NUM_SUB_FRAMES; idx++)
3913 if (cell->sfAllocArr[idx].rarInfo.raRntiInfo != NULLP)
3915 for(indx = 0; indx < RGSCH_MAX_RARNTI_PER_DL_SF; indx++)
3917 if (cell->sfAllocArr[idx].rarInfo.raRntiInfo[indx].crntiInfo != NULLP)
3918 /* ccpu00117052 - MOD - Passing double pointer
3919 for proper NULLP assignment*/
3920 rgSCHUtlFreeSBuf(inst,
3921 (Data**)(&(cell->sfAllocArr[idx].rarInfo.raRntiInfo[indx].\
3923 (sizeof(RgInfCrntiInfo)* (cellUl->maxMsg3PerUlSf)));
3925 /* Deallocate memory for "scheduled RAR" Info */
3926 /* ccpu00117052 - MOD - Passing double pointer
3927 for proper NULLP assignment*/
3928 rgSCHUtlFreeSBuf(inst,
3929 (Data**)(&(cell->sfAllocArr[idx].rarInfo.raRntiInfo)),
3930 (sizeof(RgInfRaRntiInfo)*RGSCH_MAX_RARNTI_PER_DL_SF));
3932 /* Deallocate memory for "scheduled UE" Info */
3933 if (cell->sfAllocArr[idx].ueInfo.allocInfo != NULLP)
3935 /* Freeing with additional location, to accommodate TA
3936 scheduling along with maximum no of UEs per SF */
3937 /* ccpu00117052 - MOD - Passing double pointer
3938 for proper NULLP assignment*/
3939 rgSCHUtlFreeSBuf(inst,
3940 (Data**)(&(cell->sfAllocArr[idx].ueInfo.allocInfo)),
3941 (sizeof(RgInfUeAlloc)*RGSCH_MAX_UE_PER_DL_SF));
3946 rgSCHEmtcUtlPutSfAlloc(cell);
3952 /***********************************************************
3954 * Func : rgSCHUtlAllocSBuf
3956 * Desc : Utility Function to Allocate static buffer.
3957 * Memory allocated is assumed contiguous.
3963 * Notes: Caller doesnt need to raise the alarm in case of memory
3964 * allocation gets failed.
3968 **********************************************************/
3969 S16 rgSCHUtlAllocSBuf
3971 Inst inst, /* Instance of the invoking scheduler */
3972 Data **pData, /* Pointer of the data to be returned */
3973 Size size /* size */
3976 /* Moving alarm diagnostics to available scope */
3978 /* Initialize the param to NULLP */
3981 /* May not be necessary for data performance path */
3989 /* allocate buffer */
3990 #ifdef MS_MBUF_CORRUPTION /* Should be enabled when debugging mbuf corruption */
3991 MS_BUF_ADD_ALLOC_CALLER();
3993 SCH_ALLOC(pData, size);
3996 RgUstaDgn dgn; /* Alarm diagnostics structure */
3997 dgn.type = LRG_USTA_DGNVAL_MEM;
3998 dgn.u.mem.region = rgSchCb[inst].rgSchInit.region;
3999 dgn.u.mem.pool = rgSchCb[inst].rgSchInit.pool;
4000 /* Send an alarm to Layer Manager */
4001 rgSCHLmmStaInd(inst, LCM_CATEGORY_RESOURCE, LCM_EVENT_SMEM_ALLOC_FAIL,
4002 LCM_CAUSE_MEM_ALLOC_FAIL, &dgn);
4003 DU_LOG("\nERROR --> SCH : Unable to Allocate the Buffer");
4008 /* zero out the allocated memory */
4009 memset(*pData, 0x00, size);
4013 } /* end of rgSCHUtlAllocSBuf */
4018 * Fun: rgSCHUtlFreeSBuf
4020 * Desc: The argument to rgSCHUtlFreeSBuf() is a pointer to a block
4021 * previously allocated by rgSCHUtlAllocSBuf() and size. It
4022 * deallocates the memory.
4029 Void rgSCHUtlFreeSBuf
4031 Inst inst, /* Instance of the invoking scheduler */
4032 Data **data, /* pointer to data */
4033 Size size /* size */
4037 if ((data == NULLP) || (*data == NULLP) || (size == 0))
4043 #ifdef MS_MBUF_CORRUPTION /* Should be enabled when debugging mbuf corruption */
4044 MS_BUF_ADD_CALLER();
4046 /* Deallocate buffer */
4047 SCH_FREE((*data), size);
4051 DU_LOG("\nERROR --> SCH : rgSCHUtlFreeSBuf failed");
4055 /* ccpu00117052 - ADD - Assigning the pointer to NULLP */
4059 } /* end of rgSCHUtlFreeSBuf */
4065 * Fun: rgSCHUtlFreeWarningSiSeg
4067 * Desc: This is used to deallocate Warning SI Seg.
4075 Void rgSCHUtlFreeWarningSiSeg(Region reg,Pool pool,CmLListCp *siPduLst)
4080 while (siPduLst->first != NULLP)
4082 node = siPduLst->first;
4083 pdu = (Buffer *)node->node;
4084 cmLListDelFrm(siPduLst, node);
4085 RGSCH_FREE_MSG(pdu);
4086 SCH_FREE(node,sizeof(CmLList));
4091 } /* end of rgSCHUtlFreeWarningSiSeg */
4096 * Fun: rgSCHUtlFreeWarningSiPdu
4098 * Desc: This is used to deallocate Warning SI PDU.
4106 Void rgSCHUtlFreeWarningSiPdu(RgSchCellCb *cell)
4110 RgSchWarningSiInfo *warningSi;
4111 RgSchWarningSiPdu *warningSiPdu;
4113 warningSi = (RgSchWarningSiInfo *) cell->siCb.\
4114 siArray[cell->siCb.siCtx.siId-1].si;
4115 /* ccpu00136659: CMAS ETWS design changes */
4116 CM_LLIST_FIRST_NODE(&warningSi->warningSiMsg.segLstCp, node);
4122 warningSiPdu = (RgSchWarningSiPdu *)node->node;
4123 pdu = warningSiPdu->pdu;
4124 /* ccpu00136659: CMAS ETWS design changes */
4125 cmLListDelFrm(&warningSi->warningSiMsg.segLstCp, node);
4126 RGSCH_FREE_MSG(pdu);
4127 if(warningSi->warningSiMsg.segLstCp.count == 0)
4129 /* ccpu00136659: CMAS ETWS design changes */
4130 cell->siCb.siArray[cell->siCb.siCtx.siId-1].si = NULLP;
4131 rgSCHUtlRgrWarningSiCfgCfm(cell->instIdx,
4132 rgSchCb[cell->instIdx].rgrSap->sapCfg.spId,
4133 cell->siCb.warningSi[warningSi->idx].siId,
4134 warningSi->warningSiMsg.transId, RGR_CFG_CFM_TX_COMPLETE);
4139 } /* end of rgSCHUtlFreeWarningSiPdu */
4144 * Fun: rgSCHUtlGetWarningSiPdu
4146 * Desc: This is used to get Warning SI PDU for Scheduling.
4154 Buffer *rgSCHUtlGetWarningSiPdu(RgSchCellCb *cell)
4156 RgSchWarningSiInfo *warningSi;
4157 RgSchWarningSiPdu *warningSiPdu;
4161 warningSi = (RgSchWarningSiInfo *) cell->siCb.
4162 siArray[cell->siCb.siCtx.siId-1].si;
4163 /* ccpu00136659: CMAS ETWS design changes */
4164 CM_LLIST_FIRST_NODE(&warningSi->warningSiMsg.segLstCp, node);
4167 warningSiPdu = (RgSchWarningSiPdu *)node->node;
4168 pdu = warningSiPdu->pdu;
4175 } /* rgSCHUtlGetWarningSiPdu */
4180 * Fun: rgSCHUtlGetMcsAndNPrb
4182 * Desc: This is used to get mcs and nPrb value.
4190 S16 rgSCHUtlGetMcsAndNPrb(RgSchCellCb *cell,uint8_t *nPrb,uint8_t *mcs,MsgLen *msgLen)
4192 RgSchWarningSiInfo *warningSi;
4193 RgSchWarningSiPdu *warningSiPdu;
4196 if(cell->siCb.siCtx.warningSiFlag == FALSE)
4198 *mcs = cell->siCb.crntSiInfo.siInfo[cell->siCb.siCtx.siId-1].mcs;
4199 *nPrb = cell->siCb.crntSiInfo.siInfo[cell->siCb.siCtx.siId-1].nPrb;
4200 *msgLen = cell->siCb.crntSiInfo.siInfo[cell->siCb.siCtx.siId-1].msgLen;
4204 warningSi = (RgSchWarningSiInfo *) cell->siCb.
4205 siArray[cell->siCb.siCtx.siId-1].si;
4206 /* ccpu00136659: CMAS ETWS design changes */
4207 CM_LLIST_FIRST_NODE(&warningSi->warningSiMsg.segLstCp, node);
4213 warningSiPdu = (RgSchWarningSiPdu *)node->node;
4214 *mcs = warningSiPdu->mcs;
4215 *nPrb = warningSiPdu->nPrb;
4216 *msgLen = warningSiPdu->msgLen;
4221 } /* rgSCHUtlGetMcsAndNPrb */
4225 * Fun: rgSCHUtlCalMacAndPrb
4227 * Desc: This is used to Calculate mcs and nPrb value for SIB1 and SIs.
4235 S16 rgSCHUtlCalMcsAndNPrb(RgSchCellCb *cell,uint8_t cfgType,MsgLen msgLen,uint8_t siId)
4240 /*Get the nPrb and mcs parametr values */
4241 if (rgSCHUtlGetAllwdCchTbSz(msgLen*8, &nPrb, &mcs) != (msgLen*8))
4243 DU_LOG("\nERROR --> SCH : msgLen does "
4244 "not match any valid TB Size");
4249 if(cfgType == RGR_SI_CFG_TYPE_SIB1 || cfgType == RGR_SI_CFG_TYPE_SIB1_PWS)
4252 if(cell->siCb.crntSiInfo.sib1Info.sib1 == NULLP)
4254 cell->siCb.crntSiInfo.sib1Info.mcs = mcs;
4255 cell->siCb.crntSiInfo.sib1Info.nPrb = nPrb;
4256 cell->siCb.crntSiInfo.sib1Info.msgLen = msgLen;
4260 cell->siCb.newSiInfo.sib1Info.mcs = mcs;
4261 cell->siCb.newSiInfo.sib1Info.nPrb= nPrb;
4262 cell->siCb.newSiInfo.sib1Info.msgLen = msgLen;
4267 if(cfgType == RGR_SI_CFG_TYPE_SI)
4269 if(cell->siCb.crntSiInfo.siInfo[siId-1].si == NULLP &&
4270 !(cell->siCb.siBitMask & RGSCH_SI_SICFG_UPD))
4272 cell->siCb.crntSiInfo.siInfo[siId-1].mcs = mcs;
4273 cell->siCb.crntSiInfo.siInfo[siId-1].nPrb = nPrb;
4274 cell->siCb.crntSiInfo.siInfo[siId-1].msgLen = msgLen;
4278 cell->siCb.newSiInfo.siInfo[siId-1].mcs = mcs;
4279 cell->siCb.newSiInfo.siInfo[siId-1].nPrb= nPrb;
4280 cell->siCb.newSiInfo.siInfo[siId-1].msgLen = msgLen;
4284 if(cfgType == RGR_SI_CFG_TYPE_SIB8_CDMA)
4286 cell->siCb.crntSiInfo.siInfo[siId-1].mcs = mcs;
4287 cell->siCb.crntSiInfo.siInfo[siId-1].nPrb = nPrb;
4288 cell->siCb.crntSiInfo.siInfo[siId-1].msgLen = msgLen;
4295 /***********************************************************
4297 * Func : rgSCHUtlFillDgnParams
4299 * Desc : Utility Function to Fill Diagonostic params.
4307 **********************************************************/
4308 Void rgSCHUtlFillDgnParams(Inst inst,RgUstaDgn *dgn,uint8_t dgnType)
4313 case LRG_USTA_DGNVAL_MEM:
4314 dgn->type = (uint8_t) LRG_USTA_DGNVAL_MEM;
4315 dgn->u.mem.region = rgSchCb[inst].rgSchInit.region;
4316 dgn->u.mem.pool = rgSchCb[inst].rgSchInit.pool;
4324 } /* end of rgSCHUtlFillDgnParams */
4326 /***********************************************************
4328 * Func : rgSCHUtlGetPstToLyr
4330 * Desc : Utility Function to get the pst structure to post a message to MAC
4336 * Notes: This function should be called while sending a msg from
4337 * scheduler instance to MAC
4341 **********************************************************/
4342 Void rgSCHUtlGetPstToLyr(Pst *pst,RgSchCb *schCb,Inst macInst)
4345 /* Only the needed params are filled */
4346 pst->region = schCb->rgSchInit.region;
4347 pst->pool = schCb->rgSchInit.pool;
4348 pst->srcInst = schCb->rgSchInit.inst+SCH_INST_START;
4349 pst->srcProcId = schCb->rgSchInit.procId;
4350 pst->dstProcId = schCb->rgSchInit.procId;
4352 pst->dstInst = macInst;
4353 pst->dstEnt = ENTMAC;
4354 pst->srcEnt = ENTMAC;
4356 pst->prior = PRIOR0;
4358 pst->route = RTESPEC;
4361 } /* end of rgSCHUtlGetPstToLyr */
4363 /** @brief This function fills in the common lc information to be sent to MAC
4367 * Function: rgSCHUtlFillRgInfCmnLcInfo
4368 * @param RgSchDlSf *sf,
4369 * @param RgInfSfAlloc *sfAlloc,
4370 * @param CmLteLcId lcId,
4371 * @param Bool sendInd
4377 S16 rgSCHUtlFillRgInfCmnLcInfo(RgSchDlSf *sf,RgInfSfAlloc *sfAlloc,CmLteLcId lcId,Bool sendInd)
4380 if((sf->bch.tbSize)&&
4381 !(sfAlloc->cmnLcInfo.bitMask & RGINF_BCH_INFO))
4384 sfAlloc->cmnLcInfo.bchInfo.lcId = lcId;
4386 sfAlloc->cmnLcInfo.bitMask |= RGINF_BCH_INFO;
4388 else if((sf->bcch.pdcch != NULLP)&&
4389 !(sfAlloc->cmnLcInfo.bitMask & RGINF_BCCH_INFO))
4391 sfAlloc->cmnLcInfo.bcchInfo.rnti = RGSCH_SI_RNTI;
4392 rgSCHUtlFillPdschDciInfo(&(sfAlloc->cmnLcInfo.bcchInfo.dciInfo),
4393 &(sf->bcch.pdcch->dci));
4395 sfAlloc->cmnLcInfo.bcchInfo.lcId = lcId;
4396 sfAlloc->cmnLcInfo.bcchInfo.sndStatInd = sendInd;
4398 sfAlloc->cmnLcInfo.bitMask |= RGINF_BCCH_INFO;
4400 else if((sf->pcch.pdcch != NULLP) &&
4401 !(sfAlloc->cmnLcInfo.bitMask & RGINF_PCCH_INFO))
4403 sfAlloc->cmnLcInfo.pcchInfo.rnti = RGSCH_P_RNTI;
4404 rgSCHUtlFillPdschDciInfo(&(sfAlloc->cmnLcInfo.pcchInfo.dciInfo),
4405 &(sf->pcch.pdcch->dci));
4406 sfAlloc->cmnLcInfo.pcchInfo.lcId = lcId;
4407 sfAlloc->cmnLcInfo.bitMask |= RGINF_PCCH_INFO;
4412 /** @brief This function fills in the RAR information to be sent to MAC
4416 * Function: rgSCHUtlFillRgInfRarInfo
4418 * @param RgSchCellCb *cell
4419 * @param RgSchDlSf *sf
4420 * @param RgInfSfAlloc *sfAlloc
4425 S16 rgSCHUtlFillRgInfRarInfo(RgSchDlSf *sf,RgInfSfAlloc *sfAlloc,RgSchCellCb *cell)
4432 RgInfRaRntiInfo *raRntiAlloc;
4434 RgSchCmnDlCell *cellDl = RG_SCH_CMN_GET_DL_CELL(cell);
4437 noRaRsps = RGSCH_MAX_TDD_RA_RSP_ALLOC;
4439 noRaRsps = RGSCH_MAX_RA_RSP_ALLOC;
4442 for(idx =0; idx < noRaRsps; idx++)
4444 if (sf->raRsp[idx].pdcch == NULLP)
4446 /* No further raResp Allocations. */
4449 /* Added Dl TB count for RACH Response transmission*/
4451 cell->dlUlTbCnt.tbTransDlTotalCnt++;
4453 raRntiAlloc = &(sfAlloc->rarInfo.raRntiInfo[idx]);
4454 raRntiAlloc->raRnti = sf->raRsp[idx].raRnti;
4455 raRntiAlloc->schdTbSz = sf->raRsp[idx].tbSz;
4456 raRntiAlloc->numCrnti = 0;
4457 rgSCHUtlFillPdschDciInfo(&(raRntiAlloc->dciInfo),
4458 &(sf->raRsp[idx].pdcch->dci));
4459 /* RACHO : fill backoff indicator information */
4460 raRntiAlloc->backOffInd = sf->raRsp[idx].backOffInd;
4462 /* Fill for contention free UEs*/
4463 lnkLst = &(sf->raRsp[idx].contFreeUeLst);
4464 CM_LLIST_FIRST_NODE(lnkLst, tmp);
4467 ue = (RgSchUeCb *)tmp->node;
4469 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].tmpCrnti = ue->ueId;
4470 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].isContFree = TRUE;
4471 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].rapId = ue->ul.rarGrnt.rapId;
4472 #ifndef MAC_5GTF_UPDATE
4473 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.hop =
4475 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.cqiBit =
4476 ue->ul.rarGrnt.cqiReqBit;
4478 /* SHASHAHNK ADD RIV CALC */
4479 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.rbStart =
4480 ue->ul.rarGrnt.rbStart;
4481 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.numRb =
4482 ue->ul.rarGrnt.numRb;
4483 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.tpc =
4485 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.iMcsCrnt =
4486 ue->ul.rarGrnt.iMcsCrnt;
4487 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].ta = ue->ul.rarGrnt.ta;
4488 raRntiAlloc->numCrnti++;
4489 cmLListDelFrm(lnkLst, &ue->ul.rarGrnt.raRspLnk);
4490 ue->ul.rarGrnt.raRspLnk.node = (PTR)NULLP;
4492 /* Fill for contention based UEs*/
4493 lnkLst = &(sf->raRsp[idx].raRspLst);
4495 CM_LLIST_FIRST_NODE(lnkLst, tmp);
4497 while((NULLP != tmp) && ((RgSchRaCb *)tmp->node != NULLP))
4499 raCb = (RgSchRaCb *)tmp->node;
4501 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].tmpCrnti = raCb->tmpCrnti;
4502 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].isContFree = FALSE;
4503 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].rapId = raCb->rapId;
4504 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].ta.pres = TRUE;
4505 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].ta.val = raCb->ta.val;
4506 #ifndef MAC_5GTF_UPDATE
4507 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.hop =
4509 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.cqiBit = FALSE;
4511 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.rbStart =
4512 raCb->msg3Grnt.rbStart;
4513 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.numRb =
4514 raCb->msg3Grnt.numRb;
4515 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.tpc =
4517 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.iMcsCrnt =
4518 raCb->msg3Grnt.iMcsCrnt;
4519 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.delayBit =
4520 raCb->msg3Grnt.delayBit;
4521 /* For initial attaching UEs Aperiodic CQI need not be triggered */
4522 raRntiAlloc->numCrnti++;
4523 /* Search the next node */
4524 CM_LLIST_NEXT_NODE(lnkLst, tmp);
4527 sfAlloc->rarInfo.numRaRntis = idx;
4528 /* ccpu00132314-ADD-Update the tx power allocation info
4529 TODO-Need to add a check for max tx power per symbol */
4530 sfAlloc->rarInfo.txPwrOffset = cellDl->rarTxPwrOffset;
4533 } /* end of rgSCHUtlFillRgInfRarInfo */
4535 /** @brief This function fills in the pdsch data related allocation Info
4536 * from the pdcch DCI info.
4541 * Function: rgSCHUtlFillPdschDciInfo
4544 * - Depending upon the DCI Format, fill the appropriate fields.
4546 * @param [out] TfuPdschDciInfo *pdschDci
4547 * @param [in] TfuDciInfo *pdcchDci
4552 S16 rgSCHUtlFillPdschDciInfo(TfuPdschDciInfo *pdsch,TfuDciInfo *pdcchDci)
4558 pdsch->format = pdcchDci->dciFormat;
4559 switch(pdcchDci->dciFormat)
4561 case TFU_DCI_FORMAT_1:
4562 pdsch->u.format1AllocInfo = pdcchDci->u.format1Info.allocInfo;
4564 case TFU_DCI_FORMAT_1A:
4565 if (pdcchDci->u.format1aInfo.isPdcchOrder == FALSE)
4567 pdsch->u.format1aAllocInfo = pdcchDci->u.format1aInfo.t.pdschInfo.allocInfo;
4570 case TFU_DCI_FORMAT_1B:
4571 pdsch->u.format1bAllocInfo = pdcchDci->u.format1bInfo.allocInfo;
4573 case TFU_DCI_FORMAT_1C:
4574 pdsch->u.format1cAllocInfo = pdcchDci->u.format1cInfo;
4576 case TFU_DCI_FORMAT_1D:
4577 pdsch->u.format1dAllocInfo = pdcchDci->u.format1dInfo.allocInfo;
4579 case TFU_DCI_FORMAT_2:
4580 pdsch->u.format2AllocInfo = pdcchDci->u.format2Info.allocInfo;
4582 case TFU_DCI_FORMAT_2A:
4583 pdsch->u.format2AAllocInfo = pdcchDci->u.format2AInfo.allocInfo;
4586 case TFU_DCI_FORMAT_B1:
4587 pdsch->u.formatB1Info = pdcchDci->u.formatB1Info;
4589 case TFU_DCI_FORMAT_B2:
4590 pdsch->u.formatB2Info = pdcchDci->u.formatB2Info;
4595 ret = rgSCHEmtcUtlFillPdschDciInfo(pdsch, pdcchDci);
4607 /* LTE_ADV_FLAG_REMOVED_START */
4609 * @brief This function resets temporary variables in Pool
4612 * Function: rgSchSFRResetPoolVariables
4614 * Invoked by: rgSCHSFRUtlTotalPoolInit
4616 * @param[in] RgSchCellCb* cell
4617 * @param[in] RgSubFrm* subFrm
4621 Void rgSchDSFRPwrCheck(RgSchDlSf *sf,Bool *isAllUePwrHigh)
4623 RgSchSFRPoolInfo *sfrCCPool;
4628 l = &sf->sfrTotalPoolInfo.ccPool;
4629 n = cmLListFirst(l);
4632 sfrCCPool = (RgSchSFRPoolInfo*)n->node;
4633 if((sfrCCPool->poolstartRB == sfrCCPool->pwrHiCCRange.startRb) &&
4634 (sfrCCPool->poolendRB == sfrCCPool->pwrHiCCRange.endRb))
4641 *isAllUePwrHigh = TRUE;
4648 /* LTE_ADV_FLAG_REMOVED_END */
4649 /***********************************************************
4651 * Func : rgSCHUtlFillRgInfTbInfo
4653 * Desc : Utility Function to fill the allocation info of each Tb
4659 * Notes: This function should be called while sending a msg from
4660 * scheduler instance to MAC
4664 **********************************************************/
4665 static Void rgSCHUtlFillRgInfTbInfo(RgSchDlHqProcCb *hqP,RgInfUeAlloc *allocInfo,RgSchCellCb *cell)
4669 RgInfUeTbInfo *tbInfo;
4671 /* LTE_ADV_FLAG_REMOVED_START */
4673 static uint32_t tmpCnt = 0;
4674 Bool isAllUePwrHigh = FALSE;
4676 /* LTE_ADV_FLAG_REMOVED_END */
4677 RgSchDlLcCb *dlLcCb = NULLP;
4678 uint16_t rlcHdrEstmt;
4682 uint8_t prbUsed = 0;
4686 CmLteTimingInfo frm;
4688 /* Get Downlink slot */
4689 frm = cell->crntTime;
4690 RGSCH_INCR_SUB_FRAME(frm, RG_SCH_CMN_DL_DELTA);
4691 sf = rgSCHUtlSubFrmGet(cell, frm);
4692 /* Setting of fillCtrlPdu flag
4693 If both P-cell and S-cell are present,
4694 make TRUE for P-cell and FALSE for all s-cells
4695 For all other cases set TRUE */
4697 if ((rgSchCb[cell->instIdx].genCfg.forceCntrlSrbBoOnPCel) &&
4698 !RG_SCH_CMN_IS_PCELL_HQP(hqP))
4700 allocInfo->fillCtrlPdu = FALSE;
4704 allocInfo->fillCtrlPdu = TRUE;
4708 allocInfo->tbStrtIdx = -1;
4712 allocInfo->tbReqInfo.sCellHqPId = 0xff;
4713 rgSCHLaaHndlFillRgInfTbInfo(cell, hqP, allocInfo);
4716 /*TODO:REEMA: Check and fill the isRetx */
4717 for(tbCnt = 0; tbCnt < 2; tbCnt++)
4719 RgSchUeCb *ue = NULLP;
4720 /*Changed as a result of CR timer*/
4721 if ((hqP->hqE->ue != NULLP)/* &&
4722 ((hqP->tbInfo[tbCnt].lchSchdData[0].lcId != 0) || \
4723 (hqP->tbInfo[tbCnt].schdTa.pres == PRSNT_NODEF))*/)
4726 allocInfo->rnti = ue->ueId;
4727 allocInfo->doa = hqP->hqE->ue->mimoInfo.doa;
4728 allocInfo->txMode = (TfuTxMode)(hqP->hqE->ue->mimoInfo.txMode);
4729 allocInfo->puschRptUsd = hqP->hqE->ue->mimoInfo.puschFdbkVld;
4730 allocInfo->puschPmiInfo = hqP->hqE->ue->mimoInfo.puschPmiInfo;
4731 if(hqP->tbInfo[tbCnt].schdTa.pres == PRSNT_NODEF)
4733 hqP->tbInfo[tbCnt].taSnt = TRUE;
4736 if (RG_SCH_IS_PAPRSNT(ue,hqP->hqE->cell))
4738 /*update pA value */
4739 allocInfo->pa = (RG_SCH_CMN_GET_PA(ue,hqP->hqE->cell)).val;
4743 /* LTE_ADV_FLAG_REMOVED_START */
4744 /* If ABS is enabled, calculate resource used */
4745 if((0 == tbCnt) && (RGR_ENABLE == ue->cell->lteAdvCb.absCfg.status))
4747 /* For Macro count number resource used in Non-ABS SF */
4748 if(RGR_ABS_MUTE == ue->cell->lteAdvCb.absCfg.absPatternType)
4750 if(RG_SCH_ABS_ENABLED_NONABS_SF == ue->cell->lteAdvCb.absDlSfInfo)
4752 ue->cell->lteAdvCb.absLoadInfo[ue->cell->lteAdvCb.absPatternDlIdx]+=
4753 hqP->tbInfo[tbCnt].dlGrnt.numRb;
4756 /* For pico count number resource used in ABS SF for ABS UE */
4757 else if(RGR_ABS_TRANSMIT == ue->cell->lteAdvCb.absCfg.absPatternType)
4759 if(RG_SCH_ABS_ENABLED_ABS_SF == ue->cell->lteAdvCb.absDlSfInfo)
4761 if(TRUE == ue->lteAdvUeCb.rgrLteAdvUeCfg.isAbsUe)
4763 ue->cell->lteAdvCb.absLoadInfo[ue->cell->lteAdvCb.absPatternDlIdx]+=
4764 hqP->tbInfo[tbCnt].dlGrnt.numRb;
4771 /*if SFR is enabled*/
4772 allocInfo->isEnbSFR = (uint8_t)RG_SCH_CMN_IS_SFR_ENB(ue->cell); /* KW fix for LTE_ADV */
4773 if((ue->cell->lteAdvCb.dsfrCfg.status == RGR_ENABLE) &&
4774 (ue->lteAdvUeCb.rgrLteAdvUeCfg.isUeCellEdge == FALSE))
4776 rgSchDSFRPwrCheck(sf, &isAllUePwrHigh);
4780 allocInfo->pa = (uint8_t)ue->cell->lteAdvCb.sfrCfg.pwrThreshold.pHigh; /* KW fix for LTE_ADV */
4781 if(tmpCnt++ == 100000)
4783 DU_LOG("\nDEBUG --> SCH : DSFR::ll UEs can go HIGH, PHigh(%d) for UE(%d)",allocInfo->pa, ue->ueId);
4789 if (allocInfo->isEnbSFR)
4791 /*Update pA to Plow if it is cell-centred ,else pA will be pHigh*/
4792 if (ue->lteAdvUeCb.rgrLteAdvUeCfg.isUeCellEdge == TRUE)
4794 allocInfo->pa = ue->cell->lteAdvCb.sfrCfg.pwrThreshold.pHigh;
4795 if(tmpCnt++ == 100000)
4797 DU_LOG("\nDEBUG --> SCH : SFR::UE is CELL EDGE, PHigh(%d) for UE(%d)",allocInfo->pa, ue->ueId);
4804 if(TRUE == ue->lteAdvUeCb.isCCUePHigh)
4806 allocInfo->pa = ue->cell->lteAdvCb.sfrCfg.pwrThreshold.pHigh;
4807 ue->lteAdvUeCb.isCCUePHigh = FALSE;
4811 allocInfo->pa = ue->cell->lteAdvCb.sfrCfg.pwrThreshold.pLow;
4812 if(tmpCnt++ == 100000)
4814 DU_LOG("\nDEBUG --> SCH : SFR::UE is CELL CENTRE, PLow(%d) for UE(%d)\n",allocInfo->pa, ue->ueId);
4821 /* LTE_ADV_FLAG_REMOVED_END */
4829 RgSchCmnDlCell *cellDl = RG_SCH_CMN_GET_DL_CELL(cell);
4832 allocInfo->pdcchRnti = hqP->hqE->raCb->tmpCrnti;
4834 allocInfo->rnti = hqP->hqE->raCb->tmpCrnti;
4836 /*ccpu00132314-ADD-Use a default pA value
4838 allocInfo->pa = cellDl->msg4pAVal;
4842 /* If TB Is scheduled for this SF */
4843 if(hqP->tbInfo[tbCnt].state == HQ_TB_WAITING)
4845 if (allocInfo->tbStrtIdx == -1){
4846 allocInfo->tbStrtIdx = tbCnt;
4848 rgSCHUtlFillPdschDciInfo(&(allocInfo->dciInfo),
4849 &(hqP->pdcch->dci));
4853 rgSCHUtlFillPdschDciInfo(&(allocInfo->dciInfo),
4854 &(hqP->pdcch->dci));
4856 else if ((ue) && (ue->dl.spsOccPdcch.rnti == ue->spsRnti))
4858 rgSCHUtlFillPdschDciInfo(&(allocInfo->dciInfo),
4859 &(ue->dl.spsOccPdcch.dci));
4861 #endif /* ifndef LTEMAC_SPS */
4866 allocInfo->pdcchRnti = hqP->pdcch->rnti;
4870 allocInfo->pdcchRnti = ue->spsRnti;
4873 tbInfo = &(allocInfo->tbInfo[tbCnt]);
4874 allocInfo->nmbOfTBs++;
4875 allocInfo->hqProcId = hqP->procId;
4876 allocInfo->tbInfo[tbCnt].schdTbSz = hqP->tbInfo[tbCnt].tbSz;
4878 tbInfo->disTb = FALSE;
4879 if(!(hqP->tbInfo[tbCnt].txCntr))
4882 if(!((rgSCHLaaCheckIfLAAProc(hqP)) && (TRUE ==
4883 rgSCHLaaSCellEnabled(cell))))
4886 hqP->tbInfo[tbCnt].txCntr++;
4888 for(idx = 0; idx < hqP->tbInfo[tbCnt].numLch; idx++)
4890 tbInfo->schdDat[idx].lcId =\
4891 hqP->tbInfo[tbCnt].lchSchdData[idx].lcId;
4892 tbInfo->schdDat[idx].numBytes =\
4893 hqP->tbInfo[tbCnt].lchSchdData[idx].schdData;
4896 lcId = hqP->tbInfo[tbCnt].lchSchdData[idx].lcId;
4899 dlLcCb = hqP->hqE->ue->dl.lcCb[lcId-1];
4902 RG_SCH_CMN_DL_GET_HDR_EST(dlLcCb, rlcHdrEstmt);
4903 /* Update the totalBo with the scheduled bo */
4904 (hqP->hqE->ue->totalBo <= tbInfo->schdDat[idx].numBytes - rlcHdrEstmt)?\
4905 (hqP->hqE->ue->totalBo = 0):\
4906 (hqP->hqE->ue->totalBo -= tbInfo->schdDat[idx].numBytes-rlcHdrEstmt);
4910 prbUsed = ((hqP->tbInfo[tbCnt].\
4911 lchSchdData[idx].schdData *
4912 hqP->tbInfo[tbCnt].dlGrnt.numRb) /
4913 (hqP->tbInfo[0].tbSz + hqP->tbInfo[1].tbSz));
4914 dlLcCb->qciCb->dlPrbCount += prbUsed;
4915 if(dlLcCb->qciCb->qci > 0)
4917 RG_SCH_CALC_GBR_UTILIZATION(cell, dlLcCb, prbUsed);
4919 #endif /* RRM_RBC_Y */
4922 //if(!(hqP->hqE->ue->pfsStats.lcStats[lcId-1].isLcCntSet))
4926 if (hqP->hqE->ue->cell == hqP->hqE->cell)
4928 idx = RGSCH_PCELL_INDEX;
4932 idx = RG_SCH_GET_SCELL_INDEX((hqP->hqE->ue), (hqP->hqE->cell));
4934 hqP->hqE->ue->pfsStats.lcStats[lcId-1].ueSchdOcc[idx]++;
4935 hqP->hqE->ue->pfsStats.lcStats[lcId-1].perRefresh[ue->pfsStats.lcStats[lcId-1].lastIdx].lcSchdOcc++;
4942 /* Added Dl TB count for SRB/DRB data transmission*/
4944 cell->dlUlTbCnt.tbTransDlTotalCnt++;
4946 tbInfo->ta.pres = hqP->tbInfo[tbCnt].schdTa.pres;
4947 tbInfo->ta.val = hqP->tbInfo[tbCnt].schdTa.val;
4949 tbInfo->sCellActCe = hqP->tbInfo[tbCnt].schdSCellActCe;
4951 tbInfo->numSchLch = hqP->tbInfo[tbCnt].numLch;
4952 if(!(hqP->tbInfo[tbCnt].numLch))
4954 tbInfo->schdDat[tbInfo->numSchLch].numBytes= hqP->tbInfo[tbCnt].tbSz;
4955 /* Fix: If only TA is scheduled, use some dummy LCID */
4956 if (tbInfo->ta.pres)
4957 tbInfo->schdDat[tbInfo->numSchLch].lcId = RG_TA_LCID;
4960 tbInfo->contResCe = hqP->tbInfo[tbCnt].contResCe;
4961 tbInfo->isReTx = FALSE;
4966 if(!((rgSCHLaaCheckIfLAAProc(hqP)) && (TRUE ==
4967 rgSCHLaaSCellEnabled(cell))))
4970 hqP->tbInfo[tbCnt].txCntr++;
4972 tbInfo->isReTx = TRUE;
4974 /* As per 36.314, harq retransmission also considered for
4975 * prb utilization calculation*/
4976 for(idx = 0; idx < hqP->tbInfo[tbCnt].numLch; idx++)
4981 lcId = hqP->tbInfo[tbCnt].lchSchdData[idx].lcId;
4984 dlLcCb = hqP->hqE->ue->dl.lcCb[lcId-1];
4987 prbUsed = ((hqP->tbInfo[tbCnt].\
4988 lchSchdData[idx].schdData *
4989 hqP->tbInfo[tbCnt].dlGrnt.numRb) /
4990 (hqP->tbInfo[0].tbSz + hqP->tbInfo[1].tbSz));
4991 if(dlLcCb->qciCb->qci > 0)
4993 RG_SCH_CALC_GBR_UTILIZATION(cell, dlLcCb, prbUsed);
5005 rgSCHLaaResetDlHqProcCb(hqP);
5010 /***********************************************************
5012 * Func : rgSCHUtlFillRgInfUeInfo
5014 * Desc : Utility Function to fill the allocation info of Ue
5015 * : MIMO : Filling 2TB's of each UE
5020 * Notes: This function should be called while sending a msg from
5021 * scheduler instance to MAC
5025 **********************************************************/
5027 Void rgSCHUtlFillRgInfUeInfo(RgSchDlSf *sf,RgSchCellCb *cell,CmLListCp *dlDrxInactvTmrLst,CmLListCp *dlInActvLst,CmLListCp *ulInActvLst)
5029 RgInfSfAlloc *sfAlloc;
5030 CmLListCp *lnkLst; /* lnkLst assignment */
5033 RgSchUeCb *ue = NULLP;
5034 RgInfUeInfo *ueInfo = NULLP;
5035 RgInfUeAlloc *ueAlloc = NULLP;
5036 RgSchDlHqProcCb *hqCb = NULLP;
5038 /* Since Msg4 is sched only on PCELL, use cell arg's sfAllocArr */
5039 sfAlloc = &(cell->sfAllocArr[cell->crntSfIdx]);
5040 ueInfo = &(sfAlloc->ueInfo);
5041 ueAlloc = sfAlloc->ueInfo.allocInfo;
5043 lnkLst = &(sf->msg4HqPLst);
5044 CM_LLIST_FIRST_NODE(lnkLst, tmp);
5047 DU_LOG("\nINFO --> SCH : 5GTF_ERROR MSG4 Consolidation\n");
5048 hqCb = (RgSchDlHqProcCb *)(tmp->node);
5049 CM_LLIST_NEXT_NODE(lnkLst, tmp);
5051 rgSCHUtlFillRgInfTbInfo(hqCb, &ueAlloc[ueInfo->numUes], cell);
5057 if((!(ue->dl.dlInactvMask & RG_HQENT_INACTIVE)) && (ue->isDrxEnabled))
5059 rgSCHUtlGetDrxSchdUesInDl(cell, ue, hqCb, &ueAlloc[ueInfo->numUes],
5060 dlDrxInactvTmrLst, dlInActvLst, ulInActvLst);
5066 lnkLst = &(sf->ueLst);
5067 CM_LLIST_FIRST_NODE(lnkLst, tmp);
5070 #if defined (TENB_STATS) && defined (RG_5GTF)
5071 cell->tenbStats->sch.dl5gtfPdschCons++;
5073 ue = (RgSchUeCb *)(tmp->node);
5074 CM_LLIST_NEXT_NODE(lnkLst, tmp);
5076 hqPNode = ue->dl.dlSfHqInfo[cell->cellId][sf->dlIdx].hqPLst.first;
5079 hqCb = (RgSchDlHqProcCb *)hqPNode->node;
5080 hqPNode = hqPNode->next;
5082 sfAlloc = &(hqCb->hqE->cell->sfAllocArr[hqCb->hqE->cell->crntSfIdx]);
5083 ueInfo = &(sfAlloc->ueInfo);
5084 ueAlloc = sfAlloc->ueInfo.allocInfo;
5086 rgSCHUtlFillRgInfTbInfo(hqCb, &ueAlloc[ueInfo->numUes],
5089 if(ue->isDrxEnabled)
5091 rgSCHUtlGetDrxSchdUesInDl(cell, ue, hqCb, &ueAlloc[ueInfo->numUes],
5092 dlDrxInactvTmrLst, dlInActvLst, ulInActvLst);
5097 if (rgSchCb[cell->instIdx].genCfg.isSCellActDeactAlgoEnable == TRUE)
5099 /*If remaining BO is left then increment the count*/
5103 /* Check if trigger for Activation is met or not */
5104 if(rgSCHIsActvReqd(cell, ue))
5107 /*Passing primary cell*/
5108 rgSCHSCellSelectAndActDeAct(ue->cell, ue, RGR_SCELL_ACT);
5113 /*If remaining BO is 0 then reset the count*/
5121 } /* end of rgSCHUtlFillRgInfUeInfo */
5125 /** @brief This function shall update the scheduler with the CEs and data rcvd
5129 * Function: rgSCHUtlUpdSch
5132 * - Collate the information of all the SDUs received and inform the
5133 * scheduler rgSCHDataRcvd
5134 * - Send Data indication to the higher layer with the dedicated data
5135 * (rgUIMSndDedDatInd)
5136 * - Inform scheduler with any MAC CEs if present.
5138 * @param [in] RgCellCb *cellCb
5139 * @param [in] RgUeCb *ueCb
5140 * @param [in] RgMacPdu *pdu
5141 * @param [in] RgSchErrInfo *err
5146 S16 rgSCHUtlUpdSch(RgInfSfDatInd *subfrmInfo,RgSchCellCb *cellCb,RgSchUeCb *ueCb,RgInfUeDatInd *pdu,RgSchErrInfo *err)
5151 if (RGSCH_UL_SPS_ACT_PRSENT & pdu->ceInfo.bitMask)
5153 /* SPS to be activated due to data on SPS LCG ID*/
5154 rgSCHUtlSpsActInd(cellCb, ueCb, pdu->ceInfo.spsSduSize);
5157 /* TODO : Temp Fix for crash due to UL SDU corruption*/
5158 if (RGSCH_PHR_CE_PRSNT & pdu->ceInfo.bitMask)
5161 RGSCHCPYTIMEINFO(subfrmInfo->timingInfo, ueCb->macCeRptTime);
5162 if ((ret = rgSCHUtlUpdPhr(cellCb, ueCb, pdu->ceInfo.ces.phr, err)) != ROK)
5165 /* Note: Order of indication to Sch now is
5166 * 1st Indicate the DataInd info for each LCG's
5167 * 2nd Update the BSR reports received along with data
5168 * this is to make sure the effBsr is updated to the latest BSR
5171 cellCb->sc.apis->rgSCHUpdUeDataIndLcg(cellCb, ueCb, pdu);
5173 #ifndef MAC_5GTF_UPDATE
5174 if (RGSCH_TRUNC_BSR_CE_PRSNT & pdu->ceInfo.bitMask)
5176 RGSCHCPYTIMEINFO(subfrmInfo->timingInfo, ueCb->macCeRptTime);
5177 /*ccpu00129922 - MOD - Deleted return value
5178 * checking since it returns void*/
5179 rgSCHUtlUpdBsrTrunc (cellCb, ueCb,
5180 (uint8_t)(pdu->ceInfo.ces.bsr.truncBsr >> 6),
5181 (uint8_t)(pdu->ceInfo.ces.bsr.truncBsr & 0x3F), err);
5185 if (RGSCH_SHORT_BSR_CE_PRSNT & pdu->ceInfo.bitMask)
5187 RGSCHCPYTIMEINFO(subfrmInfo->timingInfo, ueCb->macCeRptTime);
5188 /*ccpu00129922 - MOD - Deleted return value
5189 checking since it returns void*/
5190 rgSCHUtlUpdBsrShort (cellCb, ueCb,
5191 (uint8_t)(pdu->ceInfo.ces.bsr.shortBsr >> 6),
5192 (uint8_t)(pdu->ceInfo.ces.bsr.shortBsr & 0x3F), err);
5196 if (RGSCH_LONG_BSR_CE_PRSNT & pdu->ceInfo.bitMask)
5198 if (RGSCH_BSR_CE_PRSNT & pdu->ceInfo.bitMask)
5201 RGSCHCPYTIMEINFO(subfrmInfo->timingInfo, ueCb->macCeRptTime);
5202 /*ccpu00129922 - MOD - Deleted return value
5203 checking since it returns void*/
5204 rgSCHUtlUpdBsrLong (cellCb, ueCb,
5205 pdu->ceInfo.ces.bsr.longBsr.bs1,
5206 pdu->ceInfo.ces.bsr.longBsr.bs2,
5207 pdu->ceInfo.ces.bsr.longBsr.bs3,
5208 pdu->ceInfo.ces.bsr.longBsr.bs4,
5211 #ifndef MAC_5GTF_UPDATE
5218 } /* end of rgSCHUtlUpdSch */
5221 * @brief Handler for Updating Bo received in StaRsp
5225 * Function : rgSCHUtlAddUeToCcchSduLst
5227 * This function shall be invoked once it receives staRsp on CCCH
5229 * @param[in] RgSchCellCb *cell
5230 * @param[in] RgSchUeCb *ueCb
5234 S16 rgSCHUtlAddUeToCcchSduLst(RgSchCellCb *cell,RgSchUeCb *ueCb)
5236 RgSchCmnDlUe *ueDl = RG_SCH_CMN_GET_DL_UE(ueCb, cell);
5237 RgSchDlHqProcCb *hqP = (RgSchDlHqProcCb *)ueDl->proc;
5239 /* Temp Guard: For back to back CCCH SDU BO
5240 * twice. Hence an extra guard. If already added to scheduling
5241 * queue or if scheduled and waiting for HQ FDBK, ignore */
5242 if ((ueCb->ccchSduLnk.node) ||
5243 ((!(ueCb->dl.dlInactvMask & RG_HQENT_INACTIVE)) &&
5244 ((hqP != NULLP) && (hqP->hqE->ccchSduProc))))
5246 DU_LOG("\nINFO --> SCH : RNTI:%d Unexpected CCCH SDU BO",
5251 ueCb->ccchSduLnk.node = (PTR)(ueCb);
5252 cmLListAdd2Tail(&(cell->ccchSduUeLst), &(ueCb->ccchSduLnk));
5260 * Function : rgSCHUtlUpdtBo
5262 * This function shall be invoked once it receives staRsp on CCCH
5264 * @param[in] RgSchCellCb *cell
5265 * @param[in] RgRguCmnStaRsp *staRsp
5269 S16 rgSCHUtlUpdtBo(RgSchCellCb *cell,RgInfCmnBoRpt *staRsp)
5273 if ((ueCb = rgSCHDbmGetUeCb(cell, staRsp->u.rnti)) == NULLP)
5275 /* Handle Ue fetch failure */
5276 DU_LOG("\nERROR --> SCH : Invalid UEID:%d",staRsp->u.rnti);
5279 /* Update Bo in ueCb */
5280 ueCb->dlCcchInfo.bo = (uint32_t)(staRsp->bo);
5284 rgSCHUtlAddUeToEmtcCcchSduLst(cell,ueCb);
5289 rgSCHUtlAddUeToCcchSduLst(cell, ueCb);
5293 } /* rgSCHUtlUpdtBo */
5299 * Function : rgSCHUtlHndlCcchBoUpdt
5301 * This function shall fetch the raCb with the given rnti and ask RAM to
5305 * @param[in] RgSchCellCb *cell
5306 * @param[in] RgInfCmnBoRpt *boRpt
5311 S16 rgSCHUtlHndlCcchBoUpdt(RgSchCellCb *cell,RgInfCmnBoRpt *boRpt)
5316 if ((raCb = rgSCHDbmGetRaCb(cell, boRpt->u.rnti)) == NULLP)
5319 /* CR timer implementation changes*/
5320 /*If no raCb, schedule ueCb, ueCb is extracted in rgSCHUtlUpdtBo*/
5321 return (rgSCHUtlUpdtBo(cell, boRpt));
5323 /* Handle RaCb fetch failure */
5324 DU_LOG("\nERROR --> SCH : Invalid RNTI:%d to fetch raCb",boRpt->u.rnti);
5331 /*Fix: If RaCb exists, then MSG4 is not completed yet*/
5332 /*Check if guard timer has expired, if not CR CE + CCCH SDU will be scheduled*/
5333 if((raCb->contResTmrLnk.node != NULLP) && \
5334 (raCb->schdLnk.node == NULLP) && (raCb->dlHqE->msg4Proc == NULLP))
5337 /*if contention resolution timer left ,Stop the Contention Resolution Guard Timer ,
5338 add in toBeSchduled list and update the Bo */
5339 if(TRUE == raCb->isEmtcRaCb)
5341 rgSCHRamEmtcUpdtBo(cell, raCb, boRpt);
5346 cmLListDelFrm(&cell->contResGrdTmrLst, &(raCb->contResTmrLnk));
5347 raCb->contResTmrLnk.node=NULLP;
5348 rgSCHRamUpdtBo(cell, raCb, boRpt);
5353 /*Fix:Guard timer has expired */
5354 /*Update the BO in UE CB but dont add it to the scheduling list.
5355 *Should be added to the list after MSG4 completion*/
5356 if ((ueCb = rgSCHDbmGetUeCb(cell, boRpt->u.rnti)) == NULLP)
5358 /* Handle Ue fetch failure */
5359 DU_LOG("\nERROR --> SCH : Invalid RNTI:%d",boRpt->u.rnti);
5362 /* Update Bo in ueCb */
5363 ueCb->dlCcchInfo.bo = (uint32_t)(boRpt->bo);
5367 rgSCHRamUpdtBo(cell, raCb, boRpt);
5371 } /* rgSCHUtlHndlCcchBoUpdt */
5374 * @brief Validates BO received for BCCH or PCCH.
5378 * Function : rgSCHUtlGetAllwdCchTbSz
5380 * This function shall return the tbSz equal to or
5381 * the nearest greater value for a given bo.
5382 * If no such value found return -1. The nPrb value is
5386 * @param[in] uint32_t bo
5387 * @param[out] uint8_t *nPrb
5392 S32 rgSCHUtlGetAllwdCchTbSz(uint32_t bo,uint8_t *nPrb,uint8_t *mcs)
5398 for (lt = 0, rt = 43; lt <= rt;)
5401 if (rgSchUtlBcchPcchTbSzTbl[cn].tbSz == bo)
5403 *nPrb = rgSchUtlBcchPcchTbSzTbl[cn].rbIndex;
5404 *mcs = rgSchUtlBcchPcchTbSzTbl[cn].mcs;
5405 return (rgSchUtlBcchPcchTbSzTbl[cn].tbSz);
5407 else if (rgSchUtlBcchPcchTbSzTbl[cn].tbSz < bo)
5416 *nPrb = rgSchUtlBcchPcchTbSzTbl[lt].rbIndex;
5417 *mcs = rgSchUtlBcchPcchTbSzTbl[lt].mcs;
5418 return (rgSchUtlBcchPcchTbSzTbl[lt].tbSz);
5422 * @brief Handler for BO Updt received for BCCH or PCCH.
5426 * Function : rgSCHUtlHndlBcchPcchBoUpdt
5428 * This function shall store the buffer and time to transmit in lcCb
5431 * @param[in] RgSchCellCb *cell
5432 * @param[in] RgInfCmnBoRpt *boRpt
5437 S16 rgSCHUtlHndlBcchPcchBoUpdt(RgSchCellCb *cell,RgInfCmnBoRpt *boUpdt)
5439 RgSchClcDlLcCb *dlLc;
5440 RgSchClcBoRpt *boRpt;
5441 Inst inst = cell->instIdx;
5445 dlLc = rgSCHDbmGetBcchOnBch(cell);
5448 DU_LOG("\nERROR --> SCH : No Logical Channel dlLc is NULLP for RNTI:%d LCID:%d",boUpdt->u.rnti,boUpdt->lcId);
5451 if (boUpdt->lcId != dlLc->lcId)
5453 /* Added for dropping paging Message*/
5455 if ((rgSCHChkBoUpdate(cell,boUpdt))== ROK) /* Checking if received BO falls within the window of 5120 slots*/
5457 if (rgSCHUtlGetAllwdCchTbSz(boUpdt->bo*8, &nPrb, &mcs)
5460 DU_LOG("\nERROR --> SCH : [%d]BO: does not match any "
5461 "valid TB Size RNTI:%d LCID:%d", boUpdt->bo,boUpdt->u.rnti,boUpdt->lcId);
5464 }/*end of rgSCHChkBoUpdate*/
5470 if ((dlLc = rgSCHDbmGetCmnLcCb(cell, boUpdt->lcId)) == NULLP)
5472 /* Handle lcCb fetch failure */
5473 DU_LOG("\nERROR --> SCH : LCID:%d Invalid for RNTI:%d",boUpdt->lcId,boUpdt->u.rnti);
5476 if (((rgSCHUtlAllocSBuf(inst, (Data **)(&boRpt), sizeof(RgSchClcBoRpt))) ==RFAILED) ||
5479 DU_LOG("\nERROR --> SCH : Allocation of common bo %dreport "
5480 "failed RNTI:%d LCID:%d", boUpdt->bo,boUpdt->u.rnti,boUpdt->lcId);
5484 boRpt->bo = boUpdt->bo;
5486 boRpt->timeToTx = boUpdt->u.timeToTx;
5489 if(cell->emtcEnable)
5491 boRpt->emtcDIReason = boUpdt->emtcDIReason;
5492 boRpt->pnb = boUpdt->pnb;
5495 RG_SCH_ADD_TO_CRNT_TIME(boRpt->timeToTx,
5496 boRpt->maxTimeToTx, cell->siCfg.siWinSize)
5497 if((NULLP != dlLc) && (dlLc->si))
5499 boRpt->retxCnt = cell->siCfg.retxCnt;
5505 rgSCHDbmInsCmnLcBoRpt(dlLc, boRpt);
5508 } /* rgSCHUtlHndlBcchPcchBoUpdt */
5511 * @brief API for sending bind confirm from Scheduler instance to RRM
5515 * Function: rgSCHUtlRgrBndCfm
5517 * This API is invoked to send bind confirm from Scheduler instance to RRM.
5518 * This API fills in Pst structure and SAP Ids and invokes
5519 * bind confirm API towards RRM.
5521 * @param[in] SuId suId
5522 * @param[in] uint8_t status
5527 S16 rgSCHUtlRgrBndCfm(Inst instId,SuId suId,uint8_t status)
5531 ret = RgUiRgrBndCfm(&rgSchCb[instId].rgrSap[suId].sapCfg.sapPst, rgSchCb[instId].rgrSap[suId].sapCfg.suId, status);
5534 DU_LOG("\nERROR --> SCH : rgSCHUtlRgrBndCfm: RgUiRgrBndCfm Failed ");
5538 } /* rgSCHUtlRgrBndCfm*/
5541 * @brief API for sending bind confirm from Scheduler instance to RRM via RGM
5546 * Function: rgSCHUtlRgmBndCfm
5548 * This API is invoked to send bind confirm from Scheduler instance to RRM.
5549 * This API fills in Pst structure and SAP Ids and invokes
5551 * @param[in] SuId suId
5552 * @param[in] uint8_t status
5557 S16 rgSCHUtlRgmBndCfm(Inst instId,SuId suId,uint8_t status)
5561 ret = RgUiRgmBndCfm(&rgSchCb[instId].rgmSap[suId].sapCfg.sapPst, rgSchCb[instId].rgmSap[suId].sapCfg.suId, status);
5564 DU_LOG("\nERROR --> SCH : rgSCHUtlRgmBndCfm: RgUiRgrBndCfm Failed ");
5568 } /* rgSCHUtlRgmBndCfm*/
5573 * @brief API for sending configuration confirm from Scheduler to DU APP
5577 * Function: schSendCfgCfm
5579 * This API is invoked to send configuration confirm from Scheduler to DU
5582 * @param[in] Pst pst
5583 * @param[in] RgrCfgTransId transId
5584 * @param[in] uint8_t status
5589 S16 schSendCfgCfm(Region reg,Pool pool,RgrCfgTransId transId,uint8_t status)
5593 memset((&cfmPst), 0, sizeof(Pst));
5595 cfmPst.srcEnt = (Ent)ENTDUAPP;
5596 cfmPst.srcInst = (Inst) 0;
5597 cfmPst.srcProcId = SFndProcId();
5598 cfmPst.dstEnt = (Ent)ENTMAC;
5599 cfmPst.dstInst = (Inst) 0;
5600 cfmPst.dstProcId = SFndProcId();
5601 cfmPst.selector = ODU_SELECTOR_LC;
5602 cfmPst.region = reg;
5605 if(RgUiRgrCfgCfm(&cfmPst,transId, status) != ROK)
5607 DU_LOG("\nERROR --> SCH : schSendCfgCfm: RgUiRgrCfgCfm Failed ");
5611 } /* schSendCfgCfm*/
5614 * @brief API for sending TTI indication from Scheduler to RRM.
5618 * Function: rgSCHUtlRgrTtiInd
5620 * This API is invoked to send TTI indication from Scheduler instance to RRM.
5621 * This API fills in Pst structure and RgrTtiIndInfo
5623 * @param[in] cell RgSchCellCb
5624 * @param[in] CmLteTimingInfo status
5629 S16 rgSCHUtlRgrTtiInd(RgSchCellCb *cell,RgrTtiIndInfo *rgrTti)
5632 RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
5635 Void mtTmrHdlrPublic(void);
5638 rgrSap = cell->rgrSap;
5639 if (rgrSap->sapSta.sapState != LRG_BND)
5641 DU_LOG("\nERROR --> SCH : rgSCHUtlRgrTtiInd() Upper SAP not bound (%d) ",
5642 rgrSap->sapSta.sapState);
5645 RgUiRgrTtiInd(&(cell->rgrSap->sapCfg.sapPst),
5646 cell->rgrSap->sapCfg.suId, rgrTti);
5654 } /* rgSCHUtlRgrTtiInd*/
5656 /** @brief This function is called by rgMacSchSfRecpInd. This function invokes the
5657 * scheduler with the information of the received Data and any Control Elements
5665 * - Retrieves the RaCb with the rnti provided, if it doesnt exist
5667 * - If UE exists then update the Schduler with any MAC CEs if present.
5668 * - Invoke RAM module to do Msg3 related processing rgSCHRamProcMsg3
5670 * @param [in] RgSchCellCb *cellCb
5671 * @param [in] RgSchUeCb *ueCb
5672 * @param [in] CmLteRnti rnti
5673 * @param [in] RgMacPdu *pdu
5674 * @param [in] RgSchErrInfo *err
5680 S16 rgSCHUtlProcMsg3
5682 RgInfSfDatInd *subfrmInfo,
5683 RgSchCellCb *cellCb,
5693 /* must have an raCb for this case */
5694 raCb = rgSCHDbmGetRaCb (cellCb, rnti);
5697 DU_LOG("\nERROR --> SCH : RNTI:%d Received MSG3, unable to "
5702 /* ccpu00130982: Processing CRNTI MAC CE before Short BSR, if any, such that
5703 * effBsr of current case only will be considered in scheduling of ContResLst*/
5704 ret = rgSCHRamProcMsg3 (cellCb, ueCb, raCb, pdu, err);
5707 DU_LOG("\nERROR --> SCH : Processing failed in the RAM "
5711 /* if ueCb is present */
5714 rgSCHUtlUpdSch (subfrmInfo, cellCb, ueCb, pdu, err);
5720 /** @brief This function is called by RgMacSchSpsRelInd. This function invokes the
5721 * scheduler with the information of the received Data.
5725 * Function: rgSCHUtlSpsRelInd
5730 * @param [in] RgSchCellCb *cellCb
5731 * @param [in] RgSchUeCb *ueCb
5732 * @param [in] Bool *isExplRel
5738 S16 rgSCHUtlSpsRelInd(RgSchCellCb *cellCb,RgSchUeCb *ueCb,Bool isExplRel)
5740 cellCb->sc.apis->rgSCHUlSpsRelInd(cellCb, ueCb, isExplRel);
5742 } /* end of rgSCHUtlSpsRelInd */
5745 /** @brief This function is called by RgMacSchSpsRelInd. This function invokes the
5746 * scheduler with the information of the received Data.
5750 * Function: rgSCHUtlSpsActInd
5755 * @param [in] RgSchCellCb *cellCb
5756 * @param [in] RgSchUeCb *ueCb
5757 * @param [in] uint16_t spsSduSize
5763 S16 rgSCHUtlSpsActInd(RgSchCellCb *cellCb,RgSchUeCb *ueCb,uint16_t spsSduSize)
5765 cellCb->sc.apis->rgSCHUlSpsActInd(cellCb, ueCb, spsSduSize);
5767 } /* end of rgSCHUtlSpsActInd */
5770 #endif /* LTEMAC_SPS */
5774 * @brief This API is invoked to send uplink group power control request to PHY.
5778 * Function : rgSCHUtlTfuGrpPwrCntrlReq
5780 * This API is invoked to send uplink group power control request to PHY.
5781 * It fills in the Pst structure, spId value and invokes group power
5782 * control request primitive at TFU.
5784 * @param[in] TfuGrpPwrCntrlReqInfo *grpPwrCntrlReq
5789 S16 rgSCHUtlTfuGrpPwrCntrlReq(Inst inst,S16 sapId,TfuGrpPwrCntrlReqInfo *grpPwrCntrlReq)
5792 RgSchLowSapCb *tfuSap;
5795 /* Get the lower SAP control block from the layer control block. */
5796 tfuSap = &(rgSchCb[inst].tfuSap[sapId]);
5797 if (tfuSap->sapSta.sapState != LRG_BND)
5799 DU_LOG("\nERROR --> SCH : rgSCHUtlTfuGrpPwrCntrlReq() Lower SAP not bound (%d) ",tfuSap->sapSta.sapState);
5802 memcpy (&pst, &(tfuSap->sapCfg.sapPst), sizeof(Pst));
5803 if((ret = RgLiTfuGrpPwrCntrlReq (&pst, tfuSap->sapCfg.spId, grpPwrCntrlReq)) != ROK)
5805 DU_LOG("\nERROR --> SCH : rgSCHUtlTfuGrpPwrCntrlReq() Call to RgLiTfuGrpPwrCntrlReq() failed");
5808 } /* rgSCHUtlTfuGrpPwrCntrlReq */
5811 /* FOR ACK NACK REP */
5814 * @brief This API is invoked to tell the DL Scheduler to add the UE back into
5815 * its scheduling queues.
5819 * Function : rgSCHUtlDlActvtUe
5821 * This API is invoked from Measurement gap moduled.
5823 * @param[in] RgSchCellCb *cell
5824 * @param[in] RgSchUeCb *ueCb
5830 S16 rgSCHUtlDlActvtUe(RgSchCellCb *cell,RgSchUeCb *ue)
5832 cell->sc.apis->rgSCHActvtDlUe(cell, ue);
5837 * @brief This API is invoked to tell the UL Scheduler to add the UE back into
5838 * its scheduling queues.
5842 * Function : rgSCHUtlUlActvtUe
5844 * This API is invoked from Measurement gap moduled.
5846 * @param[in] RgSchCellCb *cell
5847 * @param[in] RgSchUeCb *ueCb
5853 S16 rgSCHUtlUlActvtUe(RgSchCellCb *cell,RgSchUeCb *ue)
5855 cell->sc.apis->rgSCHActvtUlUe(cell, ue);
5859 /** @brief This function Validates the SAP information received along with the
5860 * primitive from the lower layer.
5862 * Function: rgSCHUtlValidateTfuSap
5864 * Validates SAP information.
5865 * @param suId The SAP Id
5870 S16 rgSCHUtlValidateTfuSap(Inst inst,SuId suId)
5872 RgSchLowSapCb *tfuSap;
5874 if(suId >= rgSchCb[inst].numSaps)
5876 DU_LOG("\nERROR --> SCH : Incorrect SuId");
5879 tfuSap = &(rgSchCb[inst].tfuSap[suId]);
5881 /* First lets check the suId */
5882 if( suId != tfuSap->sapCfg.suId)
5884 DU_LOG("\nERROR --> SCH : Incorrect SuId. Configured (%d) Recieved (%d)",
5885 tfuSap->sapCfg.suId, suId);
5888 if (tfuSap->sapSta.sapState != LRG_BND)
5890 DU_LOG("\nERROR --> SCH : Lower SAP not enabled SuId (%d)",
5891 tfuSap->sapCfg.suId);
5895 } /* end of rgSCHUtlValidateTfuSap */
5899 * Fun: rgSCHUtlAllocEventMem
5901 * Desc: This function allocates event memory
5903 * Ret: ROK - on success
5904 * RFAILED - on failure
5911 S16 rgSCHUtlAllocEventMem(Inst inst,Ptr *memPtr,Size memSize)
5914 volatile uint32_t startTime=0;
5917 sMem.region = rgSchCb[inst].rgSchInit.region;
5918 sMem.pool = rgSchCb[inst].rgSchInit.pool;
5920 #if (ERRCLASS & ERRCLS_DEBUG)
5923 DU_LOG("\nERROR --> SCH : rgAllocEventMem(): memSize invalid\n");
5926 #endif /* ERRCLASS & ERRCLS_DEBUG */
5928 SStartTask(&startTime, PID_SCHUTL_CMALLCEVT);
5930 #ifdef MS_MBUF_CORRUPTION /* Should be enabled when debugging mbuf corruption */
5931 MS_BUF_ADD_ALLOC_CALLER();
5933 #ifdef TFU_ALLOC_EVENT_NO_INIT
5934 if(ROK != cmAllocEvntNoInit(memSize, TFU_MAX_MEMBLK_SIZE, &sMem, memPtr))
5936 if(ROK != cmAllocEvnt(memSize, TFU_MAX_MEMBLK_SIZE, &sMem, memPtr))
5939 DU_LOG("\nERROR --> SCH : cmAllocEvnt Failed.");
5943 SStopTask(startTime, PID_SCHUTL_CMALLCEVT);
5945 } /* end of rgSCHUtlAllocEventMem*/
5949 * Fun: rgGetEventMem
5951 * Desc: This function allocates event memory
5953 * Ret: ROK - on success
5954 * RFAILED - on failure
5961 S16 rgSCHUtlGetEventMem(Ptr *ptr,Size len,Ptr memCp)
5965 #ifdef TFU_ALLOC_EVENT_NO_INIT
5966 ret = cmGetMemNoInit(memCp, len, (Ptr *)ptr);
5968 ret = cmGetMem(memCp, len, (Ptr *)ptr);
5971 } /* end of rgSCHUtlGetEventMem*/
5977 * @brief Handler to allocate memory for ACK/NACk feedback information
5981 * Function : rgSCHUtlAllocUeANFdbkInfo
5983 * It allocates memory for the UE related ACK NACK information.
5985 * @param[in] RgSchUeCb *ue
5988 S16 rgSCHUtlAllocUeANFdbkInfo(RgSchUeCb *ue,uint8_t servCellIdx)
5992 if (rgSCHUtlAllocSBuf(ue->cell->instIdx,
5993 (Data **) &(ue->cellInfo[servCellIdx]->anInfo), sizeof(RgSchTddANInfo) * \
5994 ue->cell->ackNackFdbkArrSize) != ROK)
5999 for(idx=0; idx < ue->cell->ackNackFdbkArrSize; idx++)
6001 rgSCHUtlInitUeANFdbkInfo(&ue->cellInfo[servCellIdx]->anInfo[idx]);
6004 /* Set it to the first index */
6005 ue->cellInfo[servCellIdx]->nextFreeANIdx = 0;
6007 } /* rgSCHUtlAllocUeANFdbkInfo */
6010 * @brief Handler to release memory for ACK/NACk feedback information
6014 * Function : rgSCHUtlDelUeANFdbkInfo
6016 * It releases memory for the UE related ACK NACK information.
6018 * @param[in] RgSchUeCb *ue
6021 Void rgSCHUtlDelUeANFdbkInfo(RgSchUeCb *ue,uint8_t servCellIdx)
6024 /* ccpu00117052 - MOD - Passing double pointer
6025 for proper NULLP assignment*/
6026 rgSCHUtlFreeSBuf(ue->cell->instIdx,
6027 (Data **)(&( ue->cellInfo[servCellIdx]->anInfo)), sizeof(RgSchTddANInfo) * \
6028 ue->cell->ackNackFdbkArrSize);
6031 } /* rgSCHUtlDelUeANFdbkInfo */
6034 * @brief Handler to initialise UE ACK/NACk feedback information
6038 * Function : rgSCHUtlInitUeANFdbkInfo
6040 * It initialises UE related ACK NACK information.
6042 * @param[in] RgSchTddANInfo *anFdInfo
6045 S16 rgSCHUtlInitUeANFdbkInfo(RgSchTddANInfo *anFdInfo)
6048 anFdInfo->sfn = RGSCH_MAX_SFN+1; /* defensively setting invalid sfn */
6050 anFdInfo->ulDai = RG_SCH_INVALID_DAI_VAL;
6051 anFdInfo->dlDai = RG_SCH_INVALID_DAI_VAL;
6052 anFdInfo->latestMIdx = RG_SCH_INVALID_M_VAL;
6055 } /* rgSCHUtlInitUeANFdbkInfo */
6058 * @brief Handler to get UE related ACK NACK feedback information
6062 * Function : rgSCHUtlGetUeANFdbkInfo
6064 * It gets the UE related ACK NACK information based on
6065 * SFN and slot number.
6067 * @param[in] RgSchUeCb *ueCb
6068 * @param[in] CmLteTimingInfo *time
6069 * @return RgSchTddANInfo*
6071 RgSchTddANInfo* rgSCHUtlGetUeANFdbkInfo(RgSchUeCb *ueCb,CmLteTimingInfo *timeInfo,uint8_t servCellIdx)
6075 for (idx = 0; idx < ueCb->cell->ackNackFdbkArrSize; ++idx)
6077 if( (timeInfo->sfn == ueCb->cellInfo[servCellIdx]->anInfo[idx].sfn) &&
6078 (timeInfo->slot == ueCb->cellInfo[servCellIdx]->anInfo[idx].slot))
6080 return (&ueCb->cellInfo[servCellIdx]->anInfo[idx]);
6085 } /* rgSCHUtlGetUeANFdbkInfo */
6088 * @brief To get downlink slot index
6092 * Function: rgSCHUtlGetDlSfIdx
6093 * Purpose: Gets downlink slot index based on SFN and slot no
6095 * @param[in] CmLteTimingInfo *timeInfo
6096 * @param[in] RgSchCellCb *cell
6100 uint8_t rgSCHUtlGetDlSfIdx(RgSchCellCb *cell,CmLteTimingInfo *timeInfo)
6104 idx = RGSCH_NUM_SUB_FRAMES - \
6105 rgSchTddNumUlSubfrmTbl[cell->ulDlCfgIdx][RGSCH_NUM_SUB_FRAMES-1];
6106 idx = ((idx * timeInfo->sfn) + \
6107 rgSchTddNumDlSubfrmTbl[cell->ulDlCfgIdx][timeInfo->slot]) - 1;
6108 idx = idx % cell->numDlSubfrms;
6110 return ((uint8_t)idx);
6114 * @brief To get the next downlink slot
6118 * Function: rgSCHUtlGetNxtDlSfInfo
6119 * Purpose: Gets next downlink slot based on current DL slot
6121 * @param[in] CmLteTimingInfo curDlTime
6122 * @param[in] RgSchCellCb *cell
6123 * @param[in] RgSchDlSf *dlSf
6124 * @param[in] RgSchDlSf **nxtDlsf
6125 * @param[in] CmLteTimingInfo *nxtDlTime
6129 Void rgSCHUtlGetNxtDlSfInfo(CmLteTimingInfo curDlTime,RgSchCellCb *cell,RgSchDlSf *dlSf,RgSchDlSf **nxtDlsf,CmLteTimingInfo *nxtDlTime)
6131 uint16_t idx = curDlTime.slot;
6138 idx = (idx + 1) % RGSCH_NUM_SUB_FRAMES;
6140 }while(rgSchTddUlDlSubfrmTbl[cell->ulDlCfgIdx][idx]
6141 != RG_SCH_TDD_DL_slot);
6142 RG_SCH_ADD_TO_CRNT_TIME(curDlTime, (*nxtDlTime), count);
6143 *nxtDlsf = rgSCHUtlSubFrmGet(cell, *nxtDlTime);
6144 if(dlSf->dlFdbkInfo.slot != (*nxtDlsf)->dlFdbkInfo.slot)
6153 * @brief To get the previous downlink slot
6157 * Function: rgSCHUtlGetPrevDlSfInfo
6158 * Purpose: Gets previous downlink slot based on current DL slot
6160 * @param[in] RgSchCellCb *cell
6161 * @param[in] CmLteTimingInfo curDlTime
6162 * @param[in] CmLteTimingInfo *prevDlTime
6163 * @param[in] uint8_t *numSubfrm
6167 Void rgSCHUtlGetPrevDlSfInfo(RgSchCellCb *cell,CmLteTimingInfo curDlTime,CmLteTimingInfo *prevDlTime,uint8_t *numSubfrm)
6169 S16 idx = curDlTime.slot;
6177 idx = RGSCH_NUM_SUB_FRAMES-1;
6180 }while(rgSchTddUlDlSubfrmTbl[cell->ulDlCfgIdx][idx]
6181 != RG_SCH_TDD_DL_slot);
6183 RGSCHDECRFRMCRNTTIME(curDlTime, (*prevDlTime), count);
6188 /* Added Holes Management functions for Adaptive Re transmission */
6189 /******* </AllocHolesMemMgmnt>: START *****/
6190 /***********************************************************
6192 * Func : rgSCHUtlUlSfInit
6194 * Desc : UL slot init.
6202 **********************************************************/
6203 S16 rgSCHUtlUlSfInit(RgSchCellCb *cell,RgSchUlSf *sf,uint8_t idx,uint8_t maxUePerSf)
6213 if(cell->ulDlCfgIdx == 0)
6215 /* Store the Uplink slot number corresponding to the idx */
6216 sf->ulSfIdx = rgSchTddCfg0UlSfTbl[idx%6];
6219 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&sf->allocDb,
6220 sizeof(RgSchUlAllocDb));
6225 ret = rgSCHUtlUlAllocDbInit(cell, sf->allocDb, maxUePerSf);
6228 /* ccpu00117052 - MOD - Passing double pointer
6229 for proper NULLP assignment*/
6230 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->allocDb)),
6231 sizeof(RgSchUlAllocDb));
6234 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&sf->holeDb,
6235 sizeof(RgSchUlHoleDb));
6238 rgSCHUtlUlAllocDbDeinit(cell, sf->allocDb);
6239 /* ccpu00117052 - MOD - Passing double pointer
6240 for proper NULLP assignment*/
6241 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->allocDb)),
6242 sizeof(RgSchUlAllocDb));
6245 /* Initialize the hole with CFI 1 Pusch Bw Info */
6246 ret = rgSCHUtlUlHoleDbInit(cell, sf->holeDb, (uint8_t)(maxUePerSf + 2), \
6247 0, cell->dynCfiCb.bwInfo[1].numSb);
6251 rgSCHUtlUlAllocDbDeinit(cell, sf->allocDb);
6252 /* ccpu00117052 - MOD - Passing double pointer
6253 for proper NULLP assignment*/
6254 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->allocDb)),
6255 sizeof(RgSchUlAllocDb));
6256 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->holeDb)),
6257 sizeof(RgSchUlHoleDb));
6260 cmLListInit(&sf->reTxLst);
6262 /* Fix ccpu00120610*/
6263 sf->allocCountRef = &sf->allocDb->count;
6265 /* initialize UL available subbands for current sub-frame */
6266 sf->availSubbands = cell->dynCfiCb.bwInfo[1].numSb;
6268 sf->numGrpPerTti = cell->cell5gtfCb.ueGrpPerTti;
6269 sf->numUePerGrp = cell->cell5gtfCb.uePerGrpPerTti;
6270 for(index = 0; index < MAX_5GTF_BEAMS; index++)
6272 sf->sfBeamInfo[index].totVrbgAllocated = 0;
6273 sf->sfBeamInfo[index].totVrbgRequired = 0;
6274 sf->sfBeamInfo[index].vrbgStart = 0;
6282 /***********************************************************
6284 * Func : rgSCHUtlUlSfDeinit
6286 * Desc : Deinitialises a slot
6294 **********************************************************/
6295 Void rgSCHUtlUlSfDeinit(RgSchCellCb *cell,RgSchUlSf *sf)
6299 rgSCHUtlUlAllocDbDeinit(cell, sf->allocDb);
6300 /* ccpu00117052 - MOD - Passing double pointer
6301 for proper NULLP assignment*/
6302 /* ccpu00117052 - MOD - Passing double pointer
6303 for proper NULLP assignment*/
6304 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->allocDb)),
6305 sizeof(RgSchUlAllocDb));
6309 rgSCHUtlUlHoleDbDeinit(cell, sf->holeDb);
6310 /* ccpu00117052 - MOD - Passing double pointer
6311 for proper NULLP assignment*/
6312 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->holeDb)),
6313 sizeof(RgSchUlHoleDb));
6318 /***********************************************************
6320 * Func : rgSCHUtlUlAllocDbInit
6322 * Desc : Initialise allocation DB
6324 * Ret : S16 (ROK/RFAILED)
6330 **********************************************************/
6331 static S16 rgSCHUtlUlAllocDbInit(RgSchCellCb *cell,RgSchUlAllocDb *allocDb,uint8_t maxAllocs)
6333 S16 ret = rgSCHUtlUlAllocMemInit(cell, &allocDb->mem, maxAllocs);
6339 allocDb->first = NULLP;
6343 /***********************************************************
6345 * Func : rgSCHUtlUlAllocDbDeinit
6347 * Desc : Deinitialises allocation DB
6348 * sent to UE, for a UE with accumulation disabled
6356 **********************************************************/
6357 static Void rgSCHUtlUlAllocDbDeinit(RgSchCellCb *cell,RgSchUlAllocDb *allocDb)
6359 rgSCHUtlUlAllocMemDeinit(cell, &allocDb->mem);
6361 allocDb->first = NULLP;
6365 /***********************************************************
6367 * Func : rgSCHUtlUlHoleDbInit
6369 * Desc : Initialise hole DB
6371 * Ret : S16 (ROK/RFAILED)
6377 **********************************************************/
6378 static S16 rgSCHUtlUlHoleDbInit(RgSchCellCb *cell,RgSchUlHoleDb *holeDb,uint8_t maxHoles,uint8_t start,uint8_t num)
6381 RgSchUlHole *hole = NULLP;
6383 ret = rgSCHUtlUlHoleMemInit(cell, &holeDb->mem, maxHoles, &hole);
6389 holeDb->first = hole;
6390 hole->start = start;
6392 hole->prv = hole->nxt = NULLP;
6396 /***********************************************************
6398 * Func : rgSCHUtlUlHoleDbDeinit
6400 * Desc : Deinitialises hole DB
6408 **********************************************************/
6409 static Void rgSCHUtlUlHoleDbDeinit(RgSchCellCb *cell,RgSchUlHoleDb *holeDb)
6411 rgSCHUtlUlHoleMemDeinit(cell, &holeDb->mem);
6413 holeDb->first = NULLP;
6418 /***********************************************************
6420 * Func : rgSCHUtlUlAllocGetHole
6422 * Desc : Get allocation from hole
6424 * Ret : RgSchUlAlloc *
6430 **********************************************************/
6431 RgSchUlAlloc *rgSCHUtlUlAllocGetHole(RgSchUlSf *sf,uint8_t numSb,RgSchUlHole *hole)
6433 if (numSb < hole->num)
6435 return (rgSCHUtlUlAllocGetPartHole(sf, numSb, hole));
6439 return (rgSCHUtlUlAllocGetCompHole(sf, hole));
6444 /***********************************************************
6446 * Func : rgSCHUtlUlAllocGetCompHole
6448 * Desc : Get an allocation corresponding to an entire hole
6450 * Ret : RgSchUlAlloc *
6456 **********************************************************/
6457 RgSchUlAlloc *rgSCHUtlUlAllocGetCompHole(RgSchUlSf *sf,RgSchUlHole *hole)
6459 RgSchUlAlloc *alloc;
6460 /* alloc = rgSCHUtlUlAllocGetAndIns(sf->allocDb, hole->prvAlloc, hole->nxtAlloc); */
6461 /* Calling rgSchCmnUlAllocGetAndIns is ok, but prv alloc needs to have nxtHole
6462 * updated, causing another check for prv */
6463 RgSchUlAlloc *prv = hole->prvAlloc;
6464 RgSchUlAlloc *nxt = hole->nxtAlloc;
6468 if (hole->start == prv->nxtHole->start)
6470 prv->nxtHole = NULLP;
6472 alloc = rgSCHUtlUlAllocGetAdjNxt(sf->allocDb, prv);
6476 alloc = rgSCHUtlUlAllocGetFirst(sf->allocDb);
6479 RGSCH_NULL_CHECK( 0, alloc);
6480 alloc->prvHole = NULLP;
6481 alloc->nxtHole = NULLP;
6483 alloc->sbStart = hole->start;
6484 alloc->numSb = hole->num;
6488 nxt->prvHole = NULLP;
6491 rgSCHUtlUlHoleRls(sf->holeDb, hole);
6493 /* UL_ALLOC_CHANGES*/
6494 alloc->allocDbRef = (void*)sf->allocDb;
6495 alloc->holeDbRef = (void*)sf->holeDb;
6499 /***********************************************************
6501 * Func : rgSCHUtlUlAllocGetPartHole
6503 * Desc : Get an allocation corresponding to a part of a hole.
6504 * The initial 'numSb' part of the hole shall be taken
6505 * away for this alloc.
6507 * Ret : RgSchUlAlloc *
6513 **********************************************************/
6514 RgSchUlAlloc *rgSCHUtlUlAllocGetPartHole(RgSchUlSf *sf,uint8_t numSb,RgSchUlHole *hole)
6516 RgSchUlAlloc *alloc;
6517 /* alloc = rgSCHUtlUlAllocGetAndIns(sf->allocDb, hole->prvAlloc, hole->nxtAlloc); */
6518 /* Calling rgSchCmnUlAllocGetAndIns is ok, but prv alloc needs to have nxtHole
6519 * updated, causing another check for prv */
6520 RgSchUlAlloc *prv = hole->prvAlloc;
6524 if (hole->start == prv->nxtHole->start)
6526 prv->nxtHole = NULLP;
6528 alloc = rgSCHUtlUlAllocGetAdjNxt(sf->allocDb, prv);
6532 alloc = rgSCHUtlUlAllocGetFirst(sf->allocDb);
6535 RGSCH_NULL_CHECK( 0, alloc);
6536 alloc->prvHole = NULLP;
6537 alloc->nxtHole = hole;
6538 hole->prvAlloc = alloc;
6540 alloc->sbStart = hole->start;
6541 alloc->numSb = numSb;
6542 hole->start += numSb;
6545 rgSCHUtlUlHoleDecr(sf->holeDb, hole);
6547 /* UL_ALLOC_CHANGES*/
6548 alloc->allocDbRef = (void*)sf->allocDb;
6549 alloc->holeDbRef = (void*)sf->holeDb;
6554 /***********************************************************
6556 * Func : rgSCHUtlUlAllocFirst
6558 * Desc : Get first alloc in slot
6560 * Ret : RgSchUlAlloc *
6566 **********************************************************/
6567 RgSchUlAlloc *rgSCHUtlUlAllocFirst(RgSchUlSf *sf)
6569 return (sf->allocDb->first);
6572 /***********************************************************
6574 * Func : rgSCHUtlUlAllocNxt
6576 * Desc : Get next alloc
6578 * Ret : RgSchUlAlloc *
6584 **********************************************************/
6585 RgSchUlAlloc *rgSCHUtlUlAllocNxt(RgSchUlSf *sf,RgSchUlAlloc *alloc)
6588 return (alloc->nxt);
6591 /***********************************************************
6593 * Func : rgSCHUtlUlAllocGetAdjNxt
6595 * Desc : Get alloc which is immediately after the passed one.
6596 * 1. Gets alloc from mem.
6597 * 2. Inserts alloc into list (between prv and
6598 * prv->nxt, prv is not NULLP).
6599 * 3. Increments alloc count.
6600 * Note 1: Holes are not dealt with here.
6601 * Note 2: Assumes prv to be NULL.
6603 * Ret : RgSchUlAlloc *
6609 **********************************************************/
6610 RgSchUlAlloc *rgSCHUtlUlAllocGetAdjNxt(RgSchUlAllocDb *db,RgSchUlAlloc *prv)
6612 RgSchUlAlloc *alloc = rgSCHUtlUlAllocMemGet(&db->mem);
6613 RgSchUlAlloc *nxt = prv->nxt;
6615 #if (ERRCLASS & ERRCLS_DEBUG)
6616 if ( alloc == NULLP )
6634 /***********************************************************
6636 * Func : rgSCHUtlUlAllocGetFirst
6638 * Desc : Get alloc which is to be the first one in the alloc list
6639 * 1. Gets alloc from mem.
6640 * 2. Inserts alloc as first element into list.
6641 * 3. Increments alloc count.
6642 * Note 1: Holes are not dealt with here.
6643 * Note 2: prv to necessarily NULLP.
6645 * Ret : RgSchUlAlloc *
6651 **********************************************************/
6652 RgSchUlAlloc *rgSCHUtlUlAllocGetFirst(RgSchUlAllocDb *db)
6654 RgSchUlAlloc *alloc = rgSCHUtlUlAllocMemGet(&db->mem);
6655 RgSchUlAlloc *nxt = db->first;
6657 #if (ERRCLASS & ERRCLS_DEBUG)
6658 if ( alloc == NULLP )
6677 /* UL_ALLOC_ENHANCEMENT */
6678 /***********************************************************
6680 * Func : rgSCHUtlUlHoleAddAllocation
6682 * Desc : On freeing an alloc, add to hole
6690 **********************************************************/
6691 Void rgSCHUtlUlHoleAddAllocation(RgSchUlAlloc *alloc)
6693 /* Note: rgSchCmnUlHoleUpdAllocLnks function that is used should not exist as
6694 * one, if such excessive branching is done (AllocNone, AllocNoPrv etc).
6695 * The excessive branching is meant to utilise the knowledge of whether prv
6696 * and nxt allocs exist or not. Hence for each kind (none, noprv, nonxt,
6697 * both), there should be a rgSchCmnUlHoleUpdAllocLnks... function (such as
6698 * rgSchCmnUlHoleUpdAllocLnksNone/NoPrv etc. */
6699 RgSchUlHoleDb *db = alloc->holeDbRef;
6700 RgSchUlHole *prv = alloc->prvHole;
6701 RgSchUlHole *nxt = alloc->nxtHole;
6707 rgSCHUtlUlHoleJoin(db, prv, nxt, alloc);
6710 rgSCHUtlUlHoleExtndRight(db, prv, alloc);
6716 rgSCHUtlUlHoleExtndLeft(db, nxt, alloc);
6719 rgSCHUtlUlHoleNew(db, alloc);
6725 /***********************************************************
6727 * Func : rgSCHUtlUlAllocRelease
6729 * Desc : Releases an uplink allocation, only take alloc ptr
6737 **********************************************************/
6738 Void rgSCHUtlUlAllocRelease(RgSchUlAlloc *alloc)
6740 RgSchUlAllocDb *allocDb = alloc->allocDbRef;
6741 RgSchUlAlloc *prv = alloc->prv;
6742 RgSchUlAlloc *nxt = alloc->nxt;
6745 alloc->raCb = NULLP;
6746 alloc->isAdaptive = FALSE;
6751 if (nxt) /* general case: this allocation lies btw two */
6758 allocDb->first = nxt;
6765 rgSCHUtlUlHoleAddAllocation(alloc);
6766 rgSCHUtlUlAllocMemRls(&allocDb->mem, alloc);
6772 /***********************************************************
6774 * Func : rgSCHUtlUlAllocRls
6776 * Desc : Releases an uplink allocation
6784 **********************************************************/
6785 Void rgSCHUtlUlAllocRls(RgSchUlSf *sf,RgSchUlAlloc *alloc)
6787 RgSchUlAllocDb *allocDb = sf->allocDb;
6788 RgSchUlAlloc *prv = alloc->prv;
6789 RgSchUlAlloc *nxt = alloc->nxt;
6792 alloc->raCb = NULLP;
6793 alloc->isAdaptive = FALSE;
6800 if (nxt) /* general case: this allocation lies btw two */
6807 allocDb->first = nxt;
6814 rgSCHUtlUlHoleAddAlloc(sf, alloc);
6815 rgSCHUtlUlAllocMemRls(&allocDb->mem, alloc);
6820 DU_LOG("\nERROR --> SCH : allocDb->count is ZERO ");
6823 //DU_LOG("\nallocDb->count:%u\n",allocDb->count);
6828 /***********************************************************
6830 * Func : rgSCHUtlUlHoleFirst
6832 * Desc : Get first (largest) hole
6834 * Ret : RgSchUlHole *
6840 **********************************************************/
6841 RgSchUlHole *rgSCHUtlUlHoleFirst(RgSchUlSf *sf)
6843 return (sf->holeDb->first);
6846 /***********************************************************
6848 * Func : rgSCHUtlUlHoleNxt
6850 * Desc : Get next largest hole
6852 * Ret : RgSchUlHole *
6858 **********************************************************/
6859 RgSchUlHole *rgSCHUtlUlHoleNxt(RgSchUlSf *sf,RgSchUlHole *hole)
6865 /***********************************************************
6867 * Func : rgSCHUtlUlHoleAddAlloc
6869 * Desc : On freeing an alloc, add to hole
6877 **********************************************************/
6878 Void rgSCHUtlUlHoleAddAlloc(RgSchUlSf *sf,RgSchUlAlloc *alloc)
6880 /* Note: rgSchCmnUlHoleUpdAllocLnks function that is used should not exist as
6881 * one, if such excessive branching is done (AllocNone, AllocNoPrv etc).
6882 * The excessive branching is meant to utilise the knowledge of whether prv
6883 * and nxt allocs exist or not. Hence for each kind (none, noprv, nonxt,
6884 * both), there should be a rgSchCmnUlHoleUpdAllocLnks... function (such as
6885 * rgSchCmnUlHoleUpdAllocLnksNone/NoPrv etc. */
6886 RgSchUlHoleDb *db = sf->holeDb;
6887 RgSchUlHole *prv = alloc->prvHole;
6888 RgSchUlHole *nxt = alloc->nxtHole;
6894 rgSCHUtlUlHoleJoin(db, prv, nxt, alloc);
6897 rgSCHUtlUlHoleExtndRight(db, prv, alloc);
6903 rgSCHUtlUlHoleExtndLeft(db, nxt, alloc);
6906 rgSCHUtlUlHoleNew(db, alloc);
6909 /* increment the number of subbands getting freed to total available list */
6910 sf->availSubbands += alloc->numSb;
6915 /***********************************************************
6917 * Func : rgSCHUtlUlHoleJoin
6919 * Desc : Join two holes (due to alloc being deleted)
6927 **********************************************************/
6928 Void rgSCHUtlUlHoleJoin(RgSchUlHoleDb *db,RgSchUlHole *prv,RgSchUlHole *nxt,RgSchUlAlloc *alloc)
6930 prv->num += alloc->numSb + nxt->num;
6931 rgSCHUtlUlHoleRls(db, nxt);
6932 rgSCHUtlUlHoleIncr(db, prv);
6933 rgSCHUtlUlHoleUpdAllocLnks(prv, alloc->prv, alloc->nxt);
6938 /***********************************************************
6940 * Func : rgSCHUtlUlHoleExtndRight
6942 * Desc : Extend hole due to alloc coming 'after' the hole
6951 **********************************************************/
6952 Void rgSCHUtlUlHoleExtndRight(RgSchUlHoleDb *db,RgSchUlHole *prv,RgSchUlAlloc *alloc)
6954 prv->num += alloc->numSb;
6955 rgSCHUtlUlHoleIncr(db, prv);
6956 rgSCHUtlUlHoleUpdAllocLnks(prv, alloc->prv, alloc->nxt);
6960 /***********************************************************
6962 * Func : rgSCHUtlUlHoleExtndLeft
6964 * Desc : Extend hole due to alloc coming 'before' the hole
6973 **********************************************************/
6974 Void rgSCHUtlUlHoleExtndLeft(RgSchUlHoleDb *db,RgSchUlHole *nxt,RgSchUlAlloc *alloc)
6976 nxt->num += alloc->numSb;
6977 nxt->start = alloc->sbStart;
6978 rgSCHUtlUlHoleIncr(db, nxt);
6979 rgSCHUtlUlHoleUpdAllocLnks(nxt, alloc->prv, alloc->nxt);
6983 /***********************************************************
6985 * Func : rgSCHUtlUlHoleNew
6987 * Desc : Create new hole due to alloc being deleted
6995 **********************************************************/
6996 Void rgSCHUtlUlHoleNew(RgSchUlHoleDb *db,RgSchUlAlloc *alloc)
6998 RgSchUlHole *hole = rgSCHUtlUlHoleMemGet(&db->mem);
6999 #if (ERRCLASS & ERRCLS_DEBUG)
7000 if ( hole == NULLP )
7005 hole->start = alloc->sbStart;
7006 hole->num = alloc->numSb;
7008 rgSCHUtlUlHoleIns(db, hole);
7009 rgSCHUtlUlHoleUpdAllocLnks(hole, alloc->prv, alloc->nxt);
7013 /***********************************************************
7015 * Func : rgSCHUtlUlHoleUpdAllocLnks
7017 * Desc : Update alloc links in hole
7025 **********************************************************/
7026 Void rgSCHUtlUlHoleUpdAllocLnks(RgSchUlHole *hole,RgSchUlAlloc *prvAlloc,RgSchUlAlloc *nxtAlloc)
7030 prvAlloc->nxtHole = hole;
7034 nxtAlloc->prvHole = hole;
7036 hole->prvAlloc = prvAlloc;
7037 hole->nxtAlloc = nxtAlloc;
7042 /***********************************************************
7044 * Func : rgSCHUtlUlHoleIns
7046 * Desc : Insert (newly created) hole in sorted list of holes.
7047 * Searches linearly, beginning with the largest hole.
7055 **********************************************************/
7056 Void rgSCHUtlUlHoleIns(RgSchUlHoleDb *db,RgSchUlHole *hole)
7060 if ((cur = db->first) != NULLP)
7063 if (cur->num < hole->num)
7073 for (nxt = cur->nxt; nxt; cur = nxt, nxt = nxt->nxt)
7075 if (nxt->num < hole->num)
7077 /* Insert hole: cur <-> hole <-> nxt */
7093 /* This is the first hole */
7095 hole->prv = NULLP; /* may not be needed */
7101 /***********************************************************
7103 * Func : rgSCHUtlUlHoleIncr
7105 * Desc : hole->num has increeased, reposition in sorted
7114 **********************************************************/
7115 Void rgSCHUtlUlHoleIncr(RgSchUlHoleDb *db,RgSchUlHole *hole)
7119 if ((cur = hole->prv) != NULLP)
7123 if (cur->num > hole->num)
7128 /* Remove hole from current position */
7129 cur->nxt = hole->nxt;
7132 hole->nxt->prv = cur;
7135 for (prv = cur->prv; prv; cur = prv, prv = prv->prv)
7137 if (prv->num > hole->num)
7139 /* Insert hole: prv <-> hole <-> cur */
7158 /***********************************************************
7160 * Func : rgSCHUtlUlHoleDecr
7162 * Desc : hole->num has decreeased, reposition in sorted
7171 **********************************************************/
7172 Void rgSCHUtlUlHoleDecr(RgSchUlHoleDb *db,RgSchUlHole *hole)
7176 if ((cur = hole->nxt) != NULLP)
7180 if (cur->num < hole->num)
7185 /* Remove hole from current position */
7186 cur->prv = hole->prv;
7189 hole->prv->nxt = cur;
7191 else /* no prv, so cur to replace hole as first in list */
7196 for (nxt = cur->nxt; nxt; cur = nxt, nxt = nxt->nxt)
7198 if (nxt->num < hole->num)
7200 /* Insert hole: cur <-> hole <-> nxt */
7218 /***********************************************************
7220 * Func : rgSCHUtlUlHoleRls
7222 * Desc : Releases hole.
7223 * 1. Decrements hole count.
7224 * 2. Deletes hole from list.
7225 * 3. Frees hole (hole memory release).
7233 **********************************************************/
7234 Void rgSCHUtlUlHoleRls(RgSchUlHoleDb *db,RgSchUlHole *hole)
7236 RgSchUlHole *prv = hole->prv;
7237 RgSchUlHole *nxt = hole->nxt;
7257 rgSCHUtlUlHoleMemRls(&db->mem, hole);
7262 /***********************************************************
7264 * Func : rgSCHUtlUlAllocMemInit
7266 * Desc : Initialises alloc free pool
7268 * Ret : S16 (ROK/RFAILED)
7274 **********************************************************/
7275 S16 rgSCHUtlUlAllocMemInit(RgSchCellCb *cell,RgSchUlAllocMem *mem,uint8_t maxAllocs)
7278 RgSchUlAlloc *allocs;
7280 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&allocs,
7281 maxAllocs * sizeof(*allocs));
7286 mem->allocs = allocs;
7287 mem->maxAllocs = maxAllocs;
7288 if (mem->maxAllocs == 1)
7290 allocs[0].prv = NULLP;
7291 allocs[0].nxt = NULLP;
7296 allocs[0].prv = NULLP;
7297 allocs[0].nxt = &allocs[1];
7298 for (i = 1; i < mem->maxAllocs - 1; ++i)
7300 allocs[i].prv = &allocs[i-1];
7301 allocs[i].nxt = &allocs[i+1];
7303 allocs[i].prv = &allocs[i-1];
7304 allocs[i].nxt = NULLP;
7306 mem->firstFree = &allocs[0];
7310 /***********************************************************
7312 * Func : rgSCHUtlUlAllocMemDeinit
7314 * Desc : Deinitialises alloc free pool
7322 **********************************************************/
7323 Void rgSCHUtlUlAllocMemDeinit(RgSchCellCb *cell,RgSchUlAllocMem *mem)
7325 /* ccpu00117052 - MOD - Passing double pointer
7326 for proper NULLP assignment*/
7327 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(mem->allocs)),
7328 mem->maxAllocs * sizeof(*mem->allocs));
7330 mem->firstFree = NULLP;
7334 /***********************************************************
7336 * Func : rgSCHUtlUlHoleMemInit
7338 * Desc : Initialises hole free pool. Assumes maxHoles
7341 * Ret : S16 (ROK/RFAILED)
7347 **********************************************************/
7348 S16 rgSCHUtlUlHoleMemInit(RgSchCellCb *cell,RgSchUlHoleMem *mem,uint8_t maxHoles,RgSchUlHole **holeRef)
7353 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&holes,
7354 maxHoles * sizeof(*holes));
7361 mem->maxHoles = maxHoles;
7363 /* first hole is taken up */
7364 holes[0].prv = NULLP; /* not needed */
7365 holes[0].nxt = NULLP; /* not needed */
7366 *holeRef = &holes[0];
7368 if (mem->maxHoles == 2)
7370 holes[1].prv = NULLP; /* may not be needed */
7371 holes[1].nxt = NULLP; /* may not be needed */
7376 holes[1].prv = NULLP;
7377 holes[0].nxt = &holes[1];
7378 for (i = 1; i < mem->maxHoles - 1; ++i)
7380 holes[i].prv = &holes[i-1];
7381 holes[i].nxt = &holes[i+1];
7383 holes[i].prv = &holes[i-1];
7384 holes[i].nxt = NULLP;
7386 mem->firstFree = &holes[1];
7391 /***********************************************************
7393 * Func : rgSCHUtlUlHoleMemDeinit
7395 * Desc : Deinitialises hole free pool
7403 **********************************************************/
7404 Void rgSCHUtlUlHoleMemDeinit(RgSchCellCb *cell,RgSchUlHoleMem *mem)
7406 /* ccpu00117052 - MOD - Passing double pointer
7407 for proper NULLP assignment*/
7408 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(mem->holes)),
7409 mem->maxHoles * sizeof(*mem->holes));
7411 mem->firstFree = NULLP;
7415 /***********************************************************
7417 * Func : rgSCHUtlUlAllocMemGet
7419 * Desc : Gets an 'alloc' from the free pool
7421 * Ret : RgSchUlAlloc *
7427 **********************************************************/
7428 RgSchUlAlloc *rgSCHUtlUlAllocMemGet(RgSchUlAllocMem *mem)
7430 RgSchUlAlloc *alloc;
7432 #if (ERRCLASS & ERRCLS_DEBUG)
7433 if (mem->firstFree == NULLP)
7439 alloc = mem->firstFree;
7440 mem->firstFree = alloc->nxt;
7441 alloc->nxt = NULLP; /* probably not needed */
7442 /* alloc->prv might already be NULLP, in case was needed to set it to NULLP */
7447 /***********************************************************
7449 * Func : rgSCHUtlUlAllocMemRls
7451 * Desc : Returns an 'alloc' to the free pool
7459 **********************************************************/
7460 Void rgSCHUtlUlAllocMemRls(RgSchUlAllocMem *mem,RgSchUlAlloc *alloc)
7464 alloc->nxt = mem->firstFree;
7465 if (mem->firstFree != NULLP)
7467 mem->firstFree->prv = alloc;
7469 mem->firstFree = alloc;
7473 /***********************************************************
7475 * Func : rgSCHUtlUlHoleMemGet
7477 * Desc : Gets a 'hole' from the free pool
7479 * Ret : RgSchUlHole *
7485 **********************************************************/
7486 RgSchUlHole *rgSCHUtlUlHoleMemGet(RgSchUlHoleMem *mem)
7490 #if (ERRCLASS & ERRCLS_DEBUG)
7491 if (mem->firstFree == NULLP)
7497 hole = mem->firstFree;
7498 mem->firstFree = hole->nxt;
7499 mem->firstFree->prv = NULLP; /* may not be needed, under error class */
7500 hole->nxt = NULLP; /* probably not needed */
7501 /* hole->prv is might already be NULLP, in case was needed to set it to NULLP */
7506 /***********************************************************
7508 * Func : rgSCHUtlUlHoleMemRls
7510 * Desc : Returns a 'hole' to the free pool
7518 **********************************************************/
7519 Void rgSCHUtlUlHoleMemRls(RgSchUlHoleMem *mem,RgSchUlHole *hole)
7523 hole->nxt = mem->firstFree;
7524 if (mem->firstFree != NULLP)
7526 mem->firstFree->prv = hole;
7528 mem->firstFree = hole;
7533 * @brief Get an alloc from the specified position in the BW.
7537 * Function : rgSCHUtlUlGetSpfcAlloc
7539 * - Return an alloc from the specified position in the BW.
7540 * Note: This function assumes there is always a hole
7541 * Existing which completely has the specified
7542 * allocation. The reason for such an assumption is
7543 * the function's usage as of now guarantees that there
7544 * will always be such hole. And also for efficiency.
7546 * @param[in] RgSchUlSf *sf
7547 * @param[in] uint8_t startSb
7548 * @param[in] uint8_t numSb
7549 * @return RgSchUlAlloc*
7551 RgSchUlAlloc *rgSCHUtlUlGetSpfcAlloc(RgSchUlSf *sf,uint8_t startSb,uint8_t numSb)
7553 RgSchUlHole *hole, *nxtHole;
7554 RgSchUlAlloc *alloc = NULLP;
7556 if ((hole = rgSCHUtlUlHoleFirst(sf)) == NULLP)
7562 nxtHole = rgSCHUtlUlHoleNxt(sf, hole);
7563 if ((startSb >= hole->start) &&
7564 (startSb+numSb <= hole->start+hole->num))
7566 if (startSb != hole->start)
7568 /* Create a new hole to accomodate Subbands between
7569 * hole start and req alloc start */
7570 RgSchUlHole *newHole = rgSCHUtlUlHoleMemGet(&(sf->holeDb->mem));
7572 #if (ERRCLASS & ERRCLS_DEBUG)
7573 if ( newHole == NULLP )
7578 newHole->start = hole->start;
7579 newHole->num = startSb - hole->start;
7580 hole->start = startSb;
7581 /* [ccpu00122847]-MOD- Correctly updating the hole->num */
7582 hole->num -= newHole->num;
7583 ++(sf->holeDb->count);
7584 rgSCHUtlUlHoleIns(sf->holeDb, newHole);
7585 newHole->prvAlloc = hole->prvAlloc;
7586 if (newHole->prvAlloc)
7588 newHole->prvAlloc->nxtHole = newHole;
7590 if (numSb == hole->num)
7592 alloc = rgSCHUtlUlAllocGetCompHole(sf, hole);
7596 alloc = rgSCHUtlUlAllocGetPartHole(sf, numSb, hole);
7598 alloc->prvHole = newHole;
7599 newHole->nxtAlloc = alloc;
7601 else /* Hole start and req alloc start are same */
7603 if (numSb == hole->num)
7605 alloc = rgSCHUtlUlAllocGetCompHole(sf, hole);
7609 alloc = rgSCHUtlUlAllocGetPartHole(sf, numSb, hole);
7614 } while ((hole = nxtHole) != NULLP);
7619 * @brief Validates the qci values
7623 * Function :rgSCHUtlValidateQci
7625 * @param[in] RgSchCellCb *cellCb
7626 * @param[in] uint8_t numQci
7627 * @param[out] uint8_t *qci
7632 static S16 rgSCHUtlValidateQci(RgSchCellCb *cellCb,uint8_t numQci,uint8_t *qci)
7637 for(qciIdx = 0; qciIdx < numQci; qciIdx++)
7639 qciVal = qci[qciIdx];
7640 if(qciVal == 0 || qciVal > 9)
7644 if(qciVal != cellCb->qciArray[qciVal].qci)
7651 }/* rgSCHUtlValidateQci */
7653 * @brief Validates the measurement request parameters.
7657 * Function :rgSCHUtlValidateMeasReq
7659 * @param[in] RgSchCellCb *cellCb
7660 * @param[in] LrgSchMeasReqInfo *schL2MeasInfo
7661 * @param[out] RgSchErrInfo *err
7662 * @return RgSchUlAlloc*
7664 S16 rgSCHUtlValidateMeasReq(RgSchCellCb *cellCb, LrgSchMeasReqInfo *schL2MeasInfo,RgSchErrInfo *err)
7669 measType = schL2MeasInfo->measType;
7670 if((measType == 0) ||
7673 err->errType = RGSCHERR_SCH_INVALID_MEAS_TYPE;
7674 err->errCause = RGSCHERR_SCH_L2MEAS;
7677 if((schL2MeasInfo->timePrd !=0) &&
7678 (measType & LRG_L2MEAS_AVG_PRB_PER_QCI_DL) &&
7679 ((schL2MeasInfo->avgPrbQciDl.numQci > LRG_MAX_QCI_PER_REQ)||
7680 (schL2MeasInfo->avgPrbQciDl.numQci == 0)))
7682 err->errType = RGSCHERR_SCH_INVALID_PARAM_RANGE;
7683 err->errCause = RGSCHERR_SCH_L2MEAS;
7686 if((schL2MeasInfo->timePrd !=0) &&
7687 (measType & LRG_L2MEAS_AVG_PRB_PER_QCI_UL) &&
7688 (schL2MeasInfo->avgPrbQciUl.numQci > LRG_MAX_QCI_PER_REQ))
7690 err->errType = RGSCHERR_SCH_INVALID_PARAM_RANGE;
7691 err->errCause = RGSCHERR_SCH_L2MEAS;
7694 if((measType & LRG_L2MEAS_NMB_ACTV_UE_PER_QCI_DL) &&
7695 ((schL2MeasInfo->nmbActvUeQciDl.numQci > LRG_MAX_QCI_PER_REQ) ||
7696 (schL2MeasInfo->nmbActvUeQciDl.sampPrd == 0)||
7697 ((schL2MeasInfo->timePrd !=0)&&
7698 (schL2MeasInfo->timePrd < schL2MeasInfo->nmbActvUeQciDl.sampPrd)) ||
7699 (schL2MeasInfo->nmbActvUeQciDl.sampPrd > LRG_MAX_SAMP_PRD)))
7701 err->errType = RGSCHERR_SCH_INVALID_PARAM_RANGE;
7702 err->errCause = RGSCHERR_SCH_L2MEAS;
7705 if((measType & LRG_L2MEAS_NMB_ACTV_UE_PER_QCI_UL) &&
7706 ((schL2MeasInfo->nmbActvUeQciUl.numQci > LRG_MAX_QCI_PER_REQ) ||
7707 (schL2MeasInfo->nmbActvUeQciUl.sampPrd == 0)||
7708 ((schL2MeasInfo->timePrd !=0) &&
7709 (schL2MeasInfo->timePrd < schL2MeasInfo->nmbActvUeQciUl.sampPrd)) ||
7710 (schL2MeasInfo->nmbActvUeQciUl.sampPrd > LRG_MAX_SAMP_PRD)))
7712 err->errType = RGSCHERR_SCH_INVALID_PARAM_RANGE;
7713 err->errCause = RGSCHERR_SCH_L2MEAS;
7716 if((schL2MeasInfo->timePrd !=0) &&
7717 (measType & LRG_L2MEAS_AVG_PRB_PER_QCI_DL))
7719 RGSCH_ARRAY_BOUND_CHECK(cellCb->instIdx, schL2MeasInfo->avgPrbQciDl.qci, \
7720 (schL2MeasInfo->avgPrbQciDl.numQci));
7721 ret = rgSCHUtlValidateQci(cellCb, schL2MeasInfo->avgPrbQciDl.numQci,
7722 schL2MeasInfo->avgPrbQciDl.qci);
7725 err->errType = RGSCHERR_SCH_INVALID_QCI_VAL;
7726 err->errCause = RGSCHERR_SCH_L2MEAS;
7731 }/* rgSCHUtlValidateMeasReq */
7732 #endif /* LTE_L2_MEAS */
7733 /******* </AllocHolesMemMgmnt>: END *****/
7736 * @brief API for sending SI configuration confirm from Scheduler to RRM
7740 * Function: rgSCHUtlRgrSiCfgCfm
7742 * This API is invoked to send SI configuration confirm from Scheduler
7744 * This API fills in Pst structure and SAP Ids and invokes
7745 * config confirm API towards RRM.
7747 * @param[in] RgrCfgTransId transId
7748 * @param[in] uint8_t status
7753 S16 rgSCHUtlRgrSiCfgCfm(Inst instId,SpId spId,RgrCfgTransId transId,uint8_t status)
7755 uint8_t prntTrans[RGR_CFG_TRANSID_SIZE+1];
7757 memcpy(prntTrans, transId.trans, RGR_CFG_TRANSID_SIZE);
7758 prntTrans[RGR_CFG_TRANSID_SIZE] = '\0';
7759 if(RgUiRgrSiCfgCfm(&rgSchCb[instId].rgrSap[spId].sapCfg.sapPst,
7760 rgSchCb[instId].rgrSap[spId].sapCfg.suId,
7761 transId, status) != ROK)
7763 DU_LOG("\nERROR --> SCH : rgSCHUtlRgrSiCfgCfm: "
7764 "RgUiRgrSiCfgCfm Failed ");
7769 } /* rgSCHUtlRgrSiCfgCfm */
7773 * @brief API for sending Warning SI configuration confirm from
7779 * This API is invoked to send Warning SI configuration confirm
7780 * from Scheduler to RRM.
7781 * This API fills in Pst structure and SAP Ids and invokes
7782 * config confirm API towards RRM.
7784 * @param[in] RgrCfgTransId transId
7785 * @param[in] uint8_t status
7790 S16 rgSCHUtlRgrWarningSiCfgCfm(Inst instId,SpId spId,uint8_t siId,RgrCfgTransId transId,uint8_t status)
7792 uint8_t prntTrans[RGR_CFG_TRANSID_SIZE+1];
7794 memcpy(prntTrans, transId.trans, RGR_CFG_TRANSID_SIZE);
7795 prntTrans[RGR_CFG_TRANSID_SIZE] = '\0';
7797 if(RgUiRgrWarningSiCfgCfm(&rgSchCb[instId].rgrSap[spId].sapCfg.sapPst,
7798 rgSchCb[instId].rgrSap[spId].sapCfg.suId,
7799 transId, siId, status) != ROK)
7801 DU_LOG("\nERROR --> SCH : rgSCHUtlRgrSiCfgCfm: "
7802 "RgUiRgrSiCfgCfm Failed ");
7807 } /* rgSCHUtlRgrWarningSiCfgCfm */
7809 /***********************************************************
7811 * Func : rgSCHUtlPutSiInfo
7813 * Desc : Utility Function to deallocate SI information
7821 **********************************************************/
7822 Void rgSCHUtlPutSiInfo(RgSchCellCb *cell)
7825 uint32_t sizeOfSiInfo = 0;
7826 /*Free the buffers in crntSiInfo*/
7827 RGSCH_FREE_MSG(cell->siCb.crntSiInfo.mib)
7828 RGSCH_FREE_MSG(cell->siCb.crntSiInfo.sib1Info.sib1)
7830 sizeOfSiInfo = sizeof(cell->siCb.crntSiInfo.siInfo)/sizeof(cell->siCb.crntSiInfo.siInfo[0]);
7832 for(idx=0; idx < sizeOfSiInfo; idx++)
7834 RGSCH_FREE_MSG(cell->siCb.crntSiInfo.siInfo[idx].si)
7837 /*Free the buffers in newSiInfo */
7838 RGSCH_FREE_MSG(cell->siCb.newSiInfo.mib)
7839 RGSCH_FREE_MSG(cell->siCb.newSiInfo.sib1Info.sib1)
7841 sizeOfSiInfo = sizeof(cell->siCb.newSiInfo.siInfo)/sizeof(cell->siCb.newSiInfo.siInfo[0]);
7843 for(idx=0; idx < sizeOfSiInfo; idx++)
7845 RGSCH_FREE_MSG(cell->siCb.newSiInfo.siInfo[idx].si)
7850 #endif /*RGR_SI_SCH */
7854 /***********************************************************
7856 * Func : rgSCHUtlGetDrxSchdUesInDl
7858 * Desc : Utility Function to fill the get the list of
7859 * scheduled UEs. On these UE's, drx-inactivity
7860 * timer will be started/restarted.
7869 **********************************************************/
7870 S16 rgSCHUtlGetDrxSchdUesInDl
7872 RgSchCellCb *cellCb,
7874 RgSchDlHqProcCb *dlHq,
7875 RgInfUeAlloc *allocInfo,
7876 CmLListCp *dlDrxInactvTmrLst,
7877 CmLListCp *dlInActvLst,
7878 CmLListCp *ulInActvLst
7881 Bool isNewTx = FALSE;
7883 RgSchDrxDlHqProcCb *drxHq;
7884 RgSchDRXCellCb *drxCell = cellCb->drxCb;
7885 RgSchDrxUeCb *drxUe;
7886 uint8_t cellIdx = ueCb->cellIdToCellIdxMap[RG_SCH_CELLINDEX(dlHq->hqE->cell)];
7887 uint32_t dlInactvMask;
7888 uint32_t ulInactvMask;
7890 for(idx = 0; idx < allocInfo->nmbOfTBs; idx++)
7892 if(allocInfo->tbInfo[idx].isReTx == FALSE)
7895 /* Removing break here, since in 2 TB case if 2nd TB is proceeding with
7896 retx then drxretx timer should be stopped.*/
7900 /*Stop the DRX retransmission timer as UE scheduled for retx. Here
7901 * we stop the timer and inactivate the UE for both UL and DL.
7902 * This may result in loss of one slot for UL but this trade
7903 * off is taken to avoid the overhead of maintaining a list of UEs
7904 * to be inactivated in the next slot.*/
7905 drxHq = RG_SCH_DRX_GET_DL_HQ(dlHq);
7906 drxUe = RG_SCH_DRX_GET_UE(ueCb);
7907 if(drxHq->reTxIndx != DRX_INVALID)
7909 /* This condition should never occur */
7910 if(drxHq->reTxIndx >= RG_SCH_MAX_DRXQ_SIZE)
7912 DU_LOG("\nERROR --> SCH : [%d]UE:DRXUE RETX IDX[%d]"
7913 "is out of bound,dlInactvMask %d,procId %d\n", ueCb->ueId,
7914 drxHq->reTxIndx,ueCb->dl.dlInactvMask, dlHq->procId);
7917 drxUe->drxDlInactvMaskPerCell[cellIdx] |= (RG_SCH_DRX_DLHQ_BITMASK << dlHq->procId);
7918 drxUe->drxUlInactvMaskPerCell[cellIdx] |= (RG_SCH_DRX_DLHQ_BITMASK << dlHq->procId);
7920 dlInactvMask = RG_SCH_DRX_DLHQ_BITMASK << dlHq->procId;
7921 ulInactvMask = RG_SCH_DRX_DLHQ_BITMASK << dlHq->procId;
7923 for(cellIdx = 0; cellIdx < CM_LTE_MAX_CELLS; cellIdx++)
7925 dlInactvMask &= drxUe->drxDlInactvMaskPerCell[cellIdx];
7926 ulInactvMask &= drxUe->drxUlInactvMaskPerCell[cellIdx];
7929 drxUe->drxDlInactvMask |= dlInactvMask;
7930 drxUe->drxUlInactvMask |= ulInactvMask;
7932 /* if no other condition is keeping ue active,
7935 if(!RG_SCH_DRX_DL_IS_UE_ACTIVE(drxUe))
7937 /* BUG 2 : HARQ_RTT, changed for consistency */
7938 ueCb->dl.dlInactvMask |= (RG_DRX_INACTIVE);
7940 /* Add to DL inactive list */
7941 cmLListAdd2Tail(dlInActvLst,&(ueCb->dlDrxInactvLnk));
7942 ueCb->dlDrxInactvLnk.node = (PTR)ueCb;
7945 if(!RG_SCH_DRX_UL_IS_UE_ACTIVE(drxUe))
7947 /*BUG 2: HARQ_RTT changed for consistency */
7948 ueCb->ul.ulInactvMask |= (RG_DRX_INACTIVE);
7950 cmLListAdd2Tail(ulInActvLst,&(ueCb->ulDrxInactvLnk));
7951 ueCb->ulDrxInactvLnk.node = (PTR)ueCb;
7954 /* Deleting entry from HARQ RTT queue for the same HARQ proc,
7955 * if exist. This is the special case which can happen iF UL
7956 * scheduling is done later. */
7957 if(drxHq->rttIndx != DRX_INVALID)
7959 cmLListDelFrm (&(cellCb->drxCb->drxQ[drxHq->rttIndx].harqRTTQ),
7960 &(drxHq->harqRTTEnt));
7962 drxHq->rttIndx = DRX_INVALID;
7965 cmLListDelFrm (&(drxCell->drxQ[drxHq->reTxIndx].harqRetxQ),
7966 &(drxHq->harqRetxEnt));
7967 drxHq->reTxIndx = DRX_INVALID;
7974 if(ueCb->drxCb->raRcvd == TRUE)
7976 ueCb->drxCb->raRcvd = FALSE;
7978 /* mark the ra bit */
7979 ueCb->drxCb->drxUlInactvMask |= RG_SCH_DRX_RA_BITMASK;
7980 ueCb->drxCb->drxDlInactvMask |= RG_SCH_DRX_RA_BITMASK;
7982 }/*if(ra->rcvd) == TRUE */
7984 if(ueCb->dlDrxInactvTmrLnk.node == NULLP)
7986 cmLListAdd2Tail(dlDrxInactvTmrLst,&(ueCb->dlDrxInactvTmrLnk));
7987 ueCb->dlDrxInactvTmrLnk.node = (PTR)ueCb;
7989 }/*if(isNewTx == TRUE) */
7992 }/* rgSCHUtlGetSchdUes*/
7994 /* ccpu00117452 - MOD - Changed macro name from
7995 RGR_RRM_DLPWR_CNTRL to RGR_CQI_REPT */
7998 * @brief This function fills StaInd struct
8002 * Function: rgSCHUtlFillSndStaInd
8003 * Purpose: Fills StaInd struct and sends the
8006 * @param[in] RgSchCellCb *cell pointer to Cell Control block
8007 * @param[in] RgSchUeCb *ue pointer to Ue Control block
8008 * @param[in] RgrStaIndInfo *staInfo Sta Ind struct to be filled
8009 * @param[in] uint8_t numCqiRept NUmber of reports to be filled
8013 S16 rgSCHUtlFillSndStaInd(RgSchCellCb *cell,RgSchUeCb *ue,RgrStaIndInfo *staInfo,uint8_t numCqiRept)
8017 /* Fill StaInd for sending collated Latest N CQI rpeorts */
8018 /* Find index in the array from where Latest N
8019 reports needs to be fetched. Use this value to index in the array
8020 and copy the reports into staInfo */
8022 /* Fill the Cell Id of PCC of the UE */
8023 staInfo->cellId = ue->cell->cellId;
8024 staInfo->crnti = ue->ueId;
8026 idxStart = ue->schCqiInfo.cqiCount - numCqiRept;
8028 memcpy (&(staInfo->ueCqiInfo.cqiRept),
8029 &(ue->schCqiInfo.cqiRept[idxStart]),
8030 numCqiRept * sizeof(RgrUeCqiRept));
8032 staInfo->ueCqiInfo.numCqiRept = numCqiRept;
8034 ue->schCqiInfo.cqiCount = 0;
8036 /* Call utility function (rgSCHUtlRgrStaInd) to send rpts to RRM */
8037 if(rgSCHUtlRgrStaInd(cell, staInfo) != ROK)
8039 DU_LOG("\nERROR --> SCH : Could not send "
8040 "CQI reports for RNTI:%d",ue->ueId);
8046 }/* End of rgSCHUtlFillSndStaInd */
8051 * @brief API for sending STA indication from Scheduler to RRM.
8055 * Function: rgSCHUtlRgrStaInd
8057 * This API is invoked to send STA indication from Scheduler instance to RRM.
8058 * This API fills in Pst structure and RgrStaIndInfo
8059 * and calls the Sta primitive API towards RRM.
8061 * @param[in] cell RgSchCellCb
8062 * @param[in] RgrStsIndInfo *rgrSta
8067 S16 rgSCHUtlRgrStaInd(RgSchCellCb *cell,RgrStaIndInfo *rgrSta)
8070 RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
8072 rgrSap = cell->rgrSap;
8073 if (rgrSap->sapSta.sapState != LRG_BND)
8075 DU_LOG("\nERROR --> SCH : rgSCHUtlRgrStaInd() Upper SAP not bound (%d) ",
8076 rgrSap->sapSta.sapState);
8079 RgUiRgrStaInd(&(cell->rgrSap->sapCfg.sapPst),
8080 cell->rgrSap->sapCfg.suId, rgrSta);
8082 } /* rgSCHUtlRgrStaInd*/
8083 #endif /* End of RGR_CQI_REPT */
8085 /* Fix : syed HO UE does not have a valid ue->rntiLnk */
8087 * @brief Indicates MAC to release any rnti context it has.
8090 * Function : rgSCHUtlIndRntiRls2Mac
8091 * This function indicates MAC for this rnti release.
8092 * In case of ueId change it will indicate MAC
8093 * about the new rnti to be updated.
8094 * It will post a release RNTI indication to MAC.
8098 * @param[in] RgSchCellCb *cell
8099 * @param[in] CmLteRnti rnti
8100 * @param[in] Bool ueIdChng
8101 * @param[in] CmLteRnti newRnti
8105 Void rgSCHUtlIndRntiRls2Mac(RgSchCellCb *cell,CmLteRnti rnti,Bool ueIdChng,CmLteRnti newRnti)
8108 Inst inst = cell->instIdx;
8109 RgInfRlsRnti rntiInfo;
8112 /* Copy the info to rntiInfo */
8113 rntiInfo.cellId = cell->cellId;
8114 rntiInfo.rnti = rnti;
8115 /* Fix : syed ueId change as part of reestablishment.
8116 * Now SCH to trigger this. CRG ueRecfg for ueId change
8118 rntiInfo.ueIdChng = ueIdChng;
8119 rntiInfo.newRnti = newRnti;
8121 rntiInfo.isUeSCellDel = FALSE;
8123 /* Invoke MAC to release the rnti */
8124 rgSCHUtlGetPstToLyr(&pst, &rgSchCb[inst], cell->macInst);
8125 RgSchMacRlsRnti(&pst, &rntiInfo);
8129 /* LTE_ADV_FLAG_REMOVED_START */
8131 * @brief API for sending LOAD INF indication from Scheduler to RRM.
8134 * Function: rgSCHUtlRgrLoadInfInd
8136 * This API is invoked to send LOAD INF indication from Scheduler instance to RRM.
8137 * This API fills in Pst structure and RgrLoadInfIndInfo
8138 * and calls the Sta primitive API towards RRM.
8140 * @param[in] cell RgSchCellCb
8141 * @param[in] RgrLoadInfIndInfo *rgrLoadInf
8146 S16 rgSCHUtlRgrLoadInfInd(RgSchCellCb *cell,RgrLoadInfIndInfo *rgrLoadInf)
8149 RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
8151 rgrSap = cell->rgrSap;
8152 if (rgrSap->sapSta.sapState != LRG_BND)
8154 DU_LOG("\nERROR --> SCH : rgSCHUtlRgrLoadInfInd() Upper SAP not bound (%d) ",
8155 rgrSap->sapSta.sapState);
8158 RgUiRgrLoadInfInd(&(cell->rgrSap->sapCfg.sapPst),
8159 cell->rgrSap->sapCfg.suId, rgrLoadInf);
8161 } /* rgSCHUtlRgrLoadInfInd*/
8162 /* LTE_ADV_FLAG_REMOVED_END */
8164 /* MS_FIX : syed SCH to act as MASTER in maintaining
8165 * rnti related context. Trigger to rnti del/Chng at SCH
8166 * will result in a Indication to MAC to release its
8167 * RNTI context. MAC inturn indicates the context cleared
8168 * indication to SCH, upon which SCH would set this
8170 * @brief API for sending STA indication from Scheduler to RRM.
8174 * Function: rgSCHUtlRlsRnti
8176 * This API is invoked to indicate MAC to release rnti
8178 * @param[in] RgSchCellCb *cellCb
8179 * @param[in] RgSchRntiLnk *rntiLnk,
8180 * @param[in] Bool ueIdChngd,
8181 * @param[in] CmLteRnti newRnti
8185 Void rgSCHUtlRlsRnti(RgSchCellCb *cell,RgSchRntiLnk *rntiLnk,Bool ueIdChngd,CmLteRnti newRnti)
8188 uint8_t isLegacy = 0;
8190 if(cell->emtcEnable)
8192 rgSCHEmtcUtlRlsRnti(cell, rntiLnk, &isLegacy);
8197 /*Add to Guard Pool*/
8198 cmLListAdd2Tail(&cell->rntiDb.rntiGuardPool, &rntiLnk->rntiGrdPoolLnk);
8199 rntiLnk->rntiGrdPoolLnk.node = (PTR)rntiLnk;
8201 /* Fix: syed Explicitly Inidcate MAC to release RNTI */
8202 rgSCHUtlIndRntiRls2Mac(cell, rntiLnk->rnti, ueIdChngd, newRnti);
8209 * @brief This function fills StaInd struct
8213 * Function: rgSCHUtlFillSndUeStaInd
8214 * Purpose: Fills StaInd struct and sends the
8217 * @param[in] RgSchCellCb *cell pointer to Cell Control block
8218 * @param[in] RgSchUeCb *ue pointer to Ue Control block
8219 * @param[in] uint8_t numCqiRept NUmber of reports to be filled
8223 S16 rgSCHUtlFillSndUeStaInd(RgSchCellCb *cell,RgSchUeCb *ue,RgrUeStaIndInfo *ueStaInfo)
8226 ueStaInfo->cellId = cell->cellId;
8227 ueStaInfo->crnti = ue->ueId;
8229 /* Call utility function (rgSCHUtlRgrUeStaInd) to send rpts to RRM */
8230 if(rgSCHUtlRgrUeStaInd(cell, ueStaInfo) != ROK)
8232 DU_LOG("\nERROR --> SCH : Could not send "
8233 "UE Sta reports CRNTI:%d",ue->ueId);
8239 }/* End of rgSCHUtlFillSndStaInd */
8244 * @brief API for sending STA indication from Scheduler to RRM.
8248 * Function: rgSCHUtlRgrStaInd
8250 * This API is invoked to send STA indication from Scheduler instance to RRM.
8251 * This API fills in Pst structure and RgrStaIndInfo
8252 * and calls the Sta primitive API towards RRM.
8254 * @param[in] cell RgSchCellCb
8255 * @param[in] RgrStsIndInfo *rgrSta
8260 S16 rgSCHUtlRgrUeStaInd(RgSchCellCb *cell,RgrUeStaIndInfo *rgrUeSta)
8263 RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
8265 rgrSap = cell->rgrSap;
8266 if (rgrSap->sapSta.sapState != LRG_BND)
8268 DU_LOG("\nERROR --> SCH : rgSCHUtlRgrUeStaInd() Upper SAP not bound (%d) ",
8269 rgrSap->sapSta.sapState);
8272 RgUiRgrUeStaInd(&(cell->rgrSap->sapCfg.sapPst),
8273 cell->rgrSap->sapCfg.suId, rgrUeSta);
8275 } /* rgSCHUtlRgrStaInd*/
8279 * @brief function to report DL and UL PRB usage to RRM.
8282 * Function: rgSCHUtlUpdAvgPrbUsage
8283 * This function sends the PRB usage report to
8284 * RRM with the interval configured by RRM.
8286 * @param[in] cell *RgSchCellCb
8291 S16 rgSCHUtlUpdAvgPrbUsage(RgSchCellCb *cell)
8293 CmLteTimingInfo frm;
8294 RgmPrbRprtInd *prbRprtInd;
8297 #ifdef DBG_MAC_RRM_PRB_PRINT
8298 static uint32_t count = 0;
8299 const uint32_t reprotForEvery20Sec = 20000/cell->prbUsage.rprtPeriod;
8304 frm = cell->crntTime;
8305 RGSCH_INCR_SUB_FRAME(frm, RG_SCH_CMN_DL_DELTA);
8311 if(cell->prbUsage.rprtPeriod >= RGSCH_NUM_SUB_FRAMES)
8313 /* Get the total number of DL and UL slots within the reporting period*/
8314 numDlSf = (cell->prbUsage.rprtPeriod *
8315 rgSchTddNumDlSubfrmTbl[cell->ulDlCfgIdx][RGSCH_NUM_SUB_FRAMES-1])
8316 / RGSCH_NUM_SUB_FRAMES;
8317 numUlSf = (cell->prbUsage.rprtPeriod *
8318 rgSchTddNumUlSubfrmTbl[cell->ulDlCfgIdx][RGSCH_NUM_SUB_FRAMES-1])
8319 / RGSCH_NUM_SUB_FRAMES;
8323 /* Get the total number of DL and UL slots < 10 ms interval */
8324 numDlSf = rgSchTddNumDlSubfrmTbl[cell->ulDlCfgIdx][frm.slot];
8325 numUlSf = rgSchTddNumUlSubfrmTbl[cell->ulDlCfgIdx][frm.slot];
8328 numDlSf = cell->prbUsage.rprtPeriod;
8329 numUlSf = cell->prbUsage.rprtPeriod;
8332 SCH_ALLOC(prbRprtInd, sizeof(RgmPrbRprtInd));
8333 if(prbRprtInd == NULLP)
8335 DU_LOG("\nERROR --> SCH : Failed to allocate memory for prbRprtInd");
8339 memset(&prbRprtInd->stQciPrbRpts[0],
8341 (RGM_MAX_QCI_REPORTS * sizeof(RgmPrbRptPerQci)));
8343 prbRprtInd->bCellId = cell->cellId;
8347 prbRprtInd->bPrbUsageMask |= RGM_PRB_USAGE_DL;
8348 for (idx = 0; idx < RGM_MAX_QCI_REPORTS; idx++ )
8350 prbRprtInd->stQciPrbRpts[idx].bAvgPrbDlUsage =
8351 RGSCH_DIV_ROUND((cell->prbUsage.qciPrbRpts[idx].dlTotPrbUsed*100),
8352 (numDlSf * cell->bwCfg.dlTotalBw));
8353 prbRprtInd->stQciPrbRpts[idx].bQci = cell->prbUsage.qciPrbRpts[idx].qci;
8354 cell->prbUsage.qciPrbRpts[idx].dlTotPrbUsed = 0;
8360 prbRprtInd->bPrbUsageMask |= RGM_PRB_USAGE_UL;
8361 for (idx = 0; idx < RGM_MAX_QCI_REPORTS; idx++ )
8363 prbRprtInd->stQciPrbRpts[idx].bAvgPrbUlUsage =
8364 RGSCH_DIV_ROUND((cell->prbUsage.qciPrbRpts[idx].ulTotPrbUsed*100),
8365 (numUlSf * cell->ulAvailBw));
8366 prbRprtInd->stQciPrbRpts[idx].bQci = cell->prbUsage.qciPrbRpts[idx].qci;
8367 cell->prbUsage.qciPrbRpts[idx].ulTotPrbUsed = 0;
8371 #ifdef DBG_MAC_RRM_PRB_PRINT
8372 if((count % reprotForEvery20Sec) == 0 )
8374 DU_LOG("\n====================================================================");
8375 DU_LOG("\nINFO --> SCH : QCI-1[DL:UL] | QCI-2[DL:UL] | QCI-3[DL:UL] | QCI-4[DL:UL] \n");
8376 DU_LOG("======================================================================\n");
8377 DU_LOG(" [%d: %d]\t | [%d: %d]\t | [%d: %d]\t| [%d: %d]\t\n",
8378 prbRprtInd->stQciPrbRpts[0].bAvgPrbDlUsage,
8379 prbRprtInd->stQciPrbRpts[0].bAvgPrbUlUsage,
8380 prbRprtInd->stQciPrbRpts[1].bAvgPrbDlUsage,
8381 prbRprtInd->stQciPrbRpts[1].bAvgPrbUlUsage,
8382 prbRprtInd->stQciPrbRpts[2].bAvgPrbDlUsage,
8383 prbRprtInd->stQciPrbRpts[2].bAvgPrbUlUsage,
8384 prbRprtInd->stQciPrbRpts[3].bAvgPrbDlUsage,
8385 prbRprtInd->stQciPrbRpts[3].bAvgPrbUlUsage);
8388 RgUiRgmSendPrbRprtInd(&(cell->rgmSap->sapCfg.sapPst),
8389 cell->rgmSap->sapCfg.suId, prbRprtInd);
8397 * @brief This function resends the Ta in case of
8398 * max retx failure or DTX for the Ta transmitted
8402 * Function: rgSCHUtlReTxTa
8405 * @param[in] RgSchCellCb *cell
8406 * @param[in] RgSchUeCb *ue
8410 Void rgSCHUtlReTxTa(RgSchCellCb *cellCb,RgSchUeCb *ueCb)
8413 /* If TA Timer is running. Stop it */
8414 if (ueCb->taTmr.tmrEvnt != TMR_NONE)
8416 rgSCHTmrStopTmr(cellCb, ueCb->taTmr.tmrEvnt, ueCb);
8418 /*[ccpu00121813]-ADD-If maxretx is reached then
8419 * use outstanding TA val for scheduling again */
8420 if(ueCb->dl.taCb.outStndngTa == TRUE)
8422 ueCb->dl.taCb.ta = ueCb->dl.taCb.outStndngTaval;
8423 ueCb->dl.taCb.outStndngTaval = RGSCH_NO_TA_RQD;
8424 ueCb->dl.taCb.outStndngTa = FALSE;
8427 /* Fix : syed TA state updation missing */
8428 ueCb->dl.taCb.state = RGSCH_TA_TOBE_SCHEDULED;
8429 rgSCHUtlDlTARpt(cellCb, ueCb);
8434 /* Added function for dropping Paging Message*/
8436 * @brief Handler for BO Updt received for BCCH or PCCH.
8440 * Function : rgSCHChkBoUpdate
8442 * This function shall check for BO received falls within the scheduling window or not
8445 * @param[in] RgSchCellCb *cell
8450 static S16 rgSCHChkBoUpdate(RgSchCellCb *cell,RgInfCmnBoRpt *boUpdt)
8453 uint32_t crntTimeInSubFrms = 0;
8454 uint32_t boUpdTimeInSubFrms = 0;
8455 uint32_t distance = 0;
8457 crntTimeInSubFrms = (cell->crntTime.sfn * RGSCH_NUM_SUB_FRAMES_5G) + cell->crntTime.slot +
8458 RG_SCH_CMN_DL_DELTA + 2; /* As bo received will scheduled in next TTI
8459 so incrementing with +1 more */
8460 boUpdTimeInSubFrms = (boUpdt->u.timeToTx.sfn * RGSCH_NUM_SUB_FRAMES_5G)+ boUpdt->u.timeToTx.slot;
8463 distance = boUpdTimeInSubFrms > crntTimeInSubFrms ? \
8464 boUpdTimeInSubFrms - crntTimeInSubFrms : \
8465 (RGSCH_MAX_SUBFRM_5G - crntTimeInSubFrms + boUpdTimeInSubFrms);
8467 if (distance > RGSCH_PCCHBCCH_WIN)
8473 }/*rgSCHChkBoUpdate*/
8478 * @brief Utility function to calculate the UL reTxIdx in TDD cfg0
8482 * Function : rgSchUtlCfg0ReTxIdx
8484 * Update the reTxIdx according to the rules mentioned
8485 * in 3GPP TS 36.213 section 8 for TDD Cfg0
8487 * @param[in] RgSchCellCb *cell
8488 * @param[in] CmLteTimingInfo phichTime
8489 * @param[in] uint8_t hqFdbkIdx
8492 uint8_t rgSchUtlCfg0ReTxIdx(RgSchCellCb *cell,CmLteTimingInfo phichTime,uint8_t hqFdbkIdx)
8494 uint8_t reTxIdx = RGSCH_INVALID_INFO;
8496 RgSchCmnUlCell *cellUl = RG_SCH_CMN_GET_UL_CELL(cell);
8498 uint8_t ulSF; /* UL SF in the TDD frame */
8500 ulSf = &cellUl->ulSfArr[hqFdbkIdx];
8501 ulSF = ulSf->ulSfIdx;
8503 /* Check for the UL SF 4 or 9 */
8504 if(ulSF == 9 || ulSF == 4)
8508 if(phichTime.slot == 0 || phichTime.slot == 5)
8512 /* Retx will happen according to the Pusch k table */
8513 reTxIdx = cellUl->schdIdx;
8517 /* Retx will happen at n+7 */
8518 RGSCHCMNADDTOCRNTTIME(phichTime, phichTime, 7);
8519 /* Fetch the corresponding UL slot Idx in UL sf array */
8520 reTxIdx = rgSCHCmnGetUlSfIdx(&phichTime, cell);
8523 else if(phichTime.slot == 1 || phichTime.slot == 6)
8525 /* Retx will happen at n+7 */
8526 RGSCHCMNADDTOCRNTTIME(phichTime, phichTime, 7);
8527 /* Fetch the corresponding UL slot Idx in UL sf array */
8528 reTxIdx = rgSCHCmnGetUlSfIdx(&phichTime, cell);
8535 * @brief Utility function to calculate total num of PRBs required to
8536 * satisfy DL BO for TM1/TM2/TM6/TM7
8540 * Function : rgSchUtlDlCalc1CwPrb
8542 * Calculate PRBs required for UE to satisfy BO in DL
8544 * Note : Total calculated PRBs will be assigned to *prbReqrd
8547 * @param[in] RgSchCellCb *cell
8548 * @param[in] RgSchUeCb *ue
8549 * @param[in] uint32_t bo
8550 * @param[out] uint32_t *prbReqrd
8553 Void rgSchUtlDlCalc1CwPrb(RgSchCellCb *cell,RgSchUeCb *ue,uint32_t bo,uint32_t *prbReqrd)
8555 RgSchCmnDlCell *dlCell = RG_SCH_CMN_GET_DL_CELL(cell);
8556 RgSchCmnDlUe *dlUe = RG_SCH_CMN_GET_DL_UE(ue, cell);
8560 uint8_t cfi = dlCell->currCfi;
8562 iTbs = dlUe->mimoInfo.cwInfo[0].iTbs[0];
8563 eff = (*(RgSchCmnTbSzEff *)(dlCell->cqiToEffTbl[0][cfi]))[iTbs];
8565 /* Optimization to convert totalBo (which is in-terms of bytes) to bits
8566 * i.e, << 3 and multiply with 1024 i.e, << 10 */
8567 noRes = ((uint64_t)((bo << 3) << 10)) / (eff);
8568 /* Get the number of RBs needed for this transmission */
8569 /* Number of RBs = No of REs / No of REs per RB */
8570 *prbReqrd = RGSCH_CEIL(noRes, dlCell->noResPerRb[cfi]);
8573 } /* rgSchUtlDlCalc1CwPrb*/
8576 * @brief Utility function to calculate total num of PRBs required to
8577 * satisfy DL BO(BO sum of all logical channels for that UE or an LC BO)
8582 * Function : rgSchUtlDlCalc2CwPrb
8584 * Calculate PRBs required for UE to satisfy BO in DL
8586 * Note : Total calculated PRBs will be assigned to *prbReqrd
8589 * @param[in] RgSchCellCb *cell
8590 * @param[in] RgSchUeCb *ue
8591 * @param[in] uint32_t bo
8592 * @param[out] uint32_t *prbReqrd
8595 Void rgSchUtlDlCalc2CwPrb(RgSchCellCb *cell,RgSchUeCb *ue,uint32_t bo,uint32_t *prbReqrd)
8597 RgSchCmnDlCell *dlCell = RG_SCH_CMN_GET_DL_CELL(cell);
8598 RgSchCmnDlUe *dlUe = RG_SCH_CMN_GET_DL_UE(ue, cell);
8599 uint32_t eff1, eff2;
8601 uint8_t noLyr1, noLyr2;
8602 uint8_t iTbs1, iTbs2;
8603 uint8_t cfi = dlCell->currCfi;
8605 if ((dlUe->mimoInfo.forceTD) ||/* Transmit Diversity (TD) */
8606 (dlUe->mimoInfo.ri < 2))/* 1 layer precoding */
8608 iTbs1 = dlUe->mimoInfo.cwInfo[0].iTbs[0];
8609 eff1 = (*(RgSchCmnTbSzEff *)(dlCell->cqiToEffTbl[0][cfi]))[iTbs1];
8611 /* Optimization to convert totalBo (which is in-terms of bytes) to bits
8612 * i.e, << 3 and multiply with 1024 i.e, << 10 */
8613 noRes = ((uint64_t)((bo << 3) << 10)) / (eff1);
8614 /* Get the number of RBs needed for this transmission */
8615 /* Number of RBs = No of REs / No of REs per RB */
8616 *prbReqrd = RGSCH_CEIL(noRes, dlCell->noResPerRb[cfi]);
8620 noLyr1 = dlUe->mimoInfo.cwInfo[0].noLyr;
8621 noLyr2 = dlUe->mimoInfo.cwInfo[1].noLyr;
8622 iTbs1 = dlUe->mimoInfo.cwInfo[0].iTbs[noLyr1 - 1];
8623 iTbs2 = dlUe->mimoInfo.cwInfo[1].iTbs[noLyr2 - 1];
8624 eff1 = (*(RgSchCmnTbSzEff *)(dlCell->cqiToEffTbl[noLyr1 - 1][cfi]))[iTbs1];
8625 eff2 = (*(RgSchCmnTbSzEff *)(dlCell->cqiToEffTbl[noLyr2 - 1][cfi]))[iTbs2];
8627 /* Optimization to convert totalBo (which is in-terms of bytes) to bits
8628 * i.e, << 3 and multiply with 1024 i.e, << 10 */
8629 noRes = ((uint64_t)((bo << 3) << 10)) / (eff1 + eff2);
8630 /* Get the number of RBs needed for this transmission */
8631 /* Number of RBs = No of REs / No of REs per RB */
8632 *prbReqrd = RGSCH_CEIL(noRes, dlCell->noResPerRb[cfi]);
8635 } /* rgSchUtlDlCalc2CwPrb */
8638 * @brief Utility function to calculate total num of PRBs required to
8639 * satisfy DL BO(BO sum of all logical channels for that UE or an LC BO)
8643 * Function : rgSchUtlCalcTotalPrbReq
8645 * This function calls TM specific routine to calculate PRB
8648 * @param[in] RgSchCellCb *cell
8649 * @param[in] RgSchUeCb *ue
8650 * @param[in] uint32_t bo
8651 * @param[out] uint32_t *prbReqrd
8654 Void rgSchUtlCalcTotalPrbReq(RgSchCellCb *cell,RgSchUeCb *ue,uint32_t bo,uint32_t *prbReqrd)
8656 /* Call TM specific Prb calculation routine */
8657 (dlCalcPrbFunc[ue->mimoInfo.txMode - 1])(cell, ue, bo, prbReqrd);
8660 } /* rgSchUtlCalcTotalPrbReq */
8663 /***********************************************************
8665 * Func : rgSCHUtlFetchPcqiBitSz
8668 * Desc : Fetch the CQI/PMI bits for a UE based on the mode, periodicity.
8677 **********************************************************/
8678 static uint8_t rgSCHUtlFetchPcqiBitSz(RgSchCellCb *cell, RgSchUeCb *ueCb,uint8_t numTxAnt)
8680 uint8_t confRepMode;
8683 RgSchUePCqiCb *cqiCb = RG_SCH_GET_UE_CELL_CQI_CB(ueCb,cell);
8685 confRepMode = cqiCb->cqiCfg.cqiSetup.prdModeEnum;
8686 if((ueCb->mimoInfo.txMode != RGR_UE_TM_3) &&
8687 (ueCb->mimoInfo.txMode != RGR_UE_TM_4))
8693 ri = cqiCb->perRiVal;
8697 case RGR_PRD_CQI_MOD10:
8703 case RGR_PRD_CQI_MOD11:
8716 else if(numTxAnt == 4)
8729 /* This is number of antenna case 1.
8730 * This is not applicable for Mode 1-1.
8731 * So setting it to invalid value */
8737 case RGR_PRD_CQI_MOD20:
8745 pcqiSz = 4 + cqiCb->label;
8750 case RGR_PRD_CQI_MOD21:
8765 else if(numTxAnt == 4)
8778 /* This might be number of antenna case 1.
8779 * For mode 2-1 wideband case only antenna port 2 or 4 is supported.
8780 * So setting invalid value.*/
8788 pcqiSz = 4 + cqiCb->label;
8792 pcqiSz = 7 + cqiCb->label;
8808 * @brief Utility function to returns the number of subbands based on the
8813 * Function : rgSchUtlGetNumSbs
8815 * Calculate the number of PRBs
8816 * Update the subbandRequired based on the nPrbs and subband size
8818 * @param[in] RgSchCellCb *cell
8819 * @param[in] RgSchUeCb *ue
8820 * @param[in] uint32_t *numSbs
8823 uint8_t rgSchUtlGetNumSbs(RgSchCellCb *cell,RgSchUeCb *ue,uint32_t *numSbs)
8826 //Currently hardcoding MAX prb for each UE
8827 nPrb = ue->ue5gtfCb.maxPrb;
8828 (*numSbs) = RGSCH_CEIL(nPrb, MAX_5GTF_VRBG_SIZE);
8833 * @brief Utility function to insert the UE node into UE Lst based on the
8834 * number of subbands allocated for the UE for the current TTI.
8838 * Function : rgSchUtlSortInsUeLst
8840 * If subbandRequired < Min, then insert at head
8841 * Else If subbandRequired > Max, then insert at tail
8842 * Else, traverse the list and place the node at the appropriate place
8844 * @param[in] RgSchCellCb *cell
8845 * @param[in] RgSchUeCb *ue
8848 uint8_t rgSchUtlSortInsUeLst(RgSchCellCb *cell,CmLListCp *ueLst,CmLList *node,uint8_t vrbgRequired)
8851 CmLList *firstUeInLst;
8852 CmLList *lastUeInLst;
8856 //firstUeInLst = cmLListFirst(ueLst);
8857 CM_LLIST_FIRST_NODE(ueLst,firstUeInLst);
8858 if(NULLP == firstUeInLst)
8860 /* first node to be added to the list */
8861 cmLListAdd2Tail(ueLst, node);
8865 /* Sb Required for the UE is less than the first node in the list */
8866 tempUe = (RgSchUeCb *)(firstUeInLst->node);
8867 ueUl = RG_SCH_CMN_GET_UL_UE(tempUe, cell);
8869 if(vrbgRequired <= ueUl->vrbgRequired)
8871 cmLListInsCrnt(ueLst, (node));
8875 /* Sb Required for this UE is higher than the UEs in the list */
8876 lastUeInLst = cmLListLast(ueLst);
8877 tempUe = (RgSchUeCb *)(lastUeInLst->node);
8878 if(vrbgRequired >= ueUl->vrbgRequired)
8880 cmLListAdd2Tail(ueLst, (node));
8884 /* This UE needs to be in the middle. Search and insert the UE */
8885 ueInLst = cmLListFirst(ueLst);
8888 tempUe = (RgSchUeCb *)(ueInLst->node);
8890 if(vrbgRequired <= ueUl->vrbgRequired)
8892 cmLListInsCrnt(ueLst, (node));
8896 ueInLst = cmLListNext(ueLst);
8898 } while(NULLP != ueInLst && ueInLst != firstUeInLst);
8907 * @brief Function to Send LCG GBR register to MAC
8911 * Function: rgSCHUtlBuildNSendLcgReg
8913 * Handler for sending LCG GBR registration
8920 * @param[in] RgSchCellCb *cell
8921 * @param[in] CmLteRnti crnti
8922 * @param[in] uint8_t lcgId
8923 * @param[in] Bool isGbr
8927 S16 rgSCHUtlBuildNSendLcgReg(RgSchCellCb *cell,CmLteRnti crnti,uint8_t lcgId,Bool isGbr)
8930 RgInfLcgRegReq lcgRegReq;
8932 memset(&pst, 0, sizeof(Pst));
8933 lcgRegReq.isGbr = isGbr;
8934 lcgRegReq.cellId = cell->cellId;
8935 lcgRegReq.crnti = crnti;
8936 lcgRegReq.lcgId = lcgId;
8937 rgSCHUtlGetPstToLyr(&pst, &rgSchCb[cell->instIdx], cell->macInst);
8938 /* code Coverage portion of the test case */
8939 RgSchMacLcgReg(&pst, &lcgRegReq);
8948 * @brief Function to map RGR pucch type to TFU type
8952 * Function: rgSchUtlGetFdbkMode
8960 * @param[in] RgrSchFrmt1b3TypEnum
8961 * @return TfuAckNackMode
8964 TfuAckNackMode rgSchUtlGetFdbkMode(RgrSchFrmt1b3TypEnum fdbkType)
8967 TfuAckNackMode mode = TFU_UCI_FORMAT_1A_1B;
8971 case RG_SCH_UCI_FORMAT_NON_CA:
8972 case RG_SCH_UCI_FORMAT1A_1B:
8974 mode = TFU_UCI_FORMAT_1A_1B;
8977 case RG_SCH_UCI_FORMAT1B_CS:
8979 mode = TFU_UCI_FORMAT_1B_CS;
8982 case RG_SCH_UCI_FORMAT3:
8984 mode = TFU_UCI_FORMAT_3;
8990 #endif /* TFU_TDD */
8991 #endif /* LTE_ADV */
8992 #endif /*TFU_UPGRADE */
8996 * @brief Send Ue SCell delete to SMAC.
9000 * Function : rgSCHUtlSndUeSCellDel2Mac
9001 * This function populates the struct RgInfRlsRnti and
9002 * get the pst for SMac and mark field isUeSCellDel to TRUE which
9003 * indicates that it is a Ue SCell delete.
9007 * @param[in] RgSchCellCb *cell
9008 * @param[in] CmLteRnti rnti
9012 Void rgSCHUtlSndUeSCellDel2Mac(RgSchCellCb *cell,CmLteRnti rnti)
9015 Inst inst = cell->instIdx;
9016 RgInfRlsRnti rntiInfo;
9018 DU_LOG("\nINFO --> SCH : RNTI Release IND for UE(%d)\n", rnti);
9019 /* Copy the info to rntiInfo */
9020 rntiInfo.cellId = cell->cellId;
9021 rntiInfo.rnti = rnti;
9022 /* Fix : syed ueId change as part of reestablishment.
9023 * Now SCH to trigger this. CRG ueRecfg for ueId change
9025 rntiInfo.ueIdChng = FALSE;
9026 rntiInfo.newRnti = rnti;
9027 rntiInfo.isUeSCellDel = TRUE;
9028 /* Invoke MAC to release the rnti */
9029 rgSCHUtlGetPstToLyr(&pst, &rgSchCb[inst], cell->macInst);
9030 RgSchMacRlsRnti(&pst, &rntiInfo);
9035 * @brief Returns max TB supported by a given txMode
9039 * Function : rgSCHUtlGetMaxTbSupp
9040 * Max TB supported for TM Modes (1,2,5,6 and 7) is 1
9044 * @param[in] RgrTxMode txMode
9045 * @return uint8_t maxTbCount;
9048 uint8_t rgSCHUtlGetMaxTbSupp(RgrTxMode txMode)
9074 return (maxTbCount);
9078 * @brief Send Ue SCell delete to SMAC.
9082 * Function : rgSCHTomUtlGetTrigSet
9083 * This function gets the triggerset based on cqiReq
9085 * @param[in] RgSchCellCb *cell
9086 * @param[in] RgSchUeCb ueCb
9087 * @param[in] uint8_t cqiReq,
9088 * @param[out] uint8_t *triggerSet
9093 Void rgSCHTomUtlGetTrigSet(RgSchCellCb *cell,RgSchUeCb *ueCb,uint8_t cqiReq,uint8_t *triggerSet)
9095 RgSchUeCellInfo *pCellInfo = RG_SCH_CMN_GET_PCELL_INFO(ueCb);
9098 case RG_SCH_APCQI_SERVING_CC:
9100 /* APeriodic CQI request for Current Carrier.*/
9101 uint8_t sCellIdx = ueCb->cellIdToCellIdxMap[RG_SCH_CELLINDEX(cell)];
9102 *triggerSet = 1 << (7 - sCellIdx);
9105 case RG_SCH_APCQI_1ST_SERVING_CCS_SET:
9107 *triggerSet = pCellInfo->acqiCb.aCqiCfg.triggerSet1;
9110 case RG_SCH_APCQI_2ND_SERVING_CCS_SET:
9112 *triggerSet = pCellInfo->acqiCb.aCqiCfg.triggerSet2;
9125 * @brief This function updates the value of UE specific DCI sizes
9129 * Function: rgSCHUtlUpdUeDciSize
9130 * Purpose: This function calculates and updates DCI Sizes in bits.
9132 * Invoked by: Scheduler
9134 * @param[in] RgSchCellCb *cell
9135 * @param[in] RgSchUeCb *ueCb
9136 * @param[in] isCsi2Bit *isCsi2Bit: is 1 bit or 2 bit CSI
9140 Void rgSCHUtlUpdUeDciSize(RgSchCellCb *cell,RgSchUeCb *ueCb,Bool isCsi2Bit)
9142 uint8_t dci01aCmnSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_0];
9143 uint8_t dci01aDedSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_0];
9144 if ((ueCb->accessStratumRls >= RGR_REL_10) && (cell->bwCfg.dlTotalBw >= cell->bwCfg.ulTotalBw))
9146 dci01aCmnSize += 1; /* Resource Allocation Type DCI 0 */
9147 dci01aDedSize += 1; /* Resource Allocation Type DCI 0 */
9149 if (isCsi2Bit == TRUE)
9151 dci01aDedSize += 2; /* 2 bit CSI DCI 0 */
9155 dci01aDedSize += 1; /* 1 bit CSI DCI 0 */
9158 /* Common CSI is always 1 bit DCI 0 */
9159 dci01aCmnSize += 1; /* 1 bit CSI DCI 0 */
9161 /* Compare the sizes of DCI 0 with DCI 1A and consider the greater */
9162 if (dci01aCmnSize < cell->dciSize.baseSize[TFU_DCI_FORMAT_1A])
9164 dci01aCmnSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_1A];
9166 if (dci01aDedSize < cell->dciSize.baseSize[TFU_DCI_FORMAT_1A])
9168 dci01aDedSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_1A];
9171 /* Remove the Ambiguous Sizes as mentioned in table Table 5.3.3.1.2-1 Spec 36.212-a80 Sec 5.3.3.1.3 */
9172 dci01aCmnSize += rgSchDciAmbigSizeTbl[dci01aCmnSize];
9173 dci01aDedSize += rgSchDciAmbigSizeTbl[dci01aDedSize];
9175 ueCb->dciSize.cmnSize[TFU_DCI_FORMAT_0] = dci01aCmnSize;
9176 ueCb->dciSize.cmnSize[TFU_DCI_FORMAT_1A] = dci01aCmnSize;
9178 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_0] = dci01aDedSize;
9179 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1A] = dci01aDedSize;
9181 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] = cell->dciSize.baseSize[TFU_DCI_FORMAT_1];
9183 /* Spec 36.212-a80 Sec 5.3.3.1.2: If the UE is configured to decode PDCCH with CRC scrambled
9184 * by the C-RNTI and the number of information bits in format 1 is equal to that for format 0/1A
9185 * for scheduling the same serving cell and mapped onto the UE specific search space given by the
9186 * C-RNTI as defined in [3], one bit of value zero shall be appended to format 1. */
9187 if (ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] == ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1A])
9189 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] += 1;
9192 /* Spec 36.212-a80 Sec 5.3.3.1.2: If the number of information bits in format 1 belongs
9193 * to one of the sizes in Table 5.3.3.1.2-1, one or more zero bit(s) shall be appended
9194 * to format 1 until the payload size of format 1 does not belong to one of the sizes in
9195 * Table 5.3.3.1.2-1 and is not equal to that of format 0/1A mapped onto the same search space. */
9196 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] += rgSchDciAmbigSizeTbl[ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1]];
9197 } while (ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] == ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1A]);
9199 /* Just copying the value of 2/2A to avoid multiple checks at PDCCH allocations. This values never change.*/
9200 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_2] = cell->dciSize.size[TFU_DCI_FORMAT_2];
9201 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_2A] = cell->dciSize.size[TFU_DCI_FORMAT_2A];
9202 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_2] = cell->dciSize.size[TFU_DCI_FORMAT_2];
9203 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_2A] = cell->dciSize.size[TFU_DCI_FORMAT_2A];
9205 /* Spec 36.212-a80 Sec 5.3.3.1.3: except when format 1A assigns downlink resource
9206 * on a secondary cell without an uplink configuration associated with the secondary cell */
9207 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A] = cell->dciSize.baseSize[TFU_DCI_FORMAT_1A];
9208 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A] += rgSchDciAmbigSizeTbl[ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A]];
9209 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] = cell->dciSize.baseSize[TFU_DCI_FORMAT_1];
9211 /* Spec 36.212-a80 Sec 5.3.3.1.2: If the UE is configured to decode PDCCH with CRC scrambled
9212 * by the C-RNTI and the number of information bits in format 1 is equal to that for format 0/1A
9213 * for scheduling the same serving cell and mapped onto the UE specific search space given by the
9214 * C-RNTI as defined in [3], one bit of value zero shall be appended to format 1. */
9215 if (ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] == ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A])
9217 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] += 1;
9220 /* Spec 36.212-a80 Sec 5.3.3.1.2: If the number of information bits in format 1 belongs
9221 * to one of the sizes in Table 5.3.3.1.2-1, one or more zero bit(s) shall be appended
9222 * to format 1 until the payload size of format 1 does not belong to one of the sizes in
9223 * Table 5.3.3.1.2-1 and is not equal to that of format 0/1A mapped onto the same search space. */
9224 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] += rgSchDciAmbigSizeTbl[ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1]];
9225 } while (ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] == ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A]);
9227 rgSCHEmtcUtlUpdUeDciSize(cell, ueCb);
9232 * @brief This function initialises the DCI Size table
9236 * Function: rgSCHUtlCalcDciSizes
9237 * Purpose: This function calculates and initialises DCI Sizes in bits.
9239 * Invoked by: Scheduler
9241 * @param[in] RgSchCellCb *cell
9245 Void rgSCHUtlCalcDciSizes(RgSchCellCb *cell)
9247 uint8_t dciSize = 0;
9248 uint8_t dci01aSize = 0;
9249 uint32_t bits = 0, idx = 0;
9251 switch(TFU_DCI_FORMAT_0) /* Switch case for the purpose of readability */
9253 case TFU_DCI_FORMAT_0:
9255 /* DCI 0: Spec 36.212 Section 5.3.3.1.1 */
9257 /*-- Calculate resource block assignment bits need to be set
9258 Which is ln(N(N+1)/2) 36.212 5.3.3.1 --*/
9259 bits = (cell->bwCfg.ulTotalBw * (cell->bwCfg.ulTotalBw + 1) / 2);
9260 while ((bits & 0x8000) == 0)
9267 dciSize = 1 /* DCI 0 bit indicator */ + \
9268 1 /* Frequency hoping enable bit field */ + \
9269 (uint8_t)bits /* For frequency Hopping */ + \
9276 2 /* UL Index Config 0 or DAI Config 1-6 */
9280 cell->dciSize.baseSize[TFU_DCI_FORMAT_0] = dciSize;
9282 /* If hoping flag is enabled */
9283 if (cell->bwCfg.ulTotalBw <= 49) /* Spec 36.213 Table 8.4-1, N UL_hop, if hopping is enabled */
9285 cell->dciSize.dci0HopSize = 1;
9289 cell->dciSize.dci0HopSize = 2;
9292 /* Update common non-CRNTI scrambled DCI 0/1A flag */
9293 dci01aSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_0] + 1; /* 1 bit CSI */
9295 case TFU_DCI_FORMAT_1A:
9297 /* DCI 1A: Spec 36.212 Section 5.3.3.1.3 */
9300 /* Calculate resource block assignment bits need to be set
9301 Which is ln(N(N+1)/2) */
9302 bits = (cell->bwCfg.dlTotalBw * (cell->bwCfg.dlTotalBw + 1) / 2);
9303 while ((bits & 0x8000) == 0)
9310 dciSize += 1 /* Format 1A */ + \
9311 1 /* Local or Distributed */ + \
9312 (uint8_t)bits /* Resource block Assignment */ + \
9315 4 /* HARQ Proc Id */ +
9317 3 /* HARQ Proc Id */ +
9327 cell->dciSize.baseSize[TFU_DCI_FORMAT_1A] = dciSize;
9329 /* If the UE is not configured to decode PDCCH with CRC scrambled by the C-RNTI,
9330 * and the number of information bits in format 1A is less than that of format 0,
9331 * zeros shall be appended to format 1A until the payload size equals that of format 0. */
9332 /* Compare the size with DCI 1A and DCI 0 and consider the greater one */
9333 if (dci01aSize < cell->dciSize.baseSize[TFU_DCI_FORMAT_1A])
9335 dci01aSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_1A];
9337 /* If the number of information bits in format 1A belongs to one of the sizes in
9338 * Table 5.3.3.1.2-1, one zero bit shall be appended to format 1A. */
9339 dci01aSize += rgSchDciAmbigSizeTbl[dci01aSize];
9340 cell->dciSize.size[TFU_DCI_FORMAT_1A] = cell->dciSize.size[TFU_DCI_FORMAT_0] = dci01aSize;
9342 case TFU_DCI_FORMAT_1:
9344 /* DCI 1: Spec 36.212 Section 5.3.3.1.2 */
9346 if (cell->bwCfg.dlTotalBw > 10)
9348 dciSize = 1; /* Resource Allocation header bit */
9351 /* Resouce allocation bits Type 0 and Type 1 */
9352 bits = (cell->bwCfg.dlTotalBw/cell->rbgSize);
9353 if ((cell->bwCfg.dlTotalBw % cell->rbgSize) != 0)
9358 dciSize += (uint8_t)bits /* Resource Allocation bits */ + \
9366 2 /* Redunancy Version */ + \
9375 cell->dciSize.baseSize[TFU_DCI_FORMAT_1] = dciSize;
9377 cell->dciSize.size[TFU_DCI_FORMAT_1] = dciSize;
9380 /* If the UE is not configured to decode PDCCH with CRC
9381 * scrambled by the C-RNTI and the number of information bits in format 1
9382 * is equal to that for format 0/1A, one bit of value zero shall be appended
9384 if (dci01aSize == cell->dciSize.size[TFU_DCI_FORMAT_1])
9386 cell->dciSize.size[TFU_DCI_FORMAT_1] += 1;
9389 /* If the number of information bits in format 1 belongs to one of the sizes in
9390 * Table 5.3.3.1.2-1, one or more zero bit(s) shall be appended to format 1 until
9391 * the payload size of format 1 does not belong to one of the sizes in Table 5.3.3.1.2-1
9392 * and is not equal to that of format 0/1A mapped onto the same search space. */
9393 cell->dciSize.size[TFU_DCI_FORMAT_1] += rgSchDciAmbigSizeTbl[cell->dciSize.size[TFU_DCI_FORMAT_1]];
9394 } while (cell->dciSize.size[TFU_DCI_FORMAT_1] == dci01aSize);
9396 case TFU_DCI_FORMAT_2:
9398 /* DCI 2: Spec 36.212 Section 5.3.3.1.5 */
9400 if (cell->bwCfg.dlTotalBw > 10)
9402 dciSize = 1; /* Resource Allocation bit */
9405 dciSize += (uint8_t)bits /* Resource Allocation bits */ + \
9413 1 /* CW Swap Flag */ + \
9414 5 /* MCS for TB1 */+ \
9415 1 /* NDI for TB1 */+ \
9416 2 /* RV for TB1 */ + \
9417 5 /* MCS for TB2 */+ \
9418 1 /* NDI for TB2 */+ \
9420 if (cell->numTxAntPorts == 2)
9424 else if (cell->numTxAntPorts == 4)
9428 cell->dciSize.size[TFU_DCI_FORMAT_2] = dciSize;
9429 cell->dciSize.size[TFU_DCI_FORMAT_2] += rgSchDciAmbigSizeTbl[cell->dciSize.size[TFU_DCI_FORMAT_2]];
9431 case TFU_DCI_FORMAT_2A:
9433 /* DCI 2A: Spec 36.212 Section 5.3.3.1.5A */
9435 if (cell->bwCfg.dlTotalBw > 10)
9437 dciSize = 1; /* Resource Allocation bit */
9440 dciSize += (uint8_t)bits /* Resource Allocation bits */ + \
9448 1 /* CW Swap Flag */ + \
9449 5 /* MCS for TB1 */+ \
9450 1 /* NDI for TB1 */+ \
9451 2 /* RV for TB1 */ + \
9452 5 /* MCS for TB2 */+ \
9453 1 /* NDI for TB2 */+ \
9455 if (cell->numTxAntPorts == 4)
9459 cell->dciSize.size[TFU_DCI_FORMAT_2A] = dciSize;
9460 cell->dciSize.size[TFU_DCI_FORMAT_2A] += \
9461 rgSchDciAmbigSizeTbl[cell->dciSize.size[TFU_DCI_FORMAT_2A]]; /* Spec 39.212 Table 5.3.3.1.2-1 */
9463 case TFU_DCI_FORMAT_3:
9465 /* DCI 3: Spec 36.212 Section 5.3.3.1.6 */
9466 cell->dciSize.size[TFU_DCI_FORMAT_3] = cell->dciSize.size[TFU_DCI_FORMAT_1A] / 2;
9467 if (cell->dciSize.size[TFU_DCI_FORMAT_3] % 2)
9469 cell->dciSize.size[TFU_DCI_FORMAT_3]++;
9472 case TFU_DCI_FORMAT_3A:
9474 /* DCI 3A: Spec 36.212 Section 5.3.3.1.7 */
9475 cell->dciSize.size[TFU_DCI_FORMAT_3A] = cell->dciSize.size[TFU_DCI_FORMAT_1A];
9478 case TFU_DCI_FORMAT_6_0A:
9480 rgSCHEmtcGetDciFrmt60ASize(cell);
9482 case TFU_DCI_FORMAT_6_1A:
9484 rgSCHEmtcGetDciFrmt61ASize(cell);
9489 /* DCI format not supported */
9496 * @brief Handler for the CPU OvrLd related state adjustment.
9500 * Function : rgSCHUtlCpuOvrLdAdjItbsCap
9503 * - Record dl/ulTpts
9504 * - Adjust maxItbs to acheive target throughputs
9506 * @param[in] RgSchCellCb *cell
9509 Void rgSCHUtlCpuOvrLdAdjItbsCap( RgSchCellCb *cell)
9513 if ((cell->cpuOvrLdCntrl.cpuOvrLdIns) & (RGR_CPU_OVRLD_DL_TPT_UP |
9514 RGR_CPU_OVRLD_DL_TPT_DOWN))
9516 /* Regulate DL Tpt for CPU overload */
9517 if (cell->measurements.dlTpt > cell->cpuOvrLdCntrl.tgtDlTpt)
9519 tptDelta = cell->measurements.dlTpt - cell->cpuOvrLdCntrl.tgtDlTpt;
9520 /* Upto 0.5% drift in measured vs target tpt is ignored */
9521 if (((tptDelta*1000)/cell->cpuOvrLdCntrl.tgtDlTpt) > 5)
9523 cell->thresholds.maxDlItbs = RGSCH_MAX((cell->thresholds.maxDlItbs-1), 1);
9528 tptDelta = cell->cpuOvrLdCntrl.tgtDlTpt - cell->measurements.dlTpt;
9529 /* Upto 0.5% drift in measured vs target tpt is ignored */
9530 if (((tptDelta*1000)/cell->cpuOvrLdCntrl.tgtDlTpt) > 5)
9532 cell->thresholds.maxDlItbs = RGSCH_MIN((cell->thresholds.maxDlItbs+1), RG_SCH_DL_MAX_ITBS);
9535 #ifdef CPU_OL_DBG_PRINTS
9536 DU_LOG("\nINFO --> SCH : DL CPU OL ADJ = %lu, %lu, %d\n", cell->measurements.dlTpt, cell->cpuOvrLdCntrl.tgtDlTpt,
9537 cell->thresholds.maxDlItbs);
9541 if ((cell->cpuOvrLdCntrl.cpuOvrLdIns) & (RGR_CPU_OVRLD_UL_TPT_UP |
9542 RGR_CPU_OVRLD_UL_TPT_DOWN))
9544 /* Regualte DL Tpt for CPU overload */
9545 if (cell->measurements.ulTpt > cell->cpuOvrLdCntrl.tgtUlTpt)
9547 tptDelta = cell->measurements.ulTpt - cell->cpuOvrLdCntrl.tgtUlTpt;
9548 /* Upto 1% drift in measured vs target tpt is ignored */
9549 if (((tptDelta*1000)/cell->cpuOvrLdCntrl.tgtUlTpt) > 10)
9551 cell->thresholds.maxUlItbs = RGSCH_MAX((cell->thresholds.maxUlItbs-1), 1);
9556 tptDelta = cell->cpuOvrLdCntrl.tgtUlTpt - cell->measurements.ulTpt;
9557 /* Upto 1% drift in measured vs target tpt is ignored */
9558 if (((tptDelta*1000)/cell->cpuOvrLdCntrl.tgtUlTpt) > 10)
9560 cell->thresholds.maxUlItbs = RGSCH_MIN((cell->thresholds.maxUlItbs+1), RG_SCH_UL_MAX_ITBS);
9563 #ifdef CPU_OL_DBG_PRINTS
9564 DU_LOG("\nDEBUG --> SCH : UL CPU OL ADJ = %lu, %lu, %d\n", cell->measurements.ulTpt, cell->cpuOvrLdCntrl.tgtUlTpt,
9565 cell->thresholds.maxUlItbs);
9572 * @brief Handler for the num UE per TTI based CPU OvrLd instr updating
9576 * Function : rgSCHUtlChkAndUpdNumUePerTtiCpuOvInstr
9579 * - Validate the config params.
9580 * - Update numUEperTTi CPU OL related information.
9581 * - If successful, return ROK else RFAILED.
9583 * @param[in] RgSchCellCb *cell
9584 * @param[in] uint8_t cnrtCpuOvrLdIns
9587 static Void rgSCHUtlChkAndUpdNumUePerTtiCpuOvInstr(RgSchCellCb *cell,uint8_t crntCpuOvrLdIns)
9589 RgSchCpuOvrLdCntrlCb *cpuInstr = &(cell->cpuOvrLdCntrl);
9590 RgSchCmnCell *cellSch;
9591 uint8_t maxUeNewDlTxPerTti;
9592 uint8_t maxUeNewUlTxPerTti;
9593 uint8_t tmpslot = 0;
9594 #ifdef CPU_OL_DBG_PRINTS
9597 uint8_t maxDlDecCnt;
9598 uint8_t maxUlDecCnt;
9600 cellSch = RG_SCH_CMN_GET_CELL(cell);
9602 maxUeNewDlTxPerTti = cellSch->dl.maxUeNewTxPerTti;
9603 maxUeNewUlTxPerTti = cellSch->ul.maxUeNewTxPerTti;
9605 /* Calculate Maximum Decremen */
9606 maxDlDecCnt = (10*(maxUeNewDlTxPerTti - 1))-(10-RGR_MAX_PERC_NUM_UE_PER_TTI_RED);
9607 maxUlDecCnt = (10*(maxUeNewUlTxPerTti - 1))-(10-RGR_MAX_PERC_NUM_UE_PER_TTI_RED);
9609 /* Check for DL CPU Commands */
9610 if ( crntCpuOvrLdIns & RGR_CPU_OVRLD_DL_DEC_NUM_UE_PER_TTI )
9612 /* Decrement till 90% of maxUeNewDlTxPerTti */
9613 if ( cpuInstr->dlNxtIndxDecNumUeTti < maxDlDecCnt )
9615 tmpslot = (cpuInstr->dlNxtIndxDecNumUeTti) % 10;
9616 cpuInstr->dlNxtIndxDecNumUeTti++;
9617 if ( cpuInstr->maxUeNewTxPerTti[tmpslot] > 1 )
9619 cpuInstr->maxUeNewTxPerTti[tmpslot]--;
9623 #ifdef CPU_OL_DBG_PRINTS
9624 DU_LOG("\nERROR --> SCH : CPU_OL_TTI__ERROR\n");
9626 DU_LOG("\nERROR --> SCH : Invalid CPU OL");
9629 #ifdef CPU_OL_DBG_PRINTS
9630 DU_LOG("\nDEBUG --> SCH : dlNxtIndxDecNumUeTti = %d\n", cpuInstr->dlNxtIndxDecNumUeTti);
9632 DU_LOG("\nDEBUG --> SCH : dlNxtIndxDecNumUeTti = %d",
9633 cpuInstr->dlNxtIndxDecNumUeTti);
9635 else if ( crntCpuOvrLdIns & RGR_CPU_OVRLD_DL_INC_NUM_UE_PER_TTI )
9637 if ( cpuInstr->dlNxtIndxDecNumUeTti > 0)
9639 cpuInstr->dlNxtIndxDecNumUeTti--;
9640 tmpslot = (cpuInstr->dlNxtIndxDecNumUeTti) % 10;
9641 if ( cpuInstr->maxUeNewTxPerTti[tmpslot] < maxUeNewDlTxPerTti )
9643 cpuInstr->maxUeNewTxPerTti[tmpslot]++;
9647 #ifdef CPU_OL_DBG_PRINTS
9648 DU_LOG("\nERROR --> SCH : CPU_OL_TTI__ERROR\n");
9650 DU_LOG("\nERROR --> SCH : Invalid CPU OL");
9653 #ifdef CPU_OL_DBG_PRINTS
9654 DU_LOG("\nDEBUG --> SCH : dlNxtIndxDecNumUeTti = %d\n", cpuInstr->dlNxtIndxDecNumUeTti);
9656 DU_LOG("\nERROR --> SCH : dlNxtIndxDecNumUeTti = %d",
9657 cpuInstr->dlNxtIndxDecNumUeTti);
9659 /* Check for UL CPU commands */
9660 if ( crntCpuOvrLdIns & RGR_CPU_OVRLD_UL_DEC_NUM_UE_PER_TTI )
9662 /* Decrement till 90% of maxUeNewDlTxPerTti */
9663 if ( cpuInstr->ulNxtIndxDecNumUeTti < maxUlDecCnt )
9665 tmpslot = (cpuInstr->ulNxtIndxDecNumUeTti) % 10;
9666 cpuInstr->ulNxtIndxDecNumUeTti++;
9667 if ( cpuInstr->maxUeNewRxPerTti[tmpslot] > 1 )
9669 cpuInstr->maxUeNewRxPerTti[tmpslot]--;
9673 #ifdef CPU_OL_DBG_PRINTS
9674 DU_LOG("\nERROR --> SCH : CPU_OL_TTI__ERROR\n");
9676 DU_LOG("\nERROR --> SCH : Invalid CPU OL");
9679 #ifdef CPU_OL_DBG_PRINTS
9680 DU_LOG("\nDEBUG --> SCH : ulNxtIndxDecNumUeTti = %d\n", cpuInstr->ulNxtIndxDecNumUeTti);
9682 DU_LOG("\nDEBUG --> SCH : dlNxtIndxDecNumUeTti = %d",
9683 cpuInstr->dlNxtIndxDecNumUeTti);
9685 else if ( crntCpuOvrLdIns & RGR_CPU_OVRLD_UL_INC_NUM_UE_PER_TTI )
9687 if ( cpuInstr->ulNxtIndxDecNumUeTti > 0)
9689 cpuInstr->ulNxtIndxDecNumUeTti--;
9690 tmpslot = (cpuInstr->ulNxtIndxDecNumUeTti) % 10;
9691 if ( cpuInstr->maxUeNewRxPerTti[tmpslot] < maxUeNewUlTxPerTti )
9693 cpuInstr->maxUeNewRxPerTti[tmpslot]++;
9697 #ifdef CPU_OL_DBG_PRINTS
9698 DU_LOG("\nERROR --> SCH : CPU_OL_TTI__ERROR\n");
9700 DU_LOG("\nERROR --> SCH : Invalid CPU OL");
9703 #ifdef CPU_OL_DBG_PRINTS
9704 DU_LOG("\nDEBUG --> SCH : ulNxtIndxDecNumUeTti = %d\n", cpuInstr->ulNxtIndxDecNumUeTti);
9706 DU_LOG("\nDEBUG --> SCH : dlNxtIndxDecNumUeTti = %d",
9707 cpuInstr->dlNxtIndxDecNumUeTti);
9709 #ifdef CPU_OL_DBG_PRINTS
9710 /* TODO: Debug Information - Shall be moved under CPU_OL_DBG_PRINTS */
9711 DU_LOG("\nDEBUG --> SCH : maxUeNewDlTxPerTti = %d, maxUeNewUlTxPerTti = %d\n", maxUeNewDlTxPerTti, maxUeNewUlTxPerTti);
9712 DU_LOG("\nINFO --> SCH : DL Sf numUePerTti:");
9713 for ( idx = 0; idx < 10 ; idx ++ )
9715 DU_LOG(" %d", cpuInstr->maxUeNewTxPerTti[idx]);
9717 DU_LOG("\nINFO --> SCH : UL Sf numUePerTti:");
9718 for ( idx = 0; idx < 10 ; idx ++ )
9720 DU_LOG(" %d", cpuInstr->maxUeNewRxPerTti[idx]);
9726 } /* rgSCHUtlChkAndUpdNumUePerTtiCpuOvInstr */
9729 * @brief Handler for the CPU OvrLd related cell Recfg.
9733 * Function : rgSCHUtlResetCpuOvrLdState
9736 * - Validate the config params.
9737 * - Update CPU OL related state information.
9738 * - If successful, return ROK else RFAILED.
9740 * @param[in] RgSchCellCb *cell
9741 * @param[in] uint8_t cnrtCpuOvrLdIns
9746 S16 rgSCHUtlResetCpuOvrLdState(RgSchCellCb *cell,uint8_t crntCpuOvrLdIns)
9748 uint8_t crntDlCpuOL=0;
9749 uint8_t crntUlCpuOL=0;
9750 RgSchCmnCell *schCmnCell = (RgSchCmnCell *)(cell->sc.sch);
9753 #ifdef CPU_OL_DBG_PRINTS
9754 DU_LOG("\nDEBUG --> SCH : CPU OVR LD Ins Rcvd = %d\n", (int)crntCpuOvrLdIns);
9756 DU_LOG("\nINFO --> SCH : CPU OVR LD Ins Rcvd");
9758 if ( RGR_CPU_OVRLD_RESET == crntCpuOvrLdIns )
9760 /* The CPU OL instruction received with RESET (0), hence reset it */
9761 #ifdef CPU_OL_DBG_PRINTS
9762 DU_LOG("\nDEBUG --> SCH : rgSCHUtlResetCpuOvrLdState: RESET CPU OL instr\n");
9764 DU_LOG("\nINFO --> SCH : RESET CPU OVR LD");
9765 cell->cpuOvrLdCntrl.cpuOvrLdIns = 0;
9766 /* Reset the max UL and DL itbs to 26 */
9767 cell->thresholds.maxUlItbs = RG_SCH_UL_MAX_ITBS;
9768 cell->thresholds.maxDlItbs = RG_SCH_DL_MAX_ITBS;
9769 /* Reset the num UE per TTI intructions */
9770 cell->cpuOvrLdCntrl.dlNxtIndxDecNumUeTti = 0;
9771 cell->cpuOvrLdCntrl.ulNxtIndxDecNumUeTti = 0;
9772 for ( idx = 0; idx < 10; idx++ )
9774 cell->cpuOvrLdCntrl.maxUeNewTxPerTti[idx] =
9775 schCmnCell->dl.maxUeNewTxPerTti;
9776 cell->cpuOvrLdCntrl.maxUeNewRxPerTti[idx] =
9777 schCmnCell->ul.maxUeNewTxPerTti;
9782 /* Check and Update numUEPer TTI based CPU overload instruction before
9783 * going for TP based CPU OL
9784 * TTI based intrcuctions shall be > 0xF */
9785 if ( crntCpuOvrLdIns > 0xF )
9787 rgSCHUtlChkAndUpdNumUePerTtiCpuOvInstr(cell, crntCpuOvrLdIns);
9788 /* If need to have both TP and numUePerTti instrcution together in
9789 * one command then dont return from here */
9793 crntDlCpuOL = (crntCpuOvrLdIns & RGR_CPU_OVRLD_DL_TPT_UP) +\
9794 (crntCpuOvrLdIns & RGR_CPU_OVRLD_DL_TPT_DOWN);
9795 if ((crntDlCpuOL) && (crntDlCpuOL != RGR_CPU_OVRLD_DL_TPT_UP) &&
9796 (crntDlCpuOL != RGR_CPU_OVRLD_DL_TPT_DOWN))
9798 /* Cfg validation failed. Invalid Command. Either UP/DOWN is allowed */
9801 crntUlCpuOL = (crntCpuOvrLdIns & RGR_CPU_OVRLD_UL_TPT_UP) +\
9802 (crntCpuOvrLdIns & RGR_CPU_OVRLD_UL_TPT_DOWN);
9803 if ((crntUlCpuOL) && (crntUlCpuOL != RGR_CPU_OVRLD_UL_TPT_UP) &&
9804 (crntUlCpuOL != RGR_CPU_OVRLD_UL_TPT_DOWN))
9806 /* Cfg validation failed. Invalid Command. Either UP/DOWN is allowed */
9809 if ((crntDlCpuOL == 0) && (crntUlCpuOL == 0))
9811 /* Cfg validation failed. Invalid Command. Either UP/DOWN is allowed */
9815 cell->cpuOvrLdCntrl.cpuOvrLdIns = crntCpuOvrLdIns;
9819 if (crntUlCpuOL == RGR_CPU_OVRLD_UL_TPT_DOWN)
9821 cell->cpuOvrLdCntrl.tgtUlTpt = cell->measurements.ulTpt - \
9822 (cell->measurements.ulTpt * 3 )/100;
9826 cell->cpuOvrLdCntrl.tgtUlTpt = cell->measurements.ulTpt + \
9827 (cell->measurements.ulTpt * 2 )/100;
9829 DU_LOG("\nDEBUG --> SCH : CPU OVR LD UL Reset to "
9830 "%d, %u, %u", (int)crntUlCpuOL, cell->cpuOvrLdCntrl.tgtUlTpt,cell->measurements.ulTpt);
9831 #ifdef CPU_OL_DBG_PRINTS
9832 DU_LOG("\nDEBUG --> SCH : CPU OVR LD UL Reset to= %d, %u, %u\n", (int)crntUlCpuOL, cell->cpuOvrLdCntrl.tgtUlTpt,
9833 cell->measurements.ulTpt);
9839 if (crntDlCpuOL == RGR_CPU_OVRLD_DL_TPT_DOWN)
9841 cell->cpuOvrLdCntrl.tgtDlTpt = cell->measurements.dlTpt - \
9842 (cell->measurements.dlTpt * 1 )/100;
9846 cell->cpuOvrLdCntrl.tgtDlTpt = cell->measurements.dlTpt + \
9847 (cell->measurements.dlTpt * 1 )/100;
9849 DU_LOG("\nDEBUG --> SCH : CPU OVR LD DL Reset to "
9850 "%d, %u, %u", (int)crntDlCpuOL, cell->cpuOvrLdCntrl.tgtDlTpt,cell->measurements.dlTpt);
9852 #ifdef CPU_OL_DBG_PRINTS
9853 DU_LOG("\nDEBUG --> SCH : CPU OVR LD DL Reset to= %d, %lu, %lu\n", (int)crntDlCpuOL, cell->cpuOvrLdCntrl.tgtDlTpt,
9854 cell->measurements.dlTpt);
9857 rgSCHUtlCpuOvrLdAdjItbsCap(cell);
9861 S16 rgSCHUtlAddToResLst
9867 cmLListAdd2Tail(cp, &iotRes->resLnk);
9868 iotRes->resLnk.node = (PTR)iotRes;
9871 S16 rgSCHUtlDelFrmResLst
9877 CmLListCp *cp = NULLP;
9878 RgSchEmtcUeInfo *emtcUe = NULLP;
9879 emtcUe = RG_GET_EMTC_UE_CB(ue);
9880 if(iotRes->resType == RG_SCH_EMTC_PUCCH_RES)
9882 cp = &emtcUe->ulResLst;
9883 }else if(iotRes->resType == RG_SCH_EMTC_PDSCH_RES)
9885 cp = &emtcUe->dlResLst;
9888 DU_LOG("\nINFO --> SCH : *****restype mismatch");
9894 DU_LOG("\nINFO --> SCH : ****error count*****\n");
9898 cmLListDelFrm(cp, &iotRes->resLnk);
9899 iotRes->resLnk.node = NULLP;
9903 /**********************************************************************
9906 **********************************************************************/