1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /**********************************************************************
21 Name: LTE MAC SC1 scheduler
25 Desc: Defines required by SC1 scheduler
29 **********************************************************************/
30 /** @file rg_sch_cmn.x
31 @brief This file contains data structures for the common module of the scheuler.
39 #endif /* __cplusplus */
41 /*-------------------------------------*
42 * Common Scheduler DataStructure START
43 *-------------------------------------*/
44 typedef struct _rgDlSchdApis RgDlSchdApis;
45 typedef struct _rgUlSchdApis RgUlSchdApis;
46 typedef struct _rgDlfsSchdApis RgDlfsSchdApis;
47 typedef Void (*RgDlSchdInits[RGSCH_NUM_SCHEDULERS]) ARGS((RgDlSchdApis *apis));
48 typedef Void (*RgUlSchdInits[RGSCH_NUM_SCHEDULERS]) ARGS((RgUlSchdApis *apis));
49 typedef Void (*RgDlfsSchdInits[RGSCH_NUM_SCHEDULERS]) ARGS((RgDlfsSchdApis *apis));
51 typedef struct _rgDlEmtcSchdApis RgDlEmtcSchdApis;
52 typedef Void (*RgEmtcDlSchdInits[RGSCH_NUM_EMTC_SCHEDULERS]) ARGS((RgDlEmtcSchdApis *apis));
53 typedef Void (*RgEmtcUlSchdInits[RGSCH_NUM_EMTC_SCHEDULERS]) ARGS((RgUlSchdApis *apis));
55 typedef struct rgSchCmnDlRbAllocInfo RgSchCmnDlRbAllocInfo;
56 typedef struct rgSchCmnUeUlAlloc RgSchCmnUeUlAlloc;
57 typedef struct rgSchCmnUlRbAllocInfo RgSchCmnUlRbAllocInfo;
61 * Uplink Scheduler APIs.
65 S16 (*rgSCHRgrUlUeCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgrUeCfg *cfg,
67 S16 (*rgSCHRgrUlUeRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgrUeRecfg *recfg,
69 Void (*rgSCHFreeUlUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
70 S16 (*rgSCHRgrUlCellCfg) ARGS((RgSchCellCb *cell, RgrCellCfg *cfg,
72 S16 (*rgSCHRgrUlCellRecfg) ARGS((RgSchCellCb *cell, RgrCellRecfg *recfg,
74 Void (*rgSCHFreeUlCell) ARGS((RgSchCellCb *cell));
75 S16 (*rgSCHRgrUlLcgCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
76 RgSchLcgCb *lcg, RgrLcgCfg *cfg, RgSchErrInfo *errInfo));
77 S16 (*rgSCHRgrUlLcCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
78 RgrLchCfg *cfg, RgSchErrInfo *errInfo));
79 S16 (*rgSCHRgrUlLcgRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
80 RgSchLcgCb *lcg, RgrLcgRecfg *recfg, RgSchErrInfo *errInfo));
81 S16 (*rgSCHRgrUlLcRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
82 RgrLchRecfg *recfg, RgSchErrInfo *errInfo));
83 Void (*rgSCHFreeUlLcg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchLcgCb *lcg));
84 S16 (*rgSCHRgrUlLchDel) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, CmLteLcId lcId, uint8_t lcgId));
85 Void (*rgSCHUlActvtUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
86 Void (*rgSCHUpdBsrShort) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchLcgCb *ulLcg, uint8_t bsr));
87 Void (*rgSCHUpdBsrTrunc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchLcgCb *ulLcg, uint8_t bsr));
88 Void (*rgSCHUpdBsrLong) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, uint8_t bsArr[]));
89 Void (*rgSCHContResUlGrant) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
90 Void (*rgSCHSrRcvd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
91 Void (*rgSCHUlSched) ARGS((RgSchCellCb *cell, RgSchCmnUlRbAllocInfo
93 Void (*rgSCHUlRetxSched) ARGS((RgSchCellCb *cell, RgSchCmnUlRbAllocInfo *allocInfo));
94 Void (*rgSCHUlCqiInd) ARGS(( RgSchCellCb *cell, RgSchUeCb *ue, TfuUlCqiRpt *ulCqiInfo));
95 S16 (*rgSCHRgrUlLcgUpd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgInfUeDatInd *datInd));
96 Void (*rgSCHUlUeRefresh) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
97 Void (*rgSCHUlUeReset) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
98 Void (*rgSCHUlAllocFnlz) ARGS((RgSchCellCb *cell, RgSchCmnUlRbAllocInfo
100 Void (*rgSCHUlInactvtUes) ARGS((RgSchCellCb *cell, CmLListCp *lst));
102 Void (*rgSCHUlProcAddToRetx) ARGS((RgSchCellCb *cell,RgSchUlHqProcCb *hqP));
103 S16 (*rgSCHUlUeHqEntInit) ARGS((RgSchCellCb *cell, RgUeUlHqCb *hqE));
104 S16 (*rgSCHUlUeHqEntDeInit) ARGS((RgSchCellCb *cell, RgUeUlHqCb *hqE));
110 * DL Scheduler APIs For EMTC.
112 struct _rgDlEmtcSchdApis
114 S16 (*rgSCHRgrDlUeCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgrUeCfg *cfg,
116 S16 (*rgSCHRgrDlUeRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgrUeRecfg *recfg,
118 Void (*rgSCHFreeDlUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
119 S16 (*rgSCHRgrDlCellCfg) ARGS((RgSchCellCb *cell, RgrCellCfg *cfg,
121 S16 (*rgSCHRgrDlCellRecfg) ARGS((RgSchCellCb *cell, RgrCellRecfg *recfg,
123 Void (*rgSCHFreeDlCell) ARGS((RgSchCellCb *cell));
124 S16 (*rgSCHRgrDlLcCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
125 RgSchDlLcCb *dl, RgrLchCfg *cfg,
126 RgSchErrInfo *errInfo));
127 S16 (*rgSCHRgrDlLcRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
128 RgSchDlLcCb *dl, RgrLchRecfg *recfg,
129 RgSchErrInfo *errInfo));
130 Void (*rgSCHFreeDlLc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchDlLcCb *dlLc));
131 Void (*rgSCHDlActvtUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
132 Void (*rgSCHDlNewSched) ARGS((RgSchCellCb *cell, RgSchEmtcDlSf *cntrlDlsf,RgSchEmtcDlSf *datDlsf));
133 Void (*rgSCHDlPreSched) ARGS((RgSchCellCb *cell));
134 Void (*rgSCHDlPstSched) ARGS((Inst schInst));
135 Void (*rgSCHDlRetxSched) ARGS((RgSchCellCb *cell, RgSchEmtcDlSf *cntrlDlsf, RgSchEmtcDlSf *datDlsf));
136 Void (*rgSCHDlCeSched) ARGS((RgSchCellCb *cell, RgSchCmnDlRbAllocInfo *allocInfo));
137 Void (*rgSCHDlDedBoUpd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchDlLcCb *svc));
138 Void (*rgSCHDlProcAddToRetx) ARGS((RgSchCellCb *cell,RgSchDlHqProcCb *hqP));
139 Void (*rgSCHDlCqiInd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, Bool isPucchInfo, Void *dlCqi));
141 Void (*rgSCHSrsInd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, TfuSrsRpt*srsInd));
143 Void (*rgSCHDlAllocFnlz) ARGS((RgSchCellCb *cell, RgSchCmnDlRbAllocInfo
145 Void (*rgSCHDlUeRefresh) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
146 Void (*rgSCHDlUeReset) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
147 Void (*rgSCHDlInactvtUes) ARGS((RgSchCellCb *cell, CmLListCp *lst));
149 S16 (*rgSCHDlUeHqEntInit) ARGS((RgSchCellCb *cell, RgSchDlHqEnt *hqE));
151 S16 (*rgSCHDlUeHqEntDeInit) ARGS((RgSchCellCb *cell, RgSchDlHqEnt *hqE));
152 Void (*rgSCHDlProcRmvFrmRetx) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchDlHqProcCb *hqP));
154 S16 (*rgSCHRgrSCellDlUeCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
156 S16 (*rgSCHRgrSCellDlUeDel) ARGS((RgSchUeCellInfo *sCellInfo, RgSchUeCb *ue));
157 S16 (*rgSCHDlSCellDeactv) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
158 S16 (*rgSCHDlSCellActv) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
160 Void (*rgSCHDlTickForPdbTrkng ) ARGS((RgSchCellCb *cell));
161 S16 (*rgSCHDlFillFlwCtrlInfo) ARGS((RgSchCellCb *cell, RgInfSfAlloc *sfAlloc));
171 S16 (*rgSCHRgrDlUeCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgrUeCfg *cfg,
173 S16 (*rgSCHRgrDlUeRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgrUeRecfg *recfg,
175 Void (*rgSCHFreeDlUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
176 S16 (*rgSCHRgrDlCellCfg) ARGS((RgSchCellCb *cell, RgrCellCfg *cfg,
178 S16 (*rgSCHRgrDlCellRecfg) ARGS((RgSchCellCb *cell, RgrCellRecfg *recfg,
180 Void (*rgSCHFreeDlCell) ARGS((RgSchCellCb *cell));
181 S16 (*rgSCHRgrDlLcCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
182 RgSchDlLcCb *dl, RgrLchCfg *cfg,
183 RgSchErrInfo *errInfo));
184 S16 (*rgSCHRgrDlLcRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
185 RgSchDlLcCb *dl, RgrLchRecfg *recfg,
186 RgSchErrInfo *errInfo));
187 Void (*rgSCHFreeDlLc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchDlLcCb *dlLc));
188 Void (*rgSCHDlActvtUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
189 Void (*rgSCHDlNewSched) ARGS((RgSchCellCb *cell, RgSchCmnDlRbAllocInfo *allocInfo));
190 Void (*rgSCHDlPreSched) ARGS((RgSchCellCb *cell));
191 Void (*rgSCHDlPstSched) ARGS((Inst schInst));
192 Void (*rgSCHDlRetxSched) ARGS((RgSchCellCb *cell, RgSchCmnDlRbAllocInfo *allocInfo));
193 Void (*rgSCHDlCeSched) ARGS((RgSchCellCb *cell, RgSchCmnDlRbAllocInfo *allocInfo));
194 Void (*rgSCHDlDedBoUpd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchDlLcCb *svc));
195 Void (*rgSCHDlProcAddToRetx) ARGS((RgSchCellCb *cell,RgSchDlHqProcCb *hqP));
196 Void (*rgSCHDlCqiInd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, Bool isPucchInfo, Void *dlCqi));
198 Void (*rgSCHSrsInd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, TfuSrsRpt*srsInd));
200 Void (*rgSCHDlAllocFnlz) ARGS((RgSchCellCb *cell, RgSchCmnDlRbAllocInfo
202 Void (*rgSCHDlUeRefresh) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
203 Void (*rgSCHDlUeReset) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
204 Void (*rgSCHDlInactvtUes) ARGS((RgSchCellCb *cell, CmLListCp *lst));
206 S16 (*rgSCHDlUeHqEntInit) ARGS((RgSchCellCb *cell, RgSchDlHqEnt *hqE));
208 S16 (*rgSCHDlUeHqEntDeInit) ARGS((RgSchCellCb *cell, RgSchDlHqEnt *hqE));
209 Void (*rgSCHDlProcRmvFrmRetx) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchDlHqProcCb *hqP));
211 S16 (*rgSCHRgrSCellDlUeCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
213 S16 (*rgSCHRgrSCellDlUeDel) ARGS((RgSchUeCellInfo *sCellInfo, RgSchUeCb *ue));
214 S16 (*rgSCHDlSCellDeactv) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
215 S16 (*rgSCHDlSCellActv) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
217 Void (*rgSCHDlTickForPdbTrkng ) ARGS((RgSchCellCb *cell));
218 S16 (*rgSCHDlFillFlwCtrlInfo) ARGS((RgSchCellCb *cell, RgInfSfAlloc *sfAlloc));
223 * DLFS Scheduler APIs.
225 struct _rgDlfsSchdApis
227 S16 (*rgSCHDlfsCellCfg) ARGS((RgSchCellCb *cell, RgrCellCfg *cfg,
229 S16 (*rgSCHDlfsCellRecfg) ARGS((RgSchCellCb *cell, RgrCellRecfg *recfg,
231 Void (*rgSCHDlfsCellDel) ARGS((RgSchCellCb *cell));
232 S16 (*rgSCHDlfsUeCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
233 RgrUeCfg *cfg, RgSchErrInfo *err));
234 S16 (*rgSCHDlfsUeRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
235 RgrUeRecfg *recfg, RgSchErrInfo *err));
236 Void (*rgSCHDlfsUeDel) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
237 Void (*rgSCHDlfsDlCqiInd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
240 CmLteTimingInfo timingInfo));
241 Void (*rgSCHDlfsReinitSf) ARGS((RgSchCellCb *cell, RgSchDlSf *dlSf));
242 Void (*rgSCHDlfsAllocRb) ARGS((RgSchCellCb *cell, RgSchCmnDlRbAllocInfo
244 /* Added for BCCH/PCCH handling */
245 Void (*rgSCHDlfsBcchPcchAllocRb) ARGS((RgSchCellCb *cell, RgSchCmnDlRbAllocInfo *dlRbAllocInfo));
246 Void (*rgSCHDlfsAddUeToLst) ARGS((RgSchCellCb *cell, CmLListCp *lCp, RgSchDlHqProcCb *hqP));
248 S16 (*rgSCHDlfsSCellUeCfg) ARGS((RgSchCellCb *sCell, RgSchUeCb *ueCb, RgrUeSecCellCfg *sCellCfg,RgSchErrInfo *err));
249 S16 (*rgSCHDlfsSCellUeDel) ARGS((RgSchCellCb *sCell, RgSchUeCb *ueCb));
253 typedef enum rgSchCmnTpcAccVal
255 RG_SCH_CMN_TPC_ACC_NEG_1DB = 0,
256 RG_SCH_CMN_TPC_ACC_0DB = 1,
257 RG_SCH_CMN_TPC_ACC_1DB = 2,
258 RG_SCH_CMN_TPC_ACC_3DB = 3
261 typedef enum rgSchCmnTpcAbsVal
263 RG_SCH_CMN_TPC_ABS_NEG_4DB = 0,
264 RG_SCH_CMN_TPC_ABS_NEG_1DB = 1,
265 RG_SCH_CMN_TPC_ABS_1DB = 2,
266 RG_SCH_CMN_TPC_ABS_4DB = 3
268 /* Added changes of TFU_UPGRADE */
270 typedef enum rgSchCmnRank
272 RG_SCH_CMN_RANK_1 = 1,
273 RG_SCH_CMN_RANK_2 = 2,
274 RG_SCH_CMN_RANK_3 = 3,
275 RG_SCH_CMN_RANK_4 = 4
279 typedef struct rgSchCmnUlCqiInfo
282 uint16_t eff; /* Efficiency in terms of bits/RE */
285 RgSchCmnUlCqiInfo rgSchCmnUlCqiTbl[RG_SCH_CMN_UL_NUM_CQI];
286 S8 rgSchCmnDlCqiDiffOfst[8];
287 /* Added changes of TFU_UPGRADE */
289 S8 rgSchCmnApUeSelDiffCqi[4];
290 S8 rgSchCmnApEnbConfDiffCqi[4];
294 uint8_t rgSchCmnUlCqiToTbsTbl[RG_SCH_CMN_MAX_CP][RG_SCH_CMN_UL_NUM_CQI];
296 #if (LTEMAC_SPS & LTE_TDD)
297 /* subframe offset values to be used when twoIntervalsConfig is enabled in UL
299 typedef S8 RgSchTddSfOffTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
300 RgSchTddSfOffTbl rgSchTddSfOffTbl;
302 #endif /* LTEMAC_SPS & LTE_TDD */
304 /*--------------------------*
305 * SPS specific declarations
306 *---------------------------*/
311 * Downlink SPS scheduling information per UE
313 typedef struct rgSchCmnSpsDlUeSchdInfo
315 uint8_t scaledCqi; /*!< Assumed value of CQI for transmission */
316 uint16_t actvSfTblIdx; /*!< Index into cell-wide DL SPS sub-frame
317 table during activation */
318 CmLteTimingInfo schdKey; /*!< Key into the list of DL SPS active
319 UEs: next DL SPS ocassion */
320 RgSchDlRbAlloc spsAllocInfo; /*!< Allocation information for an SPS active
322 uint8_t allocN1PucchIdx; /*!< Index value in UE's n1Pucch array
323 of the allocated n1Pucch */
324 //Bool pdcchPndng; /*!< Indicates if the activaton/
325 // reactivation PDCCH needs to be sent
326 // for this allocation */
327 } RgSchCmnSpsDlUeSchdInfo;
331 * Downlink stats information for SPS per UE
333 typedef struct rgSchCmnDlUeSpsStatInfo
335 uint32_t numSchedSPSRnti; /*!< Number of SPS occasions sched using SPS RNTI*/
336 uint32_t totalSPSSchedOcc; /*!< Number of SPS occasions sched
337 using SPS RNTI + CRNTI*/
338 uint32_t numSpsReactv; /*!< Number of Reactivations */
339 uint32_t numSpsActv; /*!< Number of activations */
340 uint32_t numSpsRel; /*!< Number of Deactivations */
341 }RgSchCmnDlUeSpsStatInfo;
345 * Downlink information for SPS per UE
347 typedef struct rgSchCmnDlUeSpsInfo
349 CmLteTimingInfo prevDlBoUpdTm; /*!< BO updation interval*/
350 CmLList zeroBOSvcUesEnt; /*!< Linked list entity for zeroBOSvcUes lst */
351 CmLList actvUeLstEnt; /*!< Linked List entry for DL SPS
353 CmLList pndngUeLstEnt;/*!< Linked List entry for UE list with
355 activation/reactivation/release */
356 /* Added handling to retrnasmit RelPDCCH in case no
357 feedback is received */
358 CmLList wtngForRelFdbkUeEnt;/*!< Linked list entry for UE who
359 have a feedback pending for
361 RgSchDlLcCb *spsSvc; /*!< Pointer to the SPS service of the
363 CmLListCp *spsList; /*!< Pointer to the SPS list of which
365 uint32_t measGapMask[RG_SCH_CMN_SPS_DL_MEASGAP_32BITMASK_SIZE];
366 /*!< Indicates the DL sub-frames with
367 ongoing measurement gap */
368 uint16_t n1PucchIdx[RG_SCH_CMN_SPS_DL_MAX_N1PUCCH_IDX_PER_UE];
369 /*!< N1Pucch indices configured for the UE */
370 uint8_t actionPndng; /*!< Indicates the action pending on the UE
371 activation/re-activation/release */
372 uint8_t dlSpsStatus; /*!< Indicates the current status of DL SPS */
373 uint8_t prdIdx; /*!< DL SPS periodicity index for the
374 configured peridicity */
375 RgSchCmnSpsDlUeSchdInfo dlSpsUeSchdInfo; /*!< Scheduled info for DL SPS
377 Bool isRelPdcchSent; /*!< Indicates if release PDCCH is sent for
378 this UE. For TDD, Used while sending DAI
379 in DCI formats 0/1/1A/1B/1D/2/2A.
380 For FDD, used to not repeat relPdcch
381 till the feddback is recieved */
382 uint8_t numRelPdcchSent; /*!< Number of times RelPdcch has been sent. */
384 RgSchCmnDlUeSpsStatInfo statInfo; /*!< SPS Metric Info */
385 uint8_t dynSchedCount; /*!< To track num of consecutive times SPS BO
386 is sched dynamically */
387 uint8_t reducedBoCount; /*!< To track num of consecutive times BO
388 is lesser than SPS BO */
389 uint32_t maxChgdBo; /* !< The Maximum of BO which is different from the
390 BO for which SPS has been activated */
391 uint32_t spsSchedBo; /* !< BO for which SPS is activated */
392 Bool isDynSched; /* !< BO is dynamically scheduled */
393 } RgSchCmnDlUeSpsInfo;
397 * Downlink information for SPS per Cell
399 typedef struct rgSchCmnSpsDlSf
401 uint32_t rbsAlloc; /*!< Allocated BW for this subframe (in actual number of
403 RgSchDlSfAllocInfo spsAllocInfo; /*!< Allocation information for SPS BW */
404 uint32_t n1PucchMask[RG_SCH_CMN_SPS_DL_N1PUCCH_32BITMASK_SIZE];
405 /*!< N1Pucch allocation mask per Sub-frame */
406 uint8_t numDlSpsActiveUes; /*!< number of DL SPS UEs that
407 have been activated */
412 * SPS N1Pucch Database for the cell
414 typedef struct rgSchCmnSpsDlN1Pucch RgSchCmnSpsDlN1Pucch;
415 struct rgSchCmnSpsDlN1Pucch
417 uint16_t idx; /*!< Index in the n1PucchLst */
418 uint16_t n1PucchVal; /*!< Pucch Value corresponding to the index */
419 uint32_t numUes; /*!< Count of UEs with this N1Pucch value configured */
420 uint16_t next; /*!< Next available index */
425 * SPS N1Pucch Database for the cell
427 typedef struct rgSchCmnSpsDlN1PucchDb
429 uint16_t numFreeN1Pucch; /*!< Number of free n1Pucch values */
430 uint16_t numInUseN1Pucch; /*!< Number of inUse n1Pucch values
432 RgSchCmnSpsDlN1Pucch *freeN1PucchStart; /*!< Start for free n1Pucch list */
433 RgSchCmnSpsDlN1Pucch *inUseN1PucchStart;/*!< Start for in-use n1Pucch list
435 RgSchCmnSpsDlN1Pucch n1PucchLst[RG_SCH_SPS_DL_MAX_N1PUCCH_PER_SF];
436 /*!< List of cell wide n1Pucch
438 } RgSchCmnSpsDlN1PucchDb;
442 * Downlink information for SPS per Cell
444 typedef struct rgSchCmnDlCellSpsInfo
446 CmLListCp zeroBOSvcUes; /*!< List of SPS services which
447 are not sched at SPS Occasion due
448 to zero BO*//* REVANTH_SPS_FIX */
449 CmLListCp toBeSchdSvcs; /*!< List of SPS services to be scheduled */
450 CmLListCp retxHqProcs; /*!< List of SPS HARQ procs for
451 re-transmission: all the HARQ procs
452 with isSpsSvcSchd = TRUE shall be
454 CmLListCp actvDlSpsUeLsts[RG_SCH_CMN_SPS_MAX_PRD];
455 /*!< Array of list of UE control blocks with
456 DL SPS activated: index - next time of
458 CmLListCp toBeActvtdUes; /*!< List of DL SPS UEs with pending
459 activation/re-activation */
460 CmLListCp toBeRelUes; /*!< List of DL SPS enabled UEs with release
462 /* Added handling when no feedback is received
463 for the Release PDCCH sent
465 CmLListCp wtngForRelFdbkUeLst[RGSCH_NUM_SUB_FRAMES]; /*!< List of DL SPS
470 uint16_t spsPrdLcmVal; /*!< LCM value for all configured
471 SPS periodicities: maxVal = 640 for FDD
472 and (640 * 3) for TDD */
473 uint8_t lcmIdx; /*!< Index value for computed LCM */
474 RgSchCmnSpsDlSf *spsSfTbl; /*!< DL sub-frame information for the cell*/
475 RgSchCmnSpsDlN1PucchDb n1PucchDb; /*!< Database of configured n1Pucch values
477 } RgSchCmnDlCellSpsInfo;
481 * Information per uplink SPS allocation
483 typedef struct rgSchCmnSpsUlAlloc
485 uint8_t sbStart; /*!< Starting subband of the alloc */
486 uint8_t numSb; /*!< Num of subbands in the alloc */
487 } RgSchCmnSpsUlAlloc;
491 * Uplink information for SPS per subframe
493 typedef struct rgSchCmnSpsUlSf
495 uint32_t ulBwBitMask[RGSCH_SPS_ULBW_MASK_LEN]; /*!< Bitmask indicating the alloc/hole info
496 for SPS BW. Bit set at position 'x'
497 indicates subband 'x' is occupied */
498 uint8_t maskLen; /*!< Length of ulBwBitMask based on numSb */
499 uint8_t numUlSpsActiveUes; /*!< Number of UL SPS Active UEs in this Subframe */
500 RgSchCmnSpsUlAlloc allocInfo; /*!< Info per SPS Allocation - Used to mark
501 previous allocations in a subframe */
506 * Uplink information for SPS per Cell
508 typedef struct rgSchCmnUlCellSpsInfo
510 uint8_t spsSbStart; /*!< Starting subband of SPS BW */
511 uint8_t numSpsSb; /*!< number of subbands for SPS */
512 uint16_t spsPrdLcmVal; /*!< LCM value for all configured UL
513 SPS periodicities:maxVal = 640 for FDD
514 and (640 * 3) for TDD */
515 RgSchCmnSpsUlSf *spsSfLst; /*!< UL subframe information for the cell*/
516 CmLListCp actvUlSpsUeLsts[RG_SCH_CMN_SPS_MAX_PRD];
517 /*!< Array of list of UeCbs with
518 UL SPS activated: index - next time of
520 CmLListCp toBeActvtdUeLst; /*!< List of ULSPS enabled UEs with pending
522 CmLListCp toBeRelUeLst; /*!< List of ULSPS enabled UEs with release
524 } RgSchCmnUlCellSpsInfo;
528 /*--------------------------*
529 * SPS specific declarations End
530 *---------------------------*/
533 * Scheduler uplink scheduling parameters related to random access.
535 typedef struct rgSchCmnUlCellRa
537 uint8_t prmblANumSb; /*!< Number of msg3 RBs to allocate for preamble A */
538 uint8_t prmblAIMcs; /*!< Imcs for msg3 when preamble A was used */
539 uint8_t prmblBNumSb; /*!< Number of msg3 RBs to allocate for preamble B */
540 uint8_t prmblBIMcs; /*!< Imcs for msg3 when preamble B was used */
543 typedef struct rgSchCmnCellClcITbs
545 uint8_t iTbs2Rbs; /*!< iTbs value for 2 Rbs precomputed at cell cfg */
546 uint8_t iTbs3Rbs; /*!< iTbs value for 3 Rbs precomputed at cell cfg */
547 }RgSchCmnCellClcITbs;
549 typedef struct rgSchCmnDlCell
551 Bool isDlFreqSel; /*!< Bool indicating if cell is frequency
553 uint8_t maxUeNewTxPerTti; /*!< Max UEs to be considered for New Tx Alloc in DL */
554 uint8_t numRaSubFrms; /*!< Number of frames of RA transmission */
555 uint8_t iTbsCap; /*!< Max value DL iTbs capped to */
556 uint16_t nCce; /*!< Number of CCEs computed based on CFI */
557 uint8_t maxDlBwPerUe; /*!< Max DL B/W per UE */
558 uint8_t maxDlRetxBw; /*!< Max DL retx B/W, as part of 256 */
559 uint8_t maxUePerDlSf; /*!< Max UE to be considered for DL scheduling
561 /*[ccpu00138609]-ADD- max Msg4/ DL CCCH UE configuration */
562 uint8_t maxCcchPerDlSf; /*!< Max Msg4/DL CCCH UE sched in Dlsf */
563 uint8_t msg4TxDelay; /*!< Max estimated time for HARQ tx
564 of msg4 based on the Harq RTT and
565 max Harq retries for msg4 */
566 RgSchCmnCellClcITbs cmnChITbs; /*!< iTbs value for 2 Rbs precomputed at cell cfg */
567 CmLteAggrLvl cmnChAggrLvl; /*!< Precomputed aggregation level for common channel */
568 uint8_t ccchCqi; /*!< Default Cqi to be used for Msg4 and UE */
569 CmLListCp msg4RetxLst; /*!< Queue to hold Msg4 procs for retransmission */
570 /* Changes for CR timer */
572 CmLListCp ccchSduRetxLst; /*!< Queue to hold CCCH SDU procs for retransmission */
575 Void *emtcCqiToTbsTbl[RGSCH_MAX_NUM_LYR_PERCW][RG_SCH_CMN_MAX_CFI];
577 Void *cqiToTbsTbl[RGSCH_MAX_NUM_LYR_PERCW][RG_SCH_CMN_MAX_CFI];
578 /* cqi to Tbs tables for each 1 and 2 layer TbSz table */
579 /*!< CQI to efficiency translation */
580 Void *cqiToEffTbl[RGSCH_MAX_NUM_LYR_PERCW][RG_SCH_CMN_MAX_CFI];
581 uint8_t newCfi; /*!< New CFI value */
582 uint8_t currCfi; /*!< Current CFI value */
584 uint16_t noResPerRb[RG_SCH_CMN_MAX_CFI]; /*!< Num REs per RB */
585 CmLteTimingInfo time; /*!< Timing info for current allocation */
586 Void *schSpfc; /*!< Scheduler Specific Cell DL dereferencing */
587 Void *dlfsCell; /*!< DLFS specific information per cell */
588 CmLListCp taLst; /*!< TA queues, holds the UEs for which TA
589 has to be scheduled */
591 RgSchCmnDlCellSpsInfo dlSpsInfo; /*!< DL SPS info for the cell */
593 /* Member to store no. of Bits per RB */
594 uint32_t bitsPerRb; /*!< Bits per RB calculated from
595 BcchPcchRaRsp Code rate configured through
598 uint16_t numReDwPts[RG_SCH_CMN_MAX_CFI-1]; /*!< Num of RE in DwPTS RB */
599 uint8_t splSfCfg; /*!<Stores the special subframe cfg */
602 /* ccpu00132314-ADD-Tx power offsets for Common PDSCH transmissions */
603 uint16_t bcchTxPwrOffset; /*!< Tx Pwr Offset for BCCH tx on PDSCH.
604 Offset to the reference signal
605 power. Value: 0 -> 10000,
606 representing -6 dB to 4 dB in 0.001
608 uint16_t pcchTxPwrOffset; /*!< Tx Pwr Offset for PCCH tx.
609 Offset to the reference signal
610 power. Value: 0 -> 10000,
611 representing -6 dB to 4 dB in 0.001
613 uint16_t rarTxPwrOffset; /*!< Tx Pwr Offset for RAR tx.
614 Offset to the reference signal
615 power. Value: 0 -> 10000,
616 representing -6 dB to 4 dB in 0.001
618 /* ccpu00138898 - Added Tx pwr offset for PHICH Tx*/
619 uint16_t phichTxPwrOffset; /*!< Tx Pwr Offset for PHICH tx.
620 Offset to the reference signal
621 power. Value: 0 -> 10000,
622 representing -6 dB to 4 dB in 0.001
624 uint32_t ncsgPrbCnt; /*!< Cumulative sum of PDSCH PRBs assigned to non-Csg UEs */
625 uint32_t totPrbCnt; /*!< Cumulative sum of PDSCH PRBs assigned to all UEs */
626 RgrUeDlPwrCntrlPaCfg msg4pAVal; /*!< Default value (Enum) of PA that is
627 used by Scheduler for msg4 */
629 CmLListCp secCellActCeLst; /*!< List for holding the UE's
630 for which sec cell act CE's needs to scheduled */
634 CmLListCp emtcTaLst; /*!< TA queues, holds the EMTC UEs for which TA
635 has to be scheduled */
636 Void *schSpfcEmtc; /*!< Scheduler Specific Cell DL dereferencing */
641 @brief Information related to TPC-PUCCH-RNTI/TPC-PUSCH-RNTI. */
642 typedef struct rgSchCmnTpcRntiCb
644 CmLteRnti tpcRnti; /*!< TPC-PUCCH-RNTI/TPC-PUSCH-RNTI*/
645 Bool isFmt3a; /*!< DCI format type: 3/3A */
646 CmLListCp toBeSchdUes; /*!< List of UEs requiring power adjustment
648 CmLListCp cfgdUes; /*!< List of UEs */
649 CmLList schdLnk; /*!< Link to the list of TPC RNTIs to be
654 @brief Uplink Power control related information per cell. */
655 typedef struct rgSchCmnUlPwrCb
657 uint8_t tpcPucchRntiCnt;/*!< Count of TPC-PUCCH-RNTIs for the cell */
658 RgSchCmnTpcRntiCb tpcPucchRntiLst[RG_SCH_CMN_MAX_NUM_TPC_PUCCH_RNTI];
659 /*!< List of TPC-PUCCH-RNTIs */
660 uint8_t tpcPuschRntiCnt;/*!< Count of TPC-PUSCH-RNTIs for the cell */
661 RgSchCmnTpcRntiCb tpcPuschRntiLst[RG_SCH_CMN_MAX_NUM_TPC_PUSCH_RNTI];
662 /*!< List of TPC-PUSCH-RNTIs */
663 CmLListCp pucchGrpPwr; /*!< List of TPC-PUCCH-RNTIs for PUCCH group
664 power control: 'RgSchCmnTpcRntiCb' */
665 CmLListCp puschGrpPwr; /*!< List of TPC-PUSCH-RNTIs for PUSCH group
666 power control: 'RgSchCmnTpcRntiCb' */
667 S8 pMax; /*!< Max allowed uplink power in cell */
668 uint8_t trgUlCqi; /*!< Default target CQI */
673 * Cell specific uplink scheduling information for Scheduler type 1.
675 typedef struct rgSchCmnUlCell
677 uint8_t maxUeNewTxPerTti; /*!< Max UEs to be considered for New Tx Alloc in UL */
678 /* Added new variable maxUlBwPerUe */
679 uint8_t maxUlBwPerUe; /*!< Max UL BW per UE */
680 uint8_t maxSbPerUe; /*!< Max subbands per UE */
681 uint8_t dfltUlCqi; /*!< Default uplink CQI assumed intitially */
682 uint8_t max16qamCqi; /*!< Highest CQI supporting 16 QAM */
683 uint8_t maxUlSpsCqi; /*!< Highest CQI supporting 16 QAM */
684 uint8_t iTbsCap; /*!< Max value UL iTbs capped to */
685 uint8_t sbSize; /*!< Subband size */
686 uint8_t dmrsArrSize; /*!< DMRS array size */
687 uint8_t *dmrsArr; /*!< DMRS array */
688 RgSchCmnUlCellRa ra; /*!< RA related info */
689 uint8_t idx; /*!< Current subframe - maps to HARQ process ID */
690 uint8_t schdIdx; /*!< Subframe to schedule for */
691 uint8_t schdHqProcIdx; /*!< Proc to schedule for */
692 uint8_t msg3SchdIdx; /*!< Subframe to schedule for msg3 */
694 RgSchCmnUlCellRa emtcRa; /*!< RA related info */
695 uint8_t emtcMsg3SchdIdx;
696 Void *schSpfcEmtc; /*!< Scheduler Specific Cell UL dereferencing */
698 uint8_t msg3SchdHqProcIdx;/*!< Proc to schedule for */
699 uint8_t rcpReqIdx; /*!< Subframe to send reception req for */
700 /* ccpu00130688 -MOD- for config-0 changes */
701 uint8_t hqFdbkIdx[2]; /*!< In FDD only Idx 0 is used.
702 In TDD n+k value is updated at idx 0.
703 For TDD Cfg 0 both indices are used */
704 uint8_t reTxIdx[2]; /*!< Retransmission Index corresponding to
707 uint8_t spsUlRsrvIdx; /*!< Subframe to reserve UL SPS cfgd grant */
708 uint8_t spsUlRsrvHqProcIdx;/*!< Proc for the cfgd UL SPS grant */
710 CmLteTimingInfo schdTime;
712 uint8_t numUlSubfrms; /*!< Number of UL subframes */
713 RgSchUlSf *ulSfArr; /*!< no msg3 alloc info here */
715 RgSchUlSf ulSfArr[RG_SCH_CMN_UL_NUM_SF]; /*!< no msg3 alloc info here */
717 Void *schSpfc; /*!< Scheduler Specific Cell UL dereferencing */
718 RgSchCmnUlPwrCb ulPwrCb; /*!< Uplink power control block */
719 uint8_t ulNumRePerRb; /*!< Number of REs per RB in UL */
720 /* Added support for non-adaptive retransmission in uplink */
721 uint8_t maxAllocPerUlSf; /*!< Max Allocations in a given SF */
723 /* Added a param to limit msg3 allocations */
724 uint8_t maxMsg3PerUlSf; /*!< Max msg3 alocs in a given SF */
728 RgSchCmnUlCellSpsInfo ulSpsInfo; /*!< UL SPS info for the cell */
729 uint16_t schdTti; /*< 0..1023, corresponding to scheduling time,
730 * can theoretically used for non-SPS
731 * purposes as well */
733 uint32_t ncsgPrbCnt; /*!< Cumulative sum of PDSCH PRBs assigned to non-Csg UEs */
734 uint32_t totPrbCnt; /*!< Cumulative sum of PDSCH PRBs assigned to all UEs */
735 CmLListCp reTxLst; /*!< Retransmission List*/
739 @brief ACK-NACK repetition related information per cell. */
740 typedef struct rgSchCmnAckNakRepCb
743 CmLListCp ackNakRepQ[2*RGSCH_NUM_SUB_FRAMES]; /*!< ACK NACK repetition queue */
745 CmLListCp ackNakRepQ[RGSCH_NUM_SUB_FRAMES]; /*!< ACK NACK repetition queue */
747 } RgSchCmnAckNakRepCb;
750 @brief Measurement Gap related information per cell. */
751 typedef struct rgSchCmnMeasGapCb
753 CmLListCp gapPrd40Q[RG_SCH_CMN_MEAS_GAPPRD40]; /*!< Measurement Gap queue
754 for UEs with 40 ms gap period */
755 CmLListCp gapPrd80Q[RG_SCH_CMN_MEAS_GAPPRD80]; /*!< Measurement Gap queue
756 for UEs with 80 ms gap period */
761 * common scheduler specific information for rapId to UE mapping. */
762 typedef struct rgSchCmnRapIdMap
765 CmLListCp assgndUes; /*!< List of UEs for which this rapId is
771 * common scheduler specific information for RACH Dedicated Preambles. */
772 typedef struct rgSchCmnRachCfg
774 uint8_t numDedPrm; /*!< number of configured dedicated prmbls */
775 uint8_t dedPrmStart; /*!< starting rapId Number */
776 uint8_t remDedPrm; /*!< remaining number of ded Prm available
778 CmLteTimingInfo applFrm; /*!< Frame under consideration for dedPrm
780 uint8_t prachMskIndx;/*!< Prach Mask Idx corresponding to
782 RgSchCmnRapIdMap rapIdMap[RG_SCH_MAX_DED_PRMBLS]; /*!< mapping of RapId
784 CmLListCp hoUeLst; /*!< List of UEs undergoing Handover */
785 CmLListCp pdcchOdrLst; /*!< Pdcch Order Q, holds the UEs for which
786 PO has to be generated. */
790 @brief Uplink Power control related information per UE. */
791 typedef struct rgSchCmnUeUlPwrCb
793 Bool isAccumulated; /*!< Indicates if power is accumulative or not */
794 Bool deltaMcsEnbld; /*!< Indicates if coding effeciency is
795 * considered or not for PUSCH power computation */
796 uint8_t pucchIdx; /*!< Index for TPC-PUCCH-RNTI */
797 uint8_t puschIdx; /*!< Index for TPC-PUSCH-RNTI */
798 uint8_t isPhrAvail; /*!< Indicates if PHR is recieved */
799 S8 phVal; /*!< Power headroom value in dB */
800 S8 pwrPerRb; /*!< UL power computed per RB */
801 S8 maxUePwr; /*!< Maximum power with which UE can transmit */
802 uint8_t maxUlRbs; /*!< Maximum number of UL Rbs for UL scheduling */
803 S8 delta; /*!< Delta corresponding to TPC, for PUSCH */
804 uint8_t numRb; /*!< Number of RBs used in last allocation */
805 S8 remPuschPwr; /*!< PUSCH power remaining to be adjusted
806 (in db) */ /* chk if needed */
807 S8 remPucchPwr; /*!< PUCCH Power remaining to be adjusted (in db) */
808 uint8_t pucchTpc; /*!< TPC to be used for PUCCH power control */
809 uint8_t puschTpc; /*!< TPC to be used for PUSCH power control */
810 uint8_t trgCqi; /*!< Target CQI */
811 RgSchCmnTpcRntiCb *tpcPucchRntiCb; /*!< Pointer to tpcPucchRntiCb for the UE */
812 CmLList pucchGrpLnk; /*!< To link together UEs in
813 * RgSchCmnTpcRntiCb */
814 CmLList schdPucchGrpLnk; /*!< To link together scheduled
815 * UEs in RgSchCmnTpcRntiCb */
816 RgSchCmnTpcRntiCb *tpcPuschRntiCb; /*!< Pointer to tpcPuschRntiCb for the UE */
817 CmLList puschGrpLnk; /*!< To link together UEs in
818 * RgSchCmnTpcRntiCb */
819 CmLList schdPuschGrpLnk; /*!< To link together scheduled
820 * UEs in RgSchCmnTpcRntiCb */
821 S8 p0UePusch; /*!< P_0UE_PUSCH*/
822 S8 p0UePucch; /*!< P_0_PUCCH*/
828 @brief Uplink RB allocation information. */
829 struct rgSchCmnUeUlAlloc
832 uint32_t reqBytes; /*!< Requested bytes */
834 /* Allocation to be filled by UL RB allocator module */
835 uint32_t allocdBytes; /*!< Allocated bytes */
836 RgSchUlAlloc *alloc; /*!< Alloc assgnd by Allocator */
837 CmLList reqLnk; /*!< To link UL Tx UEs */
838 CmLList schdLstLnk; /*!< To link scheduled/non-scheduled UL UEs */
841 typedef struct rgSchCmnAllocRecord
843 uint32_t alloc; /* allocation amount */
844 CmLteTimingInfo allocTime; /* Time at which allocation made */
845 CmLList lnk; /* To link in ulAllocLst */
846 uint8_t numRb; /* Number of RBs */
847 uint8_t cqi; /* CQI assumed for allocation */
848 uint8_t tpc; /* TPC */
849 }RgSchCmnAllocRecord;
854 * Uplink Bler LA information for UE
857 typedef struct ueUlLaCb
860 uint32_t iTbsUpperCap;
862 Bool lastiTbsIgnored;
868 * Uplink information for scheduler per UE
870 typedef struct rgSchCmnUlUe
872 uint8_t maxUlCqi; /*!< CQI for which no better Imcs can be granted */
873 uint8_t crntUlCqi[RG_SCH_MAX_UL_TX_ANT]; /*!< Current CQI */
874 /* Added changes of TFU_UPGRADE */
878 uint8_t lastCfi; /* last CFI, updated in case of SPS */
879 CmLListCp ulAllocLst; /*!< To track the outstanding Allocations
880 * node type RgSchCmnAllocRecord */
883 Void *schSpfc; /*!< scheduler specific UE DL Info */
884 RgSchCmnUeUlPwrCb ulPwrCb; /*!< Uplink power control block */
885 RgSchCmnUeUlAlloc alloc; /*!< Allocation info */
887 uint32_t schedOccns; /*!< Number of scheduling occassions in a refresh period */
888 uint32_t schedRetxOccns;
889 uint32_t avgCqi; /*!< AvgCqi in a refresh period */
890 uint32_t numCqiOccns;
894 UeUlLaCb ulLaCb; /*!< Uplink LA structure */
896 RgUeUlHqCb hqEnt; /*!< Uplink HARQ information for the UE */
897 uint8_t subbandShare; /*!< New variable added to store the number
898 * of subbands alowed for this UE */
899 uint32_t subbandRequired; /*!< Number of subbands required to
900 * serve the total BO */
901 CmLList ulSchedLnk; /*!< To link UE UL Cb to toBeSchedList */
903 RgSchUlHqProcCb *tempProc; /*!< To identify UE is serverd for Retx */
906 uint8_t vrbgRequired;
907 uint8_t vrbgAllocated;
912 @brief Downlink RB allocation information for Msg4. */
913 typedef struct rgSchCmnMsg4RbAlloc
915 RgSchDlSf *msg4DlSf; /*!< DL sub-frame for which allocation is to
916 be done: filled in by RR/MAX C/I/PFS */
917 CmLListCp msg4TxLst; /*!< List of RgSchDlRbAllocs for Msg4 Tx */
918 CmLListCp msg4RetxLst; /*!< List of RgSchDlRbAllocs for Msg4 ReTx */
919 CmLListCp schdMsg4TxLst; /*!< List of Msg4 Txs scheduled per TTI */
920 CmLListCp schdMsg4RetxLst; /*!< List of Msg4 ReTxs scheduled in the TTI */
921 CmLListCp nonSchdMsg4TxLst; /*!< List of transmitting MSG4 not scheduled in the TTI */
922 CmLListCp nonSchdMsg4RetxLst; /*!< List of re-transmitting MSG4 not
923 scheduled in the TTI */
924 } RgSchCmnMsg4RbAlloc;
926 /* Changes for CR timer implementation*/
927 typedef struct rgSchCmnCcchSduRbAlloc
929 RgSchDlSf *ccchSduDlSf; /*!< DL sub-frame for which allocation is to
930 be done: filled in by RR/MAX C/I/PFS */
931 CmLListCp ccchSduTxLst; /*!< List of RgSchDlRbAllocs for CcchSdu Tx */
932 CmLListCp ccchSduRetxLst; /*!< List of RgSchDlRbAllocs for CcchSdu ReTx */
933 CmLListCp schdCcchSduTxLst; /*!< List of CcchSdu Txs scheduled per TTI */
934 CmLListCp schdCcchSduRetxLst; /*!< List of CcchSdu ReTxs scheduled in the TTI */
935 CmLListCp nonSchdCcchSduTxLst; /*!< List of transmitting MSG4 not scheduled in the TTI */
936 CmLListCp nonSchdCcchSduRetxLst; /*!< List of re-transmitting MSG4 not
937 scheduled in the TTI */
938 } RgSchCmnCcchSduRbAlloc;
942 @brief Downlink RB allocation information for UEs. */
943 typedef struct rgSchCmnUeRbAlloc
945 RgSchDlSf *dedDlSf; /*!< DL sub-frame for which dedicated
946 allocation is to be done: filled in
948 CmLListCp txHqPLst; /*!< List of HqPs to be scheduled for Tx per
949 TTI: RgSchUeCb list */
950 CmLListCp retxHqPLst; /*!< List of HqPs scheduled for ReTx per
951 TTI: RgSchUeCb list */
952 CmLListCp errIndTxHqPLst; /*!< LAA SCELL: List of transmitting LAA Err Ind Tx HqPs scheduled per TTI */
954 CmLListCp retxSpsHqPLst; /*!< List of SPS HqPs scheduled for ReTx per
955 TTI: RgSchUeCb list */
956 CmLListCp txSpsHqPLst; /*!< List of SPS HqPs scheduled for Tx per
957 TTI: RgSchUeCb list */
959 CmLListCp txLaaHqPLst; /*!< List of LAA HqPs scheduled on PCell for Tx per
961 CmLListCp schdTxHqPLst; /*!< List of transmitting HqPs scheduled per TTI */
962 CmLListCp schdRetxHqPLst; /*!< List of re-transmitting HqPs scheduled per TTI */
963 CmLListCp nonSchdTxHqPLst; /*!< List of transmitting HqPs not scheduled in the TTI */
964 CmLListCp nonSchdRetxHqPLst;/*!< List of re-transmitting HqPs not scheduled in the TTI */
965 /* Changes for MIMO feature addition */
966 /* MIMO Tx+Retx hqProc scheduling handling */
967 CmLListCp txRetxHqPLst; /*!< List of HqPs scheduled for tx and retx per
968 TTI(MIMO case): RgSchUeCb list */
969 CmLListCp schdTxRetxHqPLst; /*!< List of TX&RETXing(MIMO case) HqPs scheduled per TTI */
970 CmLListCp nonSchdTxRetxHqPLst; /*!< List of TX&RETXing(MIMO case) HqPs not scheduled in the TTI */
972 CmLListCp schdRetxSpsHqPLst; /*!< List of re-transmitting SPS HqPs scheduled per TTI */
973 CmLListCp nonSchdRetxSpsHqPLst;/*!< List of re-transmitting SPS HqPs
974 not scheduled in the TTI */
975 CmLListCp schdTxSpsHqPLst; /*!< List of transmitting SPS HqPs scheduled per TTI */
976 CmLListCp nonSchdTxSpsHqPLst; /*!< List of transmitting SPS HqPs not scheduled per TTI */
978 CmLListCp schdTxLaaHqPLst; /*!< List of transmitting LAA TBs scheduled on PCell per TTI */
979 CmLListCp nonSchdTxLaaHqPLst; /*!< List of transmitting LAA TBs not scheduled on PCell per TTI */
980 CmLListCp schdErrIndTxHqPLst; /*!< List of transmitting LAA ErrInd TBs scheduled per TTI */
981 CmLListCp nonSchdErrIndTxHqPLst; /*!< List of transmitting LAA ErrInd not scheduled per TTI */
985 @brief Downlink RB allocation information. */
986 struct rgSchCmnDlRbAllocInfo
988 RgSchDlRbAlloc pcchAlloc; /*!< Allocation for PCCH */
989 RgSchDlRbAlloc bcchAlloc; /*!< Allocation for BCCH on DLSCH */
990 RgSchDlRbAlloc raRspAlloc[RG_SCH_CMN_MAX_CMN_PDCCH]; /*!< Allocation for RAR */
991 RgSchCmnMsg4RbAlloc msg4Alloc; /*!< Alloction for Msg4 */
993 /* Changes for CR timer implementation*/
994 RgSchCmnCcchSduRbAlloc ccchSduAlloc; /*!< Alloction for ccchSdu */
996 RgSchCmnUeRbAlloc dedAlloc; /*!< Alloction information for UEs */
1001 * Cell specific common scheduler information for all Scheduler types.
1003 typedef struct rgSchCmnCell
1005 RgrCfiCfg cfiCfg; /*!< CFI for PDCCH */
1006 RgrUlTrgCqiCfg trgUlCqi; /*!< Target UL CQI */
1007 CmTqCp tmrTqCp; /*!< Refresh Timer Task Queue
1009 CmTqType tmrTq[RG_SCH_CMN_NUM_REFRESH_Q]; /*!< Timer Task Queue */
1010 RgrDlCmnCodeRateCfg dlCmnCodeRate; /*!< Coding rate for common DL channels:
1011 Expressed in multiples of 1024 */
1012 RgrPuschSubBandCfg puschSubBand; /*!< UL subband information */
1013 RgrUlCmnCodeRateCfg ulCmnCodeRate; /*!< Coding rate for common UL channels:
1014 Expressed in multiples of 1024 */
1015 RgSchCmnRachCfg rachCfg; /*!< Rach configuration for schCmn */
1016 RgSchCmnUlCell ul; /*!< Scheduler UL info */
1017 RgSchCmnDlCell dl; /*!< Scheduler DL info */
1018 RgUlSchdApis *apisUl; /*!< Specific UL Scheduler APIs */
1019 RgDlSchdApis *apisDl; /*!< Specific DL Scheduler APIs */
1020 RgDlfsSchdApis *apisDlfs; /*!< APIs specific to DLFS scheduler */
1022 RgUlSchdApis *apisEmtcUl; /*!< Specific UL Scheduler APIs for EMTC*/
1023 RgDlEmtcSchdApis *apisEmtcDl; /*!< Specific DL Scheduler APIs for EMTC*/
1025 CmLteAggrLvl dciAggrLvl[RG_SCH_CMN_MAX_CQI][10];
1026 /*!< Aggr Level for each CQI for
1027 * each DCI Format */
1028 RgSchCmnDlRbAllocInfo allocInfo;
1034 * RACHO information for scheduler per UE.
1036 typedef struct rgSchCmnDlUeRachInfo
1038 CmLList inActUeLnk; /*!< Link UE to PO inactUeList */
1039 CmLList poLnk; /*!< To link UE to PDCCH Order Q */
1040 CmLList hoLnk; /*!< To link UE to HandOver UE lst */
1041 CmLList rapIdLnk; /*!< Link to the list assgndUes */
1042 CmLteTimingInfo asgnOppr; /*!< PRACH oppurtunity time assgined to UE */
1043 uint8_t hoRapId; /*!< RAPID assigned to UE for HandOver */
1044 uint8_t poRapId; /*!< RAPID assigned to UE for PdcchOrder */
1045 }RgSchCmnDlUeRachInfo;
1050 * Downlink CodeWord information for scheduler per UE.
1052 typedef struct rgSchCmnDlUeCwInfo
1054 uint8_t cqi; /*!< CQI reported for this CW */
1055 uint8_t iTbs[2]; /*!< [0]ITBS for CW for 1 Layer,
1056 corresponding to this CW's cqi. */
1057 /*!< [1]ITBS for CW for 2 Layer,
1058 corresponding to this CW's cqi. */
1059 uint32_t eff[2]; /*!< [0]eff for CW for 1 Layer,
1060 corresponding to this CW's cqi. */
1061 /*!< [1]eff for CW for 2 Layer,
1062 corresponding to this CW's cqi. */
1063 uint8_t noLyr; /*!< No. of layers this CW shall be using
1064 * for transmission */
1068 }RgSchCmnDlUeCwInfo;
1070 * @brief UE cmn scheduler specific MIMO Info.
1072 typedef struct rgSchCmnUeMimoInfo
1074 RgSchCmnDlUeCwInfo cwInfo[RG_SCH_CMN_MAX_CW_PER_UE];/*!< Codeword related feddback Information */
1075 uint8_t ri; /*!< Maximum allowable number of TX layers for SM */
1076 uint8_t pmi; /*!< Precoding matrix indicator(if any) */
1077 uint8_t btrCwIdx; /*!< Index of a better(efficient) CW (0 or 1) */
1078 uint8_t forceTD; /*!< Flag to indicate transmission scheme as TD
1079 * beyond any other consideration */
1080 }RgSchCmnUeMimoInfo;
1082 typedef struct ueLaCb {
1084 uint32_t iTbsUpperCap;
1086 Bool lastiTbsIgnored;
1087 uint8_t notFirstCqi;
1088 uint8_t numLastiTbsIgnored;
1093 * Downlink information for scheduler per UE.
1095 typedef struct rgSchCmnDlUe
1097 uint32_t maxSbSz; /*!< Max soft channel bits per Hq proc per TTI */
1098 uint32_t maxTbSz; /*!< Max DLSCH TB bits per TB per TTI */
1099 uint8_t maxRb; /*!< updated based on SoftBuffer Limitation and MaxDlBwPerUE */
1100 uint32_t maxTbBits;/*!< Max Transport Block Bits this UE can receive per TTI*/
1101 RgSchCmnUeMimoInfo mimoInfo; /*!< UE cmn scheduler specific MIMO Info */
1102 RgSchDlHqProcCb *proc; /*!< Proc which is picked for Trans for this Subfrm,"dlSf" */
1103 Void *schSpfc; /*!< scheduler specific UE DL Info */
1104 Void *dlfsUe; /*!< DLFS Specific information */
1105 uint32_t outStndAlloc; /*!< UEs outstanding allocation, for a given TTI.
1106 * valid for a single scheduling index */
1107 RgSchCmnDlUeRachInfo rachInfo; /*!< Ue specific RACH HO Info */
1109 RgSchCmnDlUeSpsInfo dlSpsInfo;/*!< DL SPS information for the UE */
1111 #if defined(SCH_STATS) || defined(TENB_STATS)
1112 uint32_t schedOccns;
1113 uint32_t currPdbLvl;
1114 uint32_t prevOccnLvlUpd;
1115 /* uint32_t schedRetxOccns;
1116 uint32_t prbAlloc;*/
1119 uint32_t schedRetxOccns;
1121 uint32_t numCqiOccns;
1124 uint32_t boReported;
1126 uint32_t remAmbrForStats;
1128 UeLaCb laCb[RG_SCH_CMN_MAX_CW_PER_UE];
1132 uint8_t vrbgRequired;
1133 uint8_t vrbgAllocated;
1138 @brief Uplink RB allocation information. */
1139 struct rgSchCmnUlRbAllocInfo
1142 RgSchEmtcUlSf *ulsf;
1144 RgSchUlSf *sf; /*!< Subframe to schedule for */
1145 CmLListCp contResLst; /*!< UEs to schedule for cnt resn */
1146 CmLListCp schdContResLst; /*!< Final UEs scheduled for cnt resn */
1147 CmLListCp nonSchdContResLst; /*!< UEs not scheduled for cnt resn*/
1148 CmLListCp ueLst; /*!< UEs to schedule for data */
1149 CmLListCp schdUeLst; /*!< Final UEs scheduled for data */
1150 CmLListCp nonSchdUeLst; /*!< Final UEs not scheduled for data */
1155 * Information common to DL and UL scheduler per UE.
1157 typedef struct rgSchCmnUeInfo
1159 uint8_t ueCat; /*!< UE category */
1164 * Information for scheduler per UE.
1166 typedef struct rgSchCmnUe
1168 RgSchCmnUeInfo cmn; /*!< UE specific scheduler information common to
1169 uplink and downlink */
1170 RgSchCmnUlUe ul; /*!< UE specific UL scheduler information */
1171 RgSchCmnDlUe dl; /*!< UE specific DL scheduler informaion */
1174 typedef struct rgSchCmnLcg
1176 uint32_t bs; /*!< Effective Buffer Status */
1177 uint32_t cfgdGbr; /*!< Configured GBR */
1178 uint32_t effGbr; /*!< Effective GBR */
1179 uint32_t deltaMbr; /*!< Configured MBR in excess of configured GBR */
1180 uint32_t effDeltaMbr; /*!< Effective MBR */
1181 uint32_t reportedBs; /*!< Latest Buffer Status */
1188 * SPS information for DL service
1190 typedef struct rgSchCmnDlSvcSpsInfo
1192 CmLList toBeSchdSvcEnt; /*!< Linked list entity for toBeSchdSvcs lst */
1193 uint16_t zeroBoOcassionCnt; /*!< Number of contiguous SPS ocassions for
1195 uint32_t effSpsBo; /*!< Effective BO of the SPS service */
1196 uint32_t bytesReq; /*!< Bytes Requested for this SPS service */
1197 uint8_t hdrEst; /*!< Header estimate for SPS service */
1199 } RgSchCmnDlSvcSpsInfo;
1202 typedef struct rgSchCmnDlSvc {
1203 uint8_t qci; /*!< Prio computed against Qci */
1204 uint8_t prio; /*!< Prio computed against Qci */
1205 uint32_t gbr; /*!< scaled GBR as per Refresh time resolution */
1206 uint32_t mbr; /*!< scaled MBR as per Refresh time resolution */
1207 Void *schSpfc[CM_LTE_MAX_CELLS];/*!< Scheduler specific Info */
1209 RgSchCmnDlSvcSpsInfo dlSvcSpsInfo; /*!< SPS related information for DL
1214 typedef struct rgSchCmnDlHqProc {
1215 CmLList retxLnk; /*!< To link retransmitting HARQ processes in cell */
1216 uint32_t totBytes;/*!< This maintains total allocation */
1218 Bool isSpsSvcSchd;/*!< Indicates if this HARQ process is having SPS
1219 service scheduled: TRUE for SPS and non-SPS
1221 Bool isSpsActv; /*!< Indicates if this HARQ proc
1222 is in-use for SPS transmission: TRUE only for
1224 uint8_t spsAction; /*!< SPS action associated with this HARQ proc:
1225 activation/reactivation */
1226 CmLteTimingInfo maxRetxTime; /*!< Maximum retransmission time for SPS HARQ
1229 Void *schSpfc;/*!< Scheduler specific Info */
1232 /*--------------------------*
1233 * UL specific declarations END
1234 *---------------------------*/
1236 /* Inappropriate name of CQI to ITbs table for DL. */
1237 typedef uint8_t RgSchCmnCqiToTbs[16];
1238 /* The following data type is used to store computed efficiency */
1239 /* for each MCS and consequently, will be used to derive MCS */
1240 /* for a CQI. The last row is used for storing the average */
1241 typedef uint32_t RgSchCmnTbSzEff[RG_SCH_CMN_NUM_TBS];
1243 /* Inappropriate name of CQI to ITbs table for DL. */
1244 /* Changes for MIMO feature addition */
1245 RgSchCmnTbSzEff rgSchCmnNorCfi1Eff[RGSCH_MAX_NUM_LYR_PERCW], rgSchCmnNorCfi2Eff[RGSCH_MAX_NUM_LYR_PERCW];
1246 RgSchCmnTbSzEff rgSchCmnNorCfi3Eff[RGSCH_MAX_NUM_LYR_PERCW], rgSchCmnNorCfi4Eff[RGSCH_MAX_NUM_LYR_PERCW];
1247 /* Added new variable for Ul eff */
1248 RgSchCmnTbSzEff rgSchCmnNorUlEff[1],rgSchCmnExtUlEff[1];
1249 RgSchCmnCqiToTbs rgSchCmnNorCfi1CqiToTbs[RGSCH_MAX_NUM_LYR_PERCW], rgSchCmnNorCfi2CqiToTbs[RGSCH_MAX_NUM_LYR_PERCW];
1250 RgSchCmnCqiToTbs rgSchCmnNorCfi3CqiToTbs[RGSCH_MAX_NUM_LYR_PERCW], rgSchCmnNorCfi4CqiToTbs[RGSCH_MAX_NUM_LYR_PERCW];
1251 RgSchCmnCqiToTbs *rgSchCmnCqiToTbs[RGSCH_MAX_NUM_LYR_PERCW][RG_SCH_CMN_MAX_CP][RG_SCH_CMN_MAX_CFI];
1252 RgSchCmnTbSzEff rgSchCmnExtCfi1Eff[RGSCH_MAX_NUM_LYR_PERCW], rgSchCmnExtCfi2Eff[RGSCH_MAX_NUM_LYR_PERCW];
1253 RgSchCmnTbSzEff rgSchCmnExtCfi3Eff[RGSCH_MAX_NUM_LYR_PERCW], rgSchCmnExtCfi4Eff[RGSCH_MAX_NUM_LYR_PERCW];
1254 RgSchCmnCqiToTbs rgSchCmnExtCfi1CqiToTbs[RGSCH_MAX_NUM_LYR_PERCW], rgSchCmnExtCfi2CqiToTbs[RGSCH_MAX_NUM_LYR_PERCW];
1255 RgSchCmnCqiToTbs rgSchCmnExtCfi3CqiToTbs[RGSCH_MAX_NUM_LYR_PERCW], rgSchCmnExtCfi4CqiToTbs[RGSCH_MAX_NUM_LYR_PERCW];
1256 /* Include CRS REs while calculating Efficiency */
1258 *rgSchCmnEffTbl[RGSCH_MAX_NUM_LYR_PERCW][RG_SCH_CMN_MAX_CP][RG_SCH_CMN_MAX_ANT_CONF][RG_SCH_CMN_MAX_CFI];
1259 /* Added new variable for Ul eff */
1260 RgSchCmnTbSzEff *rgSchCmnUlEffTbl[RG_SCH_CMN_MAX_CP];
1262 RgSchTbSzTbl rgTbSzTbl;
1264 Void rgSCHCmnInit ARGS((Void
1266 S16 rgSCHCmnRgrCellCfg ARGS((
1268 RgrCellCfg *cellCfg,
1271 S16 rgSCHCmnRgrCellRecfg ARGS((
1273 RgrCellRecfg *recfg,
1276 Void rgSCHCmnFreeDlLc ARGS((
1281 Void rgSCHCmnCellDel ARGS((
1284 Void rgSCHCmnDlRlsSubFrm ARGS((
1289 S16 rgSCHCmnRgrSCellUeCfg ARGS((
1292 RgrUeSecCellCfg *sCellInfoCfg,
1296 Void rgSchFreeTpcIdxForSCell ARGS((
1298 RgSchDlHqProcCb *proc,
1302 Bool rgSchIsN1PucchResAvail ARGS((
1308 Bool rgSchIsN3PucchResAvail ARGS((
1314 S16 rgSchGetAvlTpcIdx ARGS((
1321 Void rgSCHSCellDelUeSCell ARGS((
1322 RgSchCellCb *cellCb,
1327 S16 rgSCHCmnRgrSCellUeDel ARGS((
1328 RgSchUeCellInfo *sCellInfo,
1332 #endif /* LTE_ADV */
1333 S16 rgSCHCmnRgrUeCfg ARGS((
1339 S16 rgSCHCmnRgrUeRecfg ARGS((
1342 RgrUeRecfg *ueRecfg,
1345 Void rgSCHCmnUeDel ARGS((
1349 Void rgSCHCmnUeReset ARGS((
1353 S16 rgSCHCmnRgrLcgRecfg ARGS((
1360 S16 rgSCHCmnRgrLcgCfg ARGS((
1367 S16 rgSCHCmnRgrLchCfg ARGS((
1374 S16 rgSCHCmnRgrLchDel ARGS((
1380 S16 rgSCHCmnRgrLchRecfg ARGS((
1384 RgrLchRecfg *lcRecfg,
1387 Void rgSCHCmnLcgDel ARGS((
1392 S16 rgSCHCmnUpdBsrShort ARGS((
1399 S16 rgSCHCmnUpdBsrTrunc ARGS((
1406 S16 rgSCHCmnUpdBsrLong ARGS((
1412 S16 rgSCHCmnDataRcvd ARGS((
1416 RgSchUlLcCb *lcArr[],
1417 uint16_t bytesArr[],
1420 Void rgSCHCmnUlCqiInd ARGS((
1423 TfuUlCqiRpt *ulCqiInfo
1425 S16 rgSCHCmnUpdExtPhr ARGS((
1428 RgInfExtPhrCEInfo *extPhr,
1431 S16 rgSCHCmnUpdPhr ARGS((
1437 S16 rgSCHCmnUpdUlHqProc ARGS((
1439 RgSchUlHqProcCb *curProc,
1440 RgSchUlHqProcCb *oldProc
1442 S16 rgSCHCmnContResUlGrant ARGS((
1447 Void rgSCHCmnActvtUlUe ARGS((
1451 Void rgSCHCmnActvtDlUe ARGS((
1455 Void rgSCHCmnHdlUlTransInd ARGS((
1458 CmLteTimingInfo timingInfo
1460 S16 rgSCHCmnSrRcvd ARGS((
1463 CmLteTimingInfo frm,
1466 Void rgSCHCmnUlRbAllocAddUeToLst ARGS((
1471 S16 rgSCHCmnTti ARGS((
1475 Void rgSCHCmnUlHqProcForUe ARGS((
1477 CmLteTimingInfo frm,
1479 RgSchUlHqProcCb **procRef
1481 RgSchUlAlloc *rgSCHCmnFirstRcptnReq ARGS((
1484 RgSchUlAlloc *rgSCHCmnNextRcptnReq ARGS((
1488 RgSchUlAlloc *rgSCHCmnFirstHqFdbkAlloc ARGS((
1492 RgSchUlAlloc *rgSCHCmnNextHqFdbkAlloc ARGS((
1494 RgSchUlAlloc *alloc,
1497 Void rgSCHCmnDlDedBoUpd ARGS((
1502 /* Fix: syed Remove the msg4Proc from cell
1503 * msg4Retx Queue. I have used CMN scheduler function
1504 * directly. Please define a new API and call this
1505 * function through that. */
1506 Void rgSCHCmnDlMsg4ProcRmvFrmRetx ARGS((
1508 RgSchDlHqProcCb *hqP
1510 Void rgSCHCmnDlProcAddToRetx ARGS((
1512 RgSchDlHqProcCb *hqP
1516 Void rgSCHCmnEmtcUlProcAddToRetx ARGS((
1518 RgSchUlHqProcCb *hqP
1522 Void rgSCHCmnDlCqiInd ARGS((
1527 CmLteTimingInfo timingInfo
1529 /* Added changes of TFU_UPGRADE */
1531 Void rgSCHCmnRawCqiInd ARGS
1533 RgSchCellCb *cellCb,
1535 TfuRawCqiRpt *rawCqiRpt,
1536 CmLteTimingInfo timingInfo
1539 Void rgSCHCmnSrsInd ARGS
1541 RgSchCellCb *cellCb,
1544 CmLteTimingInfo timingInfo
1546 #endif /* TFU_UPGRADE */
1548 Void rgSCHCmnDlTARpt ARGS((
1552 RgSchPdcch *rgSCHCmnCmnPdcchAlloc ARGS((
1556 RgSchUlAlloc *rgSCHCmnUlSbAlloc ARGS((
1561 Void rgSCHCmnRlsUlSf ARGS((
1566 /* PHR handling for MSG3 */
1567 Void rgSCHCmnUlRecMsg3Alloc ARGS((
1573 /* Added periodic BSR timer */
1575 /*ccpu00117180 - ADD - Added Prototype in .x since the function access is now */
1576 Void rgSCHCmnUpdVars ARGS((
1581 Void rgSCHCmnFillHqPTb ARGS((
1583 RgSchDlRbAlloc *rbAllocInfo,
1588 Void rgSCHCmnDlProcAck ARGS((
1590 RgSchDlHqProcCb *hqP
1592 Void rgSCHCmnHdlCrntiCE ARGS((
1596 Void rgSCHCmnDlRelPdcchFbk ARGS((
1601 Void rgSCHCmnDlGetRbgInfo ARGS((
1604 uint8_t maxRaType1SubsetBw,
1606 RgSchBwRbgInfo *rbgInfo
1608 uint8_t rgSCHCmnDlRaType0Alloc ARGS((
1609 RgSchDlSfAllocInfo *allocedInfo,
1611 RgSchBwRbgInfo *rbgInfo,
1612 uint8_t *numAllocRbs,
1613 RgSchDlSfAllocInfo *resAllocInfo,
1616 #ifdef RGSCH_SPS_UNUSED
1617 uint8_t rgSCHCmnDlRaType1Alloc ARGS((
1618 RgSchDlSfAllocInfo *allocedInfo,
1620 RgSchBwRbgInfo *rbgInfo,
1621 uint8_t startRbgSubset,
1622 uint8_t *allocRbgSubset,
1623 RgSchDlSfAllocInfo *resAllocInfo,
1627 uint8_t rgSCHCmnDlRaType2Alloc ARGS((
1628 RgSchDlSfAllocInfo *allocedInfo,
1630 RgSchBwRbgInfo *rbgInfo,
1632 RgSchDlSfAllocInfo *resAllocInfo,
1635 Bool rgSCHCmnAllocUeInSpsBw ARGS((
1639 RgSchDlRbAlloc *rbAllocInfo,
1643 Void rgSCHCmnDrxStrtInActvTmrInUl ARGS((RgSchCellCb *cell));
1644 Void rgSCHCmnUpdUeDataIndLcg ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgInfUeDatInd *datInd));
1646 uint8_t rgSCHCmnGetPhichUlSfIdx ARGS((CmLteTimingInfo *timeInfo, RgSchCellCb *cell));
1647 uint8_t rgSCHCmnGetUlSfIdx ARGS((CmLteTimingInfo *timeInfo, RgSchCellCb *cell));
1648 uint8_t rgSCHCmnGetPValFrmCCE ARGS((RgSchCellCb *cell, uint8_t cce));
1650 uint8_t rgSCHCmnGetUlHqProcIdx ARGS((CmLteTimingInfo *timeInfo, RgSchCellCb *cell));
1652 Void rgSchCmnSetCqiReqField ARGS((
1653 RgSchUeCellInfo *cellInfo,
1655 RgSchCqiReqField *cqiReq
1658 /* APIs exposed by COMMON SCHEDULER to
1659 * SPECIFIC SCHEDULER */
1660 /* UL_ALLOC_CHANGES */
1661 Void rgSCHCmnUlFreeAlloc ARGS((
1666 Void rgSCHCmnUlFreeAllocation ARGS((
1672 Void rgSCHCmnUlFreeAllocation ARGS((
1675 RgSchUlAlloc *alloc,
1679 /* APIs exposed by DL RB allocation module */
1680 S16 rgSCHCmnAllocDlRb ARGS((
1682 RgSchCmnDlRbAllocInfo *dlRbAllocInfo
1685 /* APIs exposed by UL RB allocation module */
1686 Void rgSCHCmnAllocUlRb ARGS((
1688 RgSchCmnUlRbAllocInfo *ulRbAllocInfo
1691 /* APIs Exposed to Specific Scheduler */
1692 RgSchPdcch *rgSCHCmnPdcchAllocCrntSf ARGS((
1696 Void rgSCHCmnPdcchRlsCrntSf ARGS((
1700 Void rgSCHCmnUlFillPdcchWithAlloc ARGS((
1702 RgSchUlAlloc *alloc,
1705 Void rgSCHCmnUlAllocFillTpc ARGS((
1710 Void rgSCHCmnUlAllocFillNdmrs ARGS((
1711 RgSchCmnUlCell *cellUl,
1714 Void rgSCHCmnUlAllocLnkHqProc ARGS((
1716 RgSchUlAlloc *alloc,
1717 RgSchUlHqProcCb *proc,
1720 RgSchPdcch *rgSCHCmnPdcchAlloc ARGS((
1725 TfuDciFormat dciFrmt,
1728 Void rgSCHCmnRdcImcsTxTb ARGS((
1729 RgSchDlRbAlloc *allocInfo,
1733 Void rgSCHCmnFillPdcch ARGS((
1736 RgSchDlRbAlloc *rbAllocInfo
1738 uint8_t rgSCHCmnUpdDai ARGS((
1740 CmLteTimingInfo *fdbkTime,
1743 RgSchDlHqProcCb *hqP,
1747 Void rgSCHCmnFillHqPPdcch ARGS((
1749 RgSchDlRbAlloc *rbAllocInfo,
1750 RgSchDlHqProcCb *hqP
1752 S16 rgSCHCmnDlChkResAvl ARGS((
1756 RgSchDlHqProcCb *proc,
1761 S16 rgSCHCmnDlDedAlloc ARGS((
1765 RgSchDlHqProcCb *proc,
1771 Void rgSCHCmnUlUeFillAllocInfo ARGS((
1775 /* Fixing incorrect Imcs derivation */
1776 uint8_t rgSCHCmnUlGetITbsFrmIMcs ARGS((
1779 /* Adding ueCtg to argument list */
1780 uint8_t rgSCHCmnUlGetIMcsFrmITbs ARGS((
1782 CmLteUeCategory ueCtg
1784 uint32_t rgSCHCmnUlMinTbBitsForITbs ARGS((
1785 RgSchCmnUlCell *cellUl,
1788 uint8_t rgSCHCmnUlGetITbs ARGS((
1793 Void rgSCHCmnUlAllocFillRbInfo ARGS((
1798 Void rgSCHCmnDlUeResetTemp ARGS((
1800 RgSchDlHqProcCb *hqP
1802 Void rgSCHCmnUlUeResetTemp ARGS((
1806 /* proc is added for DTX support */
1807 /* DL per UE RB allocation API */
1808 S16 rgSCHCmnDlAllocTxRb ARGS((
1814 RgSchDlHqProcCb *proc,
1815 RgSchCmnDlRbAllocInfo *cellWdAllocInfo
1817 Bool rgSCHCmnIsDlCsgPrio ARGS((
1820 Bool rgSCHCmnIsUlCsgPrio ARGS((
1823 S16 rgSCHCmnDlAllocRetxRb ARGS((
1829 RgSchDlHqProcCb *proc,
1830 RgSchCmnDlRbAllocInfo *cellWdAllocInfo
1833 Void rgSCHCmnClcRbAlloc ARGS((
1844 uint32_t rgSCHCmnCalcRiv ARGS((
1849 #endif /* LTEMAC_SPS */
1851 /* end: Apis to add Ues in to DlRbAllocInfo Lists */
1852 /* start: Apis to add Ues in to UlRbAllocInfo Lists */
1853 Void rgSCHCmnUlAdd2UeLst ARGS((
1855 RgSchCmnUlRbAllocInfo *allocInfo,
1858 Void rgSCHCmnUlAdd2CntResLst ARGS((
1859 RgSchCmnUlRbAllocInfo *allocInfo,
1862 Void rgSCHCmnRmvFrmTaLst ARGS((
1866 /* end: Apis to add Ues in to UlRbAllocInfo Lists */
1867 Void rgSCHCmnUlUpdOutStndAlloc ARGS((
1873 Void rgSCHCmnUlRecordUeAlloc ARGS((
1880 /* APIs exposed by common power module */
1881 Void rgSCHPwrInit ARGS((
1883 uint8_t rgSCHPwrPuschTpcForUe ARGS((
1886 uint8_t rgSCHPwrGetMaxUlRb ARGS((
1889 uint8_t rgSCHPwrPucchTpcForUe ARGS((
1892 Void rgSCHPwrGrpCntrlPucch ARGS((
1895 Void rgSCHPwrGrpCntrlPusch ARGS((
1899 Void rgSCHPwrPucchDeltaInd ARGS((
1903 Void rgSCHPwrUpdExtPhr ARGS((
1906 RgInfExtPhrCEInfo *extPhr,
1907 RgSchCmnAllocRecord *allocInfo));
1908 Void rgSCHPwrUpdPhr ARGS((
1912 RgSchCmnAllocRecord *allocInfo,
1914 Void rgSCHPwrUlCqiInd ARGS((
1918 Void rgSCHPwrRecordRbAlloc ARGS((
1923 S16 rgSCHPwrCellCfg ARGS((
1926 S16 rgSCHPwrCellRecfg ARGS((
1928 RgrCellRecfg *recfg));
1929 Void rgSCHPwrCellDel ARGS((
1930 RgSchCellCb *cell));
1933 S16 rgSCHPwrUeSCellCfg ARGS((
1936 RgrUeSecCellCfg *sCellInfoCfg));
1939 S16 rgSCHPwrUeCfg ARGS((
1943 S16 rgSCHPwrUeRecfg ARGS((
1946 RgrUeRecfg *recfg));
1947 Void rgSCHPwrUeDel ARGS((
1950 Void rgSCHPwrUeReset ARGS((
1955 S16 rgSCHCmnSpsUlProcCrcInd ARGS((
1958 CmLteTimingInfo crcTime
1960 Void rgSCHCmnSpsInit ARGS((Void));
1962 Void rgSCHCmnSpsRelDlSpsActHqP ARGS((
1964 RgSchDlHqProcCb *hqP));
1966 S16 rgSCHCmnSpsCellCfg ARGS((
1968 RgrCellCfg *cellCfg,
1969 RgSchErrInfo *err));
1970 Void rgSCHCmnSpsCellDel ARGS((
1973 S16 rgSCHCmnSpsUeCfg ARGS((
1979 S16 rgSCHCmnSpsUeRecfg ARGS((
1982 RgrUeRecfg *ueRecfg,
1985 Void rgSCHCmnSpsUeDel ARGS((
1989 S16 rgSCHCmnSpsDlLcRecfg ARGS((
1993 RgrLchRecfg *lcRecfg,
1996 S16 rgSCHCmnSpsDlLcCfg ARGS((
2003 Void rgSCHCmnSpsDlLcDel ARGS((
2008 Void rgSCHCmnSpsDlCqiIndHndlr ARGS((
2011 CmLteTimingInfo timingInfo
2013 Void rgSCHCmnSpsDlDedBoUpd ARGS((
2018 Void rgSCHCmnSpsDlUeReset ARGS((
2022 Void rgSCHCmnSpsDlProcAddToRetx ARGS((
2024 RgSchDlHqProcCb *hqP
2026 Void rgSCHCmnSpsDlProcAck ARGS((
2028 RgSchDlHqProcCb *hqP
2031 Void rgSCHCmnSpsDlRelPdcchFbk ARGS((
2036 Void rgSCHCmnSpsDlSched ARGS((
2038 RgSchCmnDlRbAllocInfo *allocInfo
2041 S16 rgSCHCmnSpsGetDlActvUe ARGS((
2043 CmLteTimingInfo *timingInfo,
2044 CmLListCp *dlSpsActvUeLst
2047 Void rgSCHCmnSpsDlAllocFnlz ARGS((
2049 RgSchCmnDlRbAllocInfo *allocInfo
2052 Void rgSCHCmnSpsDlUpdDlSfAllocWithSps ARGS((
2054 CmLteTimingInfo schdTime,
2059 /* APIs exposed by UL SPS */
2060 Void rgSCHCmnSpsUlLcgDel ARGS((
2065 Void rgSCHCmnSpsUlUeReset ARGS((
2069 Void rgSCHCmnSpsUlProcRelInd ARGS((
2075 Void rgSCHCmnSpsUlProcActInd ARGS((
2080 Void rgSCHCmnSpsPhrInd ARGS((
2086 S16 rgSCHCmnSpsBsrRpt ARGS((
2093 S16 rgSCHCmnSpsUlCqiInd ARGS((
2097 S16 rgSCHCmnSpsUlProcDtxInd ARGS((
2100 CmLteTimingInfo dtxTime
2102 S16 rgSCHCmnSpsUlTti ARGS((
2104 RgSchCmnUlRbAllocInfo *allocInfo
2107 S16 rgSCHCmnSpsUlGetActvUeLst ARGS((
2109 CmLteTimingInfo timingInfo,
2110 CmLListCp *ulSpsActvUeLst
2113 Void rgSCHCmnUlSpsRelInd ARGS((
2120 Void rgSCHCmnUlSpsActInd ARGS((
2126 Void rgSCHCmnUlCrcFailInd ARGS((
2129 CmLteTimingInfo crcTime
2131 Void rgSCHCmnUlCrcInd ARGS((
2134 CmLteTimingInfo crcTime
2137 /* Added handling to retrnasmit RelPDCCH in case no
2138 feedback is received */
2139 Void rgSCHCmnSpsDlReTxRelPdcch ARGS((
2144 Void rgSCHCmnChkRetxAllowDtx
2148 RgSchDlHqProcCb *proc,
2152 S16 PtUiRgmBndCfm ARGS((Pst* pst, SuId suId, uint8_t status));
2154 S16 rgSCHCmnDlInitHqEnt
2160 Void rgSchCmnDlSfHqDel
2166 Void rgSCHCmnDlDeInitHqEnt
2171 uint8_t rgSCHCmnUlGetCqi
2175 CmLteUeCategory ueCtgy
2178 S16 rgSCHDhmUpdBlerBasediTbsEff ARGS((
2185 Void rgSchCmnUpdCfiDb ARGS((
2189 S16 RgUiRgmChangeTransModeInd ARGS((
2192 RgmTransModeInd *transModeInd));
2194 Void rgSchCheckAndTriggerModeChange ARGS((
2197 uint8_t reportediTbs,
2201 Void rgSCHRrDlProcRmvFrmRetx ARGS((
2203 RgSchDlHqProcCb *hqP
2205 uint8_t rgSchUtlGetServCellIdx ARGS((
2210 S16 rgSchUtlVldtCellId ARGS ((
2214 Void rgSCHCmnInitUlRbAllocInfo ARGS((
2215 RgSchCmnUlRbAllocInfo *allocInfo
2217 TfuDciFormat rgSCHCmnSlctPdcchFrmt ARGS((
2223 Void rgSCHCmnNonDlfsDedRbAlloc ARGS((
2225 RgSchCmnUeRbAlloc *allocInfo,
2227 CmLListCp *schdUeLst,
2228 CmLListCp *nonSchdUeLst
2231 Bool rgSCHCmnRetxAvoidTdd ARGS
2235 RgSchDlHqProcCb *proc
2242 #endif /* __cplusplus */
2243 #endif /* __RGSCHCMNX__ */
2246 /**********************************************************************
2248 **********************************************************************/