1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /**********************************************************************
25 Desc: Defines required by LTE MAC
29 **********************************************************************/
31 @brief This file contains basic data structures for the scheuler.
35 #include "pj_tenb_stats.x"
42 #include "l2_tenb_stats.x"
46 #include "rg_sch_emtc.x"
50 typedef struct rgSchHistNode
55 Void * dbgVal; /* This is specific to the data struct being debug
56 for example if the debugging is done fo list
57 then this should contain the node address */
61 #define MAX_HIST_NODES 50
63 #define RGSCH_ACTION_ADD 11
64 #define RGSCH_ACTION_DEL 12
66 typedef struct rgSchHistInfo
69 RgSchHistNode hist[MAX_HIST_NODES];
72 #define RG_SCH_RECORD(_histInfo,_action,_dbgVal)\
74 (_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].file = __FILE__;\
75 (_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].func = __FUNCTION__;\
76 (_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].line = __LINE__;\
77 (_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].action = _action;\
78 (_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].dbgVal = _dbgVal;\
79 (_histInfo)->histCount++;\
86 #endif /* __cplusplus */
88 typedef TfuDciFormat1aInfo RgDciFmt1AInfo;
89 typedef TfuRaReqInfo RgTfuRaReqInfo;
90 typedef TfuSubbandCqiInfo RgSchSubbandCqiInfo;
91 typedef TfuHqIndInfo RgTfuHqIndInfo;
92 typedef TfuHqInfo RgTfuHqInfo;
93 typedef TfuCntrlReqInfo RgTfuCntrlReqInfo;
95 /* Forward declarations for some structures */
97 typedef struct rgSchL2MeasCb RgSchL2MeasCb;
98 #endif /* LTE_L2_MEAS */
99 typedef struct rgSchQciCb RgSchQciCb;
100 typedef struct rgSchUeCb RgSchUeCb;
101 typedef struct rgSchCellCb RgSchCellCb;
102 typedef struct rgSchErrInfo RgSchErrInfo;
103 typedef struct rgSchUlAlloc RgSchUlAlloc;
104 typedef struct rgSchUlRetxAlloc RgSchUlRetxAlloc;
105 typedef struct rgSchUlHqProcCb RgSchUlHqProcCb;
106 typedef struct rgSchDlHqProcCb RgSchDlHqProcCb;
107 /* Changes for MIMO feature addition */
108 /* Removed dependency on MIMO compile-time flag */
109 typedef struct rgSchDlHqTbCb RgSchDlHqTbCb;
110 typedef struct rgSchLcgCb RgSchLcgCb;
111 typedef struct rgSchDlHqEnt RgSchDlHqEnt;
112 typedef struct rgSchRaCb RgSchRaCb;
113 typedef struct _rgSchCb RgSchCb;
114 typedef struct rgSchUlLcCb RgSchUlLcCb;
115 typedef struct rgSchDlLcCb RgSchDlLcCb;
116 typedef struct _rgSchdApis RgSchdApis;
118 typedef struct rgSchTddPhichOffInfo RgSchTddPhichOffInfo;
119 typedef uint8_t RgSchTddNpValTbl[RGSCH_TDD_MAX_P_PLUS_ONE_VAL];
121 /* Added support for SPS*/
123 typedef struct rgSchDlSfAllocInfo RgSchDlSfAllocInfo;
126 typedef struct rgSchUeCellInfo RgSchUeCellInfo;
133 S16 (*rgSCHRgrUeCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgrUeCfg *cfg,
135 S16 (*rgSCHRgrUeRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgrUeRecfg *recfg,
137 Void (*rgSCHFreeUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
138 S16 (*rgSCHRgrCellCfg) ARGS((RgSchCellCb *cell, RgrCellCfg *cfg,
140 S16 (*rgSCHRgrCellRecfg) ARGS((RgSchCellCb *cell, RgrCellRecfg *recfg,
142 Void (*rgSCHFreeCell) ARGS((RgSchCellCb *cell));
143 S16 (*rgSCHRgrLchCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
144 RgSchDlLcCb *dl, RgrLchCfg *cfg, RgSchErrInfo *errInfo));
145 S16 (*rgSCHRgrLcgCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
146 RgSchLcgCb *lcg, RgrLcgCfg *cfg, RgSchErrInfo *errInfo));
147 S16 (*rgSCHRgrLchRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
148 RgSchDlLcCb *dl, RgrLchRecfg *recfg,
149 RgSchErrInfo *errInfo));
150 S16 (*rgSCHRgrLcgRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
151 RgSchLcgCb *lcg, RgrLcgRecfg *recfg, RgSchErrInfo *errInfo));
152 Void (*rgSCHFreeDlLc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchDlLcCb *dlLc));
153 Void (*rgSCHFreeLcg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchLcgCb *lcg));
154 S16 (*rgSCHRgrLchDel) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,CmLteLcId lcId, \
156 Void (*rgSCHActvtUlUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
157 Void (*rgSCHActvtDlUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
158 Void (*rgSCHHdlUlTransInd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
159 CmLteTimingInfo timingInfo));
160 Void (*rgSCHUeReset) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
161 S16 (*rgSCHUpdBsrShort) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchLcgCb *ulLcg, uint8_t bsr, RgSchErrInfo *err));
162 S16 (*rgSCHUpdBsrTrunc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchLcgCb *ulLcg, uint8_t bsr, RgSchErrInfo *err));
163 S16 (*rgSCHUpdBsrLong) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, uint8_t bsArr[], RgSchErrInfo *err));
164 S16 (*rgSCHUpdPhr) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, uint8_t phr, RgSchErrInfo *err));
165 S16 (*rgSCHUpdExtPhr) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgInfExtPhrCEInfo * extPhr, RgSchErrInfo *err));
167 S16 (*rgSCHUpdUlHqProc) ARGS((RgSchCellCb *cell, RgSchUlHqProcCb *curProc,
168 RgSchUlHqProcCb *oldProc));
170 S16 (*rgSCHContResUlGrant) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchErrInfo *err));
171 S16 (*rgSCHSrRcvd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, CmLteTimingInfo, RgSchErrInfo *err));
172 S16 (*rgSCHTti) ARGS((RgSchCellCb *cell, RgSchErrInfo *err));
173 Void (*rgSCHUlCqiInd) ARGS(( RgSchCellCb *cell, RgSchUeCb *ue, TfuUlCqiRpt *ulCqiInfo));
174 Void (*rgSCHPucchDeltaPwrInd) ARGS(( RgSchCellCb *cell,
175 RgSchUeCb *ue, S8 delta));
176 S16 (*rgSCHlUeReset) ARGS(( RgSchCellCb *cell, RgSchUeCb *ue));
177 Void (*rgSCHDlDedBoUpd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchDlLcCb *svc));
178 /* ccpu00105914: PHR handling for MSG3 */
179 Void (*rgSCHUlRecMsg3Alloc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
181 Void (*rgSCHUlHqProcForUe) ARGS((RgSchCellCb *cell, CmLteTimingInfo frm,
182 RgSchUeCb *ue, RgSchUlHqProcCb **procRef));
183 RgSchUlAlloc *(*rgSCHFirstRcptnReq) ARGS((RgSchCellCb *cell));
184 RgSchUlAlloc *(*rgSCHNextRcptnReq) ARGS((RgSchCellCb *cell,
185 RgSchUlAlloc *alloc));
186 RgSchUlAlloc *(*rgSCHFirstHqFdbkAlloc) ARGS((RgSchCellCb *cell, uint8_t idx));
187 RgSchUlAlloc *(*rgSCHNextHqFdbkAlloc) ARGS((RgSchCellCb *cell,
188 RgSchUlAlloc *alloc,uint8_t idx));
189 Void (*rgSCHDlProcAddToRetx) ARGS((RgSchCellCb *cell,RgSchDlHqProcCb *hqP));
190 Void (*rgSCHDlCqiInd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
191 Bool isPucchInfo, Void *dlCqi, CmLteTimingInfo timingInfo));
192 /* Added changes of TFU_UPGRADE */
194 Void (*rgSCHSrsInd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
195 TfuSrsRpt* srsInd, CmLteTimingInfo timingInfo));
198 Void (*rgSCHDlTARpt) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
199 /* Changes for MIMO feature addition */
200 /* Removed dependency on MIMO compile-time flag */
201 Void (*rgSCHDlRlsSubFrm) ARGS((RgSchCellCb *cell, CmLteTimingInfo subFrm));
202 /* Added support for SPS*/
204 Void (*rgSCHHdlCrntiCE) ARGS((RgSchCellCb *cell, RgSchUeCb * ue));
205 Void (*rgSCHDlProcAck) ARGS((RgSchCellCb *cell, RgSchDlHqProcCb *hqP));
206 Void (*rgSCHDlProcDtx) ARGS((RgSchCellCb *cell, RgSchDlHqProcCb *hqP));
207 Void (*rgSCHDlRelPdcchFbk) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
209 Void (*rgSCHUlSpsRelInd) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
212 Void (*rgSCHUlSpsActInd) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
215 Void (*rgSCHUlCrcFailInd) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
216 CmLteTimingInfo crcTime));
217 Void (*rgSCHUlCrcInd) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
218 CmLteTimingInfo crcTime));
219 #endif /* LTEMAC_SPS */
220 Void (*rgSCHDrxStrtInActvTmrInUl) ARGS((RgSchCellCb *cell));
221 Void (*rgSCHUpdUeDataIndLcg) ARGS((RgSchCellCb *cell, RgSchUeCb * ue, RgInfUeDatInd *datInd));
223 S16 (*rgSCHRgrSCellUeCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue ,RgrUeSecCellCfg *sCellInfoCfg,
225 S16 (*rgSCHRgrSCellUeDel) ARGS((RgSchUeCellInfo *sCellInfo, RgSchUeCb *ue));
228 Void (*rgSCHUlProcAddToRetx) ARGS((RgSchCellCb *cell,RgSchUlHqProcCb *hqP));
232 /* Added changes of TFU_UPGRADE */
236 * @brief Periodic CQI/PMI/RI configuration parameters information
238 typedef RgrUePrdDlCqiCfg RgSchUeDlPCqiCfg;
241 * @brief Periodic CQI Setup configuration parameters information
243 /* Reference: 36.313: CQI-ReportPeriodic */
244 typedef RgrUeDlPCqiSetup RgSchUeDlPCqiSetup;
247 * @brief SRS configuration parameters information
249 /* Reference 36.313 SoundingRS-UL-Config */
251 typedef RgrUeUlSrsCfg RgSchUeUlSrsCfg;
255 * @brief SRS configuration setup parameters information
257 /* Reference 36.313 SoundingRS-UL-Config */
259 typedef RgrUeUlSrsSetupCfg RgSchUeSrsUlSetupCfg;
262 * @brief SR configuration parameters information
265 typedef RgrUeSrCfg RgSchUeSrCfg;
268 * @brief SR Setup configuration parameters information
271 typedef RgrUeSrSetupCfg RgSchUeSrSetupCfg;
273 #define IOT_INVALID_FREQSTART 0xffffffff
274 #define IOT_INFINITE_SIZE 0xffffffff
275 #define RGSCH_IOT_PDCCH_POOLSZ 100
276 #define RGSCH_IOT_PDSCH_POOLSZ 100
277 #define RGSCH_IOT_PUSCH_POOLSZ 100
278 #define RGSCH_IOT_PUCCH_POOLSZ 100
279 #define RGSCH_IOT_SCHED_POOLSZ 100
280 /* TODO: Minimum Delta between CRNT Time and TX time */
281 #define RGSCH_IOT_PDCCH_DELTA RG_SCH_CMN_DL_DELTA
282 #define RGSCH_IOT_PDSCH_DELTA RG_SCH_CMN_DL_DELTA - 1 /* UL_CNTRL_DELTA value is 2*/
283 #define RGSCH_IOT_PUCCH_DELTA 6
284 #define RGSCH_IOT_PUSCH_DELTA 6
285 #define RGSCH_IOT_PDCCH_MAXFREQSZ 24 /* MAX num of eCCEs per SF */
286 #define RGSCH_IOT_PDSCH_MAXFREQSZ 100 /* MAX num of PDSCH RB per SF */
287 #define RGSCH_IOT_PUCCH_MAXFREQSZ 2048 /* MAx num of PUCCH resource per SF */
288 #define RGSCH_IOT_PUSCH_MAXFREQSZ 100 /* MAx num of PUSCh RB per SF */
289 #define RGSCH_IOT_SCHED_MAXFREQSZ 1 /*Resource only in Time domain */
290 #define RGSCH_IOT_PUCCH_INVALID_FREQ 2049
293 * IoT PDCCH/PDSCH/PUSCH/PUCCH resource definition.
294 * For Iot Devices resource can span multiple subframes
295 * Hence resource is defined as a set of freq resources
296 * over a set of consecutive valid subframes
298 typedef struct rgSchIotRes
302 CmLteTimingInfo timeStart;
303 CmLteTimingInfo timeEnd;
308 CmLList lnk; /*!< Link to other Fragments or Allocs in resMngmt */
309 CmLList cbLnk; /*!< Link to other allocs in a given control block (ueCb) */
310 CmLList resLnk;/*!<Link to resList in UE*/
315 * IoT PDCCH/PDSCH/PUSCH resource control block.
316 * Has pre-initialized pool of resources of #poolSize.
317 * allocList will hold the allocations for PDCCH/PUSCH/PDSCH
318 * fragList will hold the context of fragments in resource
320 typedef struct rgSchIotResCb
323 RgSchIotRes *resources;
325 uint8_t maxFreqSz; /*!< Max Number of RBs/SCs/CCEs per Subframe */
326 uint32_t deltaTime; /*!< PDCCH/PUSCH/PDSCH Delta w.r.t current time */
327 RgSchIotRes *contRes; /*!< Represents continuous availability of resource
328 in frequency and time domain */
329 CmLListCp fragList; /*!< Represents list of fragmented resourcesi b4
330 contRes, ordered in time domain */
331 CmLListCp allocList; /*!< Represents list of resources allocated which
332 are ordered in time domain */
338 * IoT Resource Management Control Block
339 * for PDCCH, PDSCH and PUSCH resources
341 typedef struct rgSchIotResMngmtCb
343 RgSchIotResCb pdcchResCb;
344 RgSchIotResCb pdschResCb;
345 RgSchIotResCb puschResCb;
346 RgSchIotResCb pucchHqFdbkCb;
347 } RgSchIotResMngmtCb;
349 S16 rgSCHUtlIotResPrcTti ARGS((
353 Void rgSCHUtlIotInsAlloc2Lst ARGS((
354 CmLListCp *allocList,
359 S16 rgSCHUtlIotResMngmtInit ARGS((
361 uint32_t pdcchPoolSz,
363 uint32_t pdcchMaxFreqSz,
364 uint32_t pdschPoolSz,
366 uint32_t pdschMaxFreqSz,
367 uint32_t puschPoolSz,
369 uint32_t puschMaxFreqSz
372 Void rgSCHUtlIotResMngmtDeinit ARGS((
376 RgSchIotRes *rgSCHUtlIotAllocRes ARGS((
377 RgSchIotResCb *resCb,
380 CmLteTimingInfo tStart,
385 RgSchIotRes *rgSCHUtlIotFirstAllocForTx ARGS((
386 RgSchIotResCb *resCb,
387 CmLteTimingInfo txTime
390 RgSchIotRes *rgSCHUtlIotNextAllocForTx ARGS((
391 RgSchIotResCb *resCb,
392 RgSchIotRes *prevAlloc,
393 CmLteTimingInfo txTime
396 Void rgSCHUtlIotAllocRls ARGS((
397 RgSchIotResCb *resCb,
401 RgSchIotRes *rgSCHUtlEmtcAllocRes ARGS((
402 RgSchIotResCb *resCb,
405 CmLteTimingInfo tStart,
411 S16 rgSCHUtlEmtcResPrcTti ARGS((
415 S16 rgSCHUtlEmtcResMngmtInit ARGS((
417 uint32_t pdschPoolSz,
419 uint32_t pdschMaxFreqSz,
420 uint32_t puschPoolSz,
422 uint32_t puschMaxFreqSz,
423 uint32_t pucchPoolSz,
425 uint32_t pucchMaxFreqSz
428 Void rgSCHUtlEmtcResMngmtDeinit ARGS((
433 RgSchUlHqProcCb* rgSCHUhmGetUlProcByTime ARGS((
438 S16 rgSCHUhmGetAvlHqProc ARGS((
441 RgSchUlHqProcCb **hqP
445 * @brief Store Periodic CQI, SRS and SR tranmission instances list
448 typedef struct rgSchPerPucchCb
457 @brief UE Specific SRS Periodicity and Subframe Offset Configuration FDD */
459 typedef struct rgSchUePCqiSrsSrCfgIdxTbl
461 uint16_t min; /*!< start ISRB Index */
462 uint16_t max; /*!< end ISRB Index */
463 uint16_t peri; /*!< SRS Periodicity in ms */
464 uint16_t offset; /*!< Offset with ISRB value */
465 }RgSchUePCqiSrsSrCfgIdxTbl;
468 @brief UE Specific SRS Periodicity and Subframe Offset Configuration TDD */
470 /* Ref: Table 8.2-2: UE Specific SRS Periodicity */
472 typedef struct rgSchUeSrsCfgIdxTbl
474 uint16_t min; /*!< start ISRB Index */
475 uint16_t max; /*!< end ISRB Index */
476 uint16_t peri; /*!< SRS Periodicity in ms */
477 uint16_t offset1; /*!< Offset with ISRB value */
478 uint16_t offset2; /*!< Offset with ISRB value */
480 }RgSchUeSrsCfgIdxTbl;
484 typedef enum rgSchSfType
486 RG_SCH_SF_DLCNTRL_DLDATA = 0,
487 RG_SCH_SF_DLCNTRL_DLDATA_ULCNTRL,
488 RG_SCH_SF_DLCNTRL_ULDATA,
489 RG_SCH_SF_DLCNTRL_ULDATA_ULCNTRL
493 @brief Per UE Group Info
495 typedef struct rgSchUeGrp
497 uint8_t beamBitMask; /*!< Beam bit mask */
498 //uint8_t numUe; /*!< Ue present in Group */
502 @brief 5gtf Cell Info
504 typedef struct rgSch5gtfCellCb
506 RgSchUeGrp ueGrp5gConf[MAX_5GTF_GROUP]; /*!< Contains all the group configured */
507 RgSchSfType dynConfig[MAX_5GTF_SUBFRAME_INFO]; /*!< Get config from config file as of now */
509 uint8_t uePerGrpPerTti; /*!< Num of UEs to be scheduled in a group per TTI */
510 uint8_t ueGrpPerTti; /*!< Num of Groups to ne scheduled per Tti */
520 @brief UE Specific SRS Control Block */
522 typedef struct rgSchUeSrsCb
524 RgSchUeUlSrsCfg srsCfg; /*!< SRS Specific configuration */
525 uint16_t peri; /*!< Periodicity */
526 uint16_t offset; /*!< subframe Offset */
528 /*!< Next Tranmission instance
529 Referenence: 36.213 Section:8.2
530 ((10*sfn +sf-sfOffset))/mod(peri)) */
531 CmLList srsLstEnt; /*!< SRS List for next tranmission instance subframe */
532 uint8_t selectedAnt; /*!< Selected Antenna for SRS Reception*/
533 uint16_t srsDist; /*!< crnt Distance to get RI Transmission */
534 Bool srsRecpPrcsd; /*!< SRS Recpeption processed as part of PUCCH
535 // or PUSCH processing in current TTI or not */
540 @brief Periodic CQI/PMI Reporting configuration using PUCCH */
545 @brief Subband Size (k) and Bandwidth Parts (J) vs. DL sys BW */
547 typedef struct rgSchUeBwSubSzBwParts
549 uint8_t rbStart; /* RB Start */
550 uint8_t rbEnd; /* RB End */
551 uint8_t subSize; /* k */
552 uint8_t bwParts; /* J */
554 }RgSchUeBwSubSzBwParts;
559 * Enum for specifying priority level of various PUCCH report types
560 * RG_SCH_CQI_PRIO_LVL_0 :PUCCH Report type 1,1a
561 * RG_SCH_CQI_PRIO_LVL_1 :PUCCH Report type 2,2b,2c,4
562 * RG_SCH_CQI_PRIO_LVL_2 :PUCCH Report type 2a,3,5,6
566 RG_SCH_CQI_PRIO_LVL_0,
567 RG_SCH_CQI_PRIO_LVL_1,
568 RG_SCH_CQI_PRIO_LVL_2,
569 RG_SCH_CQI_PRIO_LVL_INVALID
575 @brief Periodic CQI/PMI/RI Control Block */
577 typedef struct rgSchUePCqiCb
579 RgrUePrdDlCqiCfg cqiCfg; /*!< Cqi Pmi Configuration */
580 uint16_t cqiPeri; /*!< Periodicity */
581 uint16_t cqiOffset; /*!< CQI offset */
582 uint16_t riOffset; /*!< RI Offset */
583 uint16_t riPeri; /*!< RI periodicity */
585 /*!< Next Active Tranmission instace index ,
587 Transmission Instance
588 Referenence: 36.213 Section:8.2 */
590 /* 1. where wideband CQI/PMI reporting is configured
592 10*sfn+floor(subframe/2)-Noffsetcqi )Mod(Nperiod)=0
593 2. where both wideband CQI/PMI and subband CQI reporting are configured
595 10*sfn+floor(subframe/2)-Noffsetcqi )Mod(Nperiod)=0
596 only the few occasations will be used for WB and
597 few will be used for subbands.
600 uint16_t nRiTrIdx; /*!< Next Active Transmission instance for RI
601 Transmission Instance Referenence:
602 36.213 Section:8.2 */
603 uint16_t riDist; /*!< crnt Distance to get RI Transmission */
604 uint16_t h; /*!< Precompute and store H */
605 uint8_t riNumBits; /*Precomputed value as it doesn't change
607 /* 1. In the case where wideband RI reporting is configured
609 (10*sfn+floor(subframe)-Noffsetcqi-NoffsetRI )Mod(NCqiperiod *
612 2. Where Widesband and Subband RI reporting is configured
614 (10*sfn+floor(subframe)-Noffsetcqi-NoffsetRI )
615 Mod(H. NCqiperiod *MriPeriod )=0
616 where H= J * K +1; J=Number of bandwidth parts(BW/subsize). K is RGR
618 Bool isWb; /*! < Is True when a WideBand CQI is to be
619 Transmitted in a SubBand CQI Config*/
620 uint8_t bpIdx; /*Index of the Bandwidth Part*/
621 uint8_t label; /*Label L associated */
622 uint8_t J; /*Number of Bandwidth Parts*/
624 CmLList cqiLstEnt;/*!< List CQI UEs for next transmission
626 CmLList riLstEnt; /*!< List RI UEs for next transmission
628 Bool invalidateCqi; /*!< If TRUE, ignore the WB/SB CQI report*/
629 uint8_t perRiVal; /*!< Latest Periodic RI value reported */
630 Bool riRecpPrcsd; /*!< RI Recpeption processed as part of
631 PUCCH or PUSCH processing in current
634 RgSchCqiPrioLvl prioLvl; /* Priority lvl set based on the PUCCH Report
636 Bool isCqiIgnoByCollsn; /*!< Is this CQI type being ignored for
637 this reporting instance due to
638 collision with higher priority
640 Bool isRiIgnoByCollsn; /*!< Is this CQI type being ignored for
641 this reporting instance due to
642 collision with higher priority CQI
645 RgSchUeCellInfo *servCellInfo; /*!< Access to the serving cell of this
647 RgSchHistInfo histElem;
649 uint8_t rgSchPucchRepNumCount; /*!< CQI repetition count for CATM1 */
656 @brief SR Configuration Index */
658 typedef struct rgSchUeSrCfgIdx
660 uint16_t sIsr; /*!< Start ISR Index */
661 uint16_t eIsr; /*!< End ISR Index */
662 uint16_t peri; /*!< SR Periodicity */
663 uint16_t offset; /*!< offset */
666 /* Reference : 36.213 Table 10.1-5 */
667 /* Note: SR is same table for TDD and FDD */
668 RgSchUeSrCfgIdx schUeSrCfgIdx[RG_SCH_ISR_INDX_MAX]=
675 /* RESERVED: Configuration should not allow Res values */
679 @brief SR Control block */
681 typedef struct rgSchUeSrCb
683 RgSchUeSrCfg srCfg; /*!< SR configuration */
684 uint16_t offset; /*!< SR offset */
685 uint16_t peri; /*!< SR periodicity */
687 uint16_t nSrTrIdx; /*!< Next Active Tranmission Instance Index ,
688 Referenence: 36.213 Section:10.1 */
691 ((10*sfn+floor(sf)-srOffset)Mod(srPeriodcity))
695 uint8_t rgSchPucchRepNumCount; /*!< SR repetition count for CATM1 */
697 CmLList srLstEnt; /*!< Next Transmission instance SR UE list */
702 * @enum rgSchCqiReqField
703 * Enumeration of CSI Request Field (Table 7.2.1-1A 36.213).
704 * "00" No aperiodic CSI report is triggered
705 * "01" Aperiodic CSI report is triggered for serving cell c
706 * "10" Aperiodic CSI report is triggered for a 1st set of
707 * serving cells configured by higher layers
708 * "11" Aperiodic CSI report is triggered for a 2nd set of
709 * serving cells configured by higher layers
712 typedef enum rgSchCqiReqField
715 RG_SCH_APCQI_SERVING_CC,
716 RG_SCH_APCQI_1ST_SERVING_CCS_SET,
717 RG_SCH_APCQI_2ND_SERVING_CCS_SET
721 @brief APeriodic CQI Control Block */
722 typedef struct rgSchUeACqiCb
724 RgrUeAprdDlCqiCfg aCqiCfg;/*!< Cqi Pmi Configuration */
725 uint8_t L; /*Unique Label through which positioning of Subbands
726 will be conveyed by the UE */
727 uint8_t N; /*Total Bandwidth / Num of Subbands*/
728 uint8_t M; /*Number of Selected Subbands*/
730 uint8_t k; /*k - SB size. 36.213 Tables:7.2.1-3, 7.2.1-5*/
731 uint8_t cqiPmiSzR1; /*CQIPMI Size for Rank =1*/
732 uint8_t cqiPmiSzRn1; /*CQIPMI Size for Rank > 1*/
733 uint32_t aCqiTrigWt; /* Metric to track Aperiodic CQI Trigger occassion */
734 RgSchCqiReqField cqiReqField; /* Cqi Request field. This Value can be 00 01 10 11, based upon
735 the cell present in which trigger list form App */
740 RG_SCH_FDD_PCQI_TBL = 0,
748 /*ccpu00116923 - ADD - SRS present support*/
750 typedef uint8_t RgSchTddCellSpSrsSubfrmTbl[RGSCH_CELLSP_SRS_SF_CONFIGS][RGSCH_NUM_SUB_FRAMES];
752 typedef uint8_t RgSchFddCellSpSrsSubfrmTbl[RGSCH_CELLSP_SRS_SF_CONFIGS][RGSCH_NUM_SUB_FRAMES];
763 * Enum to define the type of Downlink subframe.
767 RG_SCH_SPL_SF_NO_DATA = 0,
774 * TDD UE specific PUCCH recpetion information.
776 typedef struct rgSchUePucchRecpInfo
778 CmHashListEnt hashLstEnt; /*!< List of PUCCH for receiving
779 ACK/NACK feedback information */
780 TfuUeRecpReqInfo *pucchRecpInfo; /*!< UE PUCCH Reception information */
781 } RgSchUePucchRecpInfo;
785 * TDD switch point information.
787 typedef struct rgSchTddSubfrmInfo
789 uint8_t switchPoints; /*!< Number of DL-UL switch points */
790 uint8_t numFrmHf1; /*!< Number of subframes for half frame 1
791 Present for both 5ms and 10ms periodicity */
792 uint8_t numFrmHf2; /*!< Number of subframes for half frame 2
793 Present only for 5ms periodicity */
794 } RgSchTddSubfrmInfo;
798 * TDD DL Association Set information.
800 typedef struct rgSchTddDlAscSetIdxK
802 uint8_t numFdbkSubfrms; /*!< Number of Feedbacks for DL Subframes */
803 uint8_t subfrmNum[RGSCH_NUM_SUB_FRAMES-1]; /*!< List of Subframe Number */
804 } RgSchTddDlAscSetIdxK;
806 /** @brief PRACH Information for a frequency resource. */
807 typedef struct rgrSchTddPrachInfo
809 uint8_t freqIdx; /*!< Frequency Index */
810 uint8_t sfn; /*!< Even/Odd/All Radio Frames */
811 uint8_t halfFrm; /*!< First/Second Half Frame */
812 uint8_t ulStartSfIdx; /*!< Uplink Start Subframe Index*/
815 /** @brief PRACH resource Information for each of the
816 * frequency resources. */
817 typedef struct rgrSchTddPrachRscInfo
819 uint8_t numRsc; /*!< Number of frequency resources*/
820 RgSchTddPrachInfo prachInfo[RGSCH_TDD_MAX_FREQ_RSRC]; /*!< PRACH Information */
821 } RgSchTddPrachRscInfo;
825 * TDD Special subframe configuration information.
827 struct rgSchTddSplSubfrmInfo
829 uint8_t norDlDwPts; /*!< DL Normal CP: DwPTS in Ts */
830 uint8_t norDlNorUpPts; /*!< DL Normal CP: UL Normal CP:UpPTS in Ts */
831 uint8_t norDlExtUpPts; /*!< DL Normal CP: UL Extended CP: UpPTS in Ts */
832 uint8_t extDlDwPts; /*!< DL Extended CP: DwPTS in Ts */
833 uint8_t extDlNorUpPts; /*!< DL Extended CP: UL Normal CP:UpPTS in Ts */
834 uint8_t extDlExtUpPts; /*!< DL Extended CP: UL Extended CP: UpPTS in Ts */
839 * RACH response awaiting scheduling from the current time is
840 * identified with sfn offset and subframe.
842 typedef struct rgSchTddRachRspInfo
844 uint8_t sfnOffset; /*!< SFN offset with respect to
845 expected RACH available for
847 uint8_t numSubfrms; /* Number of subframes present */
848 uint8_t subframe[RGSCH_NUM_SUB_FRAMES]; /*!< List of Subframe numbers */
849 } RgSchTddRachRspInfo;
851 typedef RgSchTddRachRspInfo RgSchTddRachDelInfo;
855 * List of awaiting RACH responses for scheduling across radio frames.
858 typedef struct rgSchTddRachRspLst
860 uint8_t numRadiofrms; /*!< Number of radio frames */
861 RgSchTddRachRspInfo rachRsp[2]; /*!< RACH Occasions for which response
863 RgSchTddRachDelInfo delInfo; /*!< Previous RACH responses for
864 which the scheduling deadline
865 has expired. So those responses
867 } RgSchTddRachRspLst;
871 * Uplink association index information indicates the SFN offset and
872 * subframe in which DL HARQ ACK/NACK is expected.
874 typedef struct rgSchTddUlAscInfo
876 uint8_t subframe; /*!< Subframe number */
877 uint8_t sfnOffset; /*!< SFN offset with respect to expected
878 UL data reception time */
883 * PUSCH information indicates the SFN offset and
884 * subframe in which UL data is scheduled.
886 typedef struct rgSchTddPuschOffInfo
888 uint8_t subframe; /*!< Subframe number */
889 uint8_t sfnOffset; /*!< SFN offset with respect to expected
890 UL data reception time */
891 } RgSchTddPuschOffInfo;
895 * PHICH information indicates the SFN offset and
896 * subframe for which PHICH should be sent.
898 struct rgSchTddPhichOffInfo
900 uint8_t numSubfrms; /*!< Number of subframes */
902 uint8_t subframe; /*!< The Uplink Subframe number corresponding
904 uint8_t sfnOffset; /*!< SFN offset with respect to expected
905 UL data reception time */
910 * DL feedback reception information indicates the SFN offset
911 * and subframe at which feedback is expected.
913 typedef struct rgSchTddDlFdbkInfo
915 uint8_t subframe; /*!< Subframe number */
916 uint8_t sfnOffset; /*!< SFN offset with respect to current
918 uint8_t m; /*!< m factor used in Downlink Association
920 #ifdef LTE_ADV /*Naw:: This is not correct */
921 CmLListCp n1PucchResLst; /*!< List for storing the used N1 resource */
923 } RgSchTddDlFdbkInfo;
928 * Special subframe configuration index.
930 typedef struct rgSchTddSplSubfrmCfg
932 uint16_t dwPts; /*!< DwPTS in OFDM Symbol Duration */
933 uint16_t upPts; /*!< UpPTS in OFDM Symbol Duration */
934 Bool isDlDataAllowed; /*!< To allow scheduling of DL data on
936 } RgSchTddSplSubfrmCfg;
940 * ACK/NACK information to be used for ACK/NACK bundling mode.
942 typedef struct rgSchTddANInfo
944 uint16_t sfn; /*!< ACK/NACK is sent for PDU in this SFN */
945 uint8_t subframe; /*!< ACK/NACK is sent for PDU in this subframe */
946 uint8_t dlDai; /*!< Downlink Assignment Index for
947 UL-DL Configuration 1-6 */
948 uint8_t ulDai; /*!< DAI for uplink */
949 uint8_t latestMIdx; /*!< Last transmitted DL subframe 'm' index */
950 uint8_t n1ResTpcIdx; /*!< N1 Res idx for scell assigned in TPC command */
951 Bool isSpsOccasion; /*!< To indicate the presence of SPS occasion */
953 uint8_t wUlDai; /*!< Max Ul dai in all the cells */
960 * Information about one MCS entry.
962 typedef struct rgSchUlIMcsInfo
966 } RgSchUlIMcsTbl[29];
967 RgSchUlIMcsTbl rgUlIMcsTbl;
969 typedef struct rgSchUeCatTbl
971 uint32_t maxUlBits;/*Maximum number of
976 uint32_t maxDlBits[4];/*Maximum number of
979 received within a TTI*/
980 /* correcting DL harq softbuffer limitation logic */
981 uint32_t maxSftChBits;/*Total number of soft channel bits*/
982 Bool ul64qamSup;/*Support for 64QAM in UL*/
983 /* Changes for MIMO feature addition */
984 /* Removed dependency on MIMO compile-time flag */
985 uint32_t maxDlTbBits;/*Maximum number of DL-SCH
987 received within a TTI*/
988 uint8_t maxTxLyrs;/*Maximum number of supported
989 layers for spatial multiplexing
991 } RgSchUeCatTbl[CM_MAX_UE_CAT_SUPP + 1];
992 RgSchUeCatTbl rgUeCatTbl;
994 /* Changes for MIMO feature addition */
995 /* Removed dependency on MIMO compile-time flag */
996 typedef uint32_t RgSchTbSzTbl[RGSCH_MAX_NUM_LYR_PERCW][RGSCH_NUM_ITBS][RGSCH_MAX_NUM_RB];
999 typedef uint8_t RgSchRaPrmblToRaFrmTbl[RGSCH_MAX_TDD_RA_PREAMBLE_FMT+1];
1001 /* Added matrix 'rgRaPrmblToRaFrmTbl' for computation of RA
1002 sub-frames from preamble format */
1003 typedef uint8_t RgSchRaPrmblToRaFrmTbl[RGSCH_MAX_RA_PREAMBLE_FMT+1];
1005 RgSchRaPrmblToRaFrmTbl rgRaPrmblToRaFrmTbl;
1007 uint8_t rgRvTable[4];
1009 typedef struct rgDciFmt
1014 RgDciFmt1AInfo dci1a;
1018 typedef enum rgSchPdcchSearchSpace
1020 RG_SCH_UE_SPECIFIC_SEARCH_SPACE,
1021 RG_SCH_CMN_SEARCH_SPACE,
1022 }RgSchPdcchSearchSpace;
1026 * Information about one PDCCH.
1028 typedef struct rgSchPdcch {
1029 uint8_t nCce; /*!< CCE index */
1030 CmLteAggrLvl aggrLvl; /*!< Aggregation level */
1031 TfuDciInfo dci; /*!< PDCCH format */
1032 uint16_t rnti; /*!< RNTI to who the PDCCH is allocated */
1033 #if (defined (LTE_TDD))
1034 uint8_t dlDai; /*!< DAI associated with this PDCCH.
1035 THis is used for F1BCS resource calulcation */
1037 /* Added support for SPS*/
1039 CmLteTimingInfo relFbkTiming; /*!< Feebback timing information for release
1041 Bool isSpsRnti; /*!< TRUE if rnti is SPS RNTI */
1042 uint16_t crnti; /*!< CRNTI to who the PDCCH is allocated */
1044 CmLList lnk; /*!< To link PDCCHs in a subframe */
1048 RgSchUeCb *ue; /*!< Pointer to the UE Control Block */
1049 RgSchPdcchSearchSpace pdcchSearchSpace; /*!< Search Space from this PDCCH allocated */
1050 uint8_t dciNumOfBits; /*!< Size of DCI in bits */
1055 * PDCCH information for cell.
1057 typedef struct rgSchPdcchInfo {
1058 uint8_t *map; /*!< Bit map of PDCCHs */
1059 uint8_t currCfi; /*!< Number of CCEs */
1060 uint16_t nCce; /*!< Total CCEs */
1061 CmLListCp pdcchs; /*!< List of RgSchPdcch */
1064 typedef struct rgSchPhich
1066 CmLList lnk; /*!< To link PHICHs in a subframe */
1067 uint8_t hqFeedBack; /*!< Harq Feed Back */
1068 uint8_t rbStart; /*!< Starting RB */
1069 uint8_t nDmrs; /*!< 3 bits for DMRS cyclic shift */
1070 /* changes for passing iphich at TFU;*/
1071 Bool isForMsg3; /*! < Phich Ack/Nack conveyed for MSG 3 */
1073 uint8_t iPhich; /*!< For determining phich group */
1077 typedef struct rgSchPhichInfo
1079 CmLListCp phichs; /*!< List of RgSchPhich */
1082 typedef struct rgSchBcchTb
1089 typedef struct rgSchPcchTb
1096 typedef struct rgSchRaRspAlloc
1100 TknUInt8 backOffInd; /*!< Backoff index value */
1101 CmLListCp raRspLst; /*!< List of RaCbs */
1102 CmLListCp contFreeUeLst; /*! List of HandOver or PdcchOrder UEs */
1103 RgSchPdcch *pdcch; /*!< NULLP if no Rsp allocation done for raRnti*/
1106 typedef struct rgSchBchTb
1108 Buffer *tb; /*!< BCH data for this frame */
1109 uint16_t tbSize; /*!< Non-Zero if bch data is scheduled for this SF */
1112 /* Added support for SPS*/
1115 * TODO: check compilation
1116 @brief Downlink Resource allocation type information. */
1117 struct rgSchDlSfAllocInfo
1119 uint32_t raType0Mask; /*!< RBG allocation mask for type 0*/
1120 uint32_t raType1Mask[RG_SCH_NUM_RATYPE1_32BIT_MASK]; /*!< RA Type 1
1122 uint32_t raType1UsedRbs[RG_SCH_NUM_RATYPE1_32BIT_MASK];/*!< RA Type 1 Used RBs
1124 uint32_t nxtRbgSubset; /*!< Next RBG subset to be used for allocation */
1125 uint32_t raType2Mask[RG_SCH_NUM_RATYPE2_32BIT_MASK];
1126 /*!< Mask for resource allocation type 2 */
1128 #endif /* LTEMAC_SPS */
1130 /* LTE_ADV_FLAG_REMOVED_START */
1132 @brief RGR RB range for SFR */
1133 typedef struct rgrPwrHiCCRange
1135 uint8_t startRb; /*<! Start RB for power high cell centre user */
1136 uint8_t endRb; /*<! End RB for power high cell centre user */
1139 typedef struct rgSchSFRTotalPoolInfo
1141 CmLListCp ccPool; /*Dynamic Variable, It will change when BW is assigned.
1142 Initially assigned to 0 */
1143 Bool ccBwFull; /*If BW is full*/
1144 CmLListCp cePool; /*Dynamic Variable, It will change when BW is assigned.
1145 Initially assigned to 0 */
1146 Bool ceBwFull; /*If BW is full*/
1148 Bool CERetx; /* to check if there is any CE retransmission */
1149 Bool CCRetx; /* to check if there is any CC retransmission */
1150 Bool CC1; /* Cell centre pool 1 */
1151 Bool CC2; /* cell centre pool 2 */
1152 uint8_t CCPool1BwAvlbl; /* Cell Centre Bw available for Pool1 */
1153 uint8_t CCPool2BwAvlbl; /* Cell Centre Bw available for Pool2 */
1154 uint8_t CEPoolBwAvlbl; /* Cell Edge Bw available for CE Pool */
1155 }RgSchSFRTotalPoolInfo;
1157 typedef struct rgSchSFRPoolInfo
1159 /*Fixed RB Range of the Pool. Fixed by user configuration*/
1160 uint16_t poolstartRB;
1162 uint16_t bw; /*!< Number of RBs in the pool */
1164 uint8_t type2Start; /*!< Start RB for the next type 2 allocation */
1165 uint8_t type2End; /*!< End position of Type2 allocation with in the bit mask */
1166 uint8_t type0End; /*!< End position of Type0 allocation with in the bit mask */
1168 uint16_t bwAlloced; /*!< Number of RBs already allocated by DLFS */
1169 Bool CCPool2Exists; /*!< To check if the last pool in the RB allocation is a CC pool */
1170 struct rgSchSFRPoolInfo * adjCCPool; /*!< The CC pool adjacent to this CE Pool SFR_FIX */
1171 RgrPwrHiCCRange pwrHiCCRange; /*!< Power High Range which can be used by CC user based on RNTP info */
1173 /* LTE_ADV_FLAG_REMOVED_END */
1175 typedef struct rgSchPuschBwInfo
1177 uint8_t numSb; /*!< PUSCH BW in subbands */
1178 uint8_t startRb; /*!< Starting RB for PUSCH BW */
1181 typedef struct rgSchDynCfiCb
1183 uint8_t isDynCfiEnb; /*!< Dynamic CFI feature Flag */
1184 uint8_t maxCfi; /*!< max possible CFI in the cell */
1185 uint8_t switchOvrWinLen; /*!< Length of Switchover window */
1186 uint16_t cceFailCnt; /*!< Number of CCE allocation Failures in a
1187 CCE failure sample period */
1188 uint16_t *cceFailSamples; /*!< Array holding samples of Avg number
1189 of CCE allocation failures */
1190 uint16_t cceFailSum; /*!< Moving sum of the CCE faliures of
1192 uint16_t cfiStepUpTtiCnt; /*!< No.of TTIs to take decision for CFI
1194 uint16_t cceUsed; /*!< Total CCEs used in current monitoring
1196 uint16_t lowCceCnt; /*!< Number of TTI in which CCEs used is
1197 less than available CCEs in
1199 uint16_t cfiStepDownTtiCnt; /*!< No.of TTIs to take decision for CFI
1201 uint32_t cfiSwitches; /*!< Total number of CFI switches */
1202 uint32_t cfiIncr; /*!< Total number of CFI increments */
1203 uint32_t cfiDecr; /*!< Total number of CFI decrements */
1204 /*!< Total CCE per CFI */
1205 uint8_t cfi2NCceTbl[RG_SCH_MAX_MPHICH][RG_SCH_CMN_MAX_CFI];
1207 uint8_t numFailSamples; /*!< Number of CCE Allocation Failure
1209 uint16_t failSamplePrd; /*!< Failure Sample Period */
1210 uint16_t ttiCnt; /*!< TTI count to track monitoring period
1211 and sample period expiry */
1212 RgSchPuschBwInfo bwInfo[RG_SCH_CMN_MAX_CFI]; /*!< PUSCH BW info */
1213 uint8_t pdcchSfIdx; /*!< Subframe Idx for CFI applying */
1214 uint8_t prevCceFailIdx; /*!< To maintain Previous Index of
1215 CCE failure array */
1216 Bool switchOvrInProgress; /*!< Switchover is in progress */
1217 Bool dynCfiRecfgPend; /*!< Flag for pending dynamic cfi reconfig */
1224 * Beam information for a subframe
1226 typedef struct rgSchSfBeamInfo
1228 uint16_t totVrbgAvail; /*!< Total VRBG available */
1229 //uint16_t totRb; /*!< Total RB per Beam */
1230 uint16_t totVrbgRequired; /*!< total Rbs requested for beam */
1231 uint16_t totVrbgAllocated; /*!< total Rbs allocated for beam */
1232 uint16_t vrbgStart; /*!< VRBG start for beam */
1236 typedef struct rgSchDlSf
1238 uint8_t cceCnt; /*!< Number of CCEs used in the subframe */
1239 Bool isCceFailure; /*!< TRUE if PDCCH allocation is failed for
1241 uint8_t dlUlBothCmplt; /*!< To track that DL and UL both scheduling
1243 uint8_t sfNum; /*!< Number of the subframe */
1244 uint16_t bw; /*!< Number of RBs in the cell */
1245 uint16_t bwAlloced; /*!< Number of RBs already allocated by DLFS */
1246 uint16_t bwAssigned; /*!< Number of RBs already allocated by scheduler */
1247 /* LTE_ADV_FLAG_REMOVED_START */
1248 RgSchSFRTotalPoolInfo sfrTotalPoolInfo; /* SFR Pool Info*/
1249 TknStrOSXL rntpInfo; /* RNTP Info for the complete subframe*/
1250 /* LTE_ADV_FLAG_REMOVED_END */
1252 uint8_t type2Start; /*!< Start RB for the next type 2 allocation */
1253 uint8_t type2End; /*!< End position of Type2 allocation with
1255 uint8_t type0End; /*!< End position of Type0 allocation with
1257 uint8_t lstRbgDfct; /*!< The last RBG deficit RBs, Ex. if DLBW = 97,
1258 * RBGsz = 4, lstRbgDfct = 3 */
1259 Bool txDone; /*!< Flag to indicate if transmission is done*/
1260 uint32_t numDlActvUes; /* 4UE_TTI_DELTA: num of active Ues */
1261 RgSchBchTb bch; /*!< BCH data for this frame */
1262 RgSchBcchTb bcch; /*!< BCCH allocation for this frame */
1263 RgSchPcchTb pcch; /*!< PCCH allocation for this frame */
1264 RgSchPdcchInfo pdcchInfo; /*!< PDCCH info */
1265 RgSchPhichInfo phichInfo; /*!< PHICH info */
1268 CmLListCp ueLst; /*!< UE List which are scheduled in Perticular SF */
1270 CmLListCp msg4HqPLst; /*!< Msg4 Hq Procs that are scheduled in Perticular SF */
1272 uint8_t remUeCnt; /*!< Remaining number of UEs that can be scheduled */
1273 Bool schdAmbrNxt;/*!< Flag indicates to pick an AMBR LC after GBR LC */
1274 /*[ccpu00138609]-ADD- Counter to track the number of Msg4/DL CCCH UEs */
1275 uint8_t schdCcchUe; /*!< Num of Msg4/DL CCCH UEs scheduled in
1278 uint8_t nCce; /*!< Number of CCEs */
1279 RgSchTddPhichOffInfo phichOffInfo; /*!< PHICH Information */
1280 RgSchTddDlFdbkInfo dlFdbkInfo; /*!< HARQ Ack/Nack feedback expected time */
1281 RgSchTddUlAscInfo ulAscInfo; /*!< UL Association set Information */
1282 RgSchRaRspAlloc raRsp[RGSCH_MAX_TDD_RA_RSP_ALLOC]; /* Array of list
1284 Allocations for each rarnti */
1285 RgSchTddSfType sfType; /*!< Stores the enum value for SF type */
1287 RgSchRaRspAlloc raRsp[RGSCH_MAX_RA_RSP_ALLOC]; /* Array of list of Ra Rsp
1288 Allocations for each rarnti */
1290 Void *dlfsSf; /*!< DLFS specific information per sub-frame */
1291 CmLListCp ackNakRepQ; /*!< ACK NACK repetition queue */
1292 /* Added support for SPS*/
1294 Bool isSPSOcc; /*!< TRUE if this SF has SPS Occasion allocation */
1295 RgSchDlSfAllocInfo dlSfAllocInfo;/*!< Allocation information for DL SF */
1296 uint32_t spsAllocdBw; /*!< Number of RBs allocated for SPS */
1297 RgSchPdcch *relPdcch; /*!< Only one release PDCCH scheduled per
1302 CmLteRnti crnti; /*!< UE's C-RNTI (not SPS RNTI) */
1303 RgrTddAckNackMode ackNackMode; /*!< Ack/nack mode */
1304 } relPdcchInfo; /*!< Info required for receiving Hq fdbk
1305 * for release PDCCH (DL) */
1308 uint32_t schedLcCount; /*!< Num of LCs scheduled in this TTI */
1309 uint32_t totalLcCntOfSlctdUes; /*!< total Lc count of all UE's selected in
1311 uint32_t totPrbReq; /*!< Sum of PRBs required by selected UEs
1313 #ifdef BEST_EFFORT_2_UE_PER_TTI
1314 uint32_t beTotPrbReq;
1321 CmLListCp n1PucchResLst; /*!< List for storing the used N3 resource */
1322 CmLListCp n3PucchResLst; /*!< List for storing the used N1 resource */
1325 RgSchSfBeamInfo sfBeamInfo[MAX_5GTF_BEAMS]; /*!< Per info Beam per sf*/
1326 uint8_t numGrpPerTti; /*!< number of Group per TTI*/
1327 uint8_t numUePerGrp; /*!< number of UE per group in TTI*/
1331 /* Data Structures used for DL Allocations by Schedulers */
1333 @brief Downlink Resource allocation type 0 information. */
1334 typedef struct rgSchDlRbAllocRaType0
1336 uint8_t numDlAlloc; /*!< Number of downlink allocations */
1337 uint32_t dlAllocBitMask; /*!< Downlink allocations done for the UE */
1338 } RgSchDlRbAllocRaType0;
1340 /* Added support for SPS*/
1343 @brief Downlink Resource allocation type 1 information. */
1344 typedef struct rgSchDlRbAllocRaType1
1346 uint8_t numDlAlloc; /*!< Number of downlink allocations */
1347 uint8_t shift; /*!< Indicates if the shift is triggered in the
1349 uint8_t rbgSubset; /*!< RBG subset number selected for the allocation*/
1350 uint32_t dlAllocBitMask; /*!< Downlink allocations done for the UE */
1351 } RgSchDlRbAllocRaType1;
1352 #endif /* LTEMAC_SPS */
1354 @brief Downlink Resource allocation type 2 information. */
1355 typedef struct rgSchDlRbAllocRaType2
1357 Bool isLocal; /*!< True if localised VRB */
1358 uint8_t rbStart; /*!< Starting RB */
1359 uint8_t numRb; /*!< Number of RBs */
1360 } RgSchDlRbAllocRaType2;
1363 typedef struct rgSchcmnDlGrnt
1365 uint16_t schdTime; /*!< Time at which Harq proc has been scheduled */
1366 uint8_t rbStrt; /*!< Starting RB of the allocation */
1367 uint8_t numRb; /*!< Number of RBs allocated */
1368 uint8_t iMcs; /*!< Index to the MCS */
1369 uint8_t rv; /*!< RV for HARQ (re)transmission */
1370 uint8_t rvIdx; /*!< RVIdx for HARQ(re)transmission */
1371 #ifdef RG_5GTF /* ToDo:: Anoop need to check for other fields required*/
1375 uint8_t xPDSCHRange;
1377 TfuDciFormat dciFormat; /*!< DCI format for the allocation */
1384 @brief Downlink allocation details per TB. */
1385 typedef struct rgSchDlTbAllocInfo
1387 Bool schdlngForTb;/*!< Indicates if this TB has been scheduled */
1388 /*ccpu00120365:-ADD-is this TB disabled. Refer to 36.213-7.1.7.2 */
1389 Bool isDisabled; /*!< Indicates if this TB is disabled */
1390 uint32_t bytesReq; /*!< Number of bytes required to be allocated
1391 for each TB: filled in by RR/MAX C/I/PFS */
1392 uint32_t bytesAlloc; /*!< Num of bytes allocated for each TB */
1393 uint8_t iTbs; /*!< Itbs for allocation for this allocation
1395 uint8_t imcs; /*!< Imcs for allocation for this allocation
1397 uint8_t noLyr; /*!< No. of SM layers for this TB transmission */
1398 RgSchDlHqTbCb *tbCb; /*!< address of TB Control Block */
1400 RgSchDlCmnGrnt cmnGrnt; /*! < Alloc info to store 5GTF RAR sched */
1402 }RgSchDlTbAllocInfo;
1405 @brief Downlink MIMO related allocation details. */
1406 typedef struct rgSchMimoAllocInfo
1408 Bool hasNewTxData;/*!< Indicator from Specific Sched to Common.
1409 * Set, if UE has new data available for clubbing
1410 * with RETX in case of TM3 and TM4 */
1411 Bool swpFlg; /*!< Swap Flag to indicate TB to CW association
1412 * incase of 2 TB transmission */
1413 uint8_t precIdxInfo; /*!< Precoding index information stored */
1414 uint8_t numTxLyrs; /*!< Number of SM layers scheduled for Transmission */
1415 }RgSchMimoAllocInfo;
1419 @brief Downlink RB allocation details. */
1420 typedef struct rgSchDlRbAlloc
1422 CmLteRnti rnti; /*!< RNTI for allocation: used only for RARs and
1423 dedicated transmissions */
1424 uint8_t rbsReq; /*!< Number of RBs required to be allocated:
1425 filled in by RR/MAX C/I/PFS */
1426 RgSchDlSf *dlSf; /*!< DL sub-frame for which allocation is to be
1427 done: filled in by RR/MAX C/I/PFS */
1428 TfuDciFormat dciFormat; /*!< DCI format for the allocation */
1429 uint8_t raType; /*!< Resource allocation Type */
1430 RgSchPdcch *pdcch; /*!< Pointer to allocated PDCCH */
1433 RgSchDlRbAllocRaType0 raType0; /*!< Resource allocation type 0 information */
1434 /* Added support for SPS*/
1436 RgSchDlRbAllocRaType1 raType1; /*!< Resource allocation type 1
1439 RgSchDlRbAllocRaType2 raType2; /*!< Resource allocation type 2 information */
1440 } allocInfo; /*!< Resource allocation information */
1441 uint8_t rbsAlloc; /*!< Number of RBs allocated */
1442 uint8_t numRapids; /*!< Number of RAPIDs serviced within RAR*/
1443 /* Nprb indication at PHY for common Ch */
1444 uint8_t nPrb; /*!< NPRB column num. either 2 or 3 */
1447 /* Add BI sub-header size to the tbSize requirement */
1449 RgSchMimoAllocInfo mimoAllocInfo; /*!< Mimo specific allocation params */
1450 RgSchDlTbAllocInfo tbInfo[2]; /*!< Allocation information for each TB. */
1452 /* Added support for SPS*/
1454 uint8_t cqiForTx; /*!< Assumed value of CQI at which transmission is
1456 RgSchDlSfAllocInfo resAllocInfo; /*!< Resource allocation information for
1457 the current allocation for
1458 RA type 0, 1 and 2 */
1459 Bool isSchdBySps; /*!< Indicates if this UE is already scheduled by SPS
1461 CmLteTimingInfo spsSchdTime; /*!< Timing info at which UE was scheduled by
1466 RgSchPdcch *mpdcch; /*!< Pointer to allocated PDCCH */
1467 RgSchEmtcDlRbAlloc emtcAllocInfo; /*!< EMTC DL RB alloc Info */
1476 * Uplink Grant Information per UE.
1478 typedef struct rgSchUlGrnt
1480 uint8_t iMcs; /*!< Original MCS index */
1481 uint8_t iMcsCrnt; /*!< Current MCS index of the grant */
1482 uint8_t hop; /*!< Hopping flag, set to 0 in this version */
1483 uint8_t rbStart; /*!< Start Resource block of allocation */
1484 uint8_t numRb; /*!< Number of resource blocks allocated */
1485 uint8_t tpc; /*!< TPC command for the uplink grant */
1486 uint8_t nDmrs; /*!< n1DMRS for the uplink grant */
1487 uint8_t delayBit; /*!< Delay bit, for msg3 grant, set to 1 */
1488 /* Added for Uplink Adaptive retransmission */
1489 Bool isRtx; /*!< To indicate if this grant is for a RETX */
1490 /* To include the length and ModOrder in DataRecp Req. */
1491 uint16_t datSz; /*!< Length of the Data */
1492 TfuModScheme modOdr; /*!< Modulation order */
1497 uint8_t xPUSCHRange;
1500 uint8_t uciOnxPUSCH;
1503 TfuDciFormat dciFrmt;
1509 /* Added for Uplink Adaptive retransmission */
1512 * Uplink retransmission allocation.
1514 struct rgSchUlRetxAlloc
1516 CmLteRnti rnti; /*!< RNTI */
1517 uint8_t numSb; /*!< Number of subbands */
1518 uint32_t tbSz; /*!< Transmission Block Size */
1519 uint8_t iMcs; /*!< Original MCS index */
1520 RgSchUeCb *ue; /*!< UE assocated with allocation */
1521 Bool forMsg3; /*!< If allocation is for Msg3 */
1522 /* PHR handling for MSG3 */
1523 RgSchRaCb *raCb; /*!< Pointer to RaCb, if forMsg3 = TRUE */
1525 RgSchEmtcUlGrnt emtcGrnt;
1528 TfuDciFormat dciFrmt;
1532 TfuModScheme modOdr; /*!< Modulation order */
1538 * Hole information, pertaining to uplink bandwidth
1540 typedef struct rgSchUlHole
1542 uint8_t start; /*!< Beginning of hole */
1543 uint8_t num; /*!< Number of elements making up the hole */
1544 struct rgSchUlHole *prv; /*!< Previous hole */
1545 struct rgSchUlHole *nxt; /*!< Next hole */
1546 struct rgSchUlAlloc *nxtAlloc; /*!< Next allocation */
1547 struct rgSchUlAlloc *prvAlloc; /*!< Previous allocation */
1556 RgSchUlHqProcCb *hqProc; /*!< HARQ process */
1557 CmLteRnti rnti; /*!< RNTI */
1558 uint8_t sbStart; /*!< Subband start idx */
1559 uint8_t numSb; /*!< Number of subbands */
1560 RgSchUlGrnt grnt; /*!< Grant info */
1561 /* Not keeping grant attributes now */
1562 RgSchPdcch *pdcch; /*!< Associated PDCCH */
1563 RgSchUeCb *ue; /*!< UE assocated with allocation */
1564 Bool forMsg3; /*!< If allocation is for Msg3 */
1565 Bool isMsg3CCCHSdu; /*!<Msg3 contains CCCH Sdu */
1566 Bool isMsg3CrntiCe; /*!< Msg3 contains CRNTI CE */
1567 /* PHR handling for MSG3 */
1568 RgSchRaCb *raCb; /*!< RaCb, if forMsg3 = TRUE */
1569 Bool mrgdNewTxAlloc; /*!< Alloc corresponding to newTx
1570 * that was merged in the process of
1571 * comdining txSf and reTxSf. */
1572 RgSchUlAlloc *prv; /*!< Previous alloc */
1573 RgSchUlAlloc *nxt; /*!< Next alloc */
1574 RgSchUlHole *prvHole; /*!< Next hole */
1575 RgSchUlHole *nxtHole; /*!< Prev hole */
1576 /* UL_ALLOC_CHANGES*/
1577 void *allocDbRef; /*!< The db from which this allocation was made*/
1578 void *holeDbRef; /*!< The db from which this allocation was made*/
1582 RgSchEmtcUlGrnt emtcGrnt;
1583 RgSchDlRbAllocRaType0 raType0; /*!< Resource Alloction type zero for eMTC */
1584 #endif /* EMTC_ENABLE */
1589 * Allocation free pool for an allocation db
1591 typedef struct rgSchUlAllocMem
1593 uint8_t maxAllocs; /*!< Maximum possible allocations per subframe */
1594 RgSchUlAlloc *firstFree; /*!< First free index */
1595 RgSchUlAlloc *allocs; /*!< Array of 'maxAllocs' elems */
1600 * Allocation information for a subframe
1602 typedef struct rgSchUlAllocDb
1604 uint8_t count; /*!< Number of allocations */
1605 RgSchUlAlloc *first; /*!< First allocation */
1606 RgSchUlAllocMem mem; /*!< Alloc pool management */
1611 * Hole free pool for a hole db
1613 typedef struct rgSchUlHoleMem
1615 uint8_t maxHoles; /*!< Maximum possible holes per subframe */
1616 RgSchUlHole *firstFree; /*!< First free index */
1617 RgSchUlHole *holes; /*!< Array of 'maxHoles' elems */
1622 * Holes information for a subframe
1624 typedef struct rgSchUlHoleDb
1626 uint8_t count; /*!< Number of holes */
1627 RgSchUlHole *first; /*!< First hole */
1628 RgSchUlHoleMem mem; /*!< Hole pool management */
1633 * Uplink subframe information.
1635 typedef struct rgSchUlSf
1637 uint8_t idx; /*!< Identifier for uplink subframe (range: 0-7)
1638 - maps to HARQ proc ID */
1639 CmLListCp reTxLst; /*!< Retransmission List*/
1641 RgSchTddPuschOffInfo puschOffset; /*!< PUSCH offset information */
1642 uint8_t ulSfIdx; /*!< The Uplink subframe number
1643 in the TDD frame. Range [2-9]
1644 Used only in TDD Cfg 0 */
1646 uint32_t totPrb; /*!< Total PRB used in this sub frame */
1647 /* ccpu00129725 -DEL- removed Platform flag */
1648 /* Fix:ccpu00120610 add a counter to keep track of remaining allocations */
1649 uint8_t *allocCountRef; /*!< Allocation count in this
1650 * subframe, it is a reference to the actual
1651 * counter held in allocDb (no additional
1652 * logic needed to maintain this) */
1653 /* Added for Uplink Adaptive retransmission */
1654 RgSchUlAllocDb *allocDb; /*!< Allocation info */
1655 RgSchUlHoleDb *holeDb; /*!< Holes info */
1656 uint8_t availSubbands; /*!< Number of total available subbands
1657 * for the current sub-frame */
1658 uint8_t numACqiCount; /*!< Used to Restrict 2 Aperiodic cqi per TTI*/
1660 RgSchSfBeamInfo sfBeamInfo[MAX_5GTF_BEAMS]; /*!< Per info Beam per sf*/
1661 uint8_t numGrpPerTti; /*!< number of Group per TTI*/
1662 uint8_t numUePerGrp; /*!< number of UE per group in TTI*/
1666 /* Nprb indication at PHY for common Ch */
1669 * Bo report given for common logical channel.
1671 typedef struct rgSchClcBoRpt
1673 CmLList boLstEnt; /*!< Linked list entity for BO list */
1674 uint32_t bo; /*!< Bo in bytes */
1675 CmLteTimingInfo timeToTx; /*!< Time at which the BO needs to be satisfied
1676 (data to be sent to PHY) */
1678 uint8_t emtcDIReason; /*!< Reason for DI message to send. */
1679 uint8_t pnb; /*!< Paging narrowBand on which Ue performs reception of paging*/
1681 CmLteTimingInfo maxTimeToTx;
1684 uint8_t nPrb; /*! NPRB column. Allowed values {2,3} */
1685 /* Corrected allocation for common channels */
1691 * Logical channel control block for BCCH and PCCH channels.
1693 typedef struct rgSchClcDlLcCb
1695 uint8_t lcId; /*!< Logical channel ID */
1697 CmLListCp boLst; /*!< List of BOs reported (RgSchClcBoRpt) */
1702 * Transmission offset configuration for SRS.
1704 typedef struct rgSchSrsTxOffst
1706 uint8_t count; /*!< Number of offsets in the array */
1707 uint8_t offst[RGSCH_MAX_SRS_TX_OFFSET]; /*!< SRS TX offset value */
1712 * Cell Control block per cell.
1714 typedef struct rgSchSrsCfg
1716 /*ccpu00130768 - ADD - SRS CFG Present flag to enable/disable cell specific SRS*/
1717 Bool isSrsCfgPres; /*!< cell specific SRS CFG enable/disable flag */
1718 RgrSrsCfgPrd srsCfgPrdEnum; /*!< SRS configuration period (in subframes) */
1719 RgrSrsBwCfg srsBwEnum; /*!< SRS Bandwidth configuration per cell.*/
1720 RgSchSrsTxOffst srsTxOffst; /*!< Transmission offset for SRS */
1721 /*ccpu00116923 - ADD - SRS present support*/
1723 uint8_t srsSubFrameCfg;/*!< SRS subframe configuration index per cell.
1731 * MAC Configuration element for CRG interface.
1733 typedef struct rgSchCfgElem
1735 CmLList cfgReqLstEnt; /*!< Linked list entry for cfgReqLst */
1736 CmLteTimingInfo actvTime; /*!< Activation time to apply configuration */
1741 RgrCfgReqInfo *rgrCfgReq; /*!< Configuration request information from
1743 RgrCfgTransId transId; /*!< Transaction ID for the config request */
1744 } rgrCfg; /*!< RGR configuration information */
1750 * Configuration Control block per cell.
1752 typedef struct rgSchCfgCb
1754 CmLListCp crntRgrCfgLst; /*!< List of config requests recieved in the
1755 current TTI from RRM */
1756 CmLListCp pndngRgrCfgLst; /*!< List of pending config requests recieved in the
1757 previous TTIs from RRM */
1762 * Link of RNTIs managed by MAC.
1764 typedef struct rgSchRntiLnk
1766 uint16_t rnti; /*!< RNTI */
1767 /*Fix: Overcome race condition between MAC and Scheduler delete*/
1768 CmLList rntiGrdPoolLnk; /*!< Link for RNTI guard pool*/
1769 struct rgSchRntiLnk *prv; /*!< Link to previous RNTI */
1770 struct rgSchRntiLnk *nxt; /*!< Link to next RNTI */
1775 * Database of RNTIs managed by MAC.
1777 typedef struct rgSchRntiDb
1779 uint16_t rntiStart; /*!< Start RNTI */
1780 uint16_t maxRntis; /*!< Maximum number of RNTIs managed by MAC */
1782 RgSchRntiLnk *freeRnti; /*!< first free RNTI in the list */
1783 RgSchRntiLnk *lastRnti; /*!< last RNTI in the list */
1784 RgSchRntiLnk *rntiPool; /*!< Linked list of RNTIs */
1785 /*Fix:Overcome Race condition between MAC and Scheduler delete*/
1786 CmLListCp rntiGuardPool; /*!< Holds guard pool for RNTIs when deleted in
1787 Scheduler but not deleted at MAC */
1792 * Random access information per cell.
1794 typedef struct rgSchRaInfoCb
1797 uint8_t maxRaSize; /*!< Number of RA-RNTIs stored
1798 across radio frames */
1799 uint8_t lstSize; /*!< list size */
1800 CmLListCp *raReqLst; /*!< Each array elem is linked
1804 /* ccpu00132523 Doubled the array size from MAX_RARNTI because window expiry
1805 * is overlapping with newly received TACH reqs in max RAR window*/
1806 /* Array Size should be more than gap towards window start */
1807 CmLListCp raReqLst[RGSCH_RAREQ_ARRAY_SIZE]; /*!< Each array elem is linked
1809 (per max ra-rnti*2) */
1811 CmLListCp raCbLst; /*!< List of RaCbs */
1812 CmLListCp toBeSchdLst; /*!< List of RaCbs to be
1816 /** @brief This structure is part of the uplink HARQ process, this structure
1817 * encapsulates all the DRX related information.
1819 typedef struct rgSchDrxUlHqProcCb
1821 CmLList harqRTTEnt; /*!< Entry into the HARQ RTT timer list */
1822 CmLList harqRetxEnt; /*!< Entry into the harqRetxQ */
1824 uint16_t rttIndx; /*!< Current Index into HARQ RTT Q */
1825 uint16_t reTxIndx; /*!< Current Index into Re-Tx Q */
1826 uint8_t retxTmrReduction; /*!< Due to platform specific timing diff between
1827 UL HARQ processing and UL Scheduling, the
1828 drx retx timer may start at a later time, than
1829 actual. That delay in starting the timer is
1832 } RgSchDrxUlHqProcCb;
1838 * Uplink HARQ process information per UE
1840 struct rgSchUlHqProcCb
1842 uint8_t ndi; /*!< NDI */
1843 uint8_t remTx; /*!< Number of remaining transmissions */
1844 RgSchUlAlloc *alloc; /*!< Uplink allocation */
1845 /* Renamed rcvdDatInd to rcvdCrcInd */
1846 Bool rcvdCrcInd; /*!< Set to true when data rcvd, false when
1848 uint8_t rvIdx; /*!< Redundancy version index */
1849 TknUInt8 rvIdxPhy; /*!< Whatever is given by PHY. To be inspected in case
1850 of NACK.Always initialised to 'not present' */
1851 CmLList reTxLnk; /*!< Retransmission List */
1852 RgSchUlRetxAlloc reTxAlloc; /*!< Retransmission allocation
1854 Bool isRetx; /*!< Awaiting retransmission */
1855 uint8_t procId; /*!< HARQ Process ID */
1856 uint8_t ulSfIdx; /*!< UL Subframe Index */
1858 /* Changes for passing iPhich at TFU*/
1859 uint8_t iPhich; /*!< Needed to Calculate PHICH
1860 location. For TDD only */
1863 Bool isSpsActvnHqP; /*!< Set to true when this HqP is used for
1864 UL SPS Activation */
1865 Bool isSpsOccnHqP; /*!< Set to true when this HqP is used for
1866 UL SPS Occasion TX */
1870 RgSchDrxUlHqProcCb drxCb;
1873 /* 5gtf: TODO two links are not required */
1874 CmLList lnk; /*!< To link to inUse/Free Pool */
1875 CmLteTimingInfo schdTime; /*!< SFN,SF of schd time */
1880 * Uplink HARQ entity information per UE.
1882 typedef struct rgSchUlHqCb
1884 uint8_t maxHqRetx; /*!< Maximum number of harq
1885 * re-transmissions */
1886 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
1888 RgSchUlHqProcCb *hqProcCb; /*!< Uplink harq process info */
1890 RgSchUlHqProcCb hqProcCb[RGSCH_NUM_UL_HQ_PROC]; /*!< Uplink harq process info */
1893 uint8_t numBusyHqProcs; /*!< Total Num of Hq procs in use */
1899 CmLListCp free; /*!< List of free HARQ processes */
1900 CmLListCp inUse; /*!< List of in-use HARQ processes */
1905 * Logical channel group.
1910 * Structure to store values for Ra Preambles received values
1912 typedef struct rgSchRaPreambles
1914 uint8_t dedPream; /*!< Dedicated RA Preamble received */
1915 uint8_t preamGrpA; /*!< Randomly selected preambles in low range */
1916 uint8_t preamGrpB; /*!< Randomly selected preambles in high range */
1920 * @brief strutcure to store Avergae PRB usage for a given Time period in
1923 typedef struct rgSchAvgPrbDl
1925 Bool cntActive; /* Set to TRUE if counting activated */
1926 CmLteTimingInfo startTime; /*!< Start Time */
1927 uint8_t timePrd; /*!< Period For which meas to be done */
1928 uint32_t prbCount; /*!< PRB Count Updated every Per TTI */
1932 * @brief strutcure to store Avergae PRB usage for a given Time period in
1935 typedef struct rgSchAvgPrbUl
1937 Bool cntActive; /*!< Set to TRUE if counting activated */
1938 CmLteTimingInfo startTime; /*!< Start Time */
1939 uint8_t timePrd; /*!< Period For which meas to be done */
1940 uint32_t prbCount; /*!< PRB Count Updated every Per TTI */
1944 * L2 measurement control block.
1946 struct rgSchL2MeasCb
1948 CmLList measLnk; /*!< MeasCb node */
1949 LrgSchMeasReqInfo measReq; /*!< Request received for measurement */
1950 CmLteTimingInfo startTime; /*!< Time at which measurement started */
1951 RgInfPrbCfm avgPrbQciUl; /*!< Used to store result from MAC */
1952 Bool cfmRcvd; /*!< Used to check if confirm received from MAC */
1953 /*!< For average PRB usage in UL */
1954 uint16_t sfnCycle; /*<! Count of Num of SFN wraps */
1955 uint32_t dlTotalBw; /*!< Total DL Bw between meas Req and Meas Send Req */
1956 uint32_t ulTotalBw; /*!< Total UL Bw between meas Req and Meas Send Req */
1959 typedef struct rgSchTbCnt
1961 uint32_t tbTransDlTotalCnt; /*!< Total DL TB count */
1962 uint32_t tbTransDlFaulty; /*!< Total DL Faulty TB count */
1963 uint32_t tbTransUlTotalCnt; /*!< Total UL TB count */
1964 uint32_t tbTransUlFaulty; /*!< Total UL Faulty TB count */
1966 #endif /* LTE_L2_MEAS */
1968 * Control block to store measurement details per QCI.
1972 uint8_t qci; /*!< QCI of the Logical Channel */
1973 uint32_t dlPrbCount; /*!< Cumulative Prb Count for this QCI */
1974 uint32_t dlUeCount; /*!< Cumulative number of active UE's */
1975 uint32_t dlTotal_UeCount; /*!< Cummulative count added for every sampling
1977 uint32_t ulUeCount; /*!< Cumulative number of active UE's */
1978 uint32_t ulTotal_UeCount; /*!< Cummulative count added for every sampling
1983 /* Right now not keeping associated logical channels, searching for
1984 * associated channels needed only during config */
1985 uint8_t lcgId; /*!< Group ID */
1988 uint8_t numLch; /*!< Number fo LC's for this LCG*/
1989 RgSchUlLcCb *lcArray[RGSCH_MAX_LC_PER_UE]; /*!< Dedicated Uplink logical
1991 #endif /* LTE_L2_MEAS */
1992 /* Added support for SPS*/
1995 uint8_t lcId[RGR_MAX_SPS_LC];
2001 * Uplink Dedicated Logical channel control block.
2005 Bool isValid; /*!< If this struct holds valid values*/
2006 uint8_t lcId; /*!< Logical channel ID */
2007 uint8_t lcgArrIdx; /*!< Index of this LC in the LCG Array*/
2008 RgSchLcgCb *lcg; /*!< Logical channel group */
2009 RgrLchQosCfg ulQos; /*!< UL Qos parameters */
2010 /* After Merging from 2.1 to 2.2 */
2011 RgSchQciCb *qciCb; /* QCI Details for this LC */
2016 * Ul Grnt Info for Ho/Po UE in RAR.
2018 typedef struct rgSchHoPoUeGrnt
2020 uint8_t rapId; /*!< dedicated rapId */
2021 uint8_t hop; /*!< Hopping flag, set to 0 in this version */
2022 uint8_t rbStart; /*!< Start Resource block of allocation */
2023 uint8_t numRb; /*!< Number of resource blocks allocated */
2024 uint8_t tpc; /*!< TPC command for the uplink grant */
2025 uint8_t iMcsCrnt; /*!< Current MCS index of the grant */
2026 TknUInt16 ta; /*!< Timing Adjustment */
2027 CmLList raRspLnk; /*!< To link UE to RaRsp cont free list */
2028 /* Added support for SPS*/
2029 uint16_t datSz; /*!< Length of the Data */
2030 Bool cqiReqBit; /*!< Aperiodic CQI is requested or not */
2035 * Uplink SPS scheduling information per UE
2037 typedef struct rgSchCmnSpsUlUeSchdInfo
2039 uint32_t allocBwMask[RGSCH_SPS_ULBW_MASK_LEN]; /*!< Bitmask indicating the allocation info
2040 for the UE. Bit set at position 'x'
2041 indicates subband 'x' is allocated */
2042 uint8_t scaledCqi; /*!< Assumed value of CQI for transmission */
2043 uint16_t actvSfLstIdx; /*!< Index into cell-wide UL SPS sub-frame
2044 table during activation */
2045 CmLteTimingInfo ulSpsActvOcc; /*!< Time at which SPS is activated/reactivated
2047 CmLteTimingInfo crntUlSpsOcc;/*!< Key into the list of UL SPS active
2048 UEs: next UL SPS ocassion */
2049 RgSchUlAlloc allocInfo; /*!< Allocation information of the UE */
2050 RgSchUlAlloc *crntAlloc; /*!< Allocation pointer in the subframe */
2051 RgSchUlSf *crntAllocSf; /*!< sf in which crntAlloc was made */
2052 } RgSchCmnSpsUlUeSchdInfo;
2056 * Uplink information for SPS per UE
2058 typedef struct rgSchCmnUlUeSpsInfo
2060 CmLList actvUeLstEnt; /*!< Linked List entry for UL SPS
2062 CmLList pndngUeLstEnt;/*!< Linked List entry for UE list with
2064 activation/reactivation/release */
2065 Bool isUlSpsActv; /*!< Indicates if UE's UL SPS is
2067 uint8_t measGapMask[RGSCH_SPS_MG_MASK_LEN]; /*!< Indicates the UL sub-frames with
2068 ongoing measurement gap. Mask is
2070 uint8_t state; /*!< State of the UE: can be one of
2071 ACTV_REACTV_SENT (pdcch for
2072 (re)activation sent),REL_SENT,
2074 Bool pdcchToRetx; /*!< set to TRUE if DTX occurs at the
2075 (re)activated SPS occasion */
2076 RgSchCmnSpsUlUeSchdInfo ulSpsSchdInfo; /*!< Scheduled info for UL SPS
2079 uint8_t spsOccIdx; /*!< N value for nxt sps occasion */
2081 uint32_t packetSize; /*!< Packet size for SPS - SPS allocation*/
2082 uint32_t spsSduSize; /*!< SDU Size recvd on SPS Occasion*/
2083 uint32_t spsGrantSize; /*!< Grant size for SPS allocation */
2085 CmLteTimingInfo lastSpsDatRecvdTime; /*!< timing info on which the
2086 SPS data is recieved*/
2087 CmLListCp *spsList; /*!< Pointer to the SPS list of which
2089 uint32_t actPdcchCrcFailCount; /*!< Num of consecutive CRC fails for
2090 SPS Activation PDCCH */
2091 uint32_t crcFailCntSpsOcc; /*!< Consecutive CRC fail for SPS Occasion
2093 uint32_t relPdcchSntCnt; /*!< Num ber Rel PDCCH sent to UE*/
2094 #ifdef RGSCH_SPS_STATS
2095 uint32_t crcFailStats;
2096 uint32_t crcPassStats;
2100 } RgSchCmnUlUeSpsInfo;
2106 * Uplink control block for UE specific information.
2108 typedef struct rgSchUeUlCb
2110 RgSchUlLcCb lcCb[RGSCH_MAX_LC_PER_UE]; /*!< Dedicated Uplink logical channel
2112 RgSchLcgCb lcgArr[RGSCH_MAX_LCG_PER_UE]; /*!< Logical channel groups */
2113 uint8_t ulInactvMask; /*!< Bitmask indicating if UE is inactive for UL scheduling */
2114 CmLList ulInactvLnk; /*!< Link to the inactive UE List for UL */
2115 RgSchHoPoUeGrnt rarGrnt; /*!< UE's RAR grant Information */
2116 RgrUeTxAntSelCfg ulTxAntSel;/*!< UL Transmit antenna selection Cfg Info */
2118 /* Added periodic BSR timer */
2119 RgrUeBsrTmrCfg bsrTmrCfg; /*!< BSR timers configuraiton for the UE */
2121 /* Added support for SPS*/
2123 RgrUeSpsUlCfg ulSpsCfg; /*!< UL SPS configuration information */
2124 uint8_t explicitRelCnt; /*!< Number of subframes after sending
2125 release to consider it successful */
2126 uint16_t spsPrdcty; /*!< Shall store the SPS periodicity of the
2127 UE. Needed to round-off in case of
2129 CmLteTimingInfo relPdcchSchdTime; /*!< This field holds the scheduled time
2133 uint32_t nPrb; /*!< Number of resource block allocated */
2136 uint8_t betaHqOffst; /*!< Delta HARQ offset used in the case where HARQ
2137 feedback is multiplexed with PUSCH data. */
2138 uint8_t betaCqiOffst;/*!< Beta offset for CQI[0-15]. Given by RRC*/
2139 uint8_t betaRiOffst;/*!Beta offset for RI[0-15]. Given by RRC */
2141 uint32_t cqiRiSz; /*!<Size of Periodic/Aperiodic CQI or RI depending
2143 uint32_t betaOffstVal; /*!< beta offset of CQI or RI depending
2145 uint32_t maxBytesPerUePerTti; /*!< Maximum bytes that can be allocated
2146 * in 1 scheduling instance per UE */
2147 uint32_t minReqBytes; /*!< The buffer amount of lcg0 */
2148 uint32_t totalBsr; /*!< Total BSR as reported by UE (in bytes) */
2149 uint32_t nonLcg0Bs; /*!< Total BSR for LCG1/LCG2/LCG3 */
2150 uint32_t nonGbrLcgBs; /*!< Total BSR as reported by UE (in bytes) for non-GBR LCG's*/
2151 uint32_t effBsr; /*!< BSR yet to be satisfied in allocations */
2153 uint32_t cfgdAmbr; /*!< Byte rate of UE Ambr per Refresh Cycle */
2154 uint32_t effAmbr; /*!< Remaining Bytes of Byte rate available in a refresh Cycle */
2155 CmLteTimingInfo ulTransTime; /*!< Timing info of the latest reception of
2156 any UL data/signal from UE */
2158 RgSchCmnUlUeSpsInfo ulSpsInfo; /*!< UL SPS information for UE */
2160 Bool isUlCaEnabled; /*!< If TRUE UL CA is enabled for the UE */
2161 CmLteCellId ctrlOnServCellIdx[RGSCH_ULCTRL_RECP_DIST]; /*!<
2162 * Serving Cell Idx on which UL CTRL INFO is to
2163 * be received of all configured
2166 Bool useExtBSRSizes; /*!< If TRUE used R10 Extended BSR Size Table*/
2171 * Downlink CCCH Tx/Retx schedule information.
2173 typedef struct rgSchCcchSchdInfo
2175 uint32_t totBytes; /*!< Total bytes allocated */
2176 CmLList retxLnk; /*!< To link hqP to retx Queues */
2177 uint8_t rvIdx; /*!< Rv Index */
2178 } RgSchCcchSchdInfo;
2182 * Downlink Grant Information per UE.
2184 typedef struct rgSchDlGrnt
2186 uint16_t schdTime; /*!< Time at which Harq proc has been scheduled */
2187 uint8_t rbStrt; /*!< Starting RB of the allocation */
2188 uint8_t numRb; /*!< Number of RBs allocated */
2189 uint8_t iMcs; /*!< Index to the MCS */
2190 uint8_t rv; /*!< RV for HARQ (re)transmission */
2191 uint8_t rvIdx; /*!< RVIdx for HARQ(re)transmission */
2192 #ifdef RG_5GTF /* ToDo:: Anoop need to check for other fields required*/
2196 uint8_t xPDSCHRange;
2198 TfuDciFormat dciFormat; /*!< DCI format for the allocation */
2205 * Logical channel data as being scheduled by the scheduler.
2207 typedef struct rgSchLchAllocInfo
2209 uint8_t lcId; /*!< Logical channel ID */
2210 uint32_t schdData; /*!< Scheduled logical channel data */
2211 } RgSchLchAllocInfo;
2213 /** @brief This structure is part of the downlink HARQ process, this structure
2214 * encapsulates all the DRX related information.
2216 typedef struct rgSchDrxDlHqProcCb
2218 CmLList harqRTTEnt; /*!< Entry into the HARQ RTT timer list */
2219 CmLList harqRetxEnt; /*!< Entry into the harqRetxQ */
2221 uint16_t rttIndx; /*!< Current Index into HARQ RTT Q */
2222 uint16_t reTxIndx; /*!< Current Index into Re-Tx Q */
2223 uint8_t retxTmrReduction; /*!< Due to platform specific timing diff between
2224 DL HARQ processing and DL Scheduling, the
2225 drx retx timer may start at a later time, than
2226 actual. That delay in starting the timer is
2230 } RgSchDrxDlHqProcCb;
2232 /** @enum TfuDciFormat
2233 * This Enum has values for Harq Proc TB state.
2243 * Downlink TB information per DL HqProc.
2245 struct rgSchDlHqTbCb
2247 uint8_t tbIdx; /*!< Index of this TB (0/1). Initialized
2248 at HqEnt allocation */
2249 uint32_t tbSz; /*!< TB size scheduled for this TB */
2250 uint8_t txCntr; /*!< Transmission counter */
2251 uint8_t ndi; /*!< New Data Indicator 0 or 1*/
2252 TknUInt8 schdTa; /*!< TA scheduled to be sent */
2253 /* CR timer implementation changes*/
2255 uint8_t numLch; /*!< No. of DL Logical Channels scheduled
2257 CmLteTimingInfo timingInfo; /*!< This field holds the scheduled time */
2258 RgSchLchAllocInfo lchSchdDataArr[RGSCH_MAX_NUM_DED_LC];
2259 RgSchLchAllocInfo *lchSchdData;
2260 RgSchCcchSchdInfo ccchSchdInfo;/*!< CCCH TX/RETX scheduler Info */
2261 uint8_t fbkRepCntr; /*!< Counter to ANRep Feedback */
2262 uint8_t fbkRecpRepCntr; /*!< Counter to ANRep Feedback */
2263 CmLList anRepLnk[6]; /*!< Links for ANRep we need
2265 simultaneously hold the
2268 RgSchDlSf *crntSubfrm[6]; /*!< Pointer to subframes */
2269 uint8_t ackCount; /*!< Counter for ACKs */
2270 uint8_t isAckNackDtx; /* ACK or NACK or DTX*/
2271 uint8_t nackCount; /* NACK Counter */
2272 uint8_t dtxCount; /* DTX Counter */
2273 RgSchDlGrnt dlGrnt; /*!< Scheduler grant */
2274 Bool taSnt; /*!< TA sent or not */
2276 CmLteTimingInfo fdbkTime; /*!< Expected feedback time */
2277 uint8_t m; /*!< Subframe Order Index within the subframe
2278 downlink association index K */
2279 RgSchTddSfType sfType; /*!< Identifies the first Tx subframe type */
2280 uint8_t pucchFdbkIdx;/*!< DL subframe idx for which fdbk is expected */
2281 uint8_t dai; /*!< DAI associated with this TB.
2282 THis is used for F1BCS resource calulcation */
2283 #ifdef XEON_TDD_SPCL
2284 uint8_t initTxNumRbs;/*!< Number of Rbs Allocated in First TX */
2289 uint8_t numLyrs; /*!< Number of layers using which this TB is
2290 being transmitted */
2291 RgSchHqTbState state; /*!< State of this Trasport Block */
2292 RgSchDlHqProcCb *hqP; /*!< Reference to the TB container */
2293 /* Freeing up the HARQ proc blocked for
2294 * indefinite time in case of Retx */
2295 uint8_t cntrRetxAllocFail; /*!< Number of times allocation failed
2296 for the retransmission of this TB */
2298 TknUInt8 schdSCellActCe; /* !< SCell Act values and whether
2301 uint32_t firstSchedTime; /*!< First time when the TB was scheduled */
2302 uint8_t minRlcReordrTmr; /*!< Min RLC reorder timer of all LCs
2303 scheduled in this hqP*/
2309 * Downlink HARQ process information per UE.
2311 struct rgSchDlHqProcCb
2313 CmLList lnk; /*!< To link with other HARQ processes */
2314 RgSchDlHqEnt *hqE; /*!< HARQ entity */
2316 uint8_t txCntr; /*!< Transmission counter */
2318 uint8_t procId; /*!< Harq process ID */
2319 Void *sch; /*!< Cmn sched Hq control block */
2321 RgSchDlHqTbCb tbInfo[2]; /*!< TB related information for 1+1(if any) TBs */
2322 RgSchDrxDlHqProcCb drxCb; /*!< DRX control block */
2324 uint8_t tbCnt; /*!< Count of the number TBs being sent with a
2325 Reception Requesti */
2328 TknUInt16 spsN1PucchRes; /*!< N1Pucch resource for HARQ process at SPS
2329 ocassions: present only when HqP contains
2330 Data without PDCCH */
2332 /* Fix: syed having a hqP added to Lists for RB assignment rather than
2333 * a UE, as adding UE was limiting handling some scenarios */
2334 CmLList reqLnk; /*!< Link for list of UEs/RACBs to be scheduled */
2335 CmLList schdLstLnk; /*!< Link for list of scheduled/non-scheduled
2336 allocations: used by RB allocation module*/
2337 Bool hasDcch; /*!< Set to TRUE if DCCH channel is present in
2338 scheduling grant over this hqProc */
2339 Bool cwSwpEnabled; /*!< Set if CW swap enabled */
2341 uint8_t tpc; /*!< TPC command to be used for Secondary cell
2342 N1PUCCH resource Index*/
2346 /* Shifted from TbCb to HqCb*/
2347 RgSchPdcch *pdcch; /*!< Pdcch Allocated for this Hq TB */
2348 RgSchDlSf *subFrm; /*!< Subfrm for which this TB is assgnd */
2350 Void *emtcHqInfo;/*!< emtc specfic hq info */
2352 uint8_t dlDai; /*!< DL DAI assosciated with this harq proc */
2353 uint8_t ulDai; /*!< UL DAI assosciated with this harq proc */
2356 uint32_t isPuschFdbk;
2359 CmLListCp *hqPLst; /*!< pointer to either inUse of free list of hqE */
2360 TfuDciFormat prevDciFormat; /*!< Previous alloction DCI format used for ERR Ind prcessing */
2363 uint32_t tbSizeAtEstimate[2];
2364 uint32_t tbSizeAtFnlz[2];
2365 uint32_t tbSizeOfMvdTb[2];
2366 uint32_t itbsAtEstimate[2];
2367 uint32_t prbAtEstimate;
2372 * Downlink HARQ entity information per UE.
2376 RgSchRaCb *raCb; /*!< Parent RACB when attached to RACB */
2377 RgSchUeCb *ue; /*!< Parent UE */
2378 CmLListCp free; /*!< List of free HARQ processes */
2379 CmLListCp inUse; /*!< List of in-use HARQ processes */
2380 uint8_t maxHqTx; /*!< Maximum number of harq transmissions */
2381 RgSchDlHqProcCb *msg4Proc; /*!< Points to MSG4 HARQ process */
2383 /* CR timer changes*/
2384 RgSchDlHqProcCb *ccchSduProc; /*!< Points to CCCH SDU HARQ process
2385 to identify feedback for CCCH SDU
2386 transmissions done without cont res CE*/
2388 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
2390 RgSchDlHqProcCb *procs; /*!< Downlink harq processes */
2392 RgSchDlHqProcCb procs[RGSCH_NUM_DL_HQ_PROC]; /*!< Downlink harq processes */
2394 Void *sch; /*!< Scheduler specific Info */
2396 RgSchCellCb *cell; /*Contains the pointer to coresponding CellCb*/
2402 * @enum rgSchTaState
2403 * Enumeration of time alignment states.
2405 typedef enum rgSchTaState
2407 RGSCH_TA_IDLE = 0, /*!< TA is to be scheduled */
2408 RGSCH_TA_TOBE_SCHEDULED,/*!< TA is to be scheduled */
2409 RGSCH_TA_SCHEDULED /*!< TA is scheduled */
2414 * Downlink Time alignment information per UE.
2416 typedef struct rgSchUeDlTaCb
2418 uint16_t cfgTaTmr; /*!< Configured TA timer value */
2419 uint8_t ta; /*!< TA value for UE */
2420 uint8_t numRemSf; /*!< Number of subframes left to apply TA */
2421 RgSchTaState state; /*!< Indicates HARQ state for TA */
2422 /*rg003.301[ccpu00121813] ADD added new var*/
2423 Bool outStndngTa; /*!< if new TA is rcvd before it gets
2425 uint8_t outStndngTaval; /*!< outstanding TA val */
2430 * Downlink Dedicated Logical channel control block.
2434 uint8_t lcId; /*!< Logical channel ID */
2436 RgSchUeCb *ue; /* UE to which this LC belongs to */
2437 /* Not validating DlQos for DCCH */
2438 CmLteLcType lcType; /* Logical channel Type*/
2439 RgSchQciCb *qciCb; /*!< Pointer to ACI Control Block */
2440 /* Added support for SPS*/
2442 RgrLchSpsCfg dlLcSpsCfg; /*!< SPS configuration for DL logical channel */
2445 uint16_t estRlcHdrSz; /*!< Estimated RLC header size */
2446 Bool staPduPrsnt; /*!< Indicate the status pdu present or not*/
2448 uint32_t staPduBo; /*!< Indicate the Status PDU BO.
2449 This amount is already included in original BO */
2450 Void *sch; /*!< Holds Scheduler Info pointer */
2451 uint32_t prbsReqd; /*!< PRBs reqd in DL for each UE in MUE scenario*/
2452 CmLList schdLnk; /*!< Link to ueCb inserted in toBeSchdList in DL*/
2453 uint32_t oldestSduArrTime; /*!< oldest SDU arrival time for this LC */
2454 CmLList lcFlowCntrlEnt; /*!<link to Lc in flow Cntrl lst */
2455 CmLList lcPdbFbkLnk; /*!<link to LC in LC flow contrl monitoring lst */
2456 Bool setMaxUlPrio; /*!<set if Poll bit is sent in the PDU */
2457 Bool setMaxDlPrio; /*!<set if there is a RLC status PDU in DL */
2463 typedef struct rgSchN1PucchResCb
2465 uint16_t n1PucchIdx; /* !< N1 resource */
2466 CmLList n1Lnk; /* !< Link for adding into dlsf N1 used list */
2468 typedef struct rgSchN3PucchResCb
2470 uint16_t n3PucchIdx; /* !< N3 resource */
2471 CmLList n3Lnk; /* !< Link for adding into dlsf N3 used list */
2472 uint8_t sCellIdx; /* !< Allocated by which scell */
2475 typedef struct rgSchSCellN3ResCb
2477 uint8_t antP0N3ResCount; /* !< Number of N3 res for antenna port 0*/
2478 uint8_t antP1N3ResCount; /* !< Number of N3 res for antenna port 0*/
2479 RgSchN3PucchResCb antP0N3Res[RG_SCH_MAX_NUM_N3PUCCH_PER_UE]; /* !< Antenna Port 0 N3 resources*/
2480 RgSchN3PucchResCb antP1N3Res[RG_SCH_MAX_NUM_N3PUCCH_PER_UE]; /* !< Antenna Port 1 N3 resources*/
2483 typedef struct rgSchSCellN1ResCb
2485 uint8_t cw1N1ResCount; /* !< Number of N1 res for CW 1*/
2486 uint8_t cw2N1ResCount; /* !< Number of N1 res for CW 2*/
2487 RgSchN1PucchResCb cw1N1Res[RG_SCH_MAX_NUM_N1PUCCH_PER_UE]; /* !< CW1 N1 resources*/
2488 RgSchN1PucchResCb cw2N1Res[RG_SCH_MAX_NUM_N1PUCCH_PER_UE]; /* !< CW2 N1 resources*/
2492 typedef struct rgSchN3PucchRes
2494 uint16_t n3PucchIdx; /* !< N3 resource */
2498 typedef struct rgSchDlHqInfo
2502 uint8_t numOfCells; /*!<This will be used to store number of unique cells in
2504 Bool isSCellPdschPres; /*!< Flag to indicate whether any PDSCH transmission
2505 present in secondary cell. Used for CSI/HARQ collision
2508 Bool isPuschHarqRecpPres;/*!< Flag to indicate pusch recp req is pres or not */
2509 RgrSchFrmt1b3TypEnum uciFrmtTyp; /*!< Store value of format1b or format3.
2511 uint8_t totalTbCnt; /*!< This will be used to store total number of TBs
2512 across all harqProcs.It will be used to identify
2513 PUCCH format type to be used in this SF*/
2514 CmLList dlSfUeLnk; /*!< list entry into dlsf->ueLst */
2516 CmLListCp hqPLst; /*!< This is a list of hq proc per DL
2517 SF which are scheduled in that SF.
2518 The number of harq procs awaiting
2519 feedback for the same subframe depends on
2520 mode TDD or FDD and max number of Carriers
2521 that can be aggregated */
2523 RgSchN3PucchRes n3ScellPucch;
2528 /** @brief This structure contains the Measurement gap configuration for an UE.
2530 typedef struct rgUeMeasGapCfg
2532 Bool isMesGapEnabled; /*!< Is Measuremnet gap enabled or disabled */
2533 uint8_t gapPrd; /*!< Gap period 40ms/80ms */
2534 uint8_t gapOffst; /*!< Gap offset - Vaue is 0 to 1*/
2538 @brief Measurement Gap related information per UE. */
2539 typedef struct rgSchUeMeasGapCb
2541 Bool isMesGapEnabled;/*!< TRUE if Measurement gap is enabled for this UE */
2542 uint8_t isMeasuring; /*!< Set to TRUE during measurement gap */
2543 uint8_t gapPrd; /*!< Measurement gap period configuration for the UE */
2544 uint8_t gapOffst; /*!< Measurement gap offset for the UE */
2545 CmLList measQLnk; /*!< To Link to the measurement gap list */
2546 CmLList ackNakQLnk; /*!< To Link to the ACK NACK Rep list */
2547 CmTimer measGapTmr; /*!< Timer for Measurement Gap */
2548 CmTimer measGapUlInactvTmr; /*!< UL Inactive timer for measurement gap */
2549 CmTimer measGapDlInactvTmr; /*!< DL Inactive timer for measurement gap */
2553 @brief ACK-NACK repetition related information per UE. */
2554 typedef struct rgSchUeAckNakRepCb
2556 Bool isAckNackEnabled; /*!< Is ACK/NACK Enabled*/
2557 uint8_t isAckNakRep; /*!< Set to TRUE during ACK-NACK repetition prd */
2558 uint8_t cfgRepCnt; /*!< Configured value for the repetition counter */
2559 uint8_t repCntr; /*!< Actual repetition counter */
2560 uint16_t pucchRes; /*!< PUCCH resource for repetition */
2561 CmTimer ackNakRepUlInactvTmr; /*!< UL Inactive timer for ack-nack repetition */
2562 CmTimer ackNakRepDlInactvTmr; /*!< DL Inactive timer for ack-nack repetition */
2563 CmTimer ackNakRepTmr; /*!< Timer for ack-nack repetition */
2564 CmLList ackNakRepLnk; /*!< ACK NACK repetition queue link */
2565 CmLListCp *prsntQ; /*!< Pointer to the Queue that this UE is current
2567 } RgSchUeAckNakRepCb;
2571 * UE's MIMO specific information.
2573 typedef struct rgSchUeMimoInfo
2575 RgrTxMode oldTMode; /*!< UE's Previous Transmission Mode */
2576 RgrTxMode txMode; /*!< UE's Transmission Mode */
2577 TknUInt32 doa; /*!< DOA indicator for this UE */
2578 Bool puschFdbkVld; /*!< True if Precoding Info in PDCCH has to be
2579 in-accordance with the latest PUSCH report */
2580 TfuDlCqiPuschInfo puschPmiInfo; /*!< PUSCH report details for explicit PMI
2581 * information to PHY during a PDSCH */
2582 RgrCodeBookRstCfg cdbkSbstRstrctn; /*!< Codebook subset restriction defined as per
2583 * 36.331 section 6.3.2. As of now, this info
2584 * is not processed by MAC. SCH shall use the
2585 * PMI reported by UE unconditionally.*/
2587 S32 txModUpChgFactor; /*!< tx mode chnage factor for step up*/
2588 S32 txModDownChgFactor; /*!< tx mode chnage factor for step
2593 /* Added changes of TFU_UPGRADE */
2596 /** @brief This structure that stores the length of Bits that
2597 * will be received over PUSCH for Aperiodic Mode 3-1.
2599 typedef struct rgSchCqiRawPuschMode31
2601 uint8_t wideBCqiCw0; /*!< Length of Wideband CQI Codeword 0 */
2602 uint8_t totLenSbDiffCqiCw0; /*!< Length of SubBand Differential CQI Codeword 0 */
2603 uint8_t r1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank =1*/
2604 uint8_t r1TotLenSbDiffCqiCw1; /*!< Length of SubBand Differential CQI Codeword 1 for Rank = 1*/
2605 uint8_t rg1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank > 1*/
2606 uint8_t rg1TotLenSbDiffCqiCw1; /*!< Length of SubBand Differential CQI Codeword 1 for Rank > 1*/
2607 uint8_t r1PmiBitLen; /*!< Length of PMI Bits for Rank = 1*/
2608 uint8_t rg1PmiBitLen; /*!< Length of PMI Bits for Rank > 1*/
2609 } RgSchCqiRawPuschMode31;
2611 /** @brief This structure that stores the length of Bits that
2612 * will be received over PUSCH for Aperiodic Mode 3-0.
2614 typedef struct rgSchCqiRawPuschMode30
2616 uint8_t wideBCqiCw; /*!< Length of Wideband CQI */
2617 uint8_t totLenSbDiffCqi; /*!< Length of SubBand Differential CQI */
2618 } RgSchCqiRawPuschMode30;
2620 /** @brief This structure that stores the length of Bits that
2621 * will be received over PUSCH for Aperiodic Mode 2-2.
2623 typedef struct rgSchCqiRawPuschMode22
2625 uint8_t wideBCqiCw0; /*!< Length of Wideband CQI Codeword 0 */
2626 uint8_t sBDiffCqiCw0; /*!< Length of SubBand Differential CQI Codeword 0 */
2627 uint8_t r1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank =1 */
2628 uint8_t r1SbDiffCqiCw1; /*!< Length of SubBand Differential CQI Codeword 1 for Rank =1*/
2629 uint8_t rg1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank > 1*/
2630 uint8_t rg1SbDiffCqiCw1; /*!< Length of SubBand Differential CQI Codeword 1 for Rank >1*/
2631 uint8_t posOfM; /*!< Position of M selected SubBands */
2632 uint8_t r1PmiBitLen; /*!< Length of PMI Bits for Rank =1*/
2633 uint8_t rg1PmiBitLen; /*!< Length of PMI Bits for Rank >1*/
2634 } RgSchCqiRawPuschMode22;
2636 /** @brief This structure that stores the length of Bits that
2637 * will be received over PUSCH for Aperiodic Mode 2-0.
2639 typedef struct rgSchCqiRawPuschMode20
2641 uint8_t wideBCqiCw; /*!< Length of Wideband CQI */
2642 uint8_t subBandDiffCqi; /*!< Length of SubBand Differential CQI */
2643 uint8_t posOfM; /*!< Position of M selected SubBands */
2644 } RgSchCqiRawPuschMode20;
2646 /** @brief This structure that stores the length of Bits that
2647 * will be received over PUSCH for Aperiodic Mode 1-2.
2649 typedef struct rgSchCqiRawPuschMode12
2651 uint8_t wideBCqiCw0; /*!< Length of Wideband CQI Codeword 0 */
2652 uint8_t r1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank =1*/
2653 uint8_t rg1WideBCqiCw1; /*!< Length of Wideband CQI Codeword for Rank > 1 */
2654 uint8_t r1TotalPmiBitLen; /*!< Aggregate length of PMI Bits for Rank =1 */
2655 uint8_t rg1TotalPmiBitLen; /*!< Aggregate length of PMI Bits for Rank > 1 */
2656 } RgSchCqiRawPuschMode12;
2659 /** @brief This structure that stores the length of Bits that
2660 * will be received over PUSCH.
2662 typedef struct rgSchDlCqiRawPusch
2664 TfuDlCqiPuschMode mode; /*!< PUSCH CQI mode */
2665 TknUInt8 ri; /*!< Rank Indicator for TM 3,4 */
2668 RgSchCqiRawPuschMode12 mode12Info; /*!< Mode 1-2 information */
2669 RgSchCqiRawPuschMode20 mode20Info; /*!< Mode 2-0 information */
2670 RgSchCqiRawPuschMode22 mode22Info; /*!< Mode 2-2 information */
2671 RgSchCqiRawPuschMode30 mode30Info; /*!< Mode 3-0 information */
2672 RgSchCqiRawPuschMode31 mode31Info; /*!< Mode 3-1 information */
2674 } RgSchDlCqiRawPusch;
2676 typedef struct rgSchPuschRawCqiInfoPerCell
2678 uint8_t sCellIdx; /*!< Serving cell idx of the cell for
2680 RgSchDlCqiRawPusch puschRawCqiInfo; /*!< Raw CQI Bit Width for PUSCH */
2681 } RgSchPuschRawCqiInfoPerCell;
2683 typedef struct rgSchPuschRawCqiInfoForSCells
2685 uint8_t numOfCells; /* Num of cells for which Apcqi is comming*/
2686 RgSchPuschRawCqiInfoPerCell cqiBitWidth[CM_LTE_MAX_CELLS];
2687 } RgSchPuschRawCqiInfoForSCells;
2689 typedef struct rgSchPucchRawCqiInfoPerCell
2691 uint8_t sCellIdx; /*!< Serving cell idx of the cell for
2693 TfuDlCqiPucch pucchRawCqiInfo; /*!< Raw CQI Bit Width for PUCCH */
2694 } RgSchPucchRawCqiInfoPerCell;
2696 typedef struct rgSchUeRawCqiBitWidthInfo
2698 TfuRecpReqType type; /*!< Type indicating PUCCH or PUSCH */
2699 CmLteTimingInfo recvTime;
2702 RgSchPucchRawCqiInfoPerCell pucch;
2703 RgSchPuschRawCqiInfoForSCells pusch;
2705 } RgSchUeRawCqiBitWidthInfo;
2714 * Enum for storing the different states of a Scell
2715 * RG_SCH_SCELL_INACTIVE : SCell is added but not activate
2716 * RG_SCH_SCELL_TOBE_ACTIVATED : SCell Activation trigger condition is met
2717 Need to be scheduled.
2718 * RG_SCH_SCELL_ACTVTN_IN_PROG : Waiting for Harq feedback for the scell activation
2719 * RG_SCH_SCELL_ACTIVE : SCell is activated succesfully
2723 RG_SCH_SCELL_INACTIVE = 0, /*!<SCELL Addition/Reset */
2724 RG_SCH_SCELL_READY, /*!<SCELL Ready is reaceived or SCell is deactivated */
2725 RG_SCH_SCELL_TOBE_ACTIVATED, /*!<Activation Trigger */
2726 RG_SCH_SCELL_ACTVTN_IN_PROG, /*<!Activation CE is sent */
2727 RG_SCH_SCELL_TOBE_DEACTIVATED, /*<!Deactivation Trigger */
2728 RG_SCH_SCELL_DEACTVTN_IN_PROG, /*<!Deactivation CE is sent */
2729 RG_SCH_SCELL_ACTIVE /*<!SCell is activated */
2734 * Enum to define the value of A for Format 1B with CS
2735 * in FDD Case and for M=1 in TDD Case.
2742 RG_SCH_A_VAL_INVALID = 5
2748 * Enum to define the value of A for Format 1B with CS
2749 * in FDD Case and for M=1 in TDD Case.
2757 RG_SCH_M_VAL_INVALID = 5
2764 * Downlink UE specific SCell information.
2766 struct rgSchUeCellInfo
2768 CmHashListEnt ueLstEnt; /*!< Hash List entity for UE List */
2769 RgSchUeCb *ue; /*!< Pointer to UECB */
2771 uint8_t sCellIdx; /*!< Serving Cell Index */
2772 uint16_t sCellId; /*!< Secondary Cell Id */
2773 RgSCellStateEnum sCellState; /* !< For holding the current state of the sec cell */
2774 CmLList sCellLnk; /*!< Node for adding this UE in secondary cell */
2776 RgSchDlHqEnt *hqEnt; /*!< Downlink HARQ information for the UE */
2777 RgSchDlRbAlloc dlAllocCb; /*!< RB Allocation Info for Ded Trans/Retrans */
2778 RgSchCellCb *cell; /* !< Reference to sec Cell Cb */
2779 Void *sch; /*!< UE Specific Scheduler information */
2780 RgrUeTxModeCfg txMode; /*!< UE transmission mode in Secondary */
2782 RgSchTddANInfo *anInfo; /*!< ACK/NACK related Information */
2783 uint8_t nextFreeANIdx; /*!< Next Available ANInfo Index */
2786 uint8_t reqForCqi; /*!< set to True if Aperiodic CQI from UE is required */
2788 RgSchUeACqiCb acqiCb; /* ! < Aperiodic CQI Report Control Block*/
2789 RgSchUePCqiCb cqiCb; /*!< Periodic CQI PMI RI Control Block */
2790 TknUInt8 pA; /* PA value configured by RRM
2791 ref: RRC 36.331, 6.3.2, PDSCH-Config*/
2792 /* RgSchUeRawCqiBitWidthInfo rawCqiBitW[MAX_CQI_RI_RPT_BUFF]; */
2794 uint8_t cqiRiWritIdx; /*!< write index to be used whenever CQI/RI reception
2795 request is being filled*/
2796 uint8_t cqiRiReadIdx; /*!< Read index to be used whenevr CQI/RI indication
2797 is recieved from PHY*/
2798 CmTimer deactTmr; /*!< SCell deactivation timer */
2799 CmTimer actDelayTmr; /*!< SCell timer */
2811 * Downlink control block for UE specific information.
2813 typedef struct rgSchUeDlCb
2815 RgSchUeDlTaCb taCb; /*!< Downlink timing adjustment information for the
2817 RgSchDlLcCb *lcCb[RGSCH_MAX_LC_PER_UE];/*!< Dedicated Downlink logical channels in
2819 RgrUeDlCqiCfg ueDlCqiCfg; /*!< UE DL CQI config */
2820 uint8_t dlInactvMask; /*!< Bitmask indicating if UE is inactive for DL scheduling */
2821 RgSchCqiReqField reqForCqi; /*!< set to True if Aperiodic CQI from UE is required */
2822 Bool pCqiPrsnt; /*!< set to True if periodic CQI from UE is expected */
2823 Bool acqiResGrntd; /*!< Aperiodic CQI resources granted in RB Estimation */
2824 CmLList dlInactvLnk; /*!< Link to the inactive UE List for DL */
2826 RgrTddAckNackMode ackNackMode; /*!< ACK/NACK Bundling/ ACK/NACK Multiplexing */
2828 /* Added support for SPS*/
2830 RgrUeSpsDlCfg dlSpsCfg; /*!< DL SPS configuration information */
2831 Bool isSpsHqPInUse; /*!< Indicates if SPS HARQ procs are in use
2832 or are to be used for SPS
2834 RgSchPdcch spsOccPdcch; /*!< PDCCH information for SPS ocassion */
2837 uint8_t numHqDlSfInfo;
2839 RgSchDlHqInfo *dlSfHqInfo;
2842 /* 5GTF TODO : Hard setting number of CCs to 3 */
2843 RgSchDlHqInfo dlSfHqInfo[MAX_5GTF_CELL][RGSCH_NUM_DL_slotS];
2845 RgSchDlHqInfo dlSfHqInfo[RGSCH_NUM_DL_slotS];
2848 /* Moved from rgSchCmnDlUe to Here, as this shouldn't be present per cell*/
2849 uint32_t ambrCfgd; /*!< UE's configured AMBR scaled to Refresh Cycle */
2851 /* Added to restrict max TB Bits in case of more than one CCs for a UE */
2852 uint32_t aggTbBits; /*!< Aggregated Transport Block Bits this UE can receive per TTI*/
2853 CmLteTimingInfo lstSchTime; /*!< Last Time UE got Scheduled */
2861 /******************************************************************************
2862 * Start of Data declarations *
2863 ******************************************************************************/
2865 @brief Half Duplex subframtion information stored per ue. */
2867 typedef struct rgSchUeHdFddSfInfo
2869 uint16_t sfn; /*!< Store the sfn for updated state
2870 Default Value= 0xffff
2874 0x01= DL DATA +(OPT:CNTRL INFO)
2876 0x04= UL DATA+(OPT: CTNRL INFO)
2879 }RgSchUeHdFddSfInfo;
2882 @brief Half Duplex control related information per ue. */
2884 typedef struct rgSchUeHdFddCb
2886 RgSchUeHdFddSfInfo subfrm[RG_SCH_HDFDD_NUMSFINFO];
2889 #endif /* LTEMAC_HDFDD */
2892 /** @brief This structure is part of rgSchUeCb structure and stored DRX related
2893 * information for a UE.
2895 typedef struct rgSchDrxUeCb
2898 TknS32 cqiMask; /*!<If pres, only value supported is SETUP i.e 0 */
2900 Bool srRcvd; /*!< TRUE if SR is received from the UE. */
2901 Bool raRcvd; /*!< TRUE if Random access request is received using a
2902 dedicated preamble for this UE. */
2903 uint16_t onDurTmrLen; /*!< Length of onDuration Timer [1 - 200]. */
2904 uint16_t drxStartOffset; /*!< Value of the DRX Starting Offset [0 - 2559]. */
2905 S16 onDurExpDistance; /*!< Keeps track of actual distance */
2907 uint16_t drxRetransTmrLen; /*!< Length of DRX Retransmission timer [1 - 33].*/
2909 uint16_t inactvtyTmrLen; /*!< Length of drx-Inactivity Timer [1 - 2560]. */
2910 S16 drxInactDistance; /*!< Keeps track of actual distance */
2913 uint16_t longDrxCycle; /*!< Value of the DRX long cycle [10 - 2560]. */
2915 Bool isShortCycleCfgd; /*!< TRUE if short cycle is enabled. */
2916 uint8_t shortCycleTmrLen; /*!< Value of DRX short cycle Timer [1-16]. */
2917 uint16_t shortDrxCycle; /*!< Value of the DRX short cycle [2 - 640]. */
2918 S16 drxShortCycleDistance; /*!< Keeps track of actual distance */
2921 CmLList onDurationEnt; /*!< Entry into the OnDuration List. */
2922 CmLList onDurationExpEnt; /*!< Entry into the onDuration Expiry List. */
2923 CmLList inActvTmrEnt; /*!< Entry into the inactivity Timer list. */
2924 CmLList shortCycleEnt; /*!< Entry into HARQ Retransmission list. */
2926 S16 distance; /*!< Keeps track of actual distance */
2928 /* The following elements track current indices into the drxQ present at the
2929 * cell level. These indicies help in fast deletion in case of UE Delete,
2930 * otherwise it might have required a linear search. */
2931 uint16_t onDurIndx; /*!< The current index for onDuration Queue. */
2932 uint16_t onDurExpIndx; /*!< The current index for onDuration Queue. */
2933 uint16_t drxInactvIndx; /*!< The current index for drx-InactityTmr Queue. */
2934 uint16_t shortCycleIndx; /*!< The current index for Short Cycle Queue. */
2936 uint8_t shortCycleTmr; /*!< Counter to keep track of Short DRX Cycle. */
2937 uint32_t drxDlInactvMask; /*!< Downlink Mask to track InActivity */
2938 uint32_t drxUlInactvMask; /*!< Uplink Mask to track InActivity */
2939 uint32_t drxDlInactvMaskPerCell[CM_LTE_MAX_CELLS]; /*!< Downlink Mask to track InActivity per cell */
2940 uint32_t drxUlInactvMaskPerCell[CM_LTE_MAX_CELLS]; /*!< Uplink Mask to track InActivity per cell */
2945 /* ccpu00117452 - MOD - Changed macro name from
2946 RGR_RRM_DLPWR_CNTRL to RGR_CQI_REPT */
2948 typedef struct RgSchCqiInfo
2950 uint8_t cqiCount; /* To keep track of CQI reports
2952 RgrUeCqiRept cqiRept[RGR_CQIRPTS_MAXN]; /* Array to maintain CQI reports */
2958 /* LTE_ADV_FLAG_REMOVED_START */
2960 /* @brief Control block for LTE Advance Feature for UE */
2961 typedef struct rgSchLteAdvUeCb
2963 RgrLteAdvancedUeConfig rgrLteAdvUeCfg; /*< RGR Configuration of LTE Adv */
2964 Bool isCCUePHigh; /* CC user gets high power after RNTP info */
2965 } RgSchLteAdvFeatureUeCb;
2966 /* LTE_ADV_FLAG_REMOVED_END */
2968 /*<! Sizes of DCI 0/1/1A/2/2A */
2969 typedef struct rgSchUeDciSize {
2971 uint8_t cmnSize[TFU_DCI_FORMAT_6_2+1]; /*!< DCI 0/1A/6-0A/6-1A final size in common Search Space and scrambled by C-RNTI */
2972 uint8_t dedSize[TFU_DCI_FORMAT_6_2+1]; /*!< DCI 0/1/1A/2/2A/6-0A/6-1A final size in UE Search Space and scrambled by C-RNTI */
2974 uint8_t cmnSize[TFU_DCI_FORMAT_1A+1]; /*!< DCI 0/1A final size in common Search Space and scrambled by C-RNTI */
2975 uint8_t dedSize[TFU_DCI_FORMAT_2A+1]; /*!< DCI 0/1/1A/2/2A final size in UE Search Space and scrambled by C-RNTI */
2977 uint8_t noUlCcSize[TFU_DCI_FORMAT_2A+1]; /*!< DCI 1/1A final size in UE/Common Search Space when the cell
2978 is SCell and no corresponding UL CC configured */
2982 typedef struct rgSchPerRefreshStats {
2984 uint32_t remDeltaMbr;
2985 uint32_t totByteSchd;
2987 }RgSchPerRefreshStats;
2989 typedef struct rgSchLcStats
2992 //uint32_t schdOccCnt;
2993 uint32_t ueSchdOcc[CM_LTE_MAX_CELLS];
2994 uint32_t gbrSatisfiedCnt;
2995 Bool ignoredFirstRefresh;
2996 uint32_t gbrRefreshCycleCnt;
2997 uint32_t totGbrBytesSchd;
2998 uint32_t totMbrBytesSchd;
2999 uint32_t achvdFracDataRate;
3001 #define RGSCH_NUM_STATS_PER_REFRESH 50
3004 uint32_t favCellCnt[CM_LTE_MAX_CELLS];
3005 RgSchPerRefreshStats perRefresh[RGSCH_NUM_STATS_PER_REFRESH];
3008 typedef struct rgSchCqiStats
3010 uint32_t totalCqiOcc;
3014 typedef struct rgSchPfsStats
3016 RgSchLcStats lcStats[RGSCH_MAX_LC_PER_UE];
3017 //uint32_t ueSchdOcc[CM_LTE_MAX_CELLS];
3018 uint32_t refreshCycleCnt;
3019 RgSchCqiStats cqiStats[CM_LTE_MAX_CELLS];
3027 * UE control block for UE specific information for 5gtf.
3029 typedef struct rgSch5gtfUeCb
3031 uint8_t grpId; // Group Id
3032 uint8_t BeamId; // Beam Id of UE
3033 uint8_t numCC; // num Carrier configured for UE
3034 uint8_t mcs; // MCS configured
3035 uint8_t maxPrb; // Max Prb configured for UE
3036 CmLteTimingInfo nxtCqiRiOccn; /*!< Next CQI RI Occn */
3037 uint16_t cqiRiPer; /*!< CQI RI periodicity in SFs */
3038 uint8_t rank; /*!< Latest Rank Report from UE */
3044 * UE control block for UE specific information.
3048 uint32_t totalBo; /*!<Sum of DL BO across all logical channels*/
3049 uint32_t totalPrbRequired;/*!<Num of PRB reqd to satisfy DL totlBo*/
3050 /* Added support for SPS*/
3052 CmHashListEnt spsUeLstEnt; /*!< Hash List entity for UE List */
3053 uint32_t spsOccasionCnt; /*!< Total number of SPS occasion cnt*/
3055 #ifdef CQI_CONFBITMASK_DROP
3056 uint8_t cqiConfBitMask;
3059 RgSchRntiLnk *rntiLnk; /*!< Link to RNTI for the UE */
3060 CmLteRnti ueId; /*!< UE identifier */
3061 RgSchUeMimoInfo mimoInfo; /*!< MIMO related information for a UE */
3062 /* Added support for SPS*/
3064 CmLteRnti spsRnti; /*!< Configured value for spsRnti if SPg
3065 is enabled for the UE */
3066 /* TODO antz - put all relPdcch related info in a struct */
3067 CmLteTimingInfo relPdcchTxTime; /*!< Time at which release pdcch is
3070 uint8_t relPdcchValm; /*!< 'm' for relPdcch */
3072 CmLteTimingInfo relPdcchFbkTiming;/*!< Release PDCCH feedback timing for
3073 the UE: value used by DHM */
3075 RgSchCellCb *cell; /*!< Cell to which this UE belongs */
3076 #ifdef XEON_SPECIFIC_CHANGES
3077 Void *sch; /*!< UE Specific Scheduler information */
3079 RgSchUeUlCb ul; /*!< UE Specific Uplink information */
3080 RgSchUeDlCb dl; /*!< UE Specific Downlink information */
3081 CmLteTimingInfo datIndTime;/*!< Timing info of the last received Dat
3083 CmLteTimingInfo macCeRptTime;/*!< Timing info of the last received
3084 * MAC CE (BSR/PHR) */
3085 uint32_t y[RGSCH_NUM_SUB_FRAMES]; /*!< 'Y' values calculated
3086 using C-RNTI and subframe
3088 present in sec 9.1.1 of
3091 CmLList taLnk; /*!< To link to the taUeLst list */
3092 CmLList dlTaLnk; /*!< To link to the Dl SCHED's taLst */
3093 CmTimer taTmr; /*!< Timer for Timing Alignment */
3094 RgSchUeMeasGapCb measGapCb; /*!< Measurement gap control block */
3095 RgSchUeAckNakRepCb ackNakRepCb; /*!< Ack-Nack Repetition control block */
3097 CmLList sCellActLnk; /*!< To link to the Dl SCHED's
3098 ScellActivation List */
3102 /* Added periodic BSR timer */
3103 CmTimer bsrTmr; /*!< BSR timer expiry handling case */
3104 /* CR timer implementation changes*/
3105 CmLList ccchSduLnk; /*!< To link raCb to the "to be
3111 uint32_t bo; /*!< Buffer occupancy for
3113 } dlCcchInfo; /*!< Params for DL
3117 CmTimer bsrTmr; /*!< BSR timer expiry handling case */
3119 /* Added changes of TFU_UPGRADE */
3121 CmLteUeCategory ueCatEnum;
3122 /* Moved to SCellInfo*/
3123 // RgSchUeACqiCb acqiCb; /* ! < Aperiodic CQI Report Control Block*/
3124 /* Periodic CQI/SRS/SR Report Feature */
3125 RgSchUeSrsCb srsCb; /*!< SRS Control Block*/
3126 RgSchUeSrCb srCb; /*!< SR Control Block */
3130 /* Half Duplex Feature */
3131 Bool hdFddEnbld; /*!< Half Duplex FDD is configured TRUE=1/FALSE=0 */
3132 RgSchUeHdFddCb *hdFddCb; /*!< Half Duplex Control Block */
3133 #endif /* LTEMAC_HDFDD */
3134 /* Added changes of TFU_UPGRADE */
3135 Bool isDrxEnabled; /*!< isDrx Enabled for this UE?*/
3136 RgSchDrxUeCb *drxCb; /*!< DRX control block. Allocated at time of
3137 UE configuration. */
3138 CmLList ulDrxInactvLnk; /*!<List of UE's which become inactive for UL */
3139 CmLList dlDrxInactvLnk; /*!<List of UE's which become inactive for DL */
3141 CmLList ulDrxInactvTmrLnk; /*!<List of UEs on which inactivity
3142 tmr has to be started for UL */
3143 CmLList dlDrxInactvTmrLnk; /*!<List of UEs on which inactivity
3144 tmr has to be started for DL */
3147 uint8_t validTxAnt; /*! < Tx Antenna selected after computing the CQI among two Antennas*/
3149 uint8_t cqiRiWritIdx; /*!< write index to be used whenever CQI/RI reception
3150 request is being filled*/
3151 uint8_t cqiRiReadIdx; /*!< Read index to be used whenevr CQI/RI indication
3152 is recieved from PHY*/
3153 RgSchUeRawCqiBitWidthInfo rawCqiBitW[MAX_CQI_RI_RPT_BUFF];
3154 uint8_t initNumRbs; /* No. of RBs allocated for UL Data New Transmission */
3157 /* ccpu00117452 - MOD - Changed macro name from
3158 RGR_RRM_DLPWR_CNTRL to RGR_CQI_REPT */
3160 RgrUeCqiReptCfg cqiReptCfgInfo; /* Holds static information such
3161 as configured values for DL
3166 /* ccpu00117452 - MOD - Changed macro name from
3167 RGR_RRM_DLPWR_CNTRL to RGR_CQI_REPT */
3169 RgSchCqiInfo schCqiInfo; /* This structure is place holder for
3170 keeping all CQI reporting related information */
3172 /* LTE_ADV_FLAG_REMOVED_START */
3173 RgSchLteAdvFeatureUeCb lteAdvUeCb; /* LTE-Advanced control block for UE */
3174 /* LTE_ADV_FLAG_REMOVED_END */
3178 uint8_t qciActiveLCs[LRG_MAX_QCI]; /* This structure has number of active LCs per
3179 Qci for this UE */ /* L2_COUNTERS */
3180 uint16_t ulActiveLCs; /* This is a bitmask - Each bit representing a QCI
3181 LSB - QCI 1 ... When bit is set, UE has an active
3183 uint16_t lastDatIndLCs; /* This is a bitmask - Each bit representing a QCI
3184 for which Data for received in UL
3185 LSB - QCI 1 ... When bit is set, UE has an active
3188 Bool isMsg4PdcchWithCrnti; /* This is to aid rgNumMsg4PdcchWithCrnti counter which counts
3189 num of PDCCH scrambled with CRNTI for CRNTI Based contention resolution */
3190 Bool isSrGrant; /*!< This is to aid Counter to check number of successful SR Grants SR_RACH_STATS*/
3191 Bool txModeTransCmplt; /*!< Flag to confirm TM Mode
3192 transition completion*/
3193 CmTimer txModeTransTmr; /*!< Timer for TxMode transition Completion */
3194 #ifdef RGSCH_SPS_STATS
3195 CmLteTimingInfo lastSpsLcBoRptTime;
3196 CmLteTimingInfo lastSpsLcSchedTime;
3198 uint64_t absTimeSched;
3200 uint8_t refreshOffset; /*!< UE referesh offset */
3201 uint8_t csgMmbrSta; /*!< CSG Membership status configured */
3203 TSL2UeStatsCb *tenbStats; /*!< UE Stats Holder */
3205 CmLListCp flowCntrlLcLst;/*!< Dedicated Downlink logical channels in UE for Flow Control*/
3206 CmLList ueFlowCntrlEnt;/*!<UE lnk to the flow control Lst*/
3208 RgSchLcgCb *repLcg;/*!<representative LCG of the UE in UL */
3209 #ifdef XEON_SPECIFIC_CHANGES
3210 CmLteTimingInfo riRecpTime; /*! To idnentify Ri wrap arround during PUSCH and
3211 PUCCH reception filling */
3214 TknUInt32 sCellDeactTmrVal; /* !< SCell Deactivation Timer Value */
3215 uint8_t f1bCsAVal; /* !< A value mentioned in table 10.12.2.1-1 of 36.213. This will tell
3216 the max number of tbs possible based on TM mode of each configured
3217 scell. It is used only for F1B with channel selection*/
3220 RgSchSCellN1ResCb n1PucchF1bResCb; /*!< N1 resouurce Cb for F1b Channel selection */
3221 RgSchSCellN3ResCb n3PucchResCb;
3222 RgrSchFrmt1b3TypEnum uciFrmtTyp; /*!< Store value of format1bcs or format3.It
3223 is updated from upper layer*/
3225 uint8_t numSCells; /* !< number of configured SCells */
3226 uint8_t cellIdToCellIdxMap[CM_LTE_MAX_CELLS]; /*!< Mapping info of Cell Id to Cell Idx */
3228 RgSchUeCellInfo *cellInfo[CM_LTE_MAX_CELLS]; /*!< DL Sec Cell Information */
3230 RgSchUePCqiCb *nPCqiCb; /*!< Pointer to Periodic Cqi CB for which next CQI is expected*/
3231 RgSchUePCqiCb *nPRiCb; /*!< Pointer to Periodic Cqi CB for which next RI is expected*/
3233 uint8_t remBoCnt; /*!< count of occurence when BO is not fullfilled
3235 uint8_t *zeroBoCnt; /*!< pointer of count of occurence when BO is
3238 Bool isScellExplicitDeAct; /*!< TRUE when SCELL deactivation timer is Infinity/Not configured */
3239 Bool allocCmnUlPdcch; /*!< If this flag is TRUE, allocate PDCCH from Common
3241 uint8_t simulAckNackCQIFormat3; /* !< Flag for simultanious A/N and CQI on PUCCH Format 3 */
3243 RgSchUeDciSize dciSize; /*!< DCI Sizes */
3244 RgrAccessStratumRls accessStratumRls; /*!< UE Release */
3246 RgSchPfsStats pfsStats;
3249 Bool isEmtcUe; /*!< flag to check EMTC UE */
3250 Void *emtcUeInfo; /*!< EMTC UE specific information */
3253 RgSch5gtfUeCb ue5gtfCb; /*!< UECb of 5gtf */
3260 * Configuration Information for Upper SAPs at RGU, CRG and RGR interfaces.
3262 typedef struct rgSchUpSapCfgInfo
3264 Pst sapPst; /*!< Post info associated with SAP */
3265 SpId spId; /*!< SpId associated with SAP */
3266 SuId suId; /*!< SuId associated with SAP */
3271 * Configuration Information for Lower SAP at TFU interface.
3273 typedef struct rgSchLowSapCfgInfo
3275 Pst sapPst; /*!< Post info associated with SAP */
3276 SpId spId; /*!< SpId associated with SAP */
3277 SuId suId; /*!< SuId associated with SAP */
3278 TmrCfg bndTmr; /*!< Bind Timer Value */
3279 }RgSchLowSapCfgInfo;
3283 * Control Block structure for Upper SAPs at RGU, CRG and RGR interfaces.
3285 typedef struct rgSchUpSapCb
3287 RgSchUpSapCfgInfo sapCfg; /*!< Configuration info */
3288 RgSapSta sapSta; /*!< SAP Status */
3289 RgSchCellCb *cell; /*!< Cell associated with this sap */
3294 * Control Block structure for Lower SAP at TFU interface.
3296 typedef struct rgSchLowSapCb
3298 RgSchLowSapCfgInfo sapCfg; /*!< SAP configuration info */
3299 RgSapSta sapSta; /*!< SAP Status */
3300 uint8_t numBndRetries; /*!< Number of Bind Retries */
3301 RgSchCellCb *cell; /*!< Cell associated with this SAP */
3302 CmTimer tmrBlk; /*!< Timer Block associated with this SAP */
3307 * structure holding Layer Manager Response information cached from control
3310 typedef struct rgSchLmResponse
3312 TranId transId; /*!< Transaction ID */
3313 Resp response; /*!< Response */
3316 /* XXX: Below structures added for PDCCH Order req for RACH Module */
3317 typedef enum sfnEnum
3324 typedef struct rgSchConfigIdx
3326 uint8_t configurationIndex; /* New RGR Cell cfg */
3328 uint8_t subframes[10];
3331 typedef struct rgSchRapId
3334 CmLteTimingInfo lastAllocPRACHMaskIdx;
3337 typedef struct pdcchOrderCfg
3339 RgSchRapId rapIds[RGSCH_MAX_RAPID];
3340 RgSchConfigIdx configIdx;
3345 @brief Measurement Gap related information per cell. */
3346 typedef struct rgSchMeasGapCb
3348 CmLListCp gapPrd40Q[RG_SCH_CMN_MEAS_GAPPRD40]; /*!< Measurement Gap queue
3349 for UEs with 40 ms gap period */
3350 CmLListCp gapPrd80Q[RG_SCH_CMN_MEAS_GAPPRD80]; /*!< Measurement Gap queue
3351 for UEs with 80 ms gap period */
3355 @brief ACK-NACK repetition related information per cell. */
3356 typedef struct rgSchAckNakRepCb
3359 CmLListCp ackNakRepQ[2*RGSCH_NUM_SUB_FRAMES]; /*!< ACK NACK repetition queue */
3361 CmLListCp ackNakRepQ[RGSCH_NUM_SUB_FRAMES]; /*!< ACK NACK repetition queue */
3366 * Structure holding RBG information for the BW
3368 typedef struct rgSchBwRbgInfo
3370 uint8_t numRbs; /*!< Total number of RBs for which information is
3372 uint8_t numRbgs; /*!< Number of RBGs for the BW (rounded off to the
3373 closest RBG number */
3374 uint8_t rbgSize; /*!< RBG size */
3375 uint8_t lastRbgSize; /*!< Last RBG size : in number of RBs */
3376 uint8_t rbgSubsetSize[RG_SCH_NUM_RATYPE1_SUBSETS]; /*!< RBG Subset 0,1,2,3
3377 sizes: number of RBs
3380 /** @brief This structure is one element of the DRX Queue mainted per cell.
3381 * @details It is composed of a list of linked lists, each tracking a specific
3382 * timer as defined in the DRX functionality.
3384 typedef struct rgSchDrxQ
3386 CmLListCp onDurationQ; /*!< Tracks the start of onDuration Timer. */
3387 CmLListCp onDurationExpQ; /*!< Tracks the Expiry of onDuration Timer. */
3388 CmLListCp inActvTmrQ; /*!< Tracks the Expiry of drx-InactivityTimer. */
3389 CmLListCp harqRTTQ; /*!< Tracks the Expiry of HARQ RTT timer. */
3390 CmLListCp harqRetxQ; /*!< Tracks the Expiry of Re-Transmission timer. */
3391 CmLListCp shortCycleQ; /*!< Tracks the Expiry of DRX Short Cycle. */
3393 CmLListCp ulHarqRTTQ; /*!< Tracks the Expiry of HARQ RTT timer for Uplink transmission */
3394 CmLListCp ulHarqRetxQ; /*!< Tracks the Expiry of Re-Transmission timer for UPLINK. */
3398 /** @brief This structure is part of the RgSchCellCb structure and stores the
3399 * DRX related information for a cell.dfort
3400 * The cell contains a single Array of queues, wherein UEs shall be enqueued
3401 * based on configured offset and periodicity and timer values. Please note the
3402 * same queue is utilized for Long and Short DRX cycle.
3404 typedef struct rgSchDRXCellCb
3406 RgSchDrxQ drxQ[RG_SCH_MAX_DRXQ_SIZE ]; /*!< Maintains all
3407 the timers for DRX. */
3408 Bool delInUlScan; /*!< Maintains whether elements
3409 from timer queue should be
3410 removed while scanning in
3415 /* Added for SI Enhancement*/
3419 typedef struct sib1Info
3428 typedef struct siInfo
3437 @brief SI Configuration information per cell. */
3438 typedef struct rgSchSiCfgInfo
3440 Buffer *mib; /*!< MIB PDU */
3441 RgSchSib1Info sib1Info;
3442 RgSchSiInfo siInfo[RGR_MAX_NUM_SI];
3446 @brief SI Context information per SI. */
3447 typedef struct rgSchSiCtx
3449 uint8_t siId; /*!< SI Id */
3450 CmLteTimingInfo timeToTx; /*!< Time at which the SI for this SI
3451 context need to be scheduled.*/
3452 CmLteTimingInfo maxTimeToTx;/*!< Max Time to TX for this SI */
3453 uint8_t retxCntRem; /*!< SI retransmit count remaining */
3454 uint16_t i; /*!< Value used to calculate the Riv of SI */
3455 Bool warningSiFlag; /*!< Flag for Warning SI */
3460 @brief Contains each PDU of Warning SI */
3461 typedef struct warningSiPdu
3472 @brief warningSi node having multiple segments */
3473 typedef struct warningSiSeg
3475 /* ccpu00136659: CMAS ETWS design changes */
3476 CmLListCp segLstCp; /*!< LList of Warning SI Segments */
3477 RgSchWarningSiPdu pduNode[RGR_MAX_WARNING_SI_SEG];
3478 RgrCfgTransId transId; /*!< Transaction Id */
3482 @brief Warning SI structure per Cell. */
3483 typedef struct warningSi
3485 /* ccpu00136659: CMAS ETWS design changes */
3486 RgSchWarningSiSeg warningSiMsg;
3487 /*!< Each node contains LList of si segments. */
3488 uint8_t siId; /*!< Warning SI ID */
3489 uint8_t idx; /*!< Warning SI Idx in RgSchWarningSiInfo */
3490 }RgSchWarningSiInfo;
3493 @brief SI Array Structure for each SI */
3494 typedef struct siArray
3496 Bool isWarningSi; /*!< Flag for Warning SI */
3497 void *si; /*!< Pointer for SI */
3501 @brief SI Control BLock per Cell. */
3502 typedef struct rgSchSiCb
3504 Bool siBitMask; /*!< Bitmask to indicate which of the SI
3505 components have been updated */
3506 RgSchSiCtx siCtx; /*!< SI Context */
3507 RgrSiCfg newSiCfg; /*!< New SI Configuration, valid if the
3508 respective bit is set in bit mask
3510 S8 inWindow; /*!< counter to indicate the start of a new
3511 si window. Reset to siWinLen at the start
3513 RgSchSiCfgInfo crntSiInfo;/*!< PDUs for current modification period */
3514 RgSchSiCfgInfo newSiInfo; /*!< PDUs for next modification period */
3515 RgSchWarningSiInfo warningSi[RGR_MAX_NUM_WARNING_SI];
3516 /*!< PDUs for warning SI */
3517 RgSchSiArray siArray[RGR_MAX_NUM_SI]; /*!< Pointers for SIs */
3519 #endif /*RGR_SI_SCH */
3521 typedef struct rgSchBiInfo
3523 uint16_t prevBiTime; /*!< Previous BI Value in ms Calculated and
3524 Sent in Previous Response */
3525 CmLteTimingInfo biTime; /*!< Time at which previous BI sent */
3529 typedef struct rgSchQciPrbUsage
3531 uint8_t qci; /*!< QCI of the Logical Channel */
3532 uint32_t dlTotPrbUsed; /*!< total PRB used for DL within one interval*/
3533 uint32_t ulTotPrbUsed; /*!< total PRB used for UL within one interval*/
3538 typedef struct rgSchPrbUsage
3540 Bool prbRprtEnabld; /*!< reporting is enabled or not*/
3541 uint16_t rprtPeriod; /*!< reporting interval to send PRB usage to the
3542 RRM (in subframes)*/
3543 CmLteTimingInfo startTime; /*!< timing information when the summation is
3544 started in terms of sfn and subframe*/
3546 RgSchQciPrbUsage qciPrbRpts[RGINF_MAX_GBR_QCI_REPORTS]; /*!< toal
3552 /* LTE_ADV_FLAG_REMOVED_START */
3553 /* @brief Enum to differntiate the subframe */
3554 /* Donot change the value of enum member - code dependency */
3555 typedef enum rgSchAbsSfEnum
3557 RG_SCH_ABS_ENABLED_NONABS_SF = 0, /* ABS is enabled and ABS SF */
3558 RG_SCH_ABS_ENABLED_ABS_SF = 1, /* ABS is enabled and non ABS SF */
3559 RG_SCH_ABS_DISABLED = 2 /* ABS is disabled */
3562 /* @brief Control block for LTE Advance Feature */
3563 typedef struct rgSchLteAdvFeatureCb
3565 RgrSfrConfig sfrCfg; /*!< Configuration of SFR feature */
3566 RgrDsfrConfig dsfrCfg; /*!< Configuration of DSFR feature */
3567 RgrAbsConfig absCfg; /*!< Configuration of ABS feature */
3568 RgSchAbsSfEnum absDlSfInfo; /*< Flag to indicate current scheduling
3569 DL subframe is ABS subframe or not */
3570 uint8_t absPatternDlIdx;
3571 uint32_t absLoadTtiCnt;
3572 uint32_t absLoadInfo[RGR_ABS_PATTERN_LEN];
3573 } RgSchLteAdvFeatureCb;
3574 /* LTE_ADV_FLAG_REMOVED_END */
3576 /*<! baseSize is the fixed sizes of the respective DCIs. If no other size
3577 * mentioned, baseSize is the final size of the DCI */
3578 typedef struct rgSchCellDciSize {
3580 uint8_t baseSize[TFU_DCI_FORMAT_6_2+1]; /*!< Fixed Base Size of DCI 0/1/1A/6-0A/6-1A/6-0B/6-1B/6-2 without any adjustment */
3581 uint8_t size[TFU_DCI_FORMAT_6_2+1]; /*!< DCI 0/1A final size in common Search Space and not scrambled by C-RNTI
3582 DCi 3/3A final sizes
3583 DCI 2/2A final sizes
3584 DCI 6-0A/6-0B final sizes
3585 DCI 6-1A/6-1B final sizes
3586 DCI 6-2 final sizes */
3588 uint8_t baseSize[TFU_DCI_FORMAT_1A+1]; /*!< Fixed Base Size of DCI 0/1/1A without any adjustment */
3589 uint8_t size[TFU_DCI_FORMAT_3A+1]; /*!< DCI 0/1A final size in common Search Space and not scrambled by C-RNTI
3590 DCi 3/3A final sizes
3591 DCI 2/2A final sizes */
3593 uint8_t dci0HopSize; /*!< DCI 0 Hop Size */
3598 * Cell level measurements
3600 typedef struct rgSchMeasCb
3602 uint32_t dlTpt; /*!< DL Bytes served in a fixed time PERIOD */
3603 uint32_t dlBytesCnt; /*!< DL Bytes served from start of this time period */
3604 uint32_t ulTpt; /*!< DL Bytes served in a fixed time PERIOD */
3605 uint32_t ulBytesCnt; /*!< UL Bytes served from start of this time period */
3610 * Cell level thresholds
3612 typedef struct rgSchThrsldsCb
3619 * CPU Overload control state info
3621 typedef struct rgSchCpuOvrLdCntrlCb
3623 uint8_t cpuOvrLdIns;
3626 uint8_t dlNxtIndxDecNumUeTti; /*!< Total DL num UE per TTI reduction instruction applied */
3627 uint8_t ulNxtIndxDecNumUeTti; /*!< Total UL num UE per TTI reduction instruction applied */
3628 uint8_t maxUeNewTxPerTti[10]; /*!< list of subframe where DL num UE per TTI reduction applied */
3629 uint8_t maxUeNewRxPerTti[10]; /*!< list of subframe where UL num UE per TTI reduction applied */
3630 }RgSchCpuOvrLdCntrlCb;
3634 * Cell Control block per cell.
3638 CmLteCellId cellId; /*!< Cell ID */
3639 Inst instIdx; /*!< Index of the scheduler instance */
3640 Inst macInst; /*!< Index of the MAC instance */
3641 uint8_t schTickDelta; /* 4UE_TTI_DELTA */
3642 Bool stopSiSch; /*!< If TRUE Bcch,Pcch Scheduling is not done */
3643 uint8_t stopDlSch; /*!< If TRUE DL scheduling is not done */
3644 Bool stopUlSch; /*!< If TRUE UL scheduling is not done */
3645 Bool isDlDataAllwd; /*!< FALSE for Uplink subframes */
3646 RgrDlHqCfg dlHqCfg; /*!< HARQ related configuration */
3647 RgSchRntiDb rntiDb; /*!< RNTIs DB: range of rntis to be managed by MAC */
3650 Void *sch; /*!< Common Scheduler specific information */
3651 RgSchdApis *apis; /*!< Common Scheduler APIs */
3654 Bool isCpUlExtend; /*!< Cyclic prefix : TRUE-extended/FALSE-normal */
3655 Bool isCpDlExtend; /*!< Cyclic prefix : TRUE-extended/FALSE-normal */
3656 uint8_t numTxAntPorts; /*!< Number of Tx antenna ports */
3657 RgrBwCfg bwCfg; /*!< Bandwidth Configuration */
3658 uint8_t pbchRbStart; /*!< Indicates the Start RB of the center 6 RBs of DL BW */
3659 uint8_t pbchRbEnd; /*!< Indicates the Start RB of the center 6 RBs of DL BW */
3660 uint8_t numCellRSPerSf; /*!< Indicates the number of cell specific
3661 Reference symbols in a Subframe */
3662 RgrPhichCfg phichCfg; /*!< PHICH Config Information */
3663 RgrPucchCfg pucchCfg; /*!< PUCCH Config Information */
3664 RgSchSrsCfg srsCfg; /*!< SRS Config Information */
3665 RgrRachCfg rachCfg; /*!< RACH Configuration */
3667 RgSchBiInfo biInfo; /* CELL wide BI Info */
3668 RgrSiCfg siCfg; /*!< SI Configuration */
3669 /* Added support for SPS*/
3671 RgrPuschCfg puschCfg; /*!< Cell-specific hopping configuration */
3673 RgrPreambleSetCfg macPreambleSet; /*!< Range of PDCCH Order Preamble Id's
3674 to be managed by MAC */
3675 CmLteTimingInfo crntTime; /*!< Current frame and subframe number for
3677 CmLteTimingInfo hiDci0Time; /*!< Scheduling SFN, SF for HIDCI-0 */
3678 CmLteTimingInfo hqRlsTime; /*!< SFN, SF for HARQ clean up */
3679 CmLteTimingInfo dlSfRlsTime; /*!< SFN, SF for Downlink subframe clean up*/
3680 CmLteTimingInfo dlDciTime; /*!< SFN, SF for DL control Request */
3681 CmLteTimingInfo rcpReqTime; /*!< SFN, SF for UL reception Request */
3682 RgSchCfgCfb rgCfgInfo; /*!< Control block for configuration related
3684 uint8_t ulCcchId; /*!< LcId for uplink CCCH */
3685 uint8_t dlCcchId; /*!< LcId for downlink CCCH */
3686 RgSchClcDlLcCb cmnLcCb[RGSCH_MAX_CMN_LC_CB]; /*!< BCCH/PCCH logical channel control block */
3687 CmHashListCp ueLst; /*!< Hash list of UE control
3688 blocks: RgSchUeCb */
3689 /* Added support for SPS*/
3691 CmHashListCp spsUeLst; /*!< Hash list of UE control blocks
3692 for spsRnti: RgSchUeCb */
3693 #endif /* LTEMAC_SPS */
3694 CmLListCp taUeLst; /*!< List of ueCbs having ta */
3696 /* CR timer changes*/
3697 CmLListCp ccchSduUeLst; /*!< List of ueCbs scheduled for CCCH
3699 CmLListCp contResGrdTmrLst; /*!< List of raCbs whose Guard timer is
3701 CmLListCp contResTmrLst; /*!< List of raCbs whose contention
3702 resolution timer is running */
3704 RgSchRaInfoCb raInfo; /*!< Random access related information for
3706 CmLListCp pdcchLst; /*!< List of free RgSchPdcch structures */
3708 CmTqType tq[RGSCH_UE_TQ_SIZE];
3709 uint8_t crntSfIdx; /*!< Current index for allocation */
3711 RgInfSfAlloc sfAllocArr[RGSCH_SF_ALLOC_SIZE]; /*!< Subframe Allocation
3712 info to be sent to MAC */
3714 RgInfSfAlloc sfAllocArr[RGSCH_NUM_SUB_FRAMES]; /*!< Subframe Allocation
3715 info to be sent to MAC */
3717 RgInfRlsHqInfo rlsHqArr[RGSCH_NUM_SUB_FRAMES]; /*!< Harq Release
3718 info to be sent to MAC */
3719 uint8_t crntHqIdx; /*!< Current index for Harq release info */
3720 RgSchLowSapCb *tfuSap;
3721 /* Added for sending TTI tick to RRM */
3722 #if (defined(RGR_RRM_TICK) || defined(RGR_CQI_REPT))
3723 RgSchUpSapCb *rgrSap; /*!< Pointer to the cell's RGR SAP
3726 RgSchUpSapCb *rgmSap; /*!< Pointer to the cell's RGM SAP
3729 uint8_t rrmTtiIndPrd; /*!< Periodicity of TTI indication from
3730 MAC towards RGR user. Range [1-255]. A
3731 value of 1 means one tick per System
3732 Frame and 2 means one tick per 2 System
3733 Frame, and so on. */
3735 PdcchOrderCfg pdcchOrdCfg;
3736 RgSchMeasGapCb measGapCb; /*!< Measurement gap control block */
3737 RgSchAckNakRepCb ackNakRepCb; /*!< Ack-Nack Repetition control block */
3739 RgSchTddRachRspLst *rachRspLst; /*!< List of awaiting RACH responses */
3740 uint8_t numDlSubfrms; /*!< Number of DL subframes */
3741 uint8_t ulDlCfgIdx; /*!< UL-DL Configuration Index */
3742 uint8_t ackNackFdbkArrSize; /*!< Maximum Number of Ack/Nack
3743 feedback information to be
3745 S8 tddHqSfnCycle; /*!< Counter to keep track of the
3746 number of sfn,sf wrap arounds.
3747 This is used for UL harq
3748 determination. It ranges from
3749 0 to num Ul Harq-1 */
3750 RgSchTddSplSubfrmCfg splSubfrmCfg; /*!< Special subframe configuration */
3751 Bool isDwPtsCnted; /*!< is DwPts counted as PDCCH sf */
3752 RgSchTddNpValTbl rgSchTddNpValTbl;/*!< Mapping between 'Np' and 'p' */
3753 RgSchDlSf **subFrms; /*!< DL subframes list */
3754 RgSchTddPrachRscInfo prachCfg; /*!< PRACH configuration */
3755 CmHashListCp ueTfuPendLst; /*!< Used for HARQ Ack/Nack
3757 /* TODO:: change to array of pointers */
3758 CmLListCp n1ResUsedLst[RGSCH_NUM_SUB_FRAMES]; /*!< For storing the used
3759 N1 resources for scell in case of F1B CS */
3761 RgSchDlSf *subFrms[RGSCH_NUM_DL_slotS];
3764 RgSchDynCfiCb dynCfiCb; /*!< Dynamic CFI control block */
3765 /* Changes for MIMO feature addition */
3766 uint8_t noOfRbgs; /*!< Number of RBGs for this bw */
3767 uint8_t rbgSize; /*!< RBG Size */
3768 /* Added support for SPS*/
3770 RgSchBwRbgInfo dlBwRbgInfo; /*!< RBG information for the configured
3772 RgrSpsCellCfg spsCellCfg; /*!< SPS specific configuration for
3774 RgSchBwRbgInfo spsBwRbgInfo; /*!< RBG information for configured maximum
3778 RgSchRaPreambles raPrmbs; /*!< Different received RA preambles */
3779 RgSchAvgPrbDl avgPrbDl; /*!< PRB usage in percentage per QCI for DL */
3780 RgSchAvgPrbUl avgPrbUl; /*!< PRB usage in percentage per QCI for UL */
3781 CmLListCp l2mList; /*!< List of all L2M requests
3783 RgSchQciCb qciArray[LRG_MAX_QCI]; /*!< Array of all qci's configured
3785 Bool sndL2Meas; /*!< send L2 Meas in case no le mesurement timer is running*/
3786 RgSchTbCnt dlUlTbCnt; /*!< Count of DL and UL TB transmitteed and Faulty
3787 TB (for wich NACK is received) */
3788 #endif /* LTE_L2_MEAS */
3789 uint8_t ulAvailBw; /*!< Total Uplink band width available
3790 for this sub frame */
3792 RgSchPerPucchCb pCqiSrsSrLst[RG_SCH_PCQI_SRS_SR_TRINS_SIZE];
3793 /*!< To store next active Periodic CQI/PMI, RI,
3794 SRS and SR Transmission instance */
3795 #endif /* TFU_UPGRADE */
3798 CmLListCp hdFddLst; /*!< Half Duplex FDD UE list */
3799 #endif /* LTEMAC_HDFDD */
3800 RgSchDRXCellCb *drxCb; /*!< Pointer to the DRX control block shall be
3801 allocated at the time of cell configuration. */
3802 /* Added for SI Enhancement*/
3804 RgSchSiCb siCb; /*!< SI Control Block */
3805 #endif /*RGR_SI_SCH */
3806 RgSchPrbUsage prbUsage; /*!< measures average PRB usage for configured interval*/
3807 uint16_t t300TmrVal; /*!< t300Timer value configured in Frames */
3808 /* LTE_ADV_FLAG_REMOVED_START */
3809 TknStrOSXL rntpAggrInfo; /*!< RNTP Info */
3810 RgrLoadInfReqInfo loadInfReqInfo; /*!< Consists startRb & endRb
3811 location for which CC to
3812 be raised to P-High */
3813 RgSchLteAdvFeatureCb lteAdvCb; /*!< Control block for LTE Adv
3815 /* LTE_ADV_FLAG_REMOVED_END */
3816 uint32_t dlNumUeSchedPerTti[RG_MAX_NUM_UE_PER_TTI]; /*!<DL mUe/Tti histograms*/
3817 uint32_t ulNumUeSchedPerTti[RG_MAX_NUM_UE_PER_TTI]; /*!<UL mUe/Tti histograms*/
3818 Bool overLoadBackOffEnab; /*!< Overload Rach Backoff enable/disable */
3819 uint8_t overLoadBackOffval; /*!< Overload Rach BackOff value */
3820 uint8_t refreshUeCnt[RGSCH_MAX_REFRESH_OFFSET]; /*! To maintain number of UE refreshed per subframe */
3821 uint8_t minDlResNonCsg; /*!< Minimum DL resources reserved for Non CSG UEs */
3822 uint8_t minUlResNonCsg; /*!< Minimum UL resources reserved for CSG UEs */
3823 Bool isAutoCfgModeEnb; /*!< Indicates Auto config of TM mode is enabled or
3824 disabled. True - Enabled, False - Disabled */
3825 CmLListCp lcMonitorLst; /*LC Lst used for flow cntrl */
3826 uint32_t prbCnt; /*!<PRB usage in flow control interval*/
3827 uint32_t maxPrbCnt; /*!<Max PRB cnt after which Flow Cntrl
3829 RgSchCpuOvrLdCntrlCb cpuOvrLdCntrl; /*!< CPU Overload control state info */
3830 RgSchMeasCb measurements; /*!< Cell level measurements */
3831 RgSchThrsldsCb thresholds; /*!< Cell level thresholds */
3833 TSL2CellStatsCb *tenbStats; /*!< CELL Stats Holder */
3835 RgSchCellDciSize dciSize;
3837 CmLListCp sCellUeLst; /*!< List of UEs for which this cell is secondary cell*/
3838 Bool isPucchFormat3Sptd;
3846 /* TODO:: Below members need to be moved
3847 * to emtc specific files and have void *
3851 RgSchRntiDb emtcRntiDb; /*!< RNTIs DB: range of rntis to be managed by MAC */
3853 RgSchIotResMngmtCb resMngmt;
3855 RgSch5gtfCellCb cell5gtfCb;
3861 * Structure holding LTE MAC's General Configuration information.
3863 typedef struct rgSchGenCb
3865 uint8_t tmrRes; /*!< Timer resolution */
3866 RgSchLmResponse *bndCfmResp; /*!< Respones value for Bind Confirm */
3867 RgSchLmResponse ustaResp; /*!< Respones value for Alarms */
3868 uint8_t startCellId; /*!< Starting Cell Id */
3870 Bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
3871 of RLC control BO and SRB BO on
3872 PCell. val 0 means don't force*/
3873 Bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
3878 /* 5GTF Dynamic TDD Specific defines */
3880 /* Number of subframes information managed */
3881 #define RG_SCH_DYNTDD_MAX_SFINFO 20
3883 /* Subframe Types */
3884 #define RG_SCH_DYNTDD_NOTDEF 0
3885 #define RG_SCH_DYNTDD_DLC_DLD 1
3886 #define RG_SCH_DYNTDD_DLC_DLD_ULC 2
3887 #define RG_SCH_DYNTDD_DLC_ULD 3
3888 #define RG_SCH_DYNTDD_DLC_ULD_ULC 4
3890 /* Mark the subframe */
3891 #define RG_SCH_DYN_TDD_MARKTYPE(_dynTdd, _sfi, _state)\
3893 (_dynTdd)->sfInfo[(_sfi)].sfType = _state;\
3896 /* Mark sfi as UL Subframe */
3897 #define RG_SCH_DYN_TDD_MARKTYPE_UL(_dynTdd, _sfi)\
3899 RG_SCH_DYN_TDD_MARKTYPE(_dynTdd, _sfi, RG_SCH_DYNTDD_DLC_ULD);\
3902 /* Mark sfi as DL Subframe */
3903 #define RG_SCH_DYN_TDD_MARKTYPE_DL(_dynTdd, _sfi)\
3905 RG_SCH_DYN_TDD_MARKTYPE(_dynTdd, _sfi, RG_SCH_DYNTDD_DLC_DLD);\
3908 /* Get SFI and SFN from given time and subframe offset */
3909 #define RG_SCH_DYN_TDD_GET_SFIDX(_sfi, _crntSfIdx, _offset)\
3910 (_sfi) = (_crntSfIdx + _offset)% RG_SCH_DYNTDD_MAX_SFINFO
3913 @brief Dynamic TDD subframe type. */
3915 typedef struct rgSchDynTddSfType
3917 uint8_t sfType; /*!< 0= NOT Defined
3918 1= DL Cntrl + DL Data
3919 2= DL Cntrl + DL Data + UL Cntrl
3920 3= DL Cntrl + UL Data
3921 4= DL Cntrl + UL Data + UL Cntrl
3926 @brief Dynamic TDD control Block */
3928 typedef struct rgSchDynTddCb
3930 Bool isDynTddEnbld; /*!< Is dynamic TDD enabled */
3931 uint8_t crntDTddSfIdx; /*!< Pivot Index corresponding
3932 cell's current subframe */
3933 RgSchDynTddSfType sfInfo[RG_SCH_DYNTDD_MAX_SFINFO];
3940 * Global Control block for LTE-MAC.
3944 TskInit rgSchInit; /*!< Task Init info */
3945 RgSchGenCb genCfg; /*!< General Config info */
3946 uint8_t numSaps; /*!< Num RGR Saps = Num TFU Saps */
3947 RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
3948 RgSchLowSapCb *tfuSap; /*!< TFU SAP Control Block */
3949 RgSchUpSapCb *rgmSap; /*!< TFU SAP Control Block */
3950 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
3951 CmTqType tmrTq[RGSCH_TQ_SIZE]; /*!< Timer Task Queue */
3952 uint8_t rgSchDlDelta; /* 4UE_TTI_DELTA */
3953 uint8_t rgSchCmnDlDelta;
3954 uint8_t rgSchUlDelta;
3955 RgSchCellCb *cells[CM_LTE_MAX_CELLS]; /* Array to store cellCb ptr */
3956 RgrSchedEnbCfg rgrSchedEnbCfg; /*!< eNB level RR/PFS Config */
3957 Void *rgSchEnbPfsDl; /*!< eNB level PFS DL Block */
3961 RgSchDynTddCb rgSchDynTdd; /*!< Dynamic TDD Control Block */
3965 /* Declaration for scheduler control blocks */
3966 RgSchCb rgSchCb[RGSCH_MAX_INST];
3969 * Data structures for RAM
3974 * Random Access Req Info to be stored in cellCb.
3976 typedef struct rgSchRaReqInfo
3978 CmLList raReqLstEnt; /*!< Linked list entity for RaReq List */
3979 CmLteTimingInfo timingInfo; /*!< RACHO: Time of RaReq Reception */
3980 RgTfuRaReqInfo raReq; /*!< Random Access Request Information */
3981 RgSchUeCb *ue; /*!< UECB if RAP ID is a dedicated one */
3985 * @enum rgSchRaState
3986 * Enumeration of random access states.
3988 typedef enum rgSchRaState
3990 RGSCH_RA_MSG3_PENDING, /*!< Msg3 reception pending */
3991 RGSCH_RA_MSG4_PENDING, /*!< Msg4 transmission pending */
3992 RGSCH_RA_MSG4_DONE /*!< Msg4 transmission successful */
3997 * Control block for Random Access.
4001 CmLList raCbLnk; /*!< To link to the raCb list */
4002 CmLList schdLnk; /*!< To link raCb to the "to be scheduled"
4004 CmLteRnti tmpCrnti; /*!< Temporary C-RNTI */
4005 CmLteTimingInfo timingInfo; /*!< Timing information */
4006 RgSchRntiLnk *rntiLnk; /*!< Link to RNTI for raCb */
4007 RgSchRaState raState; /*!< Random access state */
4010 uint32_t bo; /*!< Buffer occupancy for CCCH */
4011 } dlCcchInfo; /*!< Params for DL CCCH */
4012 uint8_t msg3HqProcId; /*!< Msg3 Harq Process ID */
4013 /*ccpu00128820 - DEL - msg3HqProcRef is delete for Msg3 alloc double delete issue*/
4014 RgSchUlHqProcCb msg3HqProc; /*!< msg3HqProcRef points to this initially */
4015 RgSchUeCb *ue; /*!< NULL initially */
4016 Bool toDel; /*!< To delete this RaCb after msg4 reject */
4017 TknUInt8 phr; /*!< To store the PHR, if received along with
4019 CmLList rspLnk; /*!< Used to link RACB to a frame for resp */
4020 uint8_t rapId; /*!< RAP ID */
4021 TknUInt16 ta; /*!< Timing Adjustment */
4022 RgSchUlGrnt msg3Grnt; /*!< Msg3 grant as given by the UL Sched */
4023 uint32_t y[RGSCH_NUM_SUB_FRAMES]; /*!< y values using tmpCrnti by DLSCHED */
4024 RgSchDlHqEnt *dlHqE; /*!< DL HARQ module */
4025 uint8_t ccchCqi; /*!< DL Cqi obtained from RaReq and Used for CCCH */
4026 RgSchDlRbAlloc rbAllocInfo; /*!< RB Allocation Info for MSG4 Trans/Retrans */
4027 /* PHR handling for MSG3 */
4028 CmLteTimingInfo msg3AllocTime; /*!< Allocation time for msg3 grant */
4030 /* CR timer changes*/
4031 CmLList contResTmrLnk; /*!< To link raCb to the
4032 Guard Timer/Contention Resolution timer list*/
4033 CmLteTimingInfo expiryTime; /*!< Expiry time for Guard/Contention
4034 Resolution timers */
4036 uint32_t ccchSduBo; /*!<To store CCCH SDU BO if it arrives while
4037 ContRes CE is transmitting or retransmitting*/
4040 Bool isEmtcRaCb; /*!< 0 - Normal, 1 - EMTC */
4047 * Carries the Error information.
4051 uint8_t errType; /*!< Error Type */
4052 uint16_t errCause; /*!< Cause of Error */
4055 /* Global Variables */
4059 uint8_t rgSchTddSpsDlMaxRetxTbl[RGSCH_MAX_TDD_UL_DL_CFG];
4061 typedef uint8_t RgSchTddUlDlSubfrmTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4062 RgSchTddUlDlSubfrmTbl rgSchTddUlDlSubfrmTbl;
4064 typedef struct rgSchTddSplSubfrmInfo RgSchTddSplSubfrmInfoTbl[RGSCH_MAX_TDD_SPL_SUBFRM_CFG];
4065 RgSchTddSplSubfrmInfoTbl rgSchTddSplSubfrmInfoTbl;
4067 typedef struct rgSchTddDlAscSetIdxK RgSchTddDlAscSetIdxKTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4068 RgSchTddDlAscSetIdxKTbl rgSchTddDlAscSetIdxKTbl;
4070 RgSchTddDlAscSetIdxKTbl rgSchTddDlHqPucchResCalTbl;
4072 typedef uint8_t RgSchTddPhichMValTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4073 RgSchTddPhichMValTbl rgSchTddPhichMValTbl;
4075 typedef uint8_t RgSchTddKPhichTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4076 RgSchTddKPhichTbl rgSchTddKPhichTbl;
4078 typedef RgSchTddPhichOffInfo RgSchTddPhichOffInfoTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4080 typedef uint8_t RgSchTddUlAscIdxKDashTbl[RGSCH_MAX_TDD_UL_DL_CFG-1][RGSCH_NUM_SUB_FRAMES];
4081 RgSchTddUlAscIdxKDashTbl rgSchTddUlAscIdxKDashTbl;
4084 typedef uint8_t RgSchTddInvDlAscSetIdxTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4085 RgSchTddInvDlAscSetIdxTbl rgSchTddInvDlAscSetIdxTbl;
4088 typedef uint8_t RgSchTddPuschTxKTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4089 RgSchTddPuschTxKTbl rgSchTddPuschTxKTbl;
4091 typedef uint8_t RgSchTddUlNumHarqProcTbl[RGSCH_MAX_TDD_UL_DL_CFG];
4092 RgSchTddUlNumHarqProcTbl rgSchTddUlNumHarqProcTbl;
4094 typedef uint8_t RgSchTddDlNumHarqProcTbl[RGSCH_MAX_TDD_UL_DL_CFG];
4095 RgSchTddDlNumHarqProcTbl rgSchTddDlNumHarqProcTbl;
4097 /* Number of ACK/NACK Feedback to be stored based on UL-DL Configuration Index */
4098 typedef uint8_t RgSchTddANFdbkMapTbl[RGSCH_MAX_TDD_UL_DL_CFG];
4099 RgSchTddANFdbkMapTbl rgSchTddANFdbkMapTbl;
4101 /* Number of UL subframes */
4102 typedef RgSchTddSubfrmInfo RgSchTddMaxUlSubfrmTbl[RGSCH_MAX_TDD_UL_DL_CFG];
4103 RgSchTddMaxUlSubfrmTbl rgSchTddMaxUlSubfrmTbl;
4105 /* Number of UL subframes */
4106 typedef uint8_t RgSchTddNumUlSubfrmTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4107 RgSchTddNumUlSubfrmTbl rgSchTddNumUlSubfrmTbl;
4109 /* Number of low UL subframes Indices*/
4110 typedef uint8_t RgSchTddLowUlSubfrmIdxTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4111 RgSchTddLowUlSubfrmIdxTbl rgSchTddLowUlSubfrmIdxTbl;
4113 /* Number of high UL subframes Indices*/
4114 typedef uint8_t RgSchTddHighUlSubfrmIdxTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4115 RgSchTddHighUlSubfrmIdxTbl rgSchTddHighUlSubfrmIdxTbl;
4117 /* Number of low DL subframes Indices*/
4118 typedef uint8_t RgSchTddLowDlSubfrmIdxTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4119 RgSchTddLowDlSubfrmIdxTbl rgSchTddLowDlSubfrmIdxTbl;
4121 /* Number of high DL subframes Indices*/
4122 typedef uint8_t RgSchTddHighDlSubfrmIdxTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4123 RgSchTddHighDlSubfrmIdxTbl rgSchTddHighDlSubfrmIdxTbl;
4125 /* Number of DL subframes and Special subframes with DwPTS */
4126 typedef uint8_t RgSchTddNumDlSubfrmTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4127 RgSchTddNumDlSubfrmTbl rgSchTddNumDlSubfrmTbl;
4129 /* Number of DL subframes and Special subframes with DwPTS */
4130 typedef RgSchTddSubfrmInfo RgSchTddMaxDlSubfrmTbl[RGSCH_MAX_TDD_UL_DL_CFG];
4131 RgSchTddMaxDlSubfrmTbl rgSchTddMaxDlSubfrmTbl;
4133 typedef uint8_t RgSchTddMsg3SubfrmTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4134 RgSchTddMsg3SubfrmTbl rgSchTddMsg3SubfrmTbl;
4136 typedef RgSchTddMsg3SubfrmTbl RgSchTddSpsUlRsrvTbl;
4137 RgSchTddMsg3SubfrmTbl rgSchTddSpsUlRsrvTbl;
4140 typedef uint8_t RgSchTddRlsDlSubfrmTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4141 RgSchTddRlsDlSubfrmTbl rgSchTddRlsDlSubfrmTbl;
4144 uint8_t rgSchTddPucchTxTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4148 RgSchCellCb* rgSchUtlGetCellCb ARGS((
4153 Void rgSCHSCellDlUeReset ARGS((
4158 Void rgSCHSCellDlLcCfg ARGS((
4164 Void rgSCHSCellDlLcDel ARGS((
4170 Void rgSCHSCellDlDedBoUpd ARGS((
4176 Void rgSCHSCellSchdActDeactCe ARGS((
4178 RgSchDlHqTbCb *tbInfo
4181 Void rgSCHSCellAddToActDeactLst ARGS((
4186 Void rgSCHSCellRmvFrmActLst ARGS((
4190 S16 rgSCHSCellIsActive ARGS((
4197 Void rgSCHSCellHndlFdbkInd ARGS((
4198 RgSchDlHqProcCb *hqP,
4201 Bool maxHqRetxReached
4204 Void rgSCHSCellDeactTmrExpry ARGS((
4205 RgSchUeCellInfo *sCell
4208 S16 rgSCHSCellTrigActDeact ARGS((
4215 S16 rgSCHSCellDelUe ARGS((
4216 RgSchCellCb *cellCb,
4220 Bool rgSCHIsActvReqd ARGS ((
4225 Void rgSCHSCellSelectAndActDeAct ARGS ((
4231 S16 rgSCHSCellPCqiCfg ARGS((
4232 RgSchCellCb *priCellCb,
4233 RgSchCellCb *secCellCb,
4235 RgrUePrdDlCqiCfg *cqiCfg,
4236 CmLteUeCategory ueCat,
4240 Void rgSCHUtlSndUeSCellDel2Mac ARGS ((
4245 uint8_t rgSCHUtlGetMaxTbSupp ARGS ((
4250 /* APIs exposed by TMR module */
4251 Void rgSCHTmrStartTmr ARGS((
4252 RgSchCellCb *cellCb,
4257 Void rgSCHTmrStopTmr ARGS((
4258 RgSchCellCb *cellCb,
4262 Void rgSCHTmrProcTmr ARGS((
4266 /* APIs exposed by TOM */
4268 S16 rgSCHTomRaReqInd ARGS((
4270 TfuRaReqIndInfo *raReqInd));
4272 S16 rgSCHTomPucchDeltaPwrInd ARGS((
4274 TfuPucchDeltaPwrIndInfo *pucchDeltaPwr));
4276 S16 rgSCHTomUlCqiInd ARGS((
4278 TfuUlCqiIndInfo *ulCqiInd));
4280 S16 rgSCHTomSrInd ARGS((
4282 TfuSrIndInfo *srInd));
4284 S16 rgSCHTomDlCqiInd ARGS((
4286 TfuDlCqiIndInfo *dlCqiInd));
4287 /* Added changes of TFU_UPGRADE */
4289 S16 rgSCHTomRawCqiInd ARGS
4292 TfuRawCqiIndInfo* rawCqiInd
4295 S16 rgSCHTomSrsInd ARGS
4298 TfuSrsIndInfo* srsInd
4303 S16 rgSCHTomDoaInd ARGS((
4305 TfuDoaIndInfo *doaInd));
4306 S16 rgSCHTomCrcInd ARGS((
4308 TfuCrcIndInfo *crcInd));
4310 S16 rgSCHTomHarqAckInd ARGS((
4312 TfuHqIndInfo *harqAckInd));
4314 S16 rgSCHTomTimingAdvInd ARGS((
4316 TfuTimingAdvIndInfo *timingAdvInd));
4320 * APIs exposed by LMM
4322 S16 rgSCHLmmStartTmr ARGS ((Inst instId, S16 tmrEvnt,
4323 uint32_t tmrVal, PTR cb));
4324 S16 rgSCHLmmStopTmr ARGS((Inst instId, S16 tmrEvnt, PTR cb));
4325 S16 rgSCHLmmTmrExpiry ARGS((PTR cb, S16 tmrEvnt));
4326 /* This function invokes a Control Confirmation to the LM from scheduler. */
4327 S16 rgSCHLmmBndCfm ARGS((Pst *pst, SuId suId, uint8_t status));
4328 S16 schActvTmr ARGS((Ent entity, Inst inst));
4329 /* To send a Unsolicited Status Indication to Layer Manager */
4330 S16 rgSCHLmmStaInd ARGS((Inst instId, uint16_t category, uint16_t event,
4331 uint16_t cause, RgUstaDgn *dgn));
4332 S16 schActvTsk ARGS((Pst *pst, Buffer *mBuf));
4333 Void SchFillCfmPst ARGS((Pst *reqPst,Pst *cfmPst,RgMngmt *cfm));
4334 uint16_t SchInstCfg ARGS((RgCfg *cfg, Inst inst));
4335 Void printSchCellInfo ARGS((Void));
4336 Void rgSCHLmmGenCntrl ARGS((RgMngmt *cntrl,RgMngmt *cfm,Pst *cfmPst));
4337 Void rgSCHLmmSapCntrl ARGS((RgMngmt *cntrl,RgMngmt *cfm,Pst *cfmPst));
4340 S16 rgSCHCfgEmtcCellCfg ARGS ((RgSchCellCb *cell,
4341 RgrEmtcCellCfg *emtcCellCfg));
4342 S16 rgSCHCfgVldtRgrEmtcCellCfg ARGS ((RgrCellCfg *cellCfg));
4344 Void rgSchTomTtiEmtcSched ARGS((RgSchCellCb *cell));
4345 S16 rgSCHCfgVldtEmtcUeCfg ARGS((RgSchCellCb *cell, RgrUeEmtcCfg *emtcUeCfg));
4346 S16 rgSCHUtlUpdUeEmtcInfo ARGS((RgSchCellCb *cell, RgrUeCfg *ueCfg, RgSchUeCb *ueCb));
4347 S16 rgSCHEmtcCellDel ARGS((RgSchCellCb *cell));
4348 S16 rgSCHEmtcUeDel ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
4349 S16 rgSCHEmtcHdFddUeCfg ARGS((RgSchCellCb *cellCb,RgSchUeCb *ueCb,Bool hdFddEnbl));
4353 * APIs exposed by CFG module
4355 S16 rgSCHCfgVldtRgrCellCfg ARGS((Inst inst, RgrCellCfg *cellCfg,
4356 RgSchCellCb *cell, RgSchErrInfo *errInfo));
4357 S16 rgSCHCfgRgrCellCfg ARGS((RgSchCb *instCb, SpId spId,
4358 RgrCellCfg *cellCfg, RgSchErrInfo *errInfo));
4359 S16 rgSCHCfgRgrSchedEnbCfg ARGS((Inst inst, SpId spId,
4360 RgrSchedEnbCfg *schedEnbCfg, RgSchErrInfo *errInfo));
4361 S16 rgSCHCfgVldtRgrCellRecfg ARGS((Inst inst, RgrCellRecfg *cellRecfg,
4362 RgSchCellCb **cell, RgSchErrInfo *errInfo));
4363 S16 rgSCHCfgRgrCellRecfg ARGS((RgSchCellCb *cell, RgrCellRecfg *cellRecfg,
4364 RgSchErrInfo *errInfo));
4366 S16 rgSCHCfgVldtRgrUeCfg ARGS((Inst inst, RgrUeCfg *ueCfg,
4367 RgSchCellCb **cell, RgSchErrInfo *errInfo));
4368 S16 rgSCHCfgRgrUeCfg ARGS((RgSchCellCb *cell, RgrUeCfg *ueCfg,
4369 RgSchErrInfo *errInfo));
4370 S16 rgSCHCfgVldtRgrUeRecfg ARGS((Inst inst, RgrUeRecfg *ueRecfg,
4371 RgSchCellCb **cell, RgSchUeCb **ue, RgSchErrInfo *errInfo));
4372 S16 rgSCHCfgRgrUeRecfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgrUeRecfg
4373 *ueRecfg, RgSchErrInfo *errInfo));
4375 S16 rgSCHCfgVldtRgrLcCfg ARGS((Inst inst, RgrLchCfg *lcCfg,
4376 RgSchCellCb **cell, RgSchUeCb **ue, RgSchErrInfo *errInfo));
4377 S16 rgSCHCfgRgrLchCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4378 RgrLchCfg *lcCfg, RgSchErrInfo *errInfo));
4379 S16 rgSCHCfgVldtRgrLchRecfg ARGS((Inst inst, RgrLchRecfg *lcRecfg,
4380 RgSchCellCb **cell, RgSchUeCb **ue, RgSchDlLcCb **dlLc,
4381 RgSchErrInfo *errInfo));
4382 S16 rgSCHCfgRgrLchRecfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4383 RgSchDlLcCb *dlLc, RgrLchRecfg *lcRecfg, RgSchErrInfo *errInfo));
4385 S16 rgSCHCfgVldtRgrLcgRecfg ARGS ((Inst inst,RgrLcgRecfg *lcgRecfg,
4386 RgSchCellCb *cell,RgSchUeCb **ue,RgSchErrInfo *errInfo ));
4387 S16 rgSCHCfgVldtRgrLcgCfg ARGS ((Inst inst,RgrLcgCfg *lcgCfg,
4388 RgSchCellCb **cell,RgSchUeCb **ue,RgSchErrInfo *errInfo ));
4389 S16 rgSCHCfgVldtRgrSchedEnbCfg ARGS ((Inst inst,
4390 RgrSchedEnbCfg *schedEnbCfg, RgSchErrInfo *errInfo ));
4391 S16 rgSCHCfgRgrLcgCfg ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
4392 RgrLcgCfg *lcgCfg,RgSchErrInfo *errInfo ));
4393 S16 rgSCHCfgRgrLcgRecfg ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
4394 RgrLcgRecfg *lcgRecfg,RgSchErrInfo *errInfo));
4396 S16 rgSCHCfgVldtRgrUeReset ARGS((Inst inst, RgrRst *reset, RgSchCellCb *cell,
4397 RgSchUeCb **ue,RgSchErrInfo *errInfo));
4398 S16 rgSCHCfgRgrUeReset ARGS((RgSchCellCb *cell,RgSchUeCb *ue,RgrRst *reset,
4399 RgSchErrInfo *errInfo));
4401 S16 rgSCHCfgRgrCellDel ARGS((RgSchCellCb *cell, RgrDel *cellDelInfo,
4402 RgSchErrInfo *errInfo));
4403 S16 rgSCHCfgRgrUeDel ARGS((RgSchCellCb *cell, RgrDel *ueDelInfo,
4404 RgSchErrInfo *errInfo));
4405 S16 rgSCHCfgRgrLcDel ARGS((RgSchCellCb *cell, RgrDel *lcDelInfo,
4406 RgSchErrInfo *errInfo));
4407 S16 rgSCHCfgRgrLcgDel ARGS ((RgSchCellCb *cell,RgrDel *lcDelInfo,
4408 RgSchErrInfo *errInfo));
4409 Void rgSCHCfgFreeCellCb ARGS((RgSchCellCb *cell));
4410 /* Added for SI Enhancement*/
4412 S16 rgSCHCfgVldtRgrSiCfg ARGS(( Inst inst, RgrSiCfgReqInfo *siCfg,
4413 RgSchCellCb *cell, RgSchErrInfo *errInfo));
4414 S16 rgSCHGomHndlSiCfg ARGS(( Region reg, Pool pool,
4415 RgSchCb *instCb, SpId spId,
4416 RgrCfgTransId transId, RgrSiCfgReqInfo *cfgReqInfo));
4417 S16 rgSCHUtlRgrSiCfgCfm ARGS ((Inst inst, SpId spId,
4418 RgrCfgTransId transId,uint8_t status));
4420 S16 rgSCHGomHndlWarningSiCfg ARGS(( Region reg, Pool pool,
4421 RgSchCb *instCb, SpId spId, RgrCfgTransId transId,
4422 RgrWarningSiCfgReqInfo *warningSiCfgReqInfo));
4424 Void rgSCHGomHndlWarningSiStopReq ARGS(( Region reg, Pool pool,
4425 RgSchCb *instCb, uint8_t siId,
4426 RgrCfgTransId transId, SpId spId));
4428 S16 rgSCHUtlRgrWarningSiCfgCfm ARGS ((Inst inst, SpId spId, uint8_t siId,
4429 RgrCfgTransId transId,uint8_t status));
4430 #endif /* RGR_SI_SCH */
4431 /* LTE_ADV_FLAG_REMOVED_START */
4432 S16 rgSchDSFRRntpInfoInit ARGS ((TknStrOSXL *rntpPtr, RgSchCellCb *cell,
4434 S16 rgSchDSFRRntpInfoFree ARGS ((TknStrOSXL *rntpPtr, RgSchCellCb *cell,
4436 S16 rgSchUpdtRNTPInfo ARGS ((RgSchCellCb *cell, RgSchDlSf *sf,
4437 RgrLoadInfReqInfo *loadInfReq));
4438 S16 rgSCHCfgVldtRgrLoadInf ARGS(( Inst inst, RgrLoadInfReqInfo *loadInfReq,
4439 RgSchCellCb *cell, RgSchErrInfo *errInfo));
4440 S16 rgSCHGomHndlLoadInf ARGS(( Region reg, Pool pool,
4441 RgSchCb *instCb, SpId spId,
4442 RgrCfgTransId transId, RgrLoadInfReqInfo *cfgReqInfo));
4443 /* LTE_ADV_FLAG_REMOVED_END */
4446 * APIs exposed by GOM module
4448 S16 rgSCHGomHndlCfg ARGS((Pst *pst, RgSchCb *instCb,
4449 RgrCfgTransId transId, RgrCfgReqInfo *cfgReqInfo));
4450 S16 rgSCHGomTtiHndlr ARGS((RgSchCellCb *cell, SpId spId));
4454 * APIs exposed by RAM module
4456 S16 rgSCHRamVldtUeCfg ARGS((
4460 S16 rgSCHRamProcRaReq ARGS((uint8_t raReqCnt, RgSchCellCb *cell, CmLteRnti raRnti,
4461 TfuRachInfo *raReqInd,
4462 CmLteTimingInfo timingInfo,
4464 RgSchErrInfo *err));
4465 S16 rgSCHRamCreateRaCb ARGS((RgSchCellCb *cell, RgSchRaCb **raCb,
4466 RgSchErrInfo *err));
4467 S16 rgSCHRamRgrUeCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4468 RgSchRaCb *raCb, RgSchErrInfo *err));
4469 S16 rgSCHRamProcMsg3 ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4470 RgSchRaCb *raCb, RgInfUeDatInd *pdu,
4471 RgSchErrInfo *err));
4472 S16 rgSCHRamUpdtBo ARGS((RgSchCellCb *cell, RgSchRaCb *raCb,
4473 RgInfCmnBoRpt *staRsp));
4474 S16 rgSCHRamMsg3DatInd ARGS((RgSchRaCb *raCb));
4475 S16 rgSCHRamMsg3FailureInd ARGS((RgSchRaCb *raCb));
4476 S16 rgSCHRamMsg4FdbkInd ARGS((RgSchRaCb *raCb));
4477 S16 rgSCHRamMsg4Done ARGS((RgSchCellCb *cell, RgSchRaCb *raCb));
4478 S16 rgSCHRamDelRaCb ARGS((RgSchCellCb *cell, RgSchRaCb *raCb,
4480 S16 rgSCHRamFreeCell ARGS((RgSchCellCb *cell));
4481 S16 rgSCHRamTtiHndlr ARGS((RgSchCellCb *cell));
4482 Void rgSCHCmnUlSch ARGS((RgSchCellCb *cell));
4483 Void rgSCHCmnDlCommonChSch ARGS ((RgSchCellCb *cell));
4485 /* Added periodic BSR timer */
4486 S16 rgSCHCmnBsrTmrExpry ARGS(( RgSchUeCb *ueCb));
4489 S16 rgSCHRamDelRaReq ARGS((RgSchCellCb *cell,
4490 CmLteTimingInfo timingInfo,
4493 S16 rgSCHRamAddToRaInfoSchdLst(RgSchCellCb *cell, RgSchRaCb *raCb);
4495 S16 rgSCHRamRmvFrmRaInfoSchdLst(RgSchCellCb *cell, RgSchRaCb *raCb);
4497 /* APIs exposed by UHM */
4498 /* Added for Uplink Adaptive retransmission */
4499 Void rgSCHUhmNonadapRetx ARGS((RgSchUlHqProcCb *hqProc));
4500 S16 rgSCHUhmHqEntInit ARGS ((RgSchCellCb *cellCb, RgSchUeCb *ueCb));
4501 #ifndef MAC_SCH_STATS
4502 Void rgSCHUhmProcDatInd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4503 CmLteTimingInfo frm));
4504 #else /* MAC_SCH_STATS */
4505 Void rgSCHUhmProcDatInd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4506 CmLteTimingInfo frm, uint8_t cqi));
4508 Void rgSCHUhmProcMsg3DatInd ARGS((RgSchUlHqProcCb *hqProc));
4509 Void rgSCHUhmProcMsg3Failure ARGS((RgSchUlHqProcCb *hqProc));
4510 #ifndef MAC_SCH_STATS
4511 Void rgSCHUhmProcHqFailure ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4512 CmLteTimingInfo frm, TknUInt8 rv));
4513 #else /* MAC_SCH_STATS */
4514 Void rgSCHUhmProcHqFailure ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4515 CmLteTimingInfo frm, TknUInt8 rv, uint8_t cqi));
4517 RgSchUlHqProcCb* rgSCHUhmGetUlHqProc ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4519 Void rgSCHUhmNewTx ARGS((RgSchUlHqProcCb *hqProc, uint8_t maxHqRetx,
4520 RgSchUlAlloc *alloc));
4521 Void rgSCHUhmFreeProc ARGS((RgSchUlHqProcCb *hqProc,
4522 RgSchCellCb *cell));
4523 Void rgSCHUhmRetx ARGS((RgSchUlHqProcCb *hqProc, RgSchUlAlloc *alloc));
4524 Void rgSCHUhmRgrUeCfg ARGS(( RgSchCellCb *cellCb, RgSchUeCb *ueCb,
4526 Void rgSCHUhmRgrUeRecfg ARGS(( RgSchCellCb *cellCb, RgSchUeCb *ueCb,
4527 RgrUeRecfg *ueRecfg));
4528 Void rgSCHUhmFreeUe ARGS(( RgSchCellCb *cellCb, RgUeUlHqCb *hqEnt));
4529 S16 rgSCHUhmAppendPhich ARGS(( RgSchCellCb *cellCb,
4530 CmLteTimingInfo frm, uint8_t idx));
4532 /* APIs exposed by DBM */
4533 S16 rgSCHDbmInitCell ARGS((RgSchCellCb *cellCb));
4534 S16 rgSCHDbmDeInitUeCbLst ARGS(( RgSchCellCb *cellCb));
4536 S16 rgSCHDbmDeInitUeTfuPendLst ARGS(( RgSchCellCb *cellCb));
4538 S16 rgSCHDbmInsUeCb ARGS(( RgSchCellCb *cellCb, RgSchUeCb *ueCb));
4539 RgSchUeCb* rgSCHDbmGetUeCb ARGS(( RgSchCellCb *cellCb, CmLteRnti ueId));
4540 RgSchUeCb* rgSCHDbmGetNextUeCb ( RgSchCellCb *cellCb, RgSchUeCb *ueCb);
4541 S16 rgSCHDbmDelUeCb ARGS(( RgSchCellCb *cellCb, RgSchUeCb *ueCb));
4543 S16 rgSCHDbmDelL2MUe ARGS(( RgSchCellCb *cellCb, RgSchUeCb *ueCb));
4545 S16 rgSCHDbmInitUe ARGS((RgSchUeCb *ueCb));
4546 Void rgSCHDbmInsDlDedLcCb ARGS((RgSchUeCb *ueCb, RgSchDlLcCb *dlLcCb));
4547 Void rgSCHDbmDelDlDedLcCb ARGS((RgSchUeCb *ueCb, RgSchDlLcCb *dlLcCb));
4548 RgSchDlLcCb* rgSCHDbmGetDlDedLcCb ARGS(( RgSchUeCb *ueCb, CmLteLcId idx));
4549 RgSchDlLcCb* rgSCHDbmGetFirstDlDedLcCb ARGS((RgSchUeCb *ueCbb));
4550 RgSchDlLcCb* rgSCHDbmGetNextDlDedLcCb ARGS((RgSchUeCb *ueCb, RgSchDlLcCb *lcCb));
4551 RgSchClcDlLcCb* rgSCHDbmGetCmnLcCb ARGS(( RgSchCellCb *cellCb, CmLteLcId lcId));
4552 RgSchClcDlLcCb* rgSCHDbmGetBcchOnBch ARGS(( RgSchCellCb *cellCb ));
4553 RgSchClcDlLcCb* rgSCHDbmGetFirstBcchOnDlsch ARGS(( RgSchCellCb *cellCb));
4554 RgSchClcDlLcCb* rgSCHDbmGetSecondBcchOnDlsch ARGS(( RgSchCellCb *cellCb));
4555 RgSchClcDlLcCb* rgSCHDbmGetPcch ARGS(( RgSchCellCb *cellCb));
4556 Void rgSCHDbmInsBcchOnBch ARGS(( RgSchCellCb *cellCb, RgSchClcDlLcCb *cmnDlLcCb));
4557 Void rgSCHDbmInsBcchOnDlsch ARGS(( RgSchCellCb *cellCb, RgSchClcDlLcCb *cmnDlLcCb));
4558 Void rgSCHDbmInsPcch ARGS(( RgSchCellCb *cellCb, RgSchClcDlLcCb *cmnDlLcCb));
4560 Void rgSCHDbmInitCmnLcBoLst ARGS(( RgSchClcDlLcCb *cmnDlLcCb));
4561 Void rgSCHDbmInsCmnLcBoRpt ARGS(( RgSchClcDlLcCb *cmnDlLcCb,
4562 RgSchClcBoRpt *cmnBoRpt));
4563 RgSchRaCb* rgSCHDbmGetRaCb ARGS(( RgSchCellCb *cellCb, CmLteRnti key));
4564 Void rgSCHDbmInsCrntRgrCfgElem ARGS(( RgSchCellCb *cellCb,
4565 RgSchCfgElem *cfgElem));
4566 Void rgSCHDbmInsPndngRgrCfgElem ARGS(( RgSchCellCb *cellCb,
4567 RgSchCfgElem *cfgElem));
4568 RgSchCfgElem* rgSCHDbmGetNextCrntRgrCfgElem ARGS(( RgSchCellCb *cellCb,
4569 RgSchCfgElem *cfgElem));
4570 RgSchCfgElem* rgSCHDbmGetNextPndngRgrCfgElem ARGS(( RgSchCellCb *cellCb,
4571 RgSchCfgElem *cfgElem));
4572 RgSchCfgElem* rgSCHDbmGetPndngRgrCfgElemByKey ARGS(( RgSchCellCb *cellCb,
4573 CmLteTimingInfo key));
4574 RgSchCfgElem* rgSCHDbmDelCrntRgrCfgElem ARGS(( RgSchCellCb *cellCb,
4575 RgSchCfgElem *cfgElem));
4576 RgSchCfgElem* rgSCHDbmDelPndngRgrCfgElem ARGS(( RgSchCellCb *cellCb,
4577 RgSchCfgElem *cfgElem));
4579 S16 rgSCHDbmRntiDbInit ARGS(( RgSchCellCb *cellCb, uint16_t rntiStart, uint16_t maxRntis));
4580 Void rgSCHDbmRntiDbDeInit ARGS(( RgSchCellCb *cellCb));
4581 RgSchRntiLnk* rgSCHDbmGetRnti ARGS(( RgSchCellCb *cellCb));
4582 Void rgSCHDbmRlsRnti ARGS(( RgSchCellCb *cellCb, RgSchRntiLnk *rntiLnk));
4583 /* Fix : syed HO UE does not have a valid ue->rntiLnk */
4584 Void rgSCHUtlIndRntiRls2Mac ARGS(( RgSchCellCb *cell, CmLteRnti rnti,
4585 Bool ueIdChng, CmLteRnti newRnti));
4587 /*rg008.201 - Added support for SPS*/
4589 S16 rgSCHDbmDeInitSpsUeCbLst ARGS((RgSchCellCb *cellCb));
4590 S16 rgSCHDbmInsSpsUeCb ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb));
4591 RgSchUeCb* rgSCHDbmGetSpsUeCb ARGS((RgSchCellCb *cellCb, CmLteRnti ueId));
4592 RgSchUeCb* rgSCHDbmGetNextSpsUeCb ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb));
4593 S16 rgSCHDbmDelSpsUeCb ARGS((RgSchCellCb *cellCb,RgSchUeCb *ueCb));
4594 #endif /* LTEMAC_SPS */
4600 S16 rgSchL2mMeasReq ARGS ((
4602 LrgSchMeasReqInfo *measInfo,
4604 S16 RgSchMacL2MeasSend ARGS
4607 RgInfL2MeasSndReq *measInfo
4610 S16 RgSchMacL2MeasStop ARGS
4613 RgInfL2MeasStopReq *measInfo
4615 #endif /* LTE_L2_MEAS */
4619 /* LTE_ADV_FLAG_REMOVED_START */
4620 S16 rgSchSFRTotalPoolInit ARGS((RgSchCellCb *cell, RgSchDlSf *sf));
4621 /* LTE_ADV_FLAG_REMOVED_END */
4622 Void rgSCHDhmHqPAdd2FreeLst ARGS (( RgSchDlHqProcCb *hqP));
4623 Void rgSCHDhmHqPAdd2InUseLst ARGS (( RgSchDlHqProcCb *hqP));
4624 Void rgSCHDhmHqPDelFrmFreeLst ARGS (( RgSchDlHqProcCb *hqP));
4625 Void rgSCHDhmHqPDelFrmInUseLst ARGS (( RgSchDlHqProcCb *hqP));
4627 RgSchDlHqEnt *rgSCHDhmHqEntInit ARGS((RgSchCellCb *cell));
4628 S16 rgSCHDhmGetAvlHqProc ARGS((RgSchCellCb *cell, RgSchUeCb *ue, CmLteTimingInfo timingInfo,
4629 RgSchDlHqProcCb **hqP));
4630 Void rgSCHDhmHqRetx ARGS((RgSchDlHqEnt *hqE, CmLteTimingInfo timeInfo,
4631 RgSchDlHqProcCb *hqP));
4632 RgSchDlHqProcCb * rgSCHDhmLastSchedHqProc ARGS((RgSchDlHqEnt *hqE));
4633 /* CR timer changes*/
4634 S16 rgSCHDhmGetCcchSduHqProc ARGS((RgSchUeCb *ueCb, CmLteTimingInfo timeInfo,
4635 RgSchDlHqProcCb **hqP));
4636 S16 rgSCHDhmGetMsg4HqProc ARGS((RgSchRaCb *raCb, CmLteTimingInfo timeInfo));
4637 Void rgSCHDhmRlsHqProc ARGS((RgSchDlHqProcCb *hqP));
4638 /* ccpu00118350 : Correcting NDI manipulation of Harq */
4639 Void rgSCHDhmRlsHqpTb ARGS((RgSchDlHqProcCb *hqP, uint8_t tbIdx, Bool togNdi));
4640 Void rgSCHUtlDlHqPTbAddToTx ARGS((RgSchDlSf *subFrm,
4641 RgSchDlHqProcCb *hqP, uint8_t tbIdx ));
4642 Void rgSCHDhmHqTbRetx ARGS(( RgSchDlHqEnt *hqE,
4643 CmLteTimingInfo timingInfo, RgSchDlHqProcCb *hqP, uint8_t tbIdx));
4644 Void rgSCHUtlDlHqPTbAddToTx ARGS((RgSchDlSf *subFrm,
4645 RgSchDlHqProcCb *hqP, uint8_t tbIdx ));
4646 Void rgSCHDhmHqTbRetx ARGS(( RgSchDlHqEnt *hqE,
4647 CmLteTimingInfo timingInfo, RgSchDlHqProcCb *hqP, uint8_t tbIdx));
4649 S16 rgSCHDhmGetHqProcFrmId ARGS((RgSchCellCb *cell, RgSchUeCb *ue, uint8_t idx,
4650 RgSchDlHqProcCb **hqP));
4652 /* Changes for MIMO feature addition */
4653 Void rgSCHDhmSchdTa ARGS((RgSchUeCb *ueCb, RgSchDlHqTbCb *tbInfo));
4654 S16 rgSCHDhmHqFdbkInd ARGS((Void *cb, uint8_t cbType, RgSchCellCb *cellCb,
4655 CmLteTimingInfo timingInfo, RgTfuHqInfo *fdbk, RgInfRlsHqInfo
4656 *rlsHqBufs,RgSchErrInfo *err));
4658 S16 rgSCHDhmEmtcHqFdbkInd ARGS((Void *cb, uint8_t cbType, RgSchCellCb *cellCb,
4659 CmLteTimingInfo timingInfo, RgTfuHqInfo *fdbk, RgInfRlsHqInfo
4660 *rlsHqBufs,RgSchErrInfo *err));
4661 S16 rgSCHUtlAddToResLst
4668 S16 rgSCHDhmPrcFdbkForTb(RgSchCellCb *cell,RgSchUeCb *ue,
4669 RgSchDlHqProcCb *hqP,RgSchDlSf *sf,Bool isMsg4,
4670 uint16_t rnti,uint8_t tbCnt,CmLteTimingInfo timingInfo, uint8_t isAck,
4671 RgInfRlsHqInfo *rlsHqBufs,RgSchErrInfo *err
4674 Void rgSCHDhmRgrUeCfg ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb,
4675 RgrUeCfg *ueCfg, RgSchErrInfo *err));
4676 Void rgSCHDhmRgrUeRecfg ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb,
4677 RgrUeRecfg *ueCfg, RgSchErrInfo *err));
4678 Void rgSCHDhmRgrCellCfg ARGS((RgSchCellCb *cellCb, RgrCellCfg *cellCfg,
4679 RgSchErrInfo *err));
4680 Void rgSCHDhmRgrCellRecfg ARGS((RgSchCellCb *cellCb, RgrCellRecfg
4681 *cellRecfg, RgSchErrInfo *err));
4682 Void rgSCHDhmFreeUe ARGS((RgSchUeCb *ueCb));
4683 Void rgSCHDhmUpdTa ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb, uint8_t ta));
4684 Void rgSCHDhmProcTAExp ARGS((RgSchUeCb *ue));
4685 /* Changes for MIMO feature addition */
4686 S16 rgSCHDhmAddLcData ARGS((Inst inst, RgSchLchAllocInfo *lchData,
4687 RgSchDlHqTbCb *tbInfo));
4688 S16 rgSCHDhmRlsDlsfHqProc ARGS((RgSchCellCb *cellCb, CmLteTimingInfo
4692 S16 rgSCHDhmTddRlsSubFrm ARGS((RgSchCellCb *cell, CmLteTimingInfo uciTimingInfo));
4693 S16 rgSCHCfgVldtTddDrxCycCfg ARGS((RgSchCellCb *cell, uint16_t drxCycle,
4694 uint8_t onDurTmr, uint16_t offSet));
4696 /* Added support for SPS*/
4698 S16 rgSCHDhmGetHqProcFrmId ARGS((
4702 RgSchDlHqProcCb **hqP
4704 #endif /* LTEMAC_SPS */
4705 /* Freeing up the HARQ proc blocked for
4706 * indefinite time in case of Retx */
4707 S16 rgSCHDhmDlRetxAllocFail ARGS((
4709 RgSchDlHqProcCb *proc
4711 /* MS_WORKAROUND for ccpu00122893 temp fix Incorrect HqProc release was done instead of
4712 * a Harq Entity reset. Fixing the same */
4713 Void rgSCHDhmHqEntReset ARGS((
4716 /* Measurement GAP and ACK NACK */
4718 S16 rgSCHMeasGapANRepUeCfg ARGS((
4723 S16 rgSCHMeasGapANRepUeRecfg ARGS((
4728 /* ccpu00133470- Added extra argument to identify UE DEL*/
4729 Void rgSCHMeasGapANRepUeDel ARGS((
4734 S16 rgSCHMeasGapANRepTtiHndl ARGS((
4737 S16 rgSCHMeasGapANRepGetDlInactvUe ARGS((
4739 CmLListCp *dlInactvUeLst
4741 S16 rgSCHMeasGapANRepGetUlInactvUe ARGS((
4743 CmLListCp *ulInactvUeLst
4745 Void rgSCHMeasGapANRepDlInactvTmrExpry ARGS((
4749 Void rgSCHMeasGapANRepUlInactvTmrExpry ARGS((
4753 Void rgSCHMeasGapANRepTmrExpry ARGS((
4756 Void rgSCHAckNakRepTmrExpry ARGS((
4759 Void rgSCHAckNakRepSndHqFbkRcpReq ARGS((
4762 CmLteTimingInfo timingInfo));
4764 Void rgSCHAckNakRepAddToQ ARGS((
4766 RgSchDlSf *crntDlSf));
4772 Void rgSCHUtlHdlCrcInd ARGS((
4775 CmLteTimingInfo timingInfo
4780 S16 rgSCHUtlValidateMeasReq ARGS ((RgSchCellCb *cellCb,
4781 LrgSchMeasReqInfo *schL2MeasInfo,
4784 S16 rgSchL2mSndCfm ARGS((Pst *pst,
4785 RgSchL2MeasCb *measCb,
4786 LrgSchMeasReqInfo *measInfo,
4789 S16 rgSchFillL2MeasCfm ARGS((
4791 RgSchL2MeasCb *measCb,
4792 LrgSchMeasCfmInfo *cfm,
4795 Void rgSchL2mFillCfmPst ARGS((
4798 LrgSchMeasReqInfo *measInfo
4800 S16 rgSCHL2Meas ARGS((
4802 uint8_t isCalrCrcInd
4804 #endif /* LTE_L2_MEAS */
4805 /* Added changes of TFU_UPGRADE */
4807 F64 rgSCHUtlPower ARGS
4813 uint32_t rgSCHUtlParse ARGS
4821 uint8_t rgSCHUtlFindDist ARGS
4827 Bool rgSCHUtlPdcchAvail ARGS((RgSchCellCb *cell, RgSchPdcchInfo
4828 *pdcchInfo, CmLteAggrLvl aggrLvl, RgSchPdcch **pdcch));
4829 Void rgSCHUtlPdcchPut ARGS((RgSchCellCb *cell, RgSchPdcchInfo *pdcchInfo,
4830 RgSchPdcch *pdcch));
4832 /* Changes for passing iPhich at TFU interface*/
4833 S16 rgSCHUtlAddPhich ARGS((RgSchCellCb *cellCb, CmLteTimingInfo frm,
4834 uint8_t hqFeedBack, uint8_t nDmrs, uint8_t rbStart, uint8_t iPhich));
4836 S16 rgSCHUtlAddPhich ARGS((RgSchCellCb *cellCb, CmLteTimingInfo frm,
4837 uint8_t hqFeedBack, uint8_t nDmrs, uint8_t rbStart,Bool isForMsg3));
4839 RgSchDlSf* rgSCHUtlSubFrmGet ARGS((RgSchCellCb *cell,
4840 CmLteTimingInfo frm));
4841 Void rgSCHUtlSubFrmPut ARGS((RgSchCellCb *cell, RgSchDlSf *sf));
4842 uint8_t rgSCHUtlLog32bitNbase2 ARGS((uint32_t n));
4843 /* Added support for SPS*/
4847 RgSchDlHqProcCb * rgSCHDhmSpsDlGetHqProc ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4848 CmLteTimingInfo timingInfo));
4851 uint8_t rgSCHUtlCalcNCce ARGS((uint8_t bw, RgrPhichNg ng, uint8_t cfi, uint8_t mPhich,
4852 uint8_t numAntna, Bool isEcp));
4854 uint8_t rgSCHUtlCalcNCce ARGS((uint8_t bw, RgrPhichNg ng, uint8_t cfi, uint8_t numAntna, Bool
4858 /* Changes for passing iPhich at TFU interface*/
4859 S16 rgSCHUtlGetPhichInfo ARGS((RgSchUlHqProcCb *hqProc, uint8_t *rbStartRef,
4860 uint8_t *nDmrsRef, uint8_t *iPhich));
4862 S16 rgSCHUtlGetPhichInfo ARGS((RgSchUlHqProcCb *hqProc, uint8_t *rbStartRef,
4863 uint8_t *nDmrsRef));
4865 /* Added changes of TFU_UPGRADE */
4867 /* To include the length and ModOrder in DataRecp Req. */
4868 /* Updating NDI and HARQ proc Id */
4869 S16 rgSCHUtlAllocRcptInfo ARGS((RgSchUlAlloc *alloc, CmLteRnti *rnti,
4870 uint8_t *iMcsRef, uint8_t *rbStartRef, uint8_t *numRbRef, uint8_t *rvRef, uint16_t *size,
4871 TfuModScheme *modType,Bool *isRtx,
4876 S16 rgSCHUtlAllocRcptInfo ARGS((
4878 RgSchUlAlloc *alloc,
4879 CmLteTimingInfo *timeInfo,
4880 TfuUeUlSchRecpInfo *recpReq
4882 #endif /* TFU_UPGRADE */
4884 S16 rgSCHUtlRgrCellCfg ARGS((RgSchCellCb *cell, RgrCellCfg *cellCfg,
4885 RgSchErrInfo *errInfo));
4886 S16 rgSCHUtlRgrCellRecfg ARGS((RgSchCellCb *cell, RgrCellRecfg *recfg,
4887 RgSchErrInfo *errInfo));
4888 S16 rgSCHUtlFreeCell ARGS((RgSchCellCb *cell));
4889 S16 rgSCHUtlRgrUeCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4890 RgrUeCfg *cfg, RgSchErrInfo *err));
4891 S16 rgSCHUtlRgrLcCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4892 RgSchDlLcCb *dl, RgrLchCfg *cfg,RgSchErrInfo *errInfo));
4893 S16 rgSCHUtlRgrLcDel ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4894 CmLteLcId lcId, uint8_t lcgId));
4895 S16 rgSCHUtlRgrLcRecfg ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
4896 RgSchDlLcCb *dlLc,RgrLchRecfg *recfg,RgSchErrInfo *err));
4897 S16 rgSCHUtlRgrLcgCfg ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
4898 RgrLcgCfg *cfg,RgSchErrInfo *errInfo));
4899 S16 rgSCHUtlRgrLcgRecfg ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
4900 RgrLcgRecfg *recfg,RgSchErrInfo *err));
4901 Void rgSCHUtlRgrLcgDel ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
4903 Void rgSCHUtlDlCqiInd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4904 TfuDlCqiRpt *dlCqiInd, CmLteTimingInfo timingInfo));
4906 /* Added changes of TFU_UPGRADE */
4908 Void rgSCHUtlRawCqiInd ARGS
4912 TfuRawCqiRpt* rawCqiRpt,
4913 CmLteTimingInfo timingInfo
4916 Void rgSCHUtlSrsInd ARGS
4921 CmLteTimingInfo timingInfo
4923 S16 rgSCHUtlGetCfgPerOff ARGS
4932 Void rgSCHUtlDoaInd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4933 TfuDoaRpt *doaInd));
4934 Void rgSCHUtlDlTARpt ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
4935 /* Changes for MIMO feature addition */
4936 Void rgSCHUtlDlRlsSubFrm ARGS((RgSchCellCb *cell, CmLteTimingInfo subFrm));
4937 Void rgSCHUtlDlProcAddToRetx ARGS((RgSchCellCb *cell,
4938 RgSchDlHqProcCb *hqP));
4939 S16 rgSCHUtlRegSch ARGS((uint8_t schIdx, RgSchdApis *apis));
4940 Void rgSCHUtlDlHqProcAddToTx ARGS((RgSchDlSf *subFrm, RgSchDlHqProcCb *hqP));
4941 /* Changes for MIMO feature addition */
4942 Void rgSCHUtlDlHqPTbRmvFrmTx ARGS((RgSchDlSf *subFrm,
4943 RgSchDlHqProcCb *hqP, uint8_t tbIdx, Bool isRepeating));
4944 S16 rgSCHUtlRgrUeRecfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4945 RgrUeRecfg *recfg, RgSchErrInfo *err));
4946 Void rgSCHUtlFreeDlLc ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4947 RgSchDlLcCb *dlLc));
4948 Void rgSCHUtlFreeUlLc ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4949 RgSchUlLcCb *ulLc));
4950 Void rgSCHUtlFreeUe ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
4951 Void rgSCHUtlDlDedBoUpd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4954 S16 rgSCHUtlUpdUlHqProc ARGS((RgSchCellCb *cell, RgSchUlHqProcCb *curProc,
4955 RgSchUlHqProcCb *oldProc));
4957 /* PHR handling for MSG3 */
4958 Void rgSCHUtlRecMsg3Alloc ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4960 S16 rgSCHUtlContResUlGrant ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4961 RgSchErrInfo *err));
4962 S16 rgSCHUtlSrRcvd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4963 CmLteTimingInfo, RgSchErrInfo *err));
4964 Void rgSCHUtlUpdBsrShort ARGS((RgSchCellCb *cell, RgSchUeCb *ue, uint8_t lcgId,
4965 uint8_t bsr, RgSchErrInfo *err));
4966 Void rgSCHUtlUpdBsrTrunc ARGS((RgSchCellCb *cell, RgSchUeCb *ue, uint8_t lcgId,
4967 uint8_t bsr, RgSchErrInfo *err));
4968 Void rgSCHUtlUpdBsrLong ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4969 uint8_t bsr1,uint8_t bsr2,uint8_t bsr3,uint8_t bsr4, RgSchErrInfo *err));
4970 S16 rgSCHUtlUpdPhr ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4971 uint8_t phr, RgSchErrInfo *err));
4972 S16 rgSCHUtlUpdExtPhr ARGS(( RgSchCellCb *cell, RgSchUeCb *ue,
4973 RgInfExtPhrCEInfo * extPhr, RgSchErrInfo *err));
4974 S16 rgSCHUtlDataRcvd ARGS((RgSchCellCb *cell, RgSchUeCb *ue, uint8_t numLc,
4975 RgSchUlLcCb *lcArr[], uint16_t bytesArr[], RgSchErrInfo *err));
4976 Void rgSCHUtlUlCqiInd ARGS(( RgSchCellCb *cell, RgSchUeCb *ue,
4977 TfuUlCqiRpt *ulCqiInfo));
4978 Void rgSCHUtlPucchDeltaPwrInd ARGS(( RgSchCellCb *cell, RgSchUeCb *ue,
4980 Void rgSCHUtlUeReset ARGS(( RgSchCellCb *cell, RgSchUeCb *ue));
4981 Void rgSCHUtlUlHqProcForUe ARGS((RgSchCellCb *cell, CmLteTimingInfo frm,
4982 RgSchUeCb *ue, RgSchUlHqProcCb **procRef));
4983 RgSchUlAlloc *rgSCHUtlFirstRcptnReq ARGS((RgSchCellCb *cell));
4984 RgSchUlAlloc *rgSCHUtlNextRcptnReq ARGS((RgSchCellCb *cell,
4985 RgSchUlAlloc *alloc));
4986 RgSchUlAlloc *rgSCHUtlFirstHqFdbkAlloc ARGS((RgSchCellCb *cell, uint8_t idx));
4987 RgSchUlAlloc *rgSCHUtlNextHqFdbkAlloc ARGS((RgSchCellCb *cell,
4988 RgSchUlAlloc *alloc, uint8_t idx));
4989 S16 rgSCHUtlTfuBndReq ARGS((Inst inst, SuId suId, SpId spId));
4990 S16 rgSCHUtlTfuUBndReq ARGS((Inst inst, RgSchLowSapCfgInfo sapCfg, Reason reason));
4992 S16 rgSCHEmtcUtlResetSfAlloc ARGS((RgInfSfAlloc *sfAlloc,
4993 Bool resetCmnLcInfo, Bool restAlloc));
4995 S16 rgSCHUtlResetSfAlloc ARGS((RgInfSfAlloc *sfAlloc,
4996 Bool resetCmnLcInfo, Bool restAlloc));
4997 S16 rgSCHUtlGetSfAlloc ARGS((RgSchCellCb *cell));
4998 S16 rgSCHUtlPutSfAlloc ARGS((RgSchCellCb *cell));
4999 S16 rgSCHUtlAllocSBuf ARGS((Inst inst, Data **pData, Size size));
5000 /* ccpu00117052 - MOD - Passing double pointer
5001 for proper NULLP assignment*/
5002 Void rgSCHUtlFreeSBuf ARGS((Inst inst, Data **data, Size size));
5003 Void rgSCHUtlFillDgnParams ARGS((Inst inst, RgUstaDgn *dgn,uint8_t dgnType));
5004 Void rgSCHUtlGetPstToLyr ARGS((Pst *pst,RgSchCb *schCb,Inst macInst));
5005 S16 rgSCHUtlFillRgInfCmnLcInfo ARGS((RgSchDlSf *sf,RgInfSfAlloc *sfAlloc,
5006 CmLteLcId lcId, Bool sendInd));
5007 S16 rgSCHUtlFillRgInfRarInfo ARGS((RgSchDlSf *sf,RgInfSfAlloc *sfAlloc,RgSchCellCb *cell));
5008 S16 rgSCHUtlFillPdschDciInfo ARGS((TfuPdschDciInfo *pdschDci,TfuDciInfo
5011 Void rgSCHUtlFillRgInfUeInfo ARGS((RgSchDlSf*, RgSchCellCb *cell, CmLListCp *dlDrxInactvTmrLst,
5012 CmLListCp *dlInActvLst, CmLListCp *ulInActvLst));
5014 S16 rgSCHUtlUpdSch ARGS((RgInfSfDatInd *subfrmInfo, RgSchCellCb *cellCb,
5015 RgSchUeCb *ueCb, RgInfUeDatInd *pdu,RgSchErrInfo *err));
5016 S16 rgSCHUtlHndlCcchBoUpdt ARGS((RgSchCellCb *cell,RgInfCmnBoRpt *boRpt));
5017 S16 rgSCHUtlHndlBcchPcchBoUpdt ARGS((RgSchCellCb *cell,RgInfCmnBoRpt
5019 S16 rgSCHUtlRgrBndCfm ARGS ((Inst inst, SuId suId,uint8_t status));
5020 /* Added for sending TTI tick to RRM */
5022 S16 rgSCHUtlRgrTtiInd ARGS ((RgSchCellCb *cell, RgrTtiIndInfo *ttiInd));
5024 S16 schSendCfgCfm ARGS ((Region reg, Pool pool, \
5025 RgrCfgTransId transId, uint8_t status));
5026 S16 rgSCHUtlProcMsg3 ARGS((RgInfSfDatInd *subfrmInfo, RgSchCellCb *cellCb,
5027 RgSchUeCb *ueCb, CmLteRnti rnti,RgInfUeDatInd *pdu,
5028 RgSchErrInfo *err ));
5030 S16 rgSCHUtlTfuGrpPwrCntrlReq ARGS((Inst inst,S16 sapId,
5031 TfuGrpPwrCntrlReqInfo *grpPwrCntrlReq));
5033 S16 rgSCHUtlTfuCntrlReq ARGS((Inst inst, S16 sapId,
5034 TfuCntrlReqInfo *cntrlReq));
5035 S16 rgSCHUtlTfuRecpReq ARGS((Inst inst, S16 sapId,
5036 TfuRecpReqInfo *recpReq));
5037 S16 rgSCHUtlValidateTfuSap ARGS((Inst inst,SuId suId));
5038 S16 rgSCHUtlAllocEventMem ARGS((Inst inst,Ptr *memPtr,Size memSize));
5039 S16 rgSCHUtlGetEventMem ARGS((Ptr *ptr,Size len,Ptr memCpa));
5040 S16 rgSCHUtlGetRlsHqAlloc ARGS((RgSchCellCb *cell));
5041 S16 rgSCHUtlPutRlsHqAlloc ARGS((RgSchCellCb *cell));
5043 S16 rgSCHUtlDlActvtUe ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
5044 S16 rgSCHUtlUlActvtUe ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
5045 Void rgSCHUtlHdlUlTransInd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
5046 CmLteTimingInfo timingInfo));
5048 Void rgSCHUtlUpdACqiTrigWt ARGS((RgSchUeCb *ue,RgSchUeCellInfo *sCellInfo, uint8_t isAck));
5050 /* Nprb indication at PHY for common Ch */
5051 /* Corrected allocation for common channels */
5052 S32 rgSCHUtlGetAllwdCchTbSz ARGS((uint32_t bo, uint8_t *nPrb, uint8_t *mcs
5054 /* CR timer changes*/
5055 S16 rgSCHUtlUpdtBo ARGS((RgSchCellCb *cell,
5056 RgInfCmnBoRpt *staRsp));
5057 S16 rgSCHUtlAddUeToCcchSduLst ARGS(
5061 S16 rgSCHUtlAddUeToEmtcCcchSduLst ARGS(
5065 S16 rgSCHRamRmvFrmEmtcRaInfoSchdLst ARGS((RgSchCellCb *cell, RgSchRaCb *raCb));
5066 Void rgSCHRamEmtcDelRaCb ARGS((RgSchCellCb *cell, RgSchRaCb *raCb));
5067 S16 rgSCHRamEmtcUpdtBo ARGS((RgSchCellCb *cell, RgSchRaCb *raCb,
5068 RgInfCmnBoRpt *staRsp));
5070 /* Added for SI Enhancement*/
5072 Void rgSCHUtlPutSiInfo ARGS((RgSchCellCb *cell));
5073 Void rgSCHUtlFreeWarningSiSeg ARGS((Region reg,Pool pool,
5074 CmLListCp *siPduLst));
5075 Void rgSCHUtlFreeWarningSiPdu ARGS((RgSchCellCb *cell));
5076 Buffer *rgSCHUtlGetWarningSiPdu ARGS((RgSchCellCb *cell));
5077 S16 rgSCHUtlGetMcsAndNPrb ARGS((RgSchCellCb *cell, uint8_t *nPrb, uint8_t *mcs, MsgLen *msgLen));
5078 S16 rgSCHUtlCalMcsAndNPrb ARGS((RgSchCellCb *cell, uint8_t cfgType, MsgLen msgLen, uint8_t siId));
5079 #endif/*RGR_SI_SCH*/
5082 S16 rgSCHUtlAllocUeANFdbkInfo ARGS((RgSchUeCb *ue,uint8_t servCellIdx));
5083 Void rgSCHUtlDelUeANFdbkInfo ARGS((RgSchUeCb *ue,uint8_t servCellIdx));
5084 S16 rgSCHUtlInitUeANFdbkInfo ARGS((RgSchTddANInfo *anInfo));
5085 RgSchTddANInfo* rgSCHUtlGetUeANFdbkInfo ARGS((RgSchUeCb *ueCb, CmLteTimingInfo *timeInfo,uint8_t servCellIdx));
5086 uint8_t rgSCHUtlGetDlSfIdx ARGS((RgSchCellCb *cell, CmLteTimingInfo *timeInfo));
5087 Void rgSCHUtlPrachCfgInit ARGS((RgSchCellCb *cell, RgrCellCfg *cellCfg ));
5088 Void rgSCHUtlGetNxtDlSfInfo ARGS((CmLteTimingInfo curDlTime, RgSchCellCb *cell, RgSchDlSf *dlSf, RgSchDlSf **nxtDlsf, CmLteTimingInfo *nxtDlTime));
5089 Void rgSCHUtlGetPrevDlSfInfo ARGS((RgSchCellCb * cell, CmLteTimingInfo curDlTime, CmLteTimingInfo *prevDlTime, uint8_t *numSubfrm));
5091 Void rgSCHCmnDlSch ARGS
5095 Void rgSCHCmnSndCnsldtInfo ARGS
5099 Void rgSCHCmnCnsldtSfAlloc ARGS
5104 /* Added support for SPS*/
5105 Void rgSCHCmnDlAllocFnlz ARGS
5111 Void rgSCHUtlDlRelPdcchFbk ARGS((
5117 Void rgSCHUtlDlProcAck ARGS((
5119 RgSchDlHqProcCb *hqP
5121 S16 rgSCHUtlSpsRelInd ARGS((
5122 RgSchCellCb *cellCb,
5127 Void rgSCHCmnDlSch ARGS
5132 S16 rgSCHUtlSpsActInd ARGS((
5133 RgSchCellCb *cellCb,
5138 Void rgSCHUtlHdlCrcFailInd ARGS((
5141 CmLteTimingInfo timingInfo
5144 Void rgSCHUtlHdlCrntiCE ARGS((
5149 #endif /* LTEMAC_SPS*/
5151 /******* </AllocHolesMemMgmnt>: START *****/
5152 S16 rgSCHUtlUlSfInit ARGS((
5158 Void rgSCHUtlUlSfDeinit ARGS((
5162 RgSchUlAlloc *rgSCHUtlUlAllocGetHole ARGS((
5167 RgSchUlAlloc *rgSCHUtlUlAllocGetCompHole ARGS((
5171 RgSchUlAlloc *rgSCHUtlUlAllocGetPartHole ARGS((
5176 Void rgSCHUtlUlAllocRls ARGS((
5181 /* UL_ALLOC_ENHANCEMENT */
5182 Void rgSCHUtlUlAllocRelease ARGS((
5185 RgSchUlAlloc *rgSCHUtlUlAllocFirst ARGS((
5188 RgSchUlAlloc *rgSCHUtlUlAllocNxt ARGS((
5192 RgSchUlHole *rgSCHUtlUlHoleFirst ARGS((
5195 RgSchUlHole *rgSCHUtlUlHoleNxt ARGS((
5199 RgSchUlAlloc *rgSCHUtlUlAllocGetAdjNxt ARGS((
5203 RgSchUlAlloc *rgSCHUtlUlAllocGetFirst ARGS((
5206 Void rgSCHUtlUlHoleAddAlloc ARGS((
5210 /* UL_ALLOC_ENHANCEMENT */
5211 Void rgSCHUtlUlHoleAddAllocation ARGS((
5215 Void rgSCHUtlUlHoleJoin ARGS((
5221 Void rgSCHUtlUlHoleExtndRight ARGS((
5226 Void rgSCHUtlUlHoleExtndLeft ARGS((
5231 Void rgSCHUtlUlHoleNew ARGS((
5235 Void rgSCHUtlUlHoleUpdAllocLnks ARGS((
5237 RgSchUlAlloc *prvAlloc,
5238 RgSchUlAlloc *nxtAlloc
5240 Void rgSCHUtlUlHoleIns ARGS((
5244 Void rgSCHUtlUlHoleIncr ARGS((
5248 Void rgSCHUtlUlHoleDecr ARGS((
5252 Void rgSCHUtlUlHoleRls ARGS((
5256 S16 rgSCHUtlUlAllocMemInit ARGS((
5258 RgSchUlAllocMem *mem,
5261 Void rgSCHUtlUlAllocMemDeinit ARGS((
5263 RgSchUlAllocMem *mem
5265 S16 rgSCHUtlUlHoleMemInit ARGS((
5267 RgSchUlHoleMem *mem,
5269 RgSchUlHole **holeRef
5271 Void rgSCHUtlUlHoleMemDeinit ARGS((
5275 RgSchUlAlloc *rgSCHUtlUlAllocMemGet ARGS((
5276 RgSchUlAllocMem *mem
5278 Void rgSCHUtlUlAllocMemRls ARGS((
5279 RgSchUlAllocMem *mem,
5282 RgSchUlHole *rgSCHUtlUlHoleMemGet ARGS((
5285 Void rgSCHUtlUlHoleMemRls ARGS((
5286 RgSchUlHoleMem *mem,
5289 RgSchUlAlloc *rgSCHUtlUlGetSpfcAlloc ARGS((
5294 /******* </AllocHolesMemMgmnt>: END *****/
5296 /* DRX function declarations */
5297 S16 rgSCHDrxCellCfg ARGS((RgSchCellCb *cell, RgrCellCfg *cellCfg));
5298 Void rgSCHDrxCellDel ARGS((RgSchCellCb *cell));
5299 S16 rgSCHDrxUeCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
5302 S16 rgSCHDrxUeReCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
5303 RgrUeRecfg *ueCfg));
5305 S16 rgSCHDrxUeDel ARGS((RgSchCellCb *cell,RgSchUeCb *ue));
5306 Void rgSCHDrxTtiInd ARGS ((RgSchCellCb *cell));
5308 S16 rgSCHDrxSfAlloc ARGS ((RgSchCellCb *cellCb, RgSchDlSf
5310 S16 rgSCHDrxDlTrnsFail ARGS((RgSchCellCb *cell, RgSchDlHqProcCb
5312 Void rgSCHDrxDedRa ARGS((RgSchCellCb *cellCb, RgSchUeCb* ueCb));
5313 S16 rgSCHDrxSrInd ARGS((RgSchCellCb *cell,RgSchUeCb *ue));
5315 Void rgSCHDrxStrtInActvTmr ARGS((RgSchCellCb *cell,
5317 uint8_t direction));
5318 S16 rgSCHUtlGetDrxSchdUesInDl ARGS((RgSchCellCb *cellCb,
5320 RgSchDlHqProcCb *dlHq,
5321 RgInfUeAlloc *allocInfo,
5322 CmLListCp *dlDrxInactvTmrLst,
5323 CmLListCp *dlInActvLst,
5324 CmLListCp *ulInActvLst));
5325 Void rgSCHDrxStartHarqRTTTmr ARGS((RgSchCellCb *cell,
5326 RgSchDlHqProcCb *hqP,
5328 Void rgSCHDrxUeHqReset ARGS((RgSchCellCb *cell,
5335 const RgSchTddCellSpSrsSubfrmTbl rgSchTddCellSpSrsSubfrmTbl;
5337 const RgSchFddCellSpSrsSubfrmTbl rgSchFddCellSpSrsSubfrmTbl;
5342 S16 rgSCHHdFddUeCfg ARGS((
5343 RgSchCellCb *cellCb,
5346 S16 rgSCHHdFddUeDel ARGS((
5347 RgSchCellCb *cellCb,
5349 Void rgSCHCmnHdFddPtUlMrk ARGS((
5350 RgSchCellCb *cellCb));
5351 Void rgSCHCmnHdFddChkUlAllow ARGS((
5352 RgSchCellCb *cellCb,
5355 Void rgSCHCmnHdFddChkDlAllow ARGS((
5356 RgSchCellCb *cellCb,
5359 Void rgSCHCmnHdFddChkNackAllow ARGS((
5360 RgSchCellCb *cellCb,
5362 CmLteTimingInfo timInfo,
5364 Void rgSCHCmnHdFddUpdULMark ARGS((
5365 RgSchCellCb *cellCb,
5367 Void rgSCHCmnHdFddUpdDLMark ARGS((
5368 RgSchCellCb *cellCb,
5370 Void rgSCHHdFddGetSfn ARGS((
5372 CmLteTimingInfo timeInfo,
5374 #endif /* ifdef LTEMAC_HDFDD */
5376 /* ccpu00117452 - MOD - Changed macro name from
5377 RGR_RRM_DLPWR_CNTRL to RGR_CQI_REPT */
5379 S16 rgSCHUtlRgrStaInd ARGS((
5381 RgrStaIndInfo *rgrSta
5384 S16 rgSCHUtlFillSndStaInd ARGS((
5387 RgrStaIndInfo *staInfo,
5390 #endif /* End of RGR_CQI_REPT */
5391 S16 rgSCHUtlRgrUeStaInd ARGS((
5393 RgrUeStaIndInfo *rgrUeSta
5396 S16 rgSCHUtlFillSndUeStaInd ARGS((
5399 RgrUeStaIndInfo *ueStaInfo
5403 /* LTE_ADV_FLAG_REMOVED_START */
5404 S16 rgSCHUtlRgrLoadInfInd ARGS((
5406 RgrLoadInfIndInfo *rgrLoadInf
5408 /* LTE_ADV_FLAG_REMOVED_END */
5411 TfuAckNackMode rgSchUtlGetFdbkMode ARGS((
5412 RgrSchFrmt1b3TypEnum fdbkType
5415 TfuAckNackMode rgSchUtlGetFdbkMode ARGS((
5416 RgrSchFrmt1b3TypEnum fdbkType
5419 #endif /*TFU_UPGRADE */
5420 #endif /* LTE_ADV */
5422 Void rgSCHUtlRlsRnti ARGS((
5423 RgSchCellCb *cellCb,
5424 RgSchRntiLnk *rntiLnk,
5428 S16 rgSCHUtlRgmBndCfm ARGS((
5433 Void rgSCHDhmDelHqEnt ARGS((
5437 Void rgSCHDhmAssgnUeHqEntFrmRaCb ARGS((
5441 Void rgSCHUtlReTxTa ARGS((
5442 RgSchCellCb *cellCb,
5444 /* LTE_ADV_FLAG_REMOVED_START */
5445 Void rgSchSFRTotalPoolFree ARGS((
5446 RgSchSFRTotalPoolInfo *sfrTotalPoolInfo,
5447 RgSchCellCb *cell));
5448 Void rgSchDSFRPwrCheck ARGS((
5450 Bool *isAllUePwrHigh));
5451 /* LTE_ADV_FLAG_REMOVED_END */
5453 S16 rgSCHUtlUpdAvgPrbUsage ARGS((
5457 uint8_t rgSchUtlCfg0ReTxIdx ARGS((
5459 CmLteTimingInfo phichTime,
5463 S16 rgSCHUtlBuildNSendLcgReg ARGS((
5470 Void rgSCHUtlPdcchInit ARGS((
5474 Void rgSCHDynCfiReCfg ARGS((
5478 Void rgSchUtlCalcTotalPrbReq ARGS((RgSchCellCb *cell,
5481 uint32_t *prbReqrd));
5482 uint8_t rgSchUtlGetNumSbs ARGS((
5488 uint8_t rgSchUtlSortInsUeLst ARGS((
5492 uint8_t subbandRequired
5494 S16 rgSCHUtlResetCpuOvrLdState ARGS((
5496 uint8_t cnrtCpuOvrLdIns
5498 Void rgSCHUtlCpuOvrLdAdjItbsCap ARGS((
5502 S16 rgSCHTomUtlPcqiSbCalcBpIdx ARGS((
5503 CmLteTimingInfo crntTimInfo,
5505 RgSchUePCqiCb *cqiCb
5509 S16 rgSCHUtlSCellHndlCqiCollsn ARGS((
5510 RgSchUePCqiCb *cqiCb
5513 S16 rgSCHUtlSCellHndlRiCollsn ARGS((
5514 RgSchUePCqiCb *cqiCb
5518 #endif/*TFU_UPGRADE*/
5520 Void rgSCHTomUtlGetTrigSet ARGS((
5527 Void rgSCHUtlUpdUeDciSize ARGS((
5532 Void rgSCHUtlCalcDciSizes ARGS((
5536 Void rgSchCmnPreDlSch ARGS ((
5539 RgSchCellCb **cellLst
5542 Void rgSchCmnPstDlSch ARGS ((
5546 uint8_t rgSCHCmnGetBiIndex ARGS ((
5551 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
5554 #endif /* __cplusplus */
5555 #endif /* __SCH__ */
5558 /**********************************************************************
5560 **********************************************************************/