1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /**********************************************************************
25 Desc: Defines required by LTE-MAC
29 **********************************************************************/
34 #define RGSCHLAYERNAME "MAC Scheduler"
36 #define MAX_5GTF_CELL 8
37 #define MAX_5GTF_GROUP 1
38 #define MAX_5GTF_BEAMS 4
39 #define MAX_5GTF_SUBFRAME_INFO 10
40 #define MAX_5GTF_VRBG_SIZE 4
41 #define MAX_5GTF_PRBS 100
42 #define MAX_5GTF_MCS 15
43 #define MAX_5GTF_VRBG 25
44 #define MAX_5GTF_TB_SIZE 66392
45 /* Total number of UEs scheduled per cell in a subframe */
46 #define MAX_5GTF_UE_SCH 4
47 #define MAX_5GTF_DCIA1B1_SIZE 60
48 #define MAX_5GTF_XPUSCH_RANGE 2
50 /* This variables must moved into cell context finally. Since this requires replacing
51 * all macros in the code with these cell specific variables, this will taken as part of
52 * delta cleanup activity in MAC. Untill then, since we only support one cell, this should be fine
54 #ifdef RG_SCH_DYNDLDELTA
55 #define RGSCH_UPDATE_DELTA(_inst, delta)\
57 rgSchCb[_inst].rgSchDlDelta = RG_ENV_DL_DELTA + delta;\
58 rgSchCb[_inst].rgSchCmnDlDelta = RG_ENV_SCH_CMN_DL_DELTA + delta;\
59 rgSchCb[_inst].rgSchUlDelta = TFU_ENV_HQFBKIND_ULDELTA + delta;\
62 #define RGSCH_UPDATE_DELTA(_inst, delta)
65 #ifdef RG_SCH_DYNDLDELTA
67 #ifdef CA_PHY_BRDCM_61765
68 #define RG_DL_DELTA rgSchCb[1].rgSchDlDelta
69 #define RG_SCH_CMN_DL_DELTA (rgSchCb[1].rgSchCmnDlDelta)
70 #define TFU_HQFBKIND_ULDELTA (rgSchCb[1].rgSchUlDelta)
72 #define RG_DL_DELTA rgSchCb[0].rgSchDlDelta
73 #define RG_SCH_CMN_DL_DELTA (rgSchCb[0].rgSchCmnDlDelta)
74 #define TFU_HQFBKIND_ULDELTA (rgSchCb[0].rgSchUlDelta)
77 #ifdef SPLIT_RLC_DL_TASK
78 #define RG_DL_DELTA (RG_ENV_DL_DELTA + 1 )
79 #define RG_SCH_CMN_DL_DELTA (RG_ENV_SCH_CMN_DL_DELTA + 1)
80 #define TFU_HQFBKIND_ULDELTA (TFU_ENV_HQFBKIND_ULDELTA + 1)
82 #define RG_DL_DELTA RG_ENV_DL_DELTA
83 #define RG_SCH_CMN_DL_DELTA RG_ENV_SCH_CMN_DL_DELTA
84 #define TFU_HQFBKIND_ULDELTA TFU_ENV_HQFBKIND_ULDELTA
88 /* Tunable parameter */
89 #define RGSCH_MAX_NUM_DED_LC 10 /* maximum dedicated logical channels in a UE */
90 #define RGSCH_MAX_NUM_CMN_LC 5 /* maximum number of common logical
94 #define RGSCH_MAX_LCG_PER_UE 4
95 #define RGSCH_CON_RES_ID_SZ 6
97 #define RGSCH_MAX_RA_RNTI 60
99 #define RGSCH_MAX_RA_RNTI 10
100 #define RGSCH_RAREQ_ARRAY_SIZE (2*RGSCH_MAX_RA_RNTI)
103 #define RGSCH_MAX_RAPID 64 /* XXX: For RACH Module */
104 /* Below two temps added by nagaraja S */
105 #define RG_MEAS_GAPPRD_40 40
106 #define RG_MEAS_GAPPRD_80 80
107 /* Added support for SPS*/
109 /* LTEMAC_SPS changes */
110 #define RG_SCH_NUM_RATYPE1_SUBSETS 4
111 #define RG_SCH_NUM_RATYPE2_32BIT_MASK 4
112 #define RG_SCH_NUM_RATYPE1_32BIT_MASK RG_SCH_NUM_RATYPE1_SUBSETS
114 #define RGSCH_SPS_ULBW_MASK_LEN 4
115 #define RGSCH_SPS_MG_MASK_LEN 10
116 /* MAX number of feedbacks in case of LTE_TDD */
119 #define RGSCH_TDD_MAX_FDBK 4
121 /* DL SPS States of UE */
122 #define RGSCH_DL_SPS_IDLE 0x00
123 #define RGSCH_DL_SPS_ACTVTN_PENDING 0x01
124 #define RGSCH_DL_SPS_WAITING_FOR_ACTV_CFM 0x02
125 #define RGSCH_DL_SPS_ACTV 0x03
126 #define RGSCH_DL_SPS_RELEASE_TRIGGERED 0x04
127 #define RGSCH_DL_SPS_REACTVTN_PENDING 0x05
129 /* UL SPS States of UE */
130 #define RGSCH_SPS_IDLE 0x00
131 #define RGSCH_SPS_TO_BE_ACTV 0x01
132 #define RGSCH_SPS_TO_BE_REACTV 0x02
133 #define RGSCH_SPS_TO_BE_REL 0x03
134 #define RGSCH_SPS_ACTV_PDCCH_SENT 0x04
135 #define RGSCH_SPS_REL_SENT 0x05
136 #define RGSCH_SPS_ACTV 0x06
138 #define RG_SCH_SPS_LCG_ID 1
139 #define RG_SCH_MAX_N1PUCCH_VAL 2047
140 #define RGSCH_INVALID_SUBFRAME 0xFF
141 #define RGSCH_INVALID_SFN 0xFFFF
144 #define RG_SCH_MAX_NUM_N1PUCCH_PER_UE 4
145 #define RG_SCH_MAX_NUM_N3PUCCH_PER_UE 4
146 #define RGSCH_MAX_DL_HQ_PROC 8
148 /* This is the delta that MAC works on Schedule's DELTA should be a function of
152 /* Well known RNTIS */
153 #define RGSCH_SI_RNTI 0xffff
154 #define RGSCH_P_RNTI 0xfffe
156 #define RGSCH_MAX_UPPERSAP 3
157 #define RGSCH_MAX_LOWERSAP 1
158 #define RGSCH_TQ_SIZE 100 /* Timing Queue Size */
159 #define RGSCH_MAX_TIMER RGSCH_MAX_LOWERSAP /* MAX number of MAC timers */
160 #define RGSCH_NMB_CELL_HASHBIN 10 /* Number of Hash Bins for cell hash
162 #define RGSCH_NMB_UE_HASHBIN 10 /* Number of Hash Bins for UE hash
164 #define RGSCH_BNDREQ_TMR 1 /* Bind Request timer event value */
165 #define RGSCH_MAX_BNDRETRY 2 /* Max number of Bind Retries for TFU SAP */
168 #define RGSCH_UE_TQ_SIZE 10 /* Timing Queue Size */
170 #define RGSCH_INVALID_SCHD_TYPE 255
171 #define RGSCH_MAX_UE_PER_CELL 0xFFFF /*!< Maximum number of UEs per cell */
172 #define RGSCH_MAX_UE_BIN_PER_CELL 128 /*!< Maximum number of UE bins per cell */
173 #define RGSCH_MIN_DL_BW 6 /*!< Minimum Downlink bandwidth in RBs */
174 #define RGSCH_MAX_DL_BW 110 /*!< Maximum Downlink bandwidth in RBs */
175 #define RGSCH_MIN_UL_BW 6 /*!< Minimum Uplink bandwidth in RBs */
176 #define RGSCH_MAX_UL_BW 110 /*!< Maximum Uplink bandwidth in RBs */
177 #define RGSCH_NUM_SC_IN_RB 12 /*!< Number of sub carriers in a RB */
178 #define RGSCH_NUM_PBCH_SYM 4 /*!< Number of PBCH symbols in subframe0.Section 6.6,36.211 */
179 #define RGSCH_NUM_PSS_SSS_SYM 2 /*!< Number of primary and secondary Synchronization symbols in subframe 0 and subframe 5 */
180 #define RGSCH_NUM_CELL_RS_ONE_ANT_PORT 8 /*!< Number of cell specific reference symbols in a Subframe */
181 #define RGSCH_NUM_CELL_RS_TWO_ANT_PORT 16 /*!< Number of cell specific reference symbols in a Subframe */
182 #define RGSCH_NUM_CELL_RS_FOUR_ANT_PORT 24 /*!< Number of cell specific reference symbols in a Subframe */
183 #define RGSCH_TOT_NUM_SYM_NORCP 168 /*!< Total number of symbols in a RB in case of Normal CP */
184 #define RGSCH_TOT_NUM_SYM_EXTCP 144 /*!< Total number of symbols in a RB in case of Extended CP */
186 #define RGSCH_MAX_NUM_CSRS_ONE_SYMBOL_RB 4
187 #define RGSCH_NUM_ANT_PORT_FOUR 4
188 #define RGSCH_MIN_NUM_ANT_PORT 1
189 #define RGSCH_NUM_REGS_1ST_SYM 2
190 #define RGSCH_NUM_REGS_2ND_SYM_FOUR_ANT_PORT 2
191 #define RGSCH_NUM_REGS_2ND_SYM_1OR2_ANT_PORT 3
192 #define RGSCH_NUM_REGS_3RD_SYM 3
193 #define RGSCH_NUM_REGS_4TH_SYM_NOR_CP 3
194 #define RGSCH_NUM_REGS_4TH_SYM_EXT_CP 2
196 #define RGSCH_MIN_CFI_VAL 1 /*!< Minimum value for CFI */
197 #define RGSCH_MAX_CFI_VAL 3 /*!< Maximum value for CFI */
198 #define RGSCH_QM_BPSK 2 /*!< Qm value for BPSK */
199 #define RGSCH_QM_QPSK 4 /*!< Qm value for QPSK */
200 #define RGSCH_QM_64QAM 6 /*!< Qm value for 64QAM */
201 #define RGSCH_MIN_SRS_SFCFG_IDX 0 /*!< Minimum value for SRS subframe
202 configurtion index */
203 #define RGSCH_MAX_SRS_SFCFG_IDX 15 /*!< Maximum value for SRS subframe
204 configurtion index */
205 #define RGSCH_MAX_SRS_TX_OFFSET 8 /*!< Maximum number of SRS transmission
208 #define RGSCH_MIN_MAC_RNTI 61 /*!< Minimum value of RNTI to be managed by
211 #define RGSCH_MIN_MAC_RNTI 11 /*!< Minimum value of RNTI to be managed by
215 #define RG_SCH_DL_MAX_ITBS 13
216 #define RG_SCH_UL_MAX_ITBS 13
218 #define RG_TIME_DIFF(_currTime,_prevTime) \
219 (_currTime < _prevTime ? ((0xffffffff - _prevTime) + _currTime ): (_currTime - _prevTime))
221 #define RGSCH_TYPE_SC1 RGR_SCH_TYPE_SC1
222 #define RGSCH_TYPE_PFS RGR_SCH_TYPE_PFS
223 #define RGSCH_TYPE_RR RGR_SCH_TYPE_RR
224 #define RGSCH_TYPE_MAXCI RGR_SCH_TYPE_MAXCI
225 /* HARQ related MACROs */
227 #define RGSCH_NUM_DL_HQ_PROC 15
229 #define RGSCH_NUM_DL_HQ_PROC 8
231 #define RGSCH_NUM_UL_HQ_PROC 8
232 #define RGSCH_MIN_HQ_TX 1
234 /* Group power related MACROs */
235 #define RGSCH_MAX_GRP_PWR_FMT3_IDX 15 /*!< Maximum index value for group power format 3 */
236 #define RGSCH_MAX_GRP_PWR_FMT3A_IDX 31 /*!< Maximum index value for group power format 3A */
238 /* MACROs to indicate cell specific config for cell to be active */
239 #define RGSCH_BCCH_BCH_CFG (1<<0)
240 #define RGSCH_BCCH_DLSCH_CFG1 (1<<1)
241 #define RGSCH_BCCH_DLSCH_CFG2 (1<<2)
242 #define RGSCH_PCCH_CFG (1<<3)
243 #define RGSCH_UL_CCCH_CFG (1<<4)
244 #define RGSCH_DL_CCCH_CFG (1<<5)
245 #define RGSCH_SCHD_CFG (1<<6)
247 #define RGSCH_CELL_ACTIVE_CFG (RGSCH_BCCH_BCH_CFG | RGSCH_BCCH_DLSCH_CFG1 | RGSCH_BCCH_DLSCH_CFG2 | RGSCH_PCCH_CFG | RGSCH_UL_CCCH_CFG | RGSCH_DL_CCCH_CFG)
249 /* Logical channel realated MACROs */
250 #define RGSCH_INVALID_LCG_ID 255
251 #define RGSCH_INVALID_LC_ID 255
252 #define RGSCH_BCCH_BCH_IDX 0
253 #define RGSCH_BCCH_DLSCH_IDX1 1
254 #define RGSCH_BCCH_DLSCH_IDX2 2
255 #define RGSCH_PCCH_IDX 3
257 /* PUCCH related macros */
258 #define RGSCH_PUCCH_MAXVAL_CS 7 /*!< Maximum value for cyclic shift of PUCCH */
259 #define RGSCH_PUCCH_MINVAL_DS 1 /*!< Mininmum value for delta shift of PUCCH */
260 #define RGSCH_PUCCH_MAXVAL_DS 3 /*!< Maximum value for delta shift of PUCCH */
262 /* DUX related macros */
263 #define RGSCH_LCID_MASK 0x1F
264 #define RGSCH_LCID_LEN 0x5
265 #define RGSCH_CCCH_LCID 0x00
266 #define RGSCH_DEDLC_MIN_LCID 0x01
267 #define RGSCH_DEDLC_MAX_LCID 0x0A
268 #define RGSCH_RES_MIN_LCID 0x0B
269 #define RGSCH_RES_MAX_LCID 0x19
270 #define RGSCH_PHR_LCID 0x1A
271 #define RGSCH_CRNTI_LCID 0X1B
272 #define RGSCH_TRUNC_BSR_LCID 0X1C
273 #define RGSCH_SHORT_BSR_LCID 0X1D
274 #define RGSCH_LONG_BSR_LCID 0X1E
275 #define RGSCH_PAD_LCID 0x1F
276 /* Fix: If only TA is scheduled, use some dummy LCID */
277 #define RG_TA_LCID 0x20
278 #define RGSCH_MAX_EXTN_PAD_SUBHDRS 0x02
280 #define RGSCH_CCCH_SDU_PRSNT (1<<0)
281 #define RGSCH_CRNTI_CE_PRSNT (1<<1)
282 #define RGSCH_PHR_CE_PRSNT (1<<2)
283 #ifndef MAC_5GTF_UPDATE
284 #define RGSCH_TRUNC_BSR_CE_PRSNT (1<<3)
285 #define RGSCH_SHORT_BSR_CE_PRSNT (1<<4)
286 #define RGSCH_LONG_BSR_CE_PRSNT (1<<5)
288 #define RGSCH_BSR_CE_PRSNT (1<<5)
291 #define RGSCH_ACTIVE_LC_PRSNT (1<<6)
293 #define RGSCH_UL_SPS_ACT_PRSENT (1<<7)
295 #define RGSCH_EXT_PHR_CE_PRSNT (1<<8)
297 /* LOGICAL CHANNEL */
298 #define RGSCH_MAX_LC_PER_UE 10
299 /* Maximum number of common logical channel control blocks */
300 #define RGSCH_MAX_CMN_LC_CB 4
302 /* Random access related MACROs */
303 #define RGSCH_MAX_RA_PREAMBLE_FMT 3 /*!< Maximun value of Random access preamble
305 #define RGSCH_MAX_RA_WINSIZE 10 /*!< Maximum size of Random access response
306 window in subframes */
307 #define RGSCH_MIN_RA_WINSIZE 2 /*!< Minimum size of Random access response
308 window in subframes */
309 #define RGSCH_MIN_NUM_RA_PREAMBLE 4 /*!< Minimum number of Random access
311 #define RGSCH_MAX_NUM_RA_PREAMBLE 64 /*!< Maximim number of Random access
313 #define RGSCH_NUM_RA_RB 6
315 #define RGSCH_MAX_UL_RB 110 /*!< MAX Uplink RBs */
317 #define RGSCH_MAX_RA_RSP_ALLOC 4 /*!< Maximum number of Random access
320 #define RGSCH_MAX_RA_RNTI_PER_SUBFRM 6
321 #define RGSCH_MAX_TDD_RA_RSP_ALLOC 6
322 #define RGSCH_MAX_TDD_RA_PREAMBLE_FMT 4
323 #define RGSCH_MAX_TDD_UL_DL_CFG 7
324 #define RGSCH_MAX_TDD_SPL_SUBFRM_CFG 9
325 #define RGSCH_INVALID_INFO 0xff
327 #define RGSCH_RGR_CFG 1 /* RGR configuration element */
329 /*CA_SPECIFIC MACROS*/
331 #define RGSCH_INVALID_CELL_IDX 255
332 #define RGSCH_PCELL_INDEX 0
333 #define RG_SCH_CELLINDEX(_cell) (uint8_t)((_cell->cellId >= rgSchCb[_cell->instIdx].genCfg.startCellId) ?\
334 (_cell->cellId - rgSchCb[_cell->instIdx].genCfg.startCellId)&(CM_LTE_MAX_CELLS-1): 0)
335 #define RG_SCH_GET_SCELL_INDEX(_ueCb, _cell) _ueCb->cellIdToCellIdxMap[RG_SCH_CELLINDEX(_cell)]
337 #define RGSCH_MIN_MSG3_GRNT_SZ 7 /*!< Minimum msg3 grant size in bytes */
339 #define RGSCH_NUM_ITBS 27
340 #define RGSCH_MAX_NUM_RB 110
341 /* Max number of layers per CW */
342 #define RGSCH_MAX_NUM_LYR_PERCW 2
344 /* New hash define for TA. Refer to 36.213, 4.2.3*/
345 #define RGSCH_NO_TA_RQD 31
347 /* ccpu00133680: Expcted alloc per LC at the end of scheduling
348 * 2 bytes for minimum RLC Header+ 1 byte for minimal MAC header
349 * + 1 byte for minimal RLC SDU*/
350 #define RGSCH_MIN_ALLOC_PER_LC 4
351 #define RGSCH_MAX_REFRESH_GRPSZ 4 /*! Max number of UEs refreshed per subframe */
352 #define RGSCH_MAX_REFRESH_OFFSET 16 /*! Max number of subframes used for UE refresh */
354 #define RGSCH_NUM_PDB_SEV_LEVELS 4 /*Number of Severity Levels the PDB can be classified as */
355 #define RG_SCH_MAX_PDB_TIME 280 /*Maximum PDB time */
356 #define RGSCH_LCG_ISCFGD(lcg) ((lcg)->lcgId != RGSCH_INVALID_LCG_ID)
357 /* Corrected the check for dlCcchId */
358 #define RGSCH_DLCCCH_ISCFGD(cell) ((cell)->dlCcchId != RGSCH_INVALID_LC_ID)
359 #define RGSCH_ULCCCH_ISCFGD(cell) ((cell)->ulCcchId != RGSCH_INVALID_LC_ID)
362 /* Note: In RGSCH_CALC_SF_DIFF, _time1 should be the latest */
363 #define RGSCH_CALC_SF_DIFF_EMTC(_time1, _time2)\
364 (_time1.hSfn*10240+_time1.sfn*10+_time1.subframe) < (_time2.hSfn*10240+_time2.sfn*10+_time2.subframe)?\
365 ((_time1.hSfn+RGSCH_MAX_SFN)*10240+_time1.sfn*10+_time1.subframe) -\
366 (_time2.hSfn*10240+_time2.sfn*10+_time2.subframe) : \
367 (_time1.hSfn*10240+_time1.sfn*10+_time1.subframe) - (_time2.hSfn*10240+_time2.sfn*10+_time2.subframe)\
370 /*LTE_L2_MEAS_PHASE2*/
371 /*#define RGSCH_CALC_SFN_SF_DIFF(_time1,_sfnCycle, _time2)\
372 (((_time1.sfn+RGSCH_MAX_SFN * _sfnCycle)*10) + _time1.subframe -\
373 (_time2.sfn*10 + _time2.subframe))*/
375 #define RG_SCH_ADD_TO_CRNT_TIME_EMTC(crntTime, toFill, incr) \
376 if ((crntTime.slot + (incr)) >= RGSCH_NUM_SUB_FRAMES) \
377 toFill.sfn = (crntTime.sfn + \
378 (crntTime.slot + (incr)) / RGSCH_NUM_SUB_FRAMES); \
380 toFill.sfn = crntTime.sfn; \
381 toFill.subframe = (crntTime.slot + (incr)) % RGSCH_NUM_SUB_FRAMES; \
382 if (toFill.sfn >= RGSCH_MAX_SFN) \
384 toFill.hSfn = (crntTime.hSfn + 1) % RGSCH_MAX_SFN; \
385 toFill.sfn = toFill.sfn % RGSCH_MAX_SFN; \
389 toFill.hSfn = crntTime.hSfn; \
392 #define RGSCHDECRFRMCRNTTIME_EMTC(_crntDl, _prevDl, decr) \
396 _subframe = _crntDl.hSfn*10240 + _crntDl.sfn * RGSCH_NUM_SUB_FRAMES + _crntDl.subframe; \
397 _subframe = _subframe - decr; \
400 _subframe = (RGSCH_MAX_SFN * RGSCH_MAX_SFN * RGSCH_NUM_SUB_FRAMES) + _subframe; \
402 _prevDl.hSfn = _subframe / (10240); \
403 _subframe = _subframe % 10240; \
404 _prevDl.sfn = _subframe / RGSCH_NUM_SUB_FRAMES; \
405 _prevDl.subframe = _subframe % RGSCH_NUM_SUB_FRAMES; \
408 /* ccpu00133109: Removed RGSCHSUBFRMCRNTTIME as it is not giving proper output
409 * if diff is more than 10. Instead using RGSCHDECRFRMCRNTTIME() as it is
410 * serving the purpose */
412 #define RGSCHCPYTIMEINFO_EMTC(src, dst) \
413 dst.hSfn = src.hSfn; \
415 dst.subframe = src.subframe;
417 #define RGSCH_SUBFRAME_INDEX(x) ( ( ( ((x).hSfn * RGSCH_MAX_SFN )+ (x).sfn) * RGSCH_NUM_SUB_FRAMES ) + (x).subframe )
419 #define RGSCH_TIMEINFO_SAME_EMTC(x, y) (((x).sfn == (y).sfn) && ((x).subframe == (y).subframe))
421 /* Added support for SPS*/
423 /*Compares time difference and returns 0 if same, - 1 if x < y, 1 if x > y
424 Special check for RGSCH_MAX_SFN is to take care of the wrap around case */
425 #define RGSCH_TIMEINFO_CMP_EMTC(_x, _y, _ret)\
427 if (RGSCH_TIMEINFO_SAME_EMTC(_x, _y))\
429 else if ((_x).hSfn > (_y).hSfn)\
430 {if ((((_x).hSfn - (_y).hSfn)) == (RGSCH_MAX_SFN -1)) *_ret = -1; else *_ret = 1; }\
431 else if ((_x).hSfn < (_y).hSfn)\
432 {if ((((_y).hSfn - (_x).hSfn)) == (RGSCH_MAX_SFN -1)) *_ret = 1; else *_ret = -1; }\
433 else if ((_x).sfn > (_y).sfn)\
435 else if ((_x).sfn < (_y).sfn)\
437 else if ((_x).sfn == (_y).sfn)\
439 if ((_x).subframe > (_y).subframe)\
449 #define RGSCH_INCR_SUB_FRAME_EMTC(x,y) do { \
450 if ((x.subframe += y) > 9) {\
451 x.sfn += (x.subframe/10); x.subframe = (x.subframe%10);\
452 if (x.sfn >= RGSCH_MAX_SFN) \
454 x.hSfn=(x.hSfn + 1)%RGSCH_MAX_SFN; \
455 x.sfn %= RGSCH_MAX_SFN; \
462 #define RGSCH_SUBFRAME_INDEX(x) ( ( ((x).sfn) * RGSCH_NUM_SUB_FRAMES_5G ) + (x).slot )
464 /* Note: In RGSCH_CALC_SF_DIFF, _time1 should be the latest */
465 #define RGSCH_CALC_SF_DIFF(_time1, _time2)\
466 (_time1.sfn*RGSCH_NUM_SUB_FRAMES_5G+_time1.slot) < (_time2.sfn*RGSCH_NUM_SUB_FRAMES_5G +_time2.slot)?\
467 (_time1.sfn*RGSCH_NUM_SUB_FRAMES_5G+_time1.slot) -\
468 (_time2.sfn*RGSCH_NUM_SUB_FRAMES_5G+_time2.slot) : \
469 (_time1.sfn*RGSCH_NUM_SUB_FRAMES_5G+_time1.slot) - (_time2.sfn*RGSCH_NUM_SUB_FRAMES_5G +_time2.slot)\
472 /*LTE_L2_MEAS_PHASE2*/
473 #define RGSCH_CALC_SFN_SF_DIFF(_time1,_sfnCycle, _time2)\
474 (((_time1.sfn+RGSCH_MAX_SFN * _sfnCycle)*RGSCH_NUM_SUB_FRAMES_5G) + _time1.slot -\
475 (_time2.sfn*RGSCH_NUM_SUB_FRAMES_5G + _time2.slot))
477 #define RG_SCH_ADD_TO_CRNT_TIME(crntTime, toFill, incr) \
478 if ((crntTime.slot + (incr)) >= RGSCH_NUM_SUB_FRAMES_5G) \
479 toFill.sfn = (crntTime.sfn + \
480 (crntTime.slot + (incr)) / RGSCH_NUM_SUB_FRAMES_5G); \
482 toFill.sfn = crntTime.sfn; \
483 toFill.slot = (crntTime.slot + (incr)) % RGSCH_NUM_SUB_FRAMES_5G; \
484 if (toFill.sfn >= RGSCH_MAX_SFN) \
486 toFill.sfn = toFill.sfn % RGSCH_MAX_SFN; \
489 #define RGSCHDECRFRMCRNTTIME(_crntDl, _prevDl, decr) \
493 _subframe = _crntDl.sfn * RGSCH_NUM_SUB_FRAMES_5G + _crntDl.slot; \
494 _subframe = _subframe - decr; \
497 _subframe = (RGSCH_MAX_SFN * RGSCH_MAX_SFN * RGSCH_NUM_SUB_FRAMES_5G) + _subframe; \
499 _subframe = _subframe % RGSCH_MAX_SUBFRM_5G; \
500 _prevDl.sfn = _subframe / RGSCH_NUM_SUB_FRAMES_5G; \
501 _prevDl.slot = _subframe % RGSCH_NUM_SUB_FRAMES_5G; \
504 /* ccpu00133109: Removed RGSCHSUBFRMCRNTTIME as it is not giving proper output
505 * if diff is more than 10. Instead using RGSCHDECRFRMCRNTTIME() as it is
506 * serving the purpose */
508 #define RGSCHCPYTIMEINFO(src, dst) \
510 dst.slot = src.slot; \
513 #define RGSCH_TIMEINFO_SAME(x, y) (((x).sfn == (y).sfn) && ((x).slot == (y).slot))
515 /* Added support for SPS*/
517 /*Compares time difference and returns 0 if same, - 1 if x < y, 1 if x > y
518 Special check for RGSCH_MAX_SFN is to take care of the wrap around case */
519 #define RGSCH_TIMEINFO_CMP(_x, _y, _ret)\
521 if (RGSCH_TIMEINFO_SAME(_x, _y))\
523 else if ((_x).sfn > (_y).sfn)\
525 else if ((_x).sfn < (_y).sfn)\
527 else if ((_x).sfn == (_y).sfn)\
529 if ((_x).slot > (_y).slot)\
538 #define RGSCH_INCR_SUB_FRAME(x,y) do { \
539 if ((x.slot += y) > (RGSCH_NUM_SUB_FRAMES_5G - 1)) {\
540 x.sfn += (x.slot/RGSCH_NUM_SUB_FRAMES_5G); x.slot = (x.slot%RGSCH_NUM_SUB_FRAMES_5G);\
541 if (x.sfn >= RGSCH_MAX_SFN) \
543 x.sfn %= RGSCH_MAX_SFN; \
550 #endif /* EMTC_ENABLE */
552 /* RACHO : TRUE if rapId is a ded preamble */
553 #define RGSCH_IS_DEDPRM(cell, rapId) ((rapId) >= (cell->rachCfg.numRaPreamble))
555 #define rgSchPBuf(inst) rgSchCb[inst].rgSchInit.prntBuf
557 /* Debug Prints for MAC */
559 #define RGSCHDBGERRNEW(inst, _args) \
560 DBGP(&rgSchCb[inst].rgSchInit, RGSCHLAYERNAME, DBGMASK_ERR, _args)
561 #define RGSCHDBGINFONEW(inst, _args) \
562 DBGP(&rgSchCb[inst].rgSchInit, RGSCHLAYERNAME, DBGMASK_INFO, _args)
563 #define RGSCHDBGPRM(inst, _args) UNUSED(inst);
564 #define RGSCHDBGERR(inst, _args) \
565 DBGP(&rgSchCb[inst].rgSchInit, RGSCHLAYERNAME, DBGMASK_ERR, _args)
566 #define RGSCHDBGINFO(inst, _args) UNUSED(inst);
568 #define RGSCHDBGERRNEW(inst, _args)
569 #define RGSCHDBGINFONEW(inst, _args)
570 #define RGSCHDBGPRM(inst, _args)
571 #define RGSCHDBGERR(inst, _args)
572 #define RGSCHDBGINFO(inst, _args)
573 #endif /* #ifdef DEBUGP */
575 #define RGSCH_IS_GBR_BEARER(cfgdGbr) ((cfgdGbr) != 0)
578 #define RGSCH_ARRAY_BOUND_CHECK(_inst, _array, _idxVal) \
579 if((_idxVal) >= (sizeof(_array)/sizeof(_array[0]))) \
581 RGSCHDBGERRNEW((_inst), (rgSchPBuf(_inst), "Array Bound Check Failed"));\
585 #define RGSCH_NULL_CHECK(_inst, _ptr ) \
586 if((_ptr) == NULLP) \
588 RGSCHDBGERRNEW((_inst), (rgSchPBuf(_inst), "Null Pointer detected"));\
591 #define RGSCH_ARRAY_BOUND_CHECK_WITH_POS_IDX(_inst, _array, _idxVal) \
592 if(((_idxVal) >= (sizeof(_array)/sizeof(_array[0])))|| (_idxVal < 0)) \
594 RGSCHDBGERRNEW((_inst), (rgSchPBuf(_inst), "Array Bound Check Failed"));\
598 #define RGSCH_PFS_AMBR_ARRAY_BOUND_CHECK(_inst, _pfsCell, _qId, _ue ) \
600 if (_ue->csgMmbrSta == TRUE)\
602 RGSCH_ARRAY_BOUND_CHECK(_inst, _pfsCell->txQueues.prioAmbrLst, _qId);\
606 RGSCH_ARRAY_BOUND_CHECK(_inst, _pfsCell->txQueues.normAmbrLst, _qId);\
610 #define RGSCH_ARRAY_BOUND_CHECK(_inst, _array, _idxVal)
611 #define RGSCH_NULL_CHECK( _inst, _ptr )
612 #define RGSCH_ARRAY_BOUND_CHECK_WITH_POS_IDX(_inst, _array, _idxVal)
613 #define RGSCH_PFS_AMBR_ARRAY_BOUND_CHECK(_inst, _pfsCell, _qId, _ue )
616 /* Macro to free the message buffer and initialize it to zero */
617 /***********************************************************
619 * Name : RGSCH_FREE_MSG
621 * Desc : Macro to free the message buffer and initialize it to zero
623 * Input : mBuf - message buffer pointer to be retunrned
629 **********************************************************/
630 #define RGSCH_FREE_MSG(_buf)\
632 if (NULLP != (_buf)) \
634 ODU_PUT_MSG_BUF((_buf)); \
639 #define RGSCH_FREE_MEM(_mem)\
641 if (NULLP != (_mem)) \
643 cmFreeMem((Ptr)(_mem)); \
647 /***********************************************************
649 * Name : RGSCH_DROP_RGUDDATREQ_MBUF
651 * Desc : Macro to free the message buffers and initialize them to zero
653 * Input : _datreq - Dedicated Data Request pointer which has mBufs
660 **********************************************************/
662 #define RGSCH_DROP_RGUDDATREQ_MBUF(_datReq)\
664 uint32_t idx1,idx2,idx;\
665 if (_datReq != NULLP)\
667 for (idx=0; idx < _datReq->numLch; idx++)\
669 for (idx1=0; idx1 < RGU_MAX_PDUSET; idx1++)\
671 for (idx2=0; idx2 < _datReq->lchData[idx].pdu[idx1].numPdu; idx2++)\
673 RGSCH_FREE_MSG(_datReq->lchData[idx].pdu[idx1].mBuf[idx2]);\
679 /***********************************************************
681 * Name : RGSCH_DROP_RGUCDATREQ_MBUF
683 * Desc : Macro to free the message buffers and initialize them to zero
685 * Input : _datreq - Common Data Request pointer which has mBufs
692 **********************************************************/
693 #define RGSCH_DROP_RGUCDATREQ_MBUF(_datReq)\
696 if (_datReq != NULLP)\
698 for (idx1 = 0; idx1 < RGU_MAX_PDUSET; idx1++)\
700 if (_datReq->pdu != NULLP)\
702 RGSCH_FREE_MSG(_datReq->pdu[idx1]);\
709 /* Macros for memory region and pool determination */
710 #define RGSCH_GET_MEM_REGION(rgCb) (rgCb.rgInit.region)
711 #define RGSCH_GET_MEM_POOL(rgCb) (rgCb.rgInit.pool)
714 #define RGSCH_UPD_HQAN_FDBKTIME(_tbInfo, _dlSf, _timingInfo) \
718 (_tbInfo)->fdbkTime.sfn = (_timingInfo.sfn + \
719 _dlSf->dlFdbkInfo.sfnOffset) % RGSCH_MAX_SFN; \
720 (_tbInfo)->fdbkTime.slot = _dlSf->dlFdbkInfo.slot; \
721 (_tbInfo)->timingInfo = _timingInfo; \
724 #define RGSCH_UPD_ANINFO_WITH_HQ(_anInfo, _tbInfo) \
727 _anInfo->sfn = (_tbInfo)->fdbkTime.sfn; \
728 _anInfo->slot = (_tbInfo)->fdbkTime.slot; \
729 _anInfo->latestMIdx = (_tbInfo)->m; \
731 /* Support for iPhich=1 for TDD*/
733 #define RGSCH_UPD_PHICH(_ulDlCfgIdx, _subframe, _hqProc) \
734 if(_ulDlCfgIdx == 0 && ((_subframe == 4) ||( _subframe == 9)))\
736 _hqProc->iPhich = 1;\
740 _hqProc->iPhich = 0;\
745 /* MUX related macros */
746 #define RGSCH_HDR_TYPE_CRES 1
747 #define RGSCH_HDR_TYPE_TA 2
749 #define RGSCH_SDU_SHDR_LEN 1
750 #define RGSCH_CE_SHDR_LEN 1
751 #define RGSCH_CRES_LEN 6
752 #define RGSCH_TA_LEN 1
753 #define RGSCH_CRES_ELM_LEN RGSCH_CE_SHDR_LEN+RGSCH_CRES_LEN
754 #define RGSCH_TA_ELM_LEN RGSCH_CE_SHDR_LEN+RGSCH_TA_LEN
756 #define RGSCH_CRES_LCID_IDX 0x1C
757 #define RGSCH_TA_LCID_IDX 0x1D
759 #define RGSCH_MAX_SUBFRAMES_IN_SFN 9
760 #define RGSCH_MAX_SFN 1024
761 #define RGSCH_NUM_SUB_FRAMES 10
763 #define RGSCH_NUM_SUB_FRAMES_5G 50
766 #define RGSCH_ULCTRL_RECP_DIST 7
768 #define RGSCH_ULCTRL_RECP_DIST 4
770 /* Definig the Macro for the Size SF alloc Info Structure
771 * The Value is defines the number of subframes the Alloc Info is maintained
772 * The SF alloc Info is used to send the scheduled Allocation Info
773 * to MAC from Scheduler
775 #define RGSCH_SF_ALLOC_SIZE 4
777 /* Defining new MACRO for DL subframes */
778 #define RGSCH_NUM_DL_slotS 20
779 /* Define for the block size for memory allocation */
780 #define RGSCH_BLKSZ 2048
782 /* Defines for RGU Statistics types */
783 #define RGSCH_RGU_SDU_DROP 1
784 #define RGSCH_RGU_SDU_RCVD 2
786 /* MACROS for General Statistics */
787 #define RGSCH_CFG_ADD 1
788 #define RGSCH_CFG_DEL 2
790 #define RGSCH_HQ_FDB_IND_CB_TYPE_HQ_ENT 1
791 #define RGSCH_HQ_FDB_IND_CB_TYPE_RA_CB 2
793 /* The value of RGSCH_TDD_MAX_P_VAL is 4, since we need the table for
794 * P+1 value the below Macro is defined and used
796 #define RGSCH_TDD_MAX_P_PLUS_ONE_VAL 5
797 #define RGSCH_TDD_MAX_FREQ_RSRC 6
800 * RG_TFU_HQ_IND_DELTA is replaced with
801 * TFU_HQFBKIND_ULDELTA and moved into envopt.h.
804 /* Macro for selecting the subframe index to be deleted */
806 #define RGSCH_RLS_SF_IDX (RG_SCH_CMN_HARQ_INTERVAL + TFU_HQFBKIND_ULDELTA)
808 /* Macro for max random access responses */
809 #define RGSCH_MAX_RA_RSP_ALLOC 4
811 /* Value used to set nDmrs in uplink grant if nDmrs is not applicable */
812 #define RGSCH_INVALID_NDMRS 10
814 /* comcodsepa : start */
815 #define RGSCH_MIN(x, y) ((x) <= (y) ? (x) : (y))
816 #define RGSCH_MAX(x, y) ((x) >= (y) ? (x) : (y))
817 #define RGSCH_CEIL(x, y) (((x) + (y)-1) / (y))
818 #define RGSCH_FLOOR(x, y) ((x) / (y))
819 #define RGSCH_CEILING(x) (((x) - (uint8_t)(x)) ? (uint8_t)(x+1) : (uint8_t)x)
820 #define RGSCH_DIV_ROUND(x, y) (((x) + (y)/2) / (y))
822 #define RGSCH_RARSP_WAIT_PERIOD 3
823 #define RGSCH_INCR_FRAME(x) x = ((x) + 1) & 0x03ff
825 #define RG_SCH_TDD_DL_SUBFRAME 1
826 #define RG_SCH_TDD_UL_SUBFRAME 2
827 #define RG_SCH_TDD_SPL_SUBFRAME 3
829 #define RG_SCH_MAX_DAI_IDX 4
830 #define RG_SCH_DAI_MAX_BIT_VAL 3
831 /* Since DAI bit value is stored and its range is 0-3 in SCH,
832 * So Invalid is Set to 0xFF */
834 #define RG_SCH_INVALID_DAI_VAL 0x00
835 /* Valid Range is 0-8, So Invalid is Set to 99 */
836 #define RG_SCH_INVALID_M_VAL 0xFF
838 /* Below macro used to get the DAI value (1 -4) for the total DL transmission
841 #define RG_SCH_GET_DAI_VALUE(dai) ((((dai) - 1) & RG_SCH_DAI_MAX_BIT_VAL) + 1)
842 /* below Macro indicates the max number of DL transmissions that can be made in
843 * a single FeedBak period
845 #define RG_SCH_MAX_NUM_EXPECTED_ACKS 9
846 /* The below macro indicates the max number of feedback report
848 #define RG_SCH_NUM_FDBK_VALUE 3
850 #define RG_SCH_ULIDX_LSB 1
851 #define RG_SCH_ULIDX_MSB 2
852 #define RG_SCH_ULIDX_BOTH 3
854 #ifdef MAC_5GTF_UPDATE
855 #define RGSCH_ONE_RAR_SIZE 8
857 #define RGSCH_ONE_RAR_SIZE 7
860 #define RGSCH_MSG4_HDRSIZE 1
861 #define RGSCH_CONT_RESID_SIZE 7
864 #define RGSCH_CCCH_SDU_HDRSIZE 1
865 #define RGSCH_CONTRES_EXP 0xffff
867 /* Corrected allocation for common channels */
868 #define RGSCH_ONE_BIHDR_SIZE 1
870 #define RGSCH_TA_SIZE 2
872 #define RGSCH_SCELL_ACT_CE_SIZE 2
873 #define RGSCH_INVALID_PUCCH3_RES 550
876 #define RGSCH_GET_RAR_BYTES(x) ((x) * RGSCH_ONE_RAR_SIZE)
878 #define RG_SCH_CMN_MEAS_GAPPRD40 40
879 #define RG_SCH_CMN_MEAS_GAPPRD80 80
880 #define RG_MEAS_GAPPRD_40 40
881 #define RG_MEAS_GAPPRD_80 80
882 #define RG_MAX_NUM_DLSF 10 /* Maximum number of Subframes */
883 #define RG_MEASGAP_INACTIVE 0x01
884 #define RG_ACKNAKREP_INACTIVE 0x02
885 #define RG_PDCCHODR_INACTIVE 0x04
886 #define RG_DRX_INACTIVE 0x08 /*UE is DRX inactive */
888 #define RG_SCH_DRX_UL 0 /*UE is DRX active in uplink*/
889 #define RG_SCH_DRX_DL 1 /*UE is DRX active in downlink*/
890 /*Fix:Inform UE delete to scheduler*/
891 #define RG_MACUEDEL_INACTIVE 0x10
892 /* Fix : syed set UE inactive for scheduling if it is not completely
894 #define RG_HQENT_INACTIVE 0x20
896 #define RG_SCH_TMR_ACKNACK_REP 1 /* Timer event for ACK NACK Rep */
897 #define RG_SCH_TMR_MEASGAP 2 /* Timer event for Measurement gap */
898 #define RG_SCH_TMR_UL_ACKNACK 3 /* Timer event for Ul Inactivity due to ack-nack */
899 #define RG_SCH_TMR_DL_ACKNACK 4 /* Timer event for Dl Inactivity due to ack-nack */
900 #define RG_SCH_TMR_UL_MEASGAP 5 /* Timer event for Ul Inactivity due to Measurement gap */
901 #define RG_SCH_TMR_DL_MEASGAP 6 /* Timer event for Dl Inactivity due to Measurement gap */
902 #define RG_SCH_TMR_TA 7 /* Timer event for Timing Alignment */
903 /* Added periodic BSR timer */
905 #define RG_SCH_TMR_BSR 8 /* Timer event for Periodic BSR */
907 #define RG_SCH_TMR_BSR 8 /* Timer event for Periodic BSR */
910 #define RG_SCH_TMR_TXMODE_TRNSTN 9 /* Timer event for TX Mode Transition */
912 #define RG_SCH_TMR_SCELL_DEACT 10 /* Timer event for Secondary Cell Deactivation */
913 #define RG_SCH_TMR_SCELL_ACT_DELAY 11 /* Timer event for Secondary Cell Activation Delay */
916 #define RG_SCH_TXMODE_TRANS_TIMER 1000 /* Timer length for Tx Mode Transition
919 #define RG_SCH_TMR_DLINACTV 2 /* Timer event for DL Inactivity */
920 #define RG_SCH_MEAS_GAP_LEN 6 /* Timer event for measurement GAP */
922 #define RGSCH_SCELL_DEACT_TMR_INFINITY_VAL 3840 /* In millisecond, thrice the maximum
923 value of deactivation timer */
925 #define RG_SCH_DRX_DL_DELTA (RG_DL_DELTA) /*!< look at timer queue
930 /* Introduced UL control timing delta in FDD */
931 #define RG_SCH_DRX_UL_DELTA (TFU_ULCNTRL_DLDELTA)
932 /*Assigning RG_SCH_DRX_MAX_DELTA to the higher delta of uplink delta and
934 #define RG_SCH_DRX_MAX_DELTA ((RG_SCH_DRX_DL_DELTA < RG_SCH_DRX_UL_DELTA)?\
935 RG_SCH_DRX_UL_DELTA:RG_SCH_DRX_DL_DELTA)
937 #define RG_SCH_NO_DELTA 0 /*Consider no delta */
938 /** @brief The lenght of array we maintain to track DRX Cycles.
940 * The periodicity of LONG DRX Cycle has a maximum value of 2560. The ideal and
941 * the fastest way would be to have an array of this size. However having an
942 * Array this large would make the cellCb a huge structure and may have
943 * performance implications as well.
944 * Hence the defined size and lower values are a multiple of the larger sizes.
945 * A distance based approach is used to get to the correct value.
946 * @sa RgSchDRXCellCb.
947 * For decreased processing hit this value maybe increased to
948 * [320, 640, 1024, 2560]
950 #define RG_SCH_MAX_DRXQ_SIZE 256 /*!< Length of the DRQ queue maintained
951 at the cell level. */
952 #define RG_SCH_MIN_HARQ_RTT 8 /*!< Minimum round trip time for Harq
955 #define RG_SCH_MIN_UL_HARQ_RTT 4 /*!< Minimum round trip time for UlHarq feedback */
958 /* MASKs for tracking DRX activity */
960 #define DRX_UE_INACTIVE 0xFFFFFFFF
961 #define DRX_INVALID 0xFFFF
962 #define DRX_TMR_EXPRD -1
964 #define RG_SCH_DRX_SR_BITMASK 0x00000001 /*DRX SR Bitmask*/
965 #define RG_SCH_DRX_RA_BITMASK 0x00000002 /*DRX RA Bitmask*/
966 #define RG_SCH_DRX_ONDUR_BITMASK 0x00000004 /*DRX on-duration bitmask */
967 #define RG_SCH_DRX_INACTVTMR_BITMASK 0x00000008 /*DRX inactive timer bitmask */
968 /* DLHQ Bitmask should always be the last */
969 #define RG_SCH_DRX_DLHQ_BITMASK 0x00000010 /*DRX DL harq bitmask*/
972 #define RG_SCH_DRX_ULHQ_BITMASK (RG_SCH_DRX_DLHQ_BITMASK << 8)
976 #define RG_SCH_MAX_SCELL (CM_LTE_MAX_CELLS - 1) /*!< Max number of sec cells per ue.
977 -1 done for Primary cell */
978 #define RG_SCH_ACTIVATION_COUNT 10 /*!< Maximum count for SCELL Activation */
982 /*if any bit in the mask is 0, ue is active */
983 #define RG_SCH_DRX_DL_IS_UE_ACTIVE(drxCb)\
984 (drxCb->drxDlInactvMask ^ DRX_UE_INACTIVE)
986 /*if any bit in the mask is 0, ue is active */
987 #define RG_SCH_DRX_UL_IS_UE_ACTIVE(drxCb)\
988 (drxCb->drxUlInactvMask ^ DRX_UE_INACTIVE)
989 /*if UE is in DL DRX on-duration */
990 #define RG_SCH_DRX_DL_IS_UE_ONDUR_INACTIVE(drxCb) \
991 (drxCb->drxDlInactvMask & RG_SCH_DRX_ONDUR_BITMASK)
992 /*if UE is in UL DRX onduration */
993 #define RG_SCH_DRX_UL_IS_UE_ONDUR_INACTIVE(drxCb) \
994 (drxCb->drxUlInactvMask & RG_SCH_DRX_ONDUR_BITMASK)
995 /*if ue is in DL DRX Inactive timer period */
996 #define RG_SCH_DRX_DL_IS_UE_INACTVTMR_INACTIVE(drxCb) \
997 (drxCb->drxDlInactvMask & RG_SCH_DRX_INACTVTMR_BITMASK)
999 /*if ue is in UL DRX Inactive timer period */
1000 #define RG_SCH_DRX_UL_IS_UE_INACTVTMR_INACTIVE(drxCb) \
1001 (drxCb->drxUlInactvMask & RG_SCH_DRX_INACTVTMR_BITMASK)
1003 #define RG_SCH_DRX_GET_CELL(_cell) ((_cell)->drxCb)
1005 #define RG_SCH_DRX_GET_UE(_ue) ((_ue)->drxCb)
1006 /*get DRX DL HARQ */
1007 #define RG_SCH_DRX_GET_DL_HQ(_hqProc) &((_hqProc)->drxCb)
1013 #define RGSCH_MAX_SFCFG 2 /* refer to rgSchDrxDlSfTddcfg in rg_sch.h to
1014 understand why this is 2 */
1015 #define RGSCH_MAX_TDD_CFG 7
1017 #define RGSCH_NUM_SFRAMES 10 /* number of subframes in a RF */
1019 #endif /* LTE_TDD */
1022 /* Introduced UL control timing delta in FDD */
1023 /* Number of subframes in advance UL control (DCI/PHICH) should be sent from SCH */
1024 #define TFU_ULCNTRL_DLDELTA (RG_SCH_CMN_HARQ_INTERVAL - TFU_CRCIND_ULDELTA)
1025 #endif/*ndef LTE_TDD*/
1027 /* Added for SI Enhancement*/
1029 /* SI Re-configuration related bit masks */
1030 #define RGSCH_SI_DFLT 0 /* Default */
1031 #define RGSCH_SI_SICFG_UPD (1<<0) /* SI CFG Updated */
1032 #define RGSCH_SI_MIB_UPD (1<<1) /* MIB CFG Updated */
1033 #define RGSCH_SI_SIB1_UPD (1<<2) /* SIB1 CFG Updated */
1034 #define RGSCH_SI_SI_UPD (1<<3) /* SI PDU CFG Updated */
1035 #define RGSCH_SI_SIB1_PWS_UPD (1<<4) /* SIB1 PWS CFG Updated */
1037 #define RGSCH_SI_EMTC_TYPE_SIB1_BR_UPD (1<<5) /* EMTC SIB1 BR CFG Updated */
1038 #define RGSCH_SI_EMTC_TYPE_SI_UPD (1<<6) /* EMTC SI PDU CFG Updated */
1040 /*SI Scheduling Specific */
1041 #define RGSCH_MIB_PERIODICITY 4 /*!< MIB Periodicity */
1042 #define RGSCH_SIB1_PERIODICITY 8 /*!< SIB1 Periodicity */
1043 #define RGSCH_SIB1_RPT_PERIODICITY 2 /*!< SIB1 Repeat Periodicity */
1044 #define RGSCH_MIB_TX_SF_NUM 0 /*!< MIB TX SF Number */
1045 #define RGSCH_SIB1_TX_SF_NUM 5 /*!< SIB1 TX SF Number */
1046 /*rg009.lpr-ccpu00116647 - Added siId validation for lower limit */
1047 #define RGSCH_SI_SIID_LOWER_LMT 1 /*!< Least usabel siId number */
1048 #define RGR_MAX_NUM_WARNING_SI 3 /*!< Max no. of Warning SI*/
1049 #define RGSCHCHKNUPDSIPDU(_CRNTINFO,_NEWINFO,_NEWPDU,_BITMSK, _BITFLG) \
1052 if(NULLP == _CRNTINFO)\
1054 _CRNTINFO = _NEWPDU; \
1058 if(NULLP != _NEWINFO)\
1060 RGSCH_FREE_MSG(_NEWINFO);\
1063 _NEWINFO = _NEWPDU;\
1064 _BITMSK |= _BITFLG;\
1068 #define RGSCH_SET_SI_INFO(_CRNTPTR,_NEWPTR)\
1071 if(NULLP != _CRNTPTR)\
1072 RGSCH_FREE_MSG(_CRNTPTR);\
1073 _CRNTPTR = _NEWPTR;\
1076 #endif /*RGR_SI_SCH */
1077 /* Added changes of TFU_UPGRADE */
1079 /***********************************************************************
1081 ***********************************************************************/
1082 /* Array Based List size to store next active Periodic CQI, SRS and SR
1083 tranmission instances at cell Cb */
1085 /* Periodic CQI max periodicity = 160 Ref: 36.213 (Table 7.2.2-1A For FDD
1087 /* SRS max periodicity = 320 Ref: 36.213 (Table 8.2-1) */
1088 /* SR max periodicity = 80 Ref: 36.213 (Table 10.1-5 ) */
1089 /* Modifying Queue Size from 320 to 321. 320 is a possible periodicity for RI
1090 * and SRS. If it is 320, then while moving to next occassion it is being added
1091 * same queue. If more than one node is available in the queue then same UE's
1092 * node is adding to the same queue and processed in same TTI. This is happening
1093 * in infinite loop. Hence modifying it to 321, which is not a possible periodicity.
1095 /* Changing this back to 320 as it was causing
1096 * problem in TDD attach and stability
1098 #define RG_SCH_PCQI_SRS_SR_TRINS_SIZE 320
1103 /* Ref 36.213 Table 8.2-2: */
1104 #define RG_SCH_ISRS_MAX_SUPP 644
1105 /* Note: <= 10 ms periodicity is not supported */
1106 #define RG_SCH_ISRS_MIN_SUPP 10
1108 /* Ref 36.213 Table 7.2.2-1C */
1110 #define RG_SCH_ICQI_MAX_SUPP 315
1111 #define RG_SCH_ICQI_MIN_SUPP 0
1114 /* Ref 36.213 Table 8.2-1: */
1115 #define RG_SCH_ISRS_MAX_SUPP 636
1116 /* Note: <= 10 ms periodicity is not supported */
1117 #define RG_SCH_ISRS_MIN_SUPP 0
1120 #define RG_SCH_ICQI_MAX_SUPP 541
1121 #define RG_SCH_ICQI_MIN_SUPP 0
1123 #define RG_SCH_ICQI_RESV_FDD 317
1127 /*Refer Table 7.2.1-5: for max BW configuration M=6*/
1128 #define RG_SCH_MAX_NUM_UE_SEL_SUBBANDS 6
1130 /*Refer Table 7.2.1-5: for max BW configuration k =4, ceil(110/4) = 28*/
1131 #define RG_SCH_MAX_TOT_NUM_SUBBANDS 28
1133 /* 36.213 Table 7.2.2-1B: */
1134 #define RG_SCH_IRI_MAX_SUPP 965
1135 #define RG_SCH_IRI_MIN_SUPP 0
1137 /*K value in CQI table min and max values*/
1138 #define RG_SCH_CQI_K_MAX 4
1139 #define RG_SCH_CQI_K_MIN 1
1141 #define RG_SCH_PUCCH_RES_MAX_SUPP 1185 /* TODO: Need to check value */
1143 #define RG_SCH_IRI_MAX_SUPP 965
1146 #define RG_SCH_ISR_MAX_SUPP 154
1147 #define RG_SCH_ISR_MIN_SUPP 0
1149 #define RG_SCH_SRS_FREQDOM_POS_MIN 0
1150 #define RG_SCH_SRS_FREQDOM_POS_MAX 23
1152 #define RG_SCH_SRS_TXCOMB_MIN 0
1153 #define RG_SCH_SRS_TXCOMB_MAX 1
1155 #define RG_SCH_SR_RES_IDX 2047 /* TODO: Need to check */
1156 /*Reference: 36.213 Table:7.2.2-1A */
1157 #define RG_SCH_CQIPMI_CFGIDX_MAX_FDD 10
1159 /* Reference: 36.213 Table:7.2.2-1C */
1160 #define RG_SCH_CQIPMI_CFGIDX_MAX_TDD 7
1163 /* Note: RI table is same for FDD and TDD */
1164 /*Reference: 36.213 Table:7.2.2-1B */
1165 #define RG_SCH_RI_CFGIDX_MAX 6
1168 /*Reference: 36.213 Table:7.2.2-2 */
1169 #define RG_SCH_BW_SUBSZ_BWPARTS_MAX 5
1171 /* Reference : 36.213 Table 8.2-1 */
1172 #define RG_SCH_SRS_ISRS_INDX_MAX_FDD 8
1174 /* Reference : 36.213 Table 8.2-2 */
1175 #define RG_SCH_SRS_ISRS_INDX_MAX_TDD 7
1177 /* Reference : 36.213 Table 10.1-5 */
1178 /* Note: SR is same table for TDD and FDD */
1179 #define RG_SCH_ISR_INDX_MAX 5
1182 /* This use used to mark as invalid index value */
1183 #define RG_SCH_INVALID_IDX 0xffff
1185 /*ccpu00116923 - ADD - SRS present support*/
1186 #define RGSCH_CELLSP_SRS_SF_CONFIGS 16
1188 /*Used for Periodic CQI. */
1189 #define RG_SCH_GET_CQI_J_VAL(_dlBw, _j) \
1195 else if(_dlBw >= 27)\
1199 else if(_dlBw >= 11 )\
1209 #define RG_SCH_GET_CQI_K_VAL(_dlBw, _k) \
1215 else if(_dlBw >= 27)\
1219 else if(_dlBw >= 11 )\
1230 #define RG_SCH_GET_SBCQI_M_K_VAL(_dlBw, _m, _k) \
1237 else if(_dlBw >= 27)\
1242 else if(_dlBw >= 11 )\
1255 /* To Get the Idx to pCqiSrsSrLst in RgSchCellCb*/
1256 #define RG_SCH_GET_IDX_PCQISRSSR(_time, _indexId)\
1258 (_indexId) = (_time.sfn)* RGSCH_NUM_SUB_FRAMES_5G + (_time.slot); \
1259 (_indexId) = (_indexId)%RG_SCH_PCQI_SRS_SR_TRINS_SIZE;\
1262 #define RG_SCH_GET_UE_CELL_CQI_CB(_ueCb, _cell) &((_ueCb)->cellInfo\
1263 [_ueCb->cellIdToCellIdxMap[RG_SCH_CELLINDEX(_cell)]]->cqiCb)
1265 /* To Get UE Next Active Periodic RI Idx to the table pCqiSrsSrLst */
1266 /* Caller should check the periodic RI is RG_SCH_INVALID_IDX or not */
1267 #define RG_SCH_GET_IDX_RI(_ueCb, _cell, _riIdx)\
1269 (_riIdx) = (_ueCb)->cellInfo[_ueCb->cellIdToCellIdxMap\
1270 [RG_SCH_CELLINDEX(_cell)]].cqiCb.nRiTrIdx;\
1274 /* To Get UE Next Active SR Idx to the table pCqiSrsSrLst */
1275 /* Caller should check the periodic SR is RG_SCH_INVALID_IDX or not */
1276 #define RG_SCH_GET_IDX_SR(_ueCb, _srIdx)\
1278 (_srIdx) = (_ueCb)->srCb..nSrTrIdx;\
1281 /* To Get UE Next Active SRS Idx to the table pCqiSrsSrLst */
1282 /* Caller should check the SRS is RG_SCH_INVALID_IDX or not */
1283 #define RG_SCH_GET_IDX_SRS(_ueCb, _ssrIdx)\
1285 (_srsIdx) = (_ueCb)->srsCb..nSrsTrIdx;\
1290 /* To Get UE Next Active Periodic CQI Idx to the table pCqiSrsSrLst */
1291 /* Caller should check the periodic CQI is RG_SCH_INVALID_IDX or not */
1292 #define RG_SCH_GET_IDX_PCQI(_ueCb, _cell, _pCqiIdx)\
1294 (_pCqiIdx) = (_ueCb)->cellInfo[_ueCb->cellIdToCellIdxMap\
1295 [RG_SCH_CELLINDEX(_cell)]].cqiCb.nCqiTrIdx;\
1299 * @def RG_SCH_PARSE_MULTI_PMI
1301 * This macro is used to parse RAW PMI
1304 * @param[in] _bitLen bit length
1305 * @param[in] _totPmiBitLen total PMI bit length
1306 * @param[in] _ueCb ue control block
1307 * @param[in] _revArray reverse array
1308 * @param[out] _psMode12 Period mode 12
1309 * @param[out] _sbOffst subband offset
1312 #define RG_SCH_PARSE_MULTI_PMI(_bitLen, _totPmiBitLen, _psMode12,\
1313 _acqiCb, _revArray,_sbOffst )\
1316 for(_loop =0; _loop<(_totPmiBitLen/_bitLen); _loop++)\
1318 (_psMode12)->subbandArr[_loop].pmi = (uint8_t)rgSCHUtlParse(_revArray,\
1319 _sbOffst,(uint8_t)(_sbOffst+_bitLen), (uint8_t)TFU_MAX_CQI_BYTES);\
1321 (_psMode12)->subbandArr[_loop].subBand.numRb = (_acqiCb).k;\
1322 (_psMode12)->subbandArr[_loop].subBand.rbStart = \
1323 (uint8_t) ((_acqiCb).k * (_loop));\
1327 /* Removed the MACRO RG_SCH_GET_PERIODICITY_TBL
1328 * The function rgSCHUtlGetPcqiSrsSrRiTbl will do the same task as this
1337 /* Half Duplex Specific defines */
1338 /* Number of subframes information managed */
1339 #define RG_SCH_HDFDD_NUMSFINFO 20
1340 /* Subframe States */
1341 #define RG_SCH_HDFDD_NOSCHD 0x00
1342 #define RG_SCH_HDFDD_DLDATA 0x01
1343 #define RG_SCH_HDFDD_DLCNTRL 0x02
1344 #define RG_SCH_HDFDD_UL 0x04
1346 #define RG_SCH_HDFDD_INVSFN (RGSCH_MAX_SFN + 100) /* Add some arbitrary number to make it invalide */
1348 #define RG_SCH_HDFDD_GRDTIM_DUR 1
1349 #define RG_SCH_HDFDD_DELTA 10
1351 /* To get the BCH is present or not at subframe */
1352 #define RG_SCH_BCCH_TRUE_FALSE( _time, _bchTrue)\
1355 /* Call the API is provided by SI module */ \
1358 /* Mark the subframe */
1359 #define RG_SCH_HDFDD_MARKSTATE(_ueCb, _state, _sfn, _sfi)\
1361 (_ueCb)->hdFddCb->subfrm[(_sfi)].subFrmDir = _state;\
1362 (_ueCb)->hdFddCb->subfrm[(_sfi)].sfn = _sfn;\
1365 /* validate the ueCb and mark */
1366 #define RG_SCH_HDFDD_VLDTANDMARK(_ueCb, _state, _sfn, _sfi)\
1368 if( (_ueCb) != NULLP && (_ueCb)->hdFddCb)\
1370 RG_SCH_HDFDD_MARKSTATE(_ueCb, _state, _sfn, _sfi);\
1374 /* Get SFN and SFI from tti numbers */
1375 #define RG_SCH_HDFDD_GETPTI(_time) ((((_time).sfn * RGSCH_NUM_SUB_FRAMES + \
1376 (_time).subframe) + RG_SCH_HDFDD_DELTA) % RG_SCH_PCQI_SRS_SR_TRINS_SIZE)
1378 /* Get SFI and SFN from given time and subframe offset */
1379 #define RG_SCH_HDFDD_GETSFN(_sfn, _time, _offset)\
1380 rgSCHHdFddGetSfn(&(_sfn), (_time), (_offset))
1382 /* Get SFI and SFN from given time and subframe offset */
1383 #define RG_SCH_HDFDD_GETSFI(_sfi, _time, _offset)\
1384 (_sfi) = (((_time).sfn * RGSCH_NUM_SUB_FRAMES) + \
1385 ((_time).subframe + _offset))% RG_SCH_HDFDD_NUMSFINFO
1387 /*If UE is HDFDD enabled */
1388 #define RG_SCH_HDFDD_UE_ENBLD(_ue) ((_ue)->hdFddEnbld)
1389 /*If HDFDD UE is scheduled */
1390 #define RG_SCH_HDFDD_ISCMN_SCHED(_dlSf) ((_dlSf)->bch.tbSize || \
1391 (_dlSf)->bcch.tbSize || (_dlSf)->pcch.tbSize)
1393 #define RG_SCH_HDFDD_ROLLSFN(_sfCount, _sfn)\
1395 if (_sfCount < -RGSCH_NUM_SUB_FRAMES) \
1397 _sfn = (_sfn + (_sfCount/RGSCH_NUM_SUB_FRAMES)) & (RGSCH_MAX_SFN - 1);\
1401 #endif /* LTEMAC_HDFDD */
1403 /* ccpu00117452 - MOD - Changed macro name from
1404 RGR_RRM_DLPWR_CNTRL to RGR_CQI_REPT */
1407 /* Macro to check if expected CQI report collation has been done */
1408 #define RG_SCH_CQIR_IS_TIMTOSEND_CQIREPT(_ue)\
1409 ((_ue)->schCqiInfo.cqiCount >= \
1410 (_ue)->cqiReptCfgInfo.numColltdCqiRept )
1412 /* Macro to check if PUSH N CQI Reporting is still active */
1413 #define RG_SCH_CQIR_IS_PUSHNCQI_ENBLE(_ue)\
1414 ((_ue)->cqiReptCfgInfo.numColltdCqiRept != 0)
1415 #endif /* ifdef RGR_CQI_REPT */
1418 /* Macro to check if Pa has valid value */
1419 #define RG_SCH_IS_PAPRSNT(_ue,_cell) (_ue->cellInfo[_ue->cellIdToCellIdxMap\
1420 [RG_SCH_CELLINDEX(_cell)]]->pA.pres == TRUE)
1423 /* Macro to check if Pa has been configured by RRM */
1424 #define RG_SCH_UE_CFG_ISPAPRSNT(_info) ((_info).pAPrsnt == TRUE)
1426 /* Macro to get absolute difference between two INT */
1427 #define RG_ABSLT_DIFF(x, y) ((x > y)? (x-y):(y-x))
1429 /* MIB transmission Count for DL TB counter */
1431 #define RG_SCH_MIB_CNT 4
1434 #define RG_SCH_PFS_FLW_CTRL_TRIG_TIME 64
1436 /* Interval between Transmission and feedback */
1437 #define RG_SCH_CMN_HARQ_INTERVAL 4
1438 #define RG_SCH_MAX_MPHICH 3
1439 #define RG_SCH_CMN_MAX_CFI 4
1441 #define RGSCH_GET_SPS_SF_CFI(_dlTotalBw, _cfi)\
1443 if(_dlTotalBw <= 10)\
1449 _cfi = RGSCH_MIN(2, _cfi); \
1454 #define RG_UPD_ACQI_TRIG_WT(_ue, _cell,_isAck)\
1456 RgSchUeCellInfo *sCellInfo = RG_SCH_CMN_GET_SCELL_INFO(_ue,_cell);\
1457 if(sCellInfo->acqiCb.aCqiCfg.pres)\
1459 rgSCHUtlUpdACqiTrigWt(_ue, sCellInfo, _isAck);\
1463 #define RG_UPD_ACQI_TRIG_WT(_ue, _cell, _isAck){}
1466 #define RG_SCH_MAX_HQP_SHIFT_Q_SZ 128 /*!< Length of the HqP Shift Q sizes maintained to
1467 maintain which HqPs shall be tried on LAA SCELL
1468 and which HqPs shall be move to PCELL */
1469 #define RG_SCH_HQP_TIME_ON_PCELL 32 /*!< Time in milliseconds to be allowed
1470 for transmission of TB on PCell*/
1472 extern uint32_t rgNumPrachRecvd; /* Num of Rach Req received including dedicated preambles */
1473 extern uint32_t rgNumRarSched; /* Num of RARs sent */
1474 extern uint32_t rgNumBI; /* Num of BackOff Ind sent */
1475 extern uint32_t rgNumMsg3CrcPassed; /* Num of CRC success for Msg3 */
1476 extern uint32_t rgNumMsg3CrcFailed ; /* Num of CRC fail for Msg 3 */
1477 extern uint32_t rgNumMsg3FailMaxRetx ; /* Num of Msg3 fail after Max Retx attempts */
1478 extern uint32_t rgNumMsg4Ack ; /* Num of Acks for Msg4 Tx */
1479 extern uint32_t rgNumMsg4Nack ;
1480 /* Num of Nacks for Msg4 Tx */
1481 extern uint32_t rgNumMsg4FailMaxRetx ; /* Num of Msg4 Tx failed after Max Retx attempts */
1482 extern uint32_t rgNumSrRecvd; /* Num of Sched Req received */
1483 extern uint32_t rgNumSrGrant; /* Num of Sched Req Grants sent */
1484 extern uint32_t rgNumMsg3CrntiCE; /* Num of Msg 3 CRNTI CE received */
1485 extern uint32_t rgNumDedPream ; /* Num of Dedicated Preambles recvd */
1486 extern uint32_t rgNumMsg3CCCHSdu; /* Num of Msg 3 CCCH Sdus recvd */
1487 extern uint32_t rgNumCCCHSduCrntiNotFound ; /*UE Ctx not found for CCCH SDU Msg 3 */
1488 extern uint32_t rgNumCrntiCeCrntiNotFound ; /*UE Ctx not found for CRNTI CE Msg 3 */
1489 extern uint32_t rgNumMsg4WithCCCHSdu ; /* Num of Msg4 with CCCH Sdu */
1490 extern uint32_t rgNumMsg4WoCCCHSdu ; /* Num of Msg4 without CCCH Sdu */
1491 extern uint32_t rgNumMsg4Dtx ; /* Num of DTX received for Msg 4 */
1492 extern uint32_t rgNumMsg3AckSent ; /* Num of PHICH Ack sent for Msg 3 */
1493 extern uint32_t rgNumMsg3NackSent ; /* Num of PHICH Nack sent for Msg 3 */
1494 extern uint32_t rgNumMsg4PdcchWithCrnti ; /* Num of PDCCH for CRNTI based contention resolution */
1495 extern uint32_t rgNumRarFailDuetoRntiExhaustion ; /* Num of RACH Failures due to RNTI pool exhaution */
1496 extern uint32_t rgNumTAModified ; /* Num of times TA received is different from prev value */
1497 extern uint32_t rgNumTASent ; /* Num of TA Command sent */
1498 extern uint32_t rgNumMsg4ToBeTx ; /* Num of times MSG4 that should be sent */
1499 extern uint32_t rgNumMsg4Txed ; /* Num of MSG4 actually sent *//* ysNumMsg4ToBeTx -ysNumMsg4Txed == Failed MSG4 TX */
1500 extern uint32_t rgNumMsg3DtxRcvd; /* CRC Fail with SINR < 0 */
1502 extern uint32_t rgNumDedPreamUECtxtFound;
1503 #endif /* __RGSCH__ */
1505 /**********************************************************************
1507 **********************************************************************/