1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /**********************************************************************
25 Desc: Defines required by LTE MAC
29 **********************************************************************/
31 @brief This file contains basic data structures for the scheuler.
35 #include "pj_tenb_stats.x"
42 #include "l2_tenb_stats.x"
46 #include "rg_sch_emtc.x"
49 typedef struct rgSchHistNode
54 Void * dbgVal; /* This is specific to the data struct being debug
55 for example if the debugging is done fo list
56 then this should contain the node address */
60 #define MAX_HIST_NODES 50
62 #define RGSCH_ACTION_ADD 11
63 #define RGSCH_ACTION_DEL 12
65 typedef struct rgSchHistInfo
68 RgSchHistNode hist[MAX_HIST_NODES];
71 #define RG_SCH_RECORD(_histInfo,_action,_dbgVal)\
73 (_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].file = __FILE__;\
74 (_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].func = __FUNCTION__;\
75 (_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].line = __LINE__;\
76 (_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].action = _action;\
77 (_histInfo)->hist[(_histInfo)->histCount%MAX_HIST_NODES].dbgVal = _dbgVal;\
78 (_histInfo)->histCount++;\
85 #endif /* __cplusplus */
87 typedef TfuDciFormat1aInfo RgDciFmt1AInfo;
88 typedef TfuRaReqInfo RgTfuRaReqInfo;
89 typedef TfuSubbandCqiInfo RgSchSubbandCqiInfo;
90 typedef TfuHqIndInfo RgTfuHqIndInfo;
91 typedef TfuHqInfo RgTfuHqInfo;
92 typedef TfuCntrlReqInfo RgTfuCntrlReqInfo;
94 /* Forward declarations for some structures */
96 typedef struct rgSchL2MeasCb RgSchL2MeasCb;
97 #endif /* LTE_L2_MEAS */
98 typedef struct rgSchQciCb RgSchQciCb;
99 typedef struct rgSchUeCb RgSchUeCb;
100 typedef struct rgSchCellCb RgSchCellCb;
101 typedef struct rgSchErrInfo RgSchErrInfo;
102 typedef struct rgSchUlAlloc RgSchUlAlloc;
103 typedef struct rgSchUlRetxAlloc RgSchUlRetxAlloc;
104 typedef struct rgSchUlHqProcCb RgSchUlHqProcCb;
105 typedef struct rgSchDlHqProcCb RgSchDlHqProcCb;
106 /* Changes for MIMO feature addition */
107 /* Removed dependency on MIMO compile-time flag */
108 typedef struct rgSchDlHqTbCb RgSchDlHqTbCb;
109 typedef struct rgSchLcgCb RgSchLcgCb;
110 typedef struct rgSchDlHqEnt RgSchDlHqEnt;
111 typedef struct rgSchRaCb RgSchRaCb;
112 typedef struct _rgSchCb RgSchCb;
113 typedef struct rgSchUlLcCb RgSchUlLcCb;
114 typedef struct rgSchDlLcCb RgSchDlLcCb;
115 typedef struct _rgSchdApis RgSchdApis;
117 typedef struct rgSchTddPhichOffInfo RgSchTddPhichOffInfo;
118 typedef U8 RgSchTddNpValTbl[RGSCH_TDD_MAX_P_PLUS_ONE_VAL];
120 /* Added support for SPS*/
122 typedef struct rgSchDlSfAllocInfo RgSchDlSfAllocInfo;
125 typedef struct rgSchUeCellInfo RgSchUeCellInfo;
132 S16 (*rgSCHRgrUeCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgrUeCfg *cfg,
134 S16 (*rgSCHRgrUeRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgrUeRecfg *recfg,
136 Void (*rgSCHFreeUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
137 S16 (*rgSCHRgrCellCfg) ARGS((RgSchCellCb *cell, RgrCellCfg *cfg,
139 S16 (*rgSCHRgrCellRecfg) ARGS((RgSchCellCb *cell, RgrCellRecfg *recfg,
141 Void (*rgSCHFreeCell) ARGS((RgSchCellCb *cell));
142 S16 (*rgSCHRgrLchCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
143 RgSchDlLcCb *dl, RgrLchCfg *cfg, RgSchErrInfo *errInfo));
144 S16 (*rgSCHRgrLcgCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
145 RgSchLcgCb *lcg, RgrLcgCfg *cfg, RgSchErrInfo *errInfo));
146 S16 (*rgSCHRgrLchRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
147 RgSchDlLcCb *dl, RgrLchRecfg *recfg,
148 RgSchErrInfo *errInfo));
149 S16 (*rgSCHRgrLcgRecfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
150 RgSchLcgCb *lcg, RgrLcgRecfg *recfg, RgSchErrInfo *errInfo));
151 Void (*rgSCHFreeDlLc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchDlLcCb *dlLc));
152 Void (*rgSCHFreeLcg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchLcgCb *lcg));
153 S16 (*rgSCHRgrLchDel) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,CmLteLcId lcId, \
155 Void (*rgSCHActvtUlUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
156 Void (*rgSCHActvtDlUe) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
157 Void (*rgSCHHdlUlTransInd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
158 CmLteTimingInfo timingInfo));
159 Void (*rgSCHUeReset) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
160 S16 (*rgSCHUpdBsrShort) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchLcgCb *ulLcg, U8 bsr, RgSchErrInfo *err));
161 S16 (*rgSCHUpdBsrTrunc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchLcgCb *ulLcg, U8 bsr, RgSchErrInfo *err));
162 S16 (*rgSCHUpdBsrLong) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, U8 bsArr[], RgSchErrInfo *err));
163 S16 (*rgSCHUpdPhr) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, U8 phr, RgSchErrInfo *err));
164 S16 (*rgSCHUpdExtPhr) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgInfExtPhrCEInfo * extPhr, RgSchErrInfo *err));
166 S16 (*rgSCHUpdUlHqProc) ARGS((RgSchCellCb *cell, RgSchUlHqProcCb *curProc,
167 RgSchUlHqProcCb *oldProc));
169 S16 (*rgSCHContResUlGrant) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchErrInfo *err));
170 S16 (*rgSCHSrRcvd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, CmLteTimingInfo, RgSchErrInfo *err));
171 S16 (*rgSCHTti) ARGS((RgSchCellCb *cell, RgSchErrInfo *err));
172 Void (*rgSCHUlCqiInd) ARGS(( RgSchCellCb *cell, RgSchUeCb *ue, TfuUlCqiRpt *ulCqiInfo));
173 Void (*rgSCHPucchDeltaPwrInd) ARGS(( RgSchCellCb *cell,
174 RgSchUeCb *ue, S8 delta));
175 S16 (*rgSCHlUeReset) ARGS(( RgSchCellCb *cell, RgSchUeCb *ue));
176 Void (*rgSCHDlDedBoUpd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgSchDlLcCb *svc));
177 /* ccpu00105914: PHR handling for MSG3 */
178 Void (*rgSCHUlRecMsg3Alloc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
180 Void (*rgSCHUlHqProcForUe) ARGS((RgSchCellCb *cell, CmLteTimingInfo frm,
181 RgSchUeCb *ue, RgSchUlHqProcCb **procRef));
182 RgSchUlAlloc *(*rgSCHFirstRcptnReq) ARGS((RgSchCellCb *cell));
183 RgSchUlAlloc *(*rgSCHNextRcptnReq) ARGS((RgSchCellCb *cell,
184 RgSchUlAlloc *alloc));
185 RgSchUlAlloc *(*rgSCHFirstHqFdbkAlloc) ARGS((RgSchCellCb *cell, U8 idx));
186 RgSchUlAlloc *(*rgSCHNextHqFdbkAlloc) ARGS((RgSchCellCb *cell,
187 RgSchUlAlloc *alloc,U8 idx));
188 Void (*rgSCHDlProcAddToRetx) ARGS((RgSchCellCb *cell,RgSchDlHqProcCb *hqP));
189 Void (*rgSCHDlCqiInd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
190 Bool isPucchInfo, Void *dlCqi, CmLteTimingInfo timingInfo));
191 /* Added changes of TFU_UPGRADE */
193 Void (*rgSCHSrsInd) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
194 TfuSrsRpt* srsInd, CmLteTimingInfo timingInfo));
197 Void (*rgSCHDlTARpt) ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
198 /* Changes for MIMO feature addition */
199 /* Removed dependency on MIMO compile-time flag */
200 Void (*rgSCHDlRlsSubFrm) ARGS((RgSchCellCb *cell, CmLteTimingInfo subFrm));
201 /* Added support for SPS*/
203 Void (*rgSCHHdlCrntiCE) ARGS((RgSchCellCb *cell, RgSchUeCb * ue));
204 Void (*rgSCHDlProcAck) ARGS((RgSchCellCb *cell, RgSchDlHqProcCb *hqP));
205 Void (*rgSCHDlProcDtx) ARGS((RgSchCellCb *cell, RgSchDlHqProcCb *hqP));
206 Void (*rgSCHDlRelPdcchFbk) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
208 Void (*rgSCHUlSpsRelInd) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
211 Void (*rgSCHUlSpsActInd) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
214 Void (*rgSCHUlCrcFailInd) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
215 CmLteTimingInfo crcTime));
216 Void (*rgSCHUlCrcInd) ARGS((RgSchCellCb *cell, RgSchUeCb * ue,
217 CmLteTimingInfo crcTime));
218 #endif /* LTEMAC_SPS */
219 Void (*rgSCHDrxStrtInActvTmrInUl) ARGS((RgSchCellCb *cell));
220 Void (*rgSCHUpdUeDataIndLcg) ARGS((RgSchCellCb *cell, RgSchUeCb * ue, RgInfUeDatInd *datInd));
222 S16 (*rgSCHRgrSCellUeCfg) ARGS((RgSchCellCb *cell, RgSchUeCb *ue ,RgrUeSecCellCfg *sCellInfoCfg,
224 S16 (*rgSCHRgrSCellUeDel) ARGS((RgSchUeCellInfo *sCellInfo, RgSchUeCb *ue));
227 Void (*rgSCHUlProcAddToRetx) ARGS((RgSchCellCb *cell,RgSchUlHqProcCb *hqP));
231 /* Added changes of TFU_UPGRADE */
235 * @brief Periodic CQI/PMI/RI configuration parameters information
237 typedef RgrUePrdDlCqiCfg RgSchUeDlPCqiCfg;
240 * @brief Periodic CQI Setup configuration parameters information
242 /* Reference: 36.313: CQI-ReportPeriodic */
243 typedef RgrUeDlPCqiSetup RgSchUeDlPCqiSetup;
246 * @brief SRS configuration parameters information
248 /* Reference 36.313 SoundingRS-UL-Config */
250 typedef RgrUeUlSrsCfg RgSchUeUlSrsCfg;
254 * @brief SRS configuration setup parameters information
256 /* Reference 36.313 SoundingRS-UL-Config */
258 typedef RgrUeUlSrsSetupCfg RgSchUeSrsUlSetupCfg;
261 * @brief SR configuration parameters information
264 typedef RgrUeSrCfg RgSchUeSrCfg;
267 * @brief SR Setup configuration parameters information
270 typedef RgrUeSrSetupCfg RgSchUeSrSetupCfg;
272 #define IOT_INVALID_FREQSTART 0xffffffff
273 #define IOT_INFINITE_SIZE 0xffffffff
274 #define RGSCH_IOT_PDCCH_POOLSZ 100
275 #define RGSCH_IOT_PDSCH_POOLSZ 100
276 #define RGSCH_IOT_PUSCH_POOLSZ 100
277 #define RGSCH_IOT_PUCCH_POOLSZ 100
278 #define RGSCH_IOT_SCHED_POOLSZ 100
279 /* TODO: Minimum Delta between CRNT Time and TX time */
280 #define RGSCH_IOT_PDCCH_DELTA RG_SCH_CMN_DL_DELTA
281 #define RGSCH_IOT_PDSCH_DELTA RG_SCH_CMN_DL_DELTA - 1 /* UL_CNTRL_DELTA value is 2*/
282 #define RGSCH_IOT_PUCCH_DELTA 6
283 #define RGSCH_IOT_PUSCH_DELTA 6
284 #define RGSCH_IOT_PDCCH_MAXFREQSZ 24 /* MAX num of eCCEs per SF */
285 #define RGSCH_IOT_PDSCH_MAXFREQSZ 100 /* MAX num of PDSCH RB per SF */
286 #define RGSCH_IOT_PUCCH_MAXFREQSZ 2048 /* MAx num of PUCCH resource per SF */
287 #define RGSCH_IOT_PUSCH_MAXFREQSZ 100 /* MAx num of PUSCh RB per SF */
288 #define RGSCH_IOT_SCHED_MAXFREQSZ 1 /*Resource only in Time domain */
289 #define RGSCH_IOT_PUCCH_INVALID_FREQ 2049
292 * IoT PDCCH/PDSCH/PUSCH/PUCCH resource definition.
293 * For Iot Devices resource can span multiple subframes
294 * Hence resource is defined as a set of freq resources
295 * over a set of consecutive valid subframes
297 typedef struct rgSchIotRes
301 CmLteTimingInfo timeStart;
302 CmLteTimingInfo timeEnd;
307 CmLList lnk; /*!< Link to other Fragments or Allocs in resMngmt */
308 CmLList cbLnk; /*!< Link to other allocs in a given control block (ueCb) */
309 CmLList resLnk;/*!<Link to resList in UE*/
314 * IoT PDCCH/PDSCH/PUSCH resource control block.
315 * Has pre-initialized pool of resources of #poolSize.
316 * allocList will hold the allocations for PDCCH/PUSCH/PDSCH
317 * fragList will hold the context of fragments in resource
319 typedef struct rgSchIotResCb
322 RgSchIotRes *resources;
324 U8 maxFreqSz; /*!< Max Number of RBs/SCs/CCEs per Subframe */
325 U32 deltaTime; /*!< PDCCH/PUSCH/PDSCH Delta w.r.t current time */
326 RgSchIotRes *contRes; /*!< Represents continuous availability of resource
327 in frequency and time domain */
328 CmLListCp fragList; /*!< Represents list of fragmented resourcesi b4
329 contRes, ordered in time domain */
330 CmLListCp allocList; /*!< Represents list of resources allocated which
331 are ordered in time domain */
337 * IoT Resource Management Control Block
338 * for PDCCH, PDSCH and PUSCH resources
340 typedef struct rgSchIotResMngmtCb
342 RgSchIotResCb pdcchResCb;
343 RgSchIotResCb pdschResCb;
344 RgSchIotResCb puschResCb;
345 RgSchIotResCb pucchHqFdbkCb;
346 } RgSchIotResMngmtCb;
348 PUBLIC S16 rgSCHUtlIotResPrcTti ARGS((
352 PUBLIC Void rgSCHUtlIotInsAlloc2Lst ARGS((
353 CmLListCp *allocList,
358 PUBLIC S16 rgSCHUtlIotResMngmtInit ARGS((
371 PUBLIC Void rgSCHUtlIotResMngmtDeinit ARGS((
375 PUBLIC RgSchIotRes *rgSCHUtlIotAllocRes ARGS((
376 RgSchIotResCb *resCb,
379 CmLteTimingInfo tStart,
384 PUBLIC RgSchIotRes *rgSCHUtlIotFirstAllocForTx ARGS((
385 RgSchIotResCb *resCb,
386 CmLteTimingInfo txTime
389 PUBLIC RgSchIotRes *rgSCHUtlIotNextAllocForTx ARGS((
390 RgSchIotResCb *resCb,
391 RgSchIotRes *prevAlloc,
392 CmLteTimingInfo txTime
395 PUBLIC Void rgSCHUtlIotAllocRls ARGS((
396 RgSchIotResCb *resCb,
400 PUBLIC RgSchIotRes *rgSCHUtlEmtcAllocRes ARGS((
401 RgSchIotResCb *resCb,
404 CmLteTimingInfo tStart,
410 PUBLIC S16 rgSCHUtlEmtcResPrcTti ARGS((
414 PUBLIC S16 rgSCHUtlEmtcResMngmtInit ARGS((
427 PUBLIC Void rgSCHUtlEmtcResMngmtDeinit ARGS((
432 EXTERN RgSchUlHqProcCb* rgSCHUhmGetUlProcByTime ARGS((
437 EXTERN S16 rgSCHUhmGetAvlHqProc ARGS((
440 RgSchUlHqProcCb **hqP
444 * @brief Store Periodic CQI, SRS and SR tranmission instances list
447 typedef struct rgSchPerPucchCb
456 @brief UE Specific SRS Periodicity and Subframe Offset Configuration FDD */
458 typedef struct rgSchUePCqiSrsSrCfgIdxTbl
460 U16 min; /*!< start ISRB Index */
461 U16 max; /*!< end ISRB Index */
462 U16 peri; /*!< SRS Periodicity in ms */
463 U16 offset; /*!< Offset with ISRB value */
464 }RgSchUePCqiSrsSrCfgIdxTbl;
467 @brief UE Specific SRS Periodicity and Subframe Offset Configuration TDD */
469 /* Ref: Table 8.2-2: UE Specific SRS Periodicity */
471 typedef struct rgSchUeSrsCfgIdxTbl
473 U16 min; /*!< start ISRB Index */
474 U16 max; /*!< end ISRB Index */
475 U16 peri; /*!< SRS Periodicity in ms */
476 U16 offset1; /*!< Offset with ISRB value */
477 U16 offset2; /*!< Offset with ISRB value */
479 }RgSchUeSrsCfgIdxTbl;
483 typedef enum rgSchSfType
485 RG_SCH_SF_DLCNTRL_DLDATA = 0,
486 RG_SCH_SF_DLCNTRL_DLDATA_ULCNTRL,
487 RG_SCH_SF_DLCNTRL_ULDATA,
488 RG_SCH_SF_DLCNTRL_ULDATA_ULCNTRL
492 @brief Per UE Group Info
494 typedef struct rgSchUeGrp
496 U8 beamBitMask; /*!< Beam bit mask */
497 //U8 numUe; /*!< Ue present in Group */
501 @brief 5gtf Cell Info
503 typedef struct rgSch5gtfCellCb
505 RgSchUeGrp ueGrp5gConf[MAX_5GTF_GROUP]; /*!< Contains all the group configured */
506 RgSchSfType dynConfig[MAX_5GTF_SUBFRAME_INFO]; /*!< Get config from config file as of now */
508 U8 uePerGrpPerTti; /*!< Num of UEs to be scheduled in a group per TTI */
509 U8 ueGrpPerTti; /*!< Num of Groups to ne scheduled per Tti */
519 @brief UE Specific SRS Control Block */
521 typedef struct rgSchUeSrsCb
523 RgSchUeUlSrsCfg srsCfg; /*!< SRS Specific configuration */
524 U16 peri; /*!< Periodicity */
525 U16 offset; /*!< subframe Offset */
527 /*!< Next Tranmission instance
528 Referenence: 36.213 Section:8.2
529 ((10*sfn +sf-sfOffset))/mod(peri)) */
530 CmLList srsLstEnt; /*!< SRS List for next tranmission instance subframe */
531 U8 selectedAnt; /*!< Selected Antenna for SRS Reception*/
532 U16 srsDist; /*!< crnt Distance to get RI Transmission */
533 Bool srsRecpPrcsd; /*!< SRS Recpeption processed as part of PUCCH
534 // or PUSCH processing in current TTI or not */
539 @brief Periodic CQI/PMI Reporting configuration using PUCCH */
544 @brief Subband Size (k) and Bandwidth Parts (J) vs. DL sys BW */
546 typedef struct rgSchUeBwSubSzBwParts
548 U8 rbStart; /* RB Start */
549 U8 rbEnd; /* RB End */
553 }RgSchUeBwSubSzBwParts;
558 * Enum for specifying priority level of various PUCCH report types
559 * RG_SCH_CQI_PRIO_LVL_0 :PUCCH Report type 1,1a
560 * RG_SCH_CQI_PRIO_LVL_1 :PUCCH Report type 2,2b,2c,4
561 * RG_SCH_CQI_PRIO_LVL_2 :PUCCH Report type 2a,3,5,6
565 RG_SCH_CQI_PRIO_LVL_0,
566 RG_SCH_CQI_PRIO_LVL_1,
567 RG_SCH_CQI_PRIO_LVL_2,
568 RG_SCH_CQI_PRIO_LVL_INVALID
574 @brief Periodic CQI/PMI/RI Control Block */
576 typedef struct rgSchUePCqiCb
578 RgrUePrdDlCqiCfg cqiCfg; /*!< Cqi Pmi Configuration */
579 U16 cqiPeri; /*!< Periodicity */
580 U16 cqiOffset; /*!< CQI offset */
581 U16 riOffset; /*!< RI Offset */
582 U16 riPeri; /*!< RI periodicity */
584 /*!< Next Active Tranmission instace index ,
586 Transmission Instance
587 Referenence: 36.213 Section:8.2 */
589 /* 1. where wideband CQI/PMI reporting is configured
591 10*sfn+floor(subframe/2)-Noffsetcqi )Mod(Nperiod)=0
592 2. where both wideband CQI/PMI and subband CQI reporting are configured
594 10*sfn+floor(subframe/2)-Noffsetcqi )Mod(Nperiod)=0
595 only the few occasations will be used for WB and
596 few will be used for subbands.
599 U16 nRiTrIdx; /*!< Next Active Transmission instance for RI
600 Transmission Instance Referenence:
601 36.213 Section:8.2 */
602 U16 riDist; /*!< crnt Distance to get RI Transmission */
603 U16 h; /*!< Precompute and store H */
604 U8 riNumBits; /*Precomputed value as it doesn't change
606 /* 1. In the case where wideband RI reporting is configured
608 (10*sfn+floor(subframe)-Noffsetcqi-NoffsetRI )Mod(NCqiperiod *
611 2. Where Widesband and Subband RI reporting is configured
613 (10*sfn+floor(subframe)-Noffsetcqi-NoffsetRI )
614 Mod(H. NCqiperiod *MriPeriod )=0
615 where H= J * K +1; J=Number of bandwidth parts(BW/subsize). K is RGR
617 Bool isWb; /*! < Is True when a WideBand CQI is to be
618 Transmitted in a SubBand CQI Config*/
619 U8 bpIdx; /*Index of the Bandwidth Part*/
620 U8 label; /*Label L associated */
621 U8 J; /*Number of Bandwidth Parts*/
623 CmLList cqiLstEnt;/*!< List CQI UEs for next transmission
625 CmLList riLstEnt; /*!< List RI UEs for next transmission
627 Bool invalidateCqi; /*!< If TRUE, ignore the WB/SB CQI report*/
628 U8 perRiVal; /*!< Latest Periodic RI value reported */
629 Bool riRecpPrcsd; /*!< RI Recpeption processed as part of
630 PUCCH or PUSCH processing in current
633 RgSchCqiPrioLvl prioLvl; /* Priority lvl set based on the PUCCH Report
635 Bool isCqiIgnoByCollsn; /*!< Is this CQI type being ignored for
636 this reporting instance due to
637 collision with higher priority
639 Bool isRiIgnoByCollsn; /*!< Is this CQI type being ignored for
640 this reporting instance due to
641 collision with higher priority CQI
644 RgSchUeCellInfo *servCellInfo; /*!< Access to the serving cell of this
646 RgSchHistInfo histElem;
648 U8 rgSchPucchRepNumCount; /*!< CQI repetition count for CATM1 */
655 @brief SR Configuration Index */
657 typedef struct rgSchUeSrCfgIdx
659 U16 sIsr; /*!< Start ISR Index */
660 U16 eIsr; /*!< End ISR Index */
661 U16 peri; /*!< SR Periodicity */
662 U16 offset; /*!< offset */
665 /* Reference : 36.213 Table 10.1-5 */
666 /* Note: SR is same table for TDD and FDD */
667 RgSchUeSrCfgIdx schUeSrCfgIdx[RG_SCH_ISR_INDX_MAX]=
674 /* RESERVED: Configuration should not allow Res values */
678 @brief SR Control block */
680 typedef struct rgSchUeSrCb
682 RgSchUeSrCfg srCfg; /*!< SR configuration */
683 U16 offset; /*!< SR offset */
684 U16 peri; /*!< SR periodicity */
686 U16 nSrTrIdx; /*!< Next Active Tranmission Instance Index ,
687 Referenence: 36.213 Section:10.1 */
690 ((10*sfn+floor(sf)-srOffset)Mod(srPeriodcity))
694 U8 rgSchPucchRepNumCount; /*!< SR repetition count for CATM1 */
696 CmLList srLstEnt; /*!< Next Transmission instance SR UE list */
701 * @enum rgSchCqiReqField
702 * Enumeration of CSI Request Field (Table 7.2.1-1A 36.213).
703 * "00" No aperiodic CSI report is triggered
704 * "01" Aperiodic CSI report is triggered for serving cell c
705 * "10" Aperiodic CSI report is triggered for a 1st set of
706 * serving cells configured by higher layers
707 * "11" Aperiodic CSI report is triggered for a 2nd set of
708 * serving cells configured by higher layers
711 typedef enum rgSchCqiReqField
714 RG_SCH_APCQI_SERVING_CC,
715 RG_SCH_APCQI_1ST_SERVING_CCS_SET,
716 RG_SCH_APCQI_2ND_SERVING_CCS_SET
720 @brief APeriodic CQI Control Block */
721 typedef struct rgSchUeACqiCb
723 RgrUeAprdDlCqiCfg aCqiCfg;/*!< Cqi Pmi Configuration */
724 U8 L; /*Unique Label through which positioning of Subbands
725 will be conveyed by the UE */
726 U8 N; /*Total Bandwidth / Num of Subbands*/
727 U8 M; /*Number of Selected Subbands*/
729 U8 k; /*k - SB size. 36.213 Tables:7.2.1-3, 7.2.1-5*/
730 U8 cqiPmiSzR1; /*CQIPMI Size for Rank =1*/
731 U8 cqiPmiSzRn1; /*CQIPMI Size for Rank > 1*/
732 U32 aCqiTrigWt; /* Metric to track Aperiodic CQI Trigger occassion */
733 RgSchCqiReqField cqiReqField; /* Cqi Request field. This Value can be 00 01 10 11, based upon
734 the cell present in which trigger list form App */
739 RG_SCH_FDD_PCQI_TBL = 0,
747 /*ccpu00116923 - ADD - SRS present support*/
749 typedef U8 RgSchTddCellSpSrsSubfrmTbl[RGSCH_CELLSP_SRS_SF_CONFIGS][RGSCH_NUM_SUB_FRAMES];
751 typedef U8 RgSchFddCellSpSrsSubfrmTbl[RGSCH_CELLSP_SRS_SF_CONFIGS][RGSCH_NUM_SUB_FRAMES];
762 * Enum to define the type of Downlink subframe.
766 RG_SCH_SPL_SF_NO_DATA = 0,
773 * TDD UE specific PUCCH recpetion information.
775 typedef struct rgSchUePucchRecpInfo
777 CmHashListEnt hashLstEnt; /*!< List of PUCCH for receiving
778 ACK/NACK feedback information */
779 TfuUeRecpReqInfo *pucchRecpInfo; /*!< UE PUCCH Reception information */
780 } RgSchUePucchRecpInfo;
784 * TDD switch point information.
786 typedef struct rgSchTddSubfrmInfo
788 U8 switchPoints; /*!< Number of DL-UL switch points */
789 U8 numFrmHf1; /*!< Number of subframes for half frame 1
790 Present for both 5ms and 10ms periodicity */
791 U8 numFrmHf2; /*!< Number of subframes for half frame 2
792 Present only for 5ms periodicity */
793 } RgSchTddSubfrmInfo;
797 * TDD DL Association Set information.
799 typedef struct rgSchTddDlAscSetIdxK
801 U8 numFdbkSubfrms; /*!< Number of Feedbacks for DL Subframes */
802 U8 subfrmNum[RGSCH_NUM_SUB_FRAMES-1]; /*!< List of Subframe Number */
803 } RgSchTddDlAscSetIdxK;
805 /** @brief PRACH Information for a frequency resource. */
806 typedef struct rgrSchTddPrachInfo
808 U8 freqIdx; /*!< Frequency Index */
809 U8 sfn; /*!< Even/Odd/All Radio Frames */
810 U8 halfFrm; /*!< First/Second Half Frame */
811 U8 ulStartSfIdx; /*!< Uplink Start Subframe Index*/
814 /** @brief PRACH resource Information for each of the
815 * frequency resources. */
816 typedef struct rgrSchTddPrachRscInfo
818 U8 numRsc; /*!< Number of frequency resources*/
819 RgSchTddPrachInfo prachInfo[RGSCH_TDD_MAX_FREQ_RSRC]; /*!< PRACH Information */
820 } RgSchTddPrachRscInfo;
824 * TDD Special subframe configuration information.
826 struct rgSchTddSplSubfrmInfo
828 U8 norDlDwPts; /*!< DL Normal CP: DwPTS in Ts */
829 U8 norDlNorUpPts; /*!< DL Normal CP: UL Normal CP:UpPTS in Ts */
830 U8 norDlExtUpPts; /*!< DL Normal CP: UL Extended CP: UpPTS in Ts */
831 U8 extDlDwPts; /*!< DL Extended CP: DwPTS in Ts */
832 U8 extDlNorUpPts; /*!< DL Extended CP: UL Normal CP:UpPTS in Ts */
833 U8 extDlExtUpPts; /*!< DL Extended CP: UL Extended CP: UpPTS in Ts */
838 * RACH response awaiting scheduling from the current time is
839 * identified with sfn offset and subframe.
841 typedef struct rgSchTddRachRspInfo
843 U8 sfnOffset; /*!< SFN offset with respect to
844 expected RACH available for
846 U8 numSubfrms; /* Number of subframes present */
847 U8 subframe[RGSCH_NUM_SUB_FRAMES]; /*!< List of Subframe numbers */
848 } RgSchTddRachRspInfo;
850 typedef RgSchTddRachRspInfo RgSchTddRachDelInfo;
854 * List of awaiting RACH responses for scheduling across radio frames.
857 typedef struct rgSchTddRachRspLst
859 U8 numRadiofrms; /*!< Number of radio frames */
860 RgSchTddRachRspInfo rachRsp[2]; /*!< RACH Occasions for which response
862 RgSchTddRachDelInfo delInfo; /*!< Previous RACH responses for
863 which the scheduling deadline
864 has expired. So those responses
866 } RgSchTddRachRspLst;
870 * Uplink association index information indicates the SFN offset and
871 * subframe in which DL HARQ ACK/NACK is expected.
873 typedef struct rgSchTddUlAscInfo
875 U8 subframe; /*!< Subframe number */
876 U8 sfnOffset; /*!< SFN offset with respect to expected
877 UL data reception time */
882 * PUSCH information indicates the SFN offset and
883 * subframe in which UL data is scheduled.
885 typedef struct rgSchTddPuschOffInfo
887 U8 subframe; /*!< Subframe number */
888 U8 sfnOffset; /*!< SFN offset with respect to expected
889 UL data reception time */
890 } RgSchTddPuschOffInfo;
894 * PHICH information indicates the SFN offset and
895 * subframe for which PHICH should be sent.
897 struct rgSchTddPhichOffInfo
899 U8 numSubfrms; /*!< Number of subframes */
901 U8 subframe; /*!< The Uplink Subframe number corresponding
903 U8 sfnOffset; /*!< SFN offset with respect to expected
904 UL data reception time */
909 * DL feedback reception information indicates the SFN offset
910 * and subframe at which feedback is expected.
912 typedef struct rgSchTddDlFdbkInfo
914 U8 subframe; /*!< Subframe number */
915 U8 sfnOffset; /*!< SFN offset with respect to current
917 U8 m; /*!< m factor used in Downlink Association
919 #ifdef LTE_ADV /*Naw:: This is not correct */
920 CmLListCp n1PucchResLst; /*!< List for storing the used N1 resource */
922 } RgSchTddDlFdbkInfo;
927 * Special subframe configuration index.
929 typedef struct rgSchTddSplSubfrmCfg
931 U16 dwPts; /*!< DwPTS in OFDM Symbol Duration */
932 U16 upPts; /*!< UpPTS in OFDM Symbol Duration */
933 Bool isDlDataAllowed; /*!< To allow scheduling of DL data on
935 } RgSchTddSplSubfrmCfg;
939 * ACK/NACK information to be used for ACK/NACK bundling mode.
941 typedef struct rgSchTddANInfo
943 U16 sfn; /*!< ACK/NACK is sent for PDU in this SFN */
944 U8 subframe; /*!< ACK/NACK is sent for PDU in this subframe */
945 U8 dlDai; /*!< Downlink Assignment Index for
946 UL-DL Configuration 1-6 */
947 U8 ulDai; /*!< DAI for uplink */
948 U8 latestMIdx; /*!< Last transmitted DL subframe 'm' index */
949 U8 n1ResTpcIdx; /*!< N1 Res idx for scell assigned in TPC command */
950 Bool isSpsOccasion; /*!< To indicate the presence of SPS occasion */
952 U8 wUlDai; /*!< Max Ul dai in all the cells */
959 * Information about one MCS entry.
961 typedef struct rgSchUlIMcsInfo
965 } RgSchUlIMcsTbl[29];
966 EXTERN RgSchUlIMcsTbl rgUlIMcsTbl;
968 typedef struct rgSchUeCatTbl
970 U32 maxUlBits;/*Maximum number of
975 U32 maxDlBits[4];/*Maximum number of
978 received within a TTI*/
979 /* correcting DL harq softbuffer limitation logic */
980 U32 maxSftChBits;/*Total number of soft channel bits*/
981 Bool ul64qamSup;/*Support for 64QAM in UL*/
982 /* Changes for MIMO feature addition */
983 /* Removed dependency on MIMO compile-time flag */
984 U32 maxDlTbBits;/*Maximum number of DL-SCH
986 received within a TTI*/
987 U8 maxTxLyrs;/*Maximum number of supported
988 layers for spatial multiplexing
990 } RgSchUeCatTbl[CM_MAX_UE_CAT_SUPP + 1];
991 EXTERN RgSchUeCatTbl rgUeCatTbl;
993 /* Changes for MIMO feature addition */
994 /* Removed dependency on MIMO compile-time flag */
995 typedef U32 RgSchTbSzTbl[RGSCH_MAX_NUM_LYR_PERCW][RGSCH_NUM_ITBS][RGSCH_MAX_NUM_RB];
998 typedef U8 RgSchRaPrmblToRaFrmTbl[RGSCH_MAX_TDD_RA_PREAMBLE_FMT+1];
1000 /* Added matrix 'rgRaPrmblToRaFrmTbl' for computation of RA
1001 sub-frames from preamble format */
1002 typedef U8 RgSchRaPrmblToRaFrmTbl[RGSCH_MAX_RA_PREAMBLE_FMT+1];
1004 EXTERN RgSchRaPrmblToRaFrmTbl rgRaPrmblToRaFrmTbl;
1006 EXTERN U8 rgRvTable[4];
1008 typedef struct rgDciFmt
1013 RgDciFmt1AInfo dci1a;
1017 typedef enum rgSchPdcchSearchSpace
1019 RG_SCH_UE_SPECIFIC_SEARCH_SPACE,
1020 RG_SCH_CMN_SEARCH_SPACE,
1021 }RgSchPdcchSearchSpace;
1025 * Information about one PDCCH.
1027 typedef struct rgSchPdcch {
1028 U8 nCce; /*!< CCE index */
1029 CmLteAggrLvl aggrLvl; /*!< Aggregation level */
1030 TfuDciInfo dci; /*!< PDCCH format */
1031 U16 rnti; /*!< RNTI to who the PDCCH is allocated */
1032 #if (defined (LTE_TDD))
1033 U8 dlDai; /*!< DAI associated with this PDCCH.
1034 THis is used for F1BCS resource calulcation */
1036 /* Added support for SPS*/
1038 CmLteTimingInfo relFbkTiming; /*!< Feebback timing information for release
1040 Bool isSpsRnti; /*!< TRUE if rnti is SPS RNTI */
1041 U16 crnti; /*!< CRNTI to who the PDCCH is allocated */
1043 CmLList lnk; /*!< To link PDCCHs in a subframe */
1047 RgSchUeCb *ue; /*!< Pointer to the UE Control Block */
1048 RgSchPdcchSearchSpace pdcchSearchSpace; /*!< Search Space from this PDCCH allocated */
1049 U8 dciNumOfBits; /*!< Size of DCI in bits */
1054 * PDCCH information for cell.
1056 typedef struct rgSchPdcchInfo {
1057 U8 *map; /*!< Bit map of PDCCHs */
1058 U8 currCfi; /*!< Number of CCEs */
1059 U16 nCce; /*!< Total CCEs */
1060 CmLListCp pdcchs; /*!< List of RgSchPdcch */
1063 typedef struct rgSchPhich
1065 CmLList lnk; /*!< To link PHICHs in a subframe */
1066 U8 hqFeedBack; /*!< Harq Feed Back */
1067 U8 rbStart; /*!< Starting RB */
1068 U8 nDmrs; /*!< 3 bits for DMRS cyclic shift */
1069 /* changes for passing iphich at TFU;*/
1070 Bool isForMsg3; /*! < Phich Ack/Nack conveyed for MSG 3 */
1072 U8 iPhich; /*!< For determining phich group */
1076 typedef struct rgSchPhichInfo
1078 CmLListCp phichs; /*!< List of RgSchPhich */
1081 typedef struct rgSchBcchTb
1088 typedef struct rgSchPcchTb
1095 typedef struct rgSchRaRspAlloc
1099 TknU8 backOffInd; /*!< Backoff index value */
1100 CmLListCp raRspLst; /*!< List of RaCbs */
1101 CmLListCp contFreeUeLst; /*! List of HandOver or PdcchOrder UEs */
1102 RgSchPdcch *pdcch; /*!< NULLP if no Rsp allocation done for raRnti*/
1105 typedef struct rgSchBchTb
1107 Buffer *tb; /*!< BCH data for this frame */
1108 U16 tbSize; /*!< Non-Zero if bch data is scheduled for this SF */
1111 /* Added support for SPS*/
1114 * TODO: check compilation
1115 @brief Downlink Resource allocation type information. */
1116 struct rgSchDlSfAllocInfo
1118 U32 raType0Mask; /*!< RBG allocation mask for type 0*/
1119 U32 raType1Mask[RG_SCH_NUM_RATYPE1_32BIT_MASK]; /*!< RA Type 1
1121 U32 raType1UsedRbs[RG_SCH_NUM_RATYPE1_32BIT_MASK];/*!< RA Type 1 Used RBs
1123 U32 nxtRbgSubset; /*!< Next RBG subset to be used for allocation */
1124 U32 raType2Mask[RG_SCH_NUM_RATYPE2_32BIT_MASK];
1125 /*!< Mask for resource allocation type 2 */
1127 #endif /* LTEMAC_SPS */
1129 /* LTE_ADV_FLAG_REMOVED_START */
1131 @brief RGR RB range for SFR */
1132 typedef struct rgrPwrHiCCRange
1134 U8 startRb; /*<! Start RB for power high cell centre user */
1135 U8 endRb; /*<! End RB for power high cell centre user */
1138 typedef struct rgSchSFRTotalPoolInfo
1140 CmLListCp ccPool; /*Dynamic Variable, It will change when BW is assigned.
1141 Initially assigned to 0 */
1142 Bool ccBwFull; /*If BW is full*/
1143 CmLListCp cePool; /*Dynamic Variable, It will change when BW is assigned.
1144 Initially assigned to 0 */
1145 Bool ceBwFull; /*If BW is full*/
1147 Bool CERetx; /* to check if there is any CE retransmission */
1148 Bool CCRetx; /* to check if there is any CC retransmission */
1149 Bool CC1; /* Cell centre pool 1 */
1150 Bool CC2; /* cell centre pool 2 */
1151 U8 CCPool1BwAvlbl; /* Cell Centre Bw available for Pool1 */
1152 U8 CCPool2BwAvlbl; /* Cell Centre Bw available for Pool2 */
1153 U8 CEPoolBwAvlbl; /* Cell Edge Bw available for CE Pool */
1154 }RgSchSFRTotalPoolInfo;
1156 typedef struct rgSchSFRPoolInfo
1158 /*Fixed RB Range of the Pool. Fixed by user configuration*/
1161 U16 bw; /*!< Number of RBs in the pool */
1163 U8 type2Start; /*!< Start RB for the next type 2 allocation */
1164 U8 type2End; /*!< End position of Type2 allocation with in the bit mask */
1165 U8 type0End; /*!< End position of Type0 allocation with in the bit mask */
1167 U16 bwAlloced; /*!< Number of RBs already allocated by DLFS */
1168 Bool CCPool2Exists; /*!< To check if the last pool in the RB allocation is a CC pool */
1169 struct rgSchSFRPoolInfo * adjCCPool; /*!< The CC pool adjacent to this CE Pool SFR_FIX */
1170 RgrPwrHiCCRange pwrHiCCRange; /*!< Power High Range which can be used by CC user based on RNTP info */
1172 /* LTE_ADV_FLAG_REMOVED_END */
1174 typedef struct rgSchPuschBwInfo
1176 U8 numSb; /*!< PUSCH BW in subbands */
1177 U8 startRb; /*!< Starting RB for PUSCH BW */
1180 typedef struct rgSchDynCfiCb
1182 U8 isDynCfiEnb; /*!< Dynamic CFI feature Flag */
1183 U8 maxCfi; /*!< max possible CFI in the cell */
1184 U8 switchOvrWinLen; /*!< Length of Switchover window */
1185 U16 cceFailCnt; /*!< Number of CCE allocation Failures in a
1186 CCE failure sample period */
1187 U16 *cceFailSamples; /*!< Array holding samples of Avg number
1188 of CCE allocation failures */
1189 U16 cceFailSum; /*!< Moving sum of the CCE faliures of
1191 U16 cfiStepUpTtiCnt; /*!< No.of TTIs to take decision for CFI
1193 U16 cceUsed; /*!< Total CCEs used in current monitoring
1195 U16 lowCceCnt; /*!< Number of TTI in which CCEs used is
1196 less than available CCEs in
1198 U16 cfiStepDownTtiCnt; /*!< No.of TTIs to take decision for CFI
1200 U32 cfiSwitches; /*!< Total number of CFI switches */
1201 U32 cfiIncr; /*!< Total number of CFI increments */
1202 U32 cfiDecr; /*!< Total number of CFI decrements */
1203 /*!< Total CCE per CFI */
1204 U8 cfi2NCceTbl[RG_SCH_MAX_MPHICH][RG_SCH_CMN_MAX_CFI];
1206 U8 numFailSamples; /*!< Number of CCE Allocation Failure
1208 U16 failSamplePrd; /*!< Failure Sample Period */
1209 U16 ttiCnt; /*!< TTI count to track monitoring period
1210 and sample period expiry */
1211 RgSchPuschBwInfo bwInfo[RG_SCH_CMN_MAX_CFI]; /*!< PUSCH BW info */
1212 U8 pdcchSfIdx; /*!< Subframe Idx for CFI applying */
1213 U8 prevCceFailIdx; /*!< To maintain Previous Index of
1214 CCE failure array */
1215 Bool switchOvrInProgress; /*!< Switchover is in progress */
1216 Bool dynCfiRecfgPend; /*!< Flag for pending dynamic cfi reconfig */
1223 * Beam information for a subframe
1225 typedef struct rgSchSfBeamInfo
1227 U16 totVrbgAvail; /*!< Total VRBG available */
1228 //U16 totRb; /*!< Total RB per Beam */
1229 U16 totVrbgRequired; /*!< total Rbs requested for beam */
1230 U16 totVrbgAllocated; /*!< total Rbs allocated for beam */
1231 U16 vrbgStart; /*!< VRBG start for beam */
1235 typedef struct rgSchDlSf
1237 U8 cceCnt; /*!< Number of CCEs used in the subframe */
1238 Bool isCceFailure; /*!< TRUE if PDCCH allocation is failed for
1240 U8 dlUlBothCmplt; /*!< To track that DL and UL both scheduling
1242 U8 sfNum; /*!< Number of the subframe */
1243 U16 bw; /*!< Number of RBs in the cell */
1244 U16 bwAlloced; /*!< Number of RBs already allocated by DLFS */
1245 U16 bwAssigned; /*!< Number of RBs already allocated by scheduler */
1246 /* LTE_ADV_FLAG_REMOVED_START */
1247 RgSchSFRTotalPoolInfo sfrTotalPoolInfo; /* SFR Pool Info*/
1248 TknStrOSXL rntpInfo; /* RNTP Info for the complete subframe*/
1249 /* LTE_ADV_FLAG_REMOVED_END */
1251 U8 type2Start; /*!< Start RB for the next type 2 allocation */
1252 U8 type2End; /*!< End position of Type2 allocation with
1254 U8 type0End; /*!< End position of Type0 allocation with
1256 U8 lstRbgDfct; /*!< The last RBG deficit RBs, Ex. if DLBW = 97,
1257 * RBGsz = 4, lstRbgDfct = 3 */
1258 Bool txDone; /*!< Flag to indicate if transmission is done*/
1259 U32 numDlActvUes; /* 4UE_TTI_DELTA: num of active Ues */
1260 RgSchBchTb bch; /*!< BCH data for this frame */
1261 RgSchBcchTb bcch; /*!< BCCH allocation for this frame */
1262 RgSchPcchTb pcch; /*!< PCCH allocation for this frame */
1263 RgSchPdcchInfo pdcchInfo; /*!< PDCCH info */
1264 RgSchPhichInfo phichInfo; /*!< PHICH info */
1267 CmLListCp ueLst; /*!< UE List which are scheduled in Perticular SF */
1269 CmLListCp msg4HqPLst; /*!< Msg4 Hq Procs that are scheduled in Perticular SF */
1271 U8 remUeCnt; /*!< Remaining number of UEs that can be scheduled */
1272 Bool schdAmbrNxt;/*!< Flag indicates to pick an AMBR LC after GBR LC */
1273 /*[ccpu00138609]-ADD- Counter to track the number of Msg4/DL CCCH UEs */
1274 U8 schdCcchUe; /*!< Num of Msg4/DL CCCH UEs scheduled in
1277 U8 nCce; /*!< Number of CCEs */
1278 RgSchTddPhichOffInfo phichOffInfo; /*!< PHICH Information */
1279 RgSchTddDlFdbkInfo dlFdbkInfo; /*!< HARQ Ack/Nack feedback expected time */
1280 RgSchTddUlAscInfo ulAscInfo; /*!< UL Association set Information */
1281 RgSchRaRspAlloc raRsp[RGSCH_MAX_TDD_RA_RSP_ALLOC]; /* Array of list
1283 Allocations for each rarnti */
1284 RgSchTddSfType sfType; /*!< Stores the enum value for SF type */
1286 RgSchRaRspAlloc raRsp[RGSCH_MAX_RA_RSP_ALLOC]; /* Array of list of Ra Rsp
1287 Allocations for each rarnti */
1289 Void *dlfsSf; /*!< DLFS specific information per sub-frame */
1290 CmLListCp ackNakRepQ; /*!< ACK NACK repetition queue */
1291 /* Added support for SPS*/
1293 Bool isSPSOcc; /*!< TRUE if this SF has SPS Occasion allocation */
1294 RgSchDlSfAllocInfo dlSfAllocInfo;/*!< Allocation information for DL SF */
1295 U32 spsAllocdBw; /*!< Number of RBs allocated for SPS */
1296 RgSchPdcch *relPdcch; /*!< Only one release PDCCH scheduled per
1301 CmLteRnti crnti; /*!< UE's C-RNTI (not SPS RNTI) */
1302 RgrTddAckNackMode ackNackMode; /*!< Ack/nack mode */
1303 } relPdcchInfo; /*!< Info required for receiving Hq fdbk
1304 * for release PDCCH (DL) */
1307 U32 schedLcCount; /*!< Num of LCs scheduled in this TTI */
1308 U32 totalLcCntOfSlctdUes; /*!< total Lc count of all UE's selected in
1310 U32 totPrbReq; /*!< Sum of PRBs required by selected UEs
1312 #ifdef BEST_EFFORT_2_UE_PER_TTI
1320 CmLListCp n1PucchResLst; /*!< List for storing the used N3 resource */
1321 CmLListCp n3PucchResLst; /*!< List for storing the used N1 resource */
1324 RgSchSfBeamInfo sfBeamInfo[MAX_5GTF_BEAMS]; /*!< Per info Beam per sf*/
1325 U8 numGrpPerTti; /*!< number of Group per TTI*/
1326 U8 numUePerGrp; /*!< number of UE per group in TTI*/
1330 /* Data Structures used for DL Allocations by Schedulers */
1332 @brief Downlink Resource allocation type 0 information. */
1333 typedef struct rgSchDlRbAllocRaType0
1335 U8 numDlAlloc; /*!< Number of downlink allocations */
1336 U32 dlAllocBitMask; /*!< Downlink allocations done for the UE */
1337 } RgSchDlRbAllocRaType0;
1339 /* Added support for SPS*/
1342 @brief Downlink Resource allocation type 1 information. */
1343 typedef struct rgSchDlRbAllocRaType1
1345 U8 numDlAlloc; /*!< Number of downlink allocations */
1346 U8 shift; /*!< Indicates if the shift is triggered in the
1348 U8 rbgSubset; /*!< RBG subset number selected for the allocation*/
1349 U32 dlAllocBitMask; /*!< Downlink allocations done for the UE */
1350 } RgSchDlRbAllocRaType1;
1351 #endif /* LTEMAC_SPS */
1353 @brief Downlink Resource allocation type 2 information. */
1354 typedef struct rgSchDlRbAllocRaType2
1356 Bool isLocal; /*!< True if localised VRB */
1357 U8 rbStart; /*!< Starting RB */
1358 U8 numRb; /*!< Number of RBs */
1359 } RgSchDlRbAllocRaType2;
1362 typedef struct rgSchcmnDlGrnt
1364 U16 schdTime; /*!< Time at which Harq proc has been scheduled */
1365 U8 rbStrt; /*!< Starting RB of the allocation */
1366 U8 numRb; /*!< Number of RBs allocated */
1367 U8 iMcs; /*!< Index to the MCS */
1368 U8 rv; /*!< RV for HARQ (re)transmission */
1369 U8 rvIdx; /*!< RVIdx for HARQ(re)transmission */
1370 #ifdef RG_5GTF /* ToDo:: Anoop need to check for other fields required*/
1376 TfuDciFormat dciFormat; /*!< DCI format for the allocation */
1383 @brief Downlink allocation details per TB. */
1384 typedef struct rgSchDlTbAllocInfo
1386 Bool schdlngForTb;/*!< Indicates if this TB has been scheduled */
1387 /*ccpu00120365:-ADD-is this TB disabled. Refer to 36.213-7.1.7.2 */
1388 Bool isDisabled; /*!< Indicates if this TB is disabled */
1389 U32 bytesReq; /*!< Number of bytes required to be allocated
1390 for each TB: filled in by RR/MAX C/I/PFS */
1391 U32 bytesAlloc; /*!< Num of bytes allocated for each TB */
1392 U8 iTbs; /*!< Itbs for allocation for this allocation
1394 U8 imcs; /*!< Imcs for allocation for this allocation
1396 U8 noLyr; /*!< No. of SM layers for this TB transmission */
1397 RgSchDlHqTbCb *tbCb; /*!< address of TB Control Block */
1399 RgSchDlCmnGrnt cmnGrnt; /*! < Alloc info to store 5GTF RAR sched */
1401 }RgSchDlTbAllocInfo;
1404 @brief Downlink MIMO related allocation details. */
1405 typedef struct rgSchMimoAllocInfo
1407 Bool hasNewTxData;/*!< Indicator from Specific Sched to Common.
1408 * Set, if UE has new data available for clubbing
1409 * with RETX in case of TM3 and TM4 */
1410 Bool swpFlg; /*!< Swap Flag to indicate TB to CW association
1411 * incase of 2 TB transmission */
1412 U8 precIdxInfo; /*!< Precoding index information stored */
1413 U8 numTxLyrs; /*!< Number of SM layers scheduled for Transmission */
1414 }RgSchMimoAllocInfo;
1418 @brief Downlink RB allocation details. */
1419 typedef struct rgSchDlRbAlloc
1421 CmLteRnti rnti; /*!< RNTI for allocation: used only for RARs and
1422 dedicated transmissions */
1423 U8 rbsReq; /*!< Number of RBs required to be allocated:
1424 filled in by RR/MAX C/I/PFS */
1425 RgSchDlSf *dlSf; /*!< DL sub-frame for which allocation is to be
1426 done: filled in by RR/MAX C/I/PFS */
1427 TfuDciFormat dciFormat; /*!< DCI format for the allocation */
1428 U8 raType; /*!< Resource allocation Type */
1429 RgSchPdcch *pdcch; /*!< Pointer to allocated PDCCH */
1432 RgSchDlRbAllocRaType0 raType0; /*!< Resource allocation type 0 information */
1433 /* Added support for SPS*/
1435 RgSchDlRbAllocRaType1 raType1; /*!< Resource allocation type 1
1438 RgSchDlRbAllocRaType2 raType2; /*!< Resource allocation type 2 information */
1439 } allocInfo; /*!< Resource allocation information */
1440 U8 rbsAlloc; /*!< Number of RBs allocated */
1441 U8 numRapids; /*!< Number of RAPIDs serviced within RAR*/
1442 /* Nprb indication at PHY for common Ch */
1443 U8 nPrb; /*!< NPRB column num. either 2 or 3 */
1446 /* Add BI sub-header size to the tbSize requirement */
1448 RgSchMimoAllocInfo mimoAllocInfo; /*!< Mimo specific allocation params */
1449 RgSchDlTbAllocInfo tbInfo[2]; /*!< Allocation information for each TB. */
1451 /* Added support for SPS*/
1453 U8 cqiForTx; /*!< Assumed value of CQI at which transmission is
1455 RgSchDlSfAllocInfo resAllocInfo; /*!< Resource allocation information for
1456 the current allocation for
1457 RA type 0, 1 and 2 */
1458 Bool isSchdBySps; /*!< Indicates if this UE is already scheduled by SPS
1460 CmLteTimingInfo spsSchdTime; /*!< Timing info at which UE was scheduled by
1465 RgSchPdcch *mpdcch; /*!< Pointer to allocated PDCCH */
1466 RgSchEmtcDlRbAlloc emtcAllocInfo; /*!< EMTC DL RB alloc Info */
1475 * Uplink Grant Information per UE.
1477 typedef struct rgSchUlGrnt
1479 U8 iMcs; /*!< Original MCS index */
1480 U8 iMcsCrnt; /*!< Current MCS index of the grant */
1481 U8 hop; /*!< Hopping flag, set to 0 in this version */
1482 U8 rbStart; /*!< Start Resource block of allocation */
1483 U8 numRb; /*!< Number of resource blocks allocated */
1484 U8 tpc; /*!< TPC command for the uplink grant */
1485 U8 nDmrs; /*!< n1DMRS for the uplink grant */
1486 U8 delayBit; /*!< Delay bit, for msg3 grant, set to 1 */
1487 /* Added for Uplink Adaptive retransmission */
1488 Bool isRtx; /*!< To indicate if this grant is for a RETX */
1489 /* To include the length and ModOrder in DataRecp Req. */
1490 U16 datSz; /*!< Length of the Data */
1491 TfuModScheme modOdr; /*!< Modulation order */
1502 TfuDciFormat dciFrmt;
1508 /* Added for Uplink Adaptive retransmission */
1511 * Uplink retransmission allocation.
1513 struct rgSchUlRetxAlloc
1515 CmLteRnti rnti; /*!< RNTI */
1516 U8 numSb; /*!< Number of subbands */
1517 U32 tbSz; /*!< Transmission Block Size */
1518 U8 iMcs; /*!< Original MCS index */
1519 RgSchUeCb *ue; /*!< UE assocated with allocation */
1520 Bool forMsg3; /*!< If allocation is for Msg3 */
1521 /* PHR handling for MSG3 */
1522 RgSchRaCb *raCb; /*!< Pointer to RaCb, if forMsg3 = TRUE */
1524 RgSchEmtcUlGrnt emtcGrnt;
1527 TfuDciFormat dciFrmt;
1531 TfuModScheme modOdr; /*!< Modulation order */
1537 * Hole information, pertaining to uplink bandwidth
1539 typedef struct rgSchUlHole
1541 U8 start; /*!< Beginning of hole */
1542 U8 num; /*!< Number of elements making up the hole */
1543 struct rgSchUlHole *prv; /*!< Previous hole */
1544 struct rgSchUlHole *nxt; /*!< Next hole */
1545 struct rgSchUlAlloc *nxtAlloc; /*!< Next allocation */
1546 struct rgSchUlAlloc *prvAlloc; /*!< Previous allocation */
1555 RgSchUlHqProcCb *hqProc; /*!< HARQ process */
1556 CmLteRnti rnti; /*!< RNTI */
1557 U8 sbStart; /*!< Subband start idx */
1558 U8 numSb; /*!< Number of subbands */
1559 RgSchUlGrnt grnt; /*!< Grant info */
1560 /* Not keeping grant attributes now */
1561 RgSchPdcch *pdcch; /*!< Associated PDCCH */
1562 RgSchUeCb *ue; /*!< UE assocated with allocation */
1563 Bool forMsg3; /*!< If allocation is for Msg3 */
1564 Bool isMsg3CCCHSdu; /*!<Msg3 contains CCCH Sdu */
1565 Bool isMsg3CrntiCe; /*!< Msg3 contains CRNTI CE */
1566 /* PHR handling for MSG3 */
1567 RgSchRaCb *raCb; /*!< RaCb, if forMsg3 = TRUE */
1568 Bool mrgdNewTxAlloc; /*!< Alloc corresponding to newTx
1569 * that was merged in the process of
1570 * comdining txSf and reTxSf. */
1571 RgSchUlAlloc *prv; /*!< Previous alloc */
1572 RgSchUlAlloc *nxt; /*!< Next alloc */
1573 RgSchUlHole *prvHole; /*!< Next hole */
1574 RgSchUlHole *nxtHole; /*!< Prev hole */
1575 /* UL_ALLOC_CHANGES*/
1576 void *allocDbRef; /*!< The db from which this allocation was made*/
1577 void *holeDbRef; /*!< The db from which this allocation was made*/
1581 RgSchEmtcUlGrnt emtcGrnt;
1582 RgSchDlRbAllocRaType0 raType0; /*!< Resource Alloction type zero for eMTC */
1583 #endif /* EMTC_ENABLE */
1588 * Allocation free pool for an allocation db
1590 typedef struct rgSchUlAllocMem
1592 U8 maxAllocs; /*!< Maximum possible allocations per subframe */
1593 RgSchUlAlloc *firstFree; /*!< First free index */
1594 RgSchUlAlloc *allocs; /*!< Array of 'maxAllocs' elems */
1599 * Allocation information for a subframe
1601 typedef struct rgSchUlAllocDb
1603 U8 count; /*!< Number of allocations */
1604 RgSchUlAlloc *first; /*!< First allocation */
1605 RgSchUlAllocMem mem; /*!< Alloc pool management */
1610 * Hole free pool for a hole db
1612 typedef struct rgSchUlHoleMem
1614 U8 maxHoles; /*!< Maximum possible holes per subframe */
1615 RgSchUlHole *firstFree; /*!< First free index */
1616 RgSchUlHole *holes; /*!< Array of 'maxHoles' elems */
1621 * Holes information for a subframe
1623 typedef struct rgSchUlHoleDb
1625 U8 count; /*!< Number of holes */
1626 RgSchUlHole *first; /*!< First hole */
1627 RgSchUlHoleMem mem; /*!< Hole pool management */
1632 * Uplink subframe information.
1634 typedef struct rgSchUlSf
1636 U8 idx; /*!< Identifier for uplink subframe (range: 0-7)
1637 - maps to HARQ proc ID */
1638 CmLListCp reTxLst; /*!< Retransmission List*/
1640 RgSchTddPuschOffInfo puschOffset; /*!< PUSCH offset information */
1641 U8 ulSfIdx; /*!< The Uplink subframe number
1642 in the TDD frame. Range [2-9]
1643 Used only in TDD Cfg 0 */
1645 U32 totPrb; /*!< Total PRB used in this sub frame */
1646 /* ccpu00129725 -DEL- removed Platform flag */
1647 /* Fix:ccpu00120610 add a counter to keep track of remaining allocations */
1648 U8 *allocCountRef; /*!< Allocation count in this
1649 * subframe, it is a reference to the actual
1650 * counter held in allocDb (no additional
1651 * logic needed to maintain this) */
1652 /* Added for Uplink Adaptive retransmission */
1653 RgSchUlAllocDb *allocDb; /*!< Allocation info */
1654 RgSchUlHoleDb *holeDb; /*!< Holes info */
1655 U8 availSubbands; /*!< Number of total available subbands
1656 * for the current sub-frame */
1657 U8 numACqiCount; /*!< Used to Restrict 2 Aperiodic cqi per TTI*/
1659 RgSchSfBeamInfo sfBeamInfo[MAX_5GTF_BEAMS]; /*!< Per info Beam per sf*/
1660 U8 numGrpPerTti; /*!< number of Group per TTI*/
1661 U8 numUePerGrp; /*!< number of UE per group in TTI*/
1665 /* Nprb indication at PHY for common Ch */
1668 * Bo report given for common logical channel.
1670 typedef struct rgSchClcBoRpt
1672 CmLList boLstEnt; /*!< Linked list entity for BO list */
1673 U32 bo; /*!< Bo in bytes */
1674 CmLteTimingInfo timeToTx; /*!< Time at which the BO needs to be satisfied
1675 (data to be sent to PHY) */
1677 U8 emtcDIReason; /*!< Reason for DI message to send. */
1678 U8 pnb; /*!< Paging narrowBand on which Ue performs reception of paging*/
1680 CmLteTimingInfo maxTimeToTx;
1683 U8 nPrb; /*! NPRB column. Allowed values {2,3} */
1684 /* Corrected allocation for common channels */
1690 * Logical channel control block for BCCH and PCCH channels.
1692 typedef struct rgSchClcDlLcCb
1694 U8 lcId; /*!< Logical channel ID */
1696 CmLListCp boLst; /*!< List of BOs reported (RgSchClcBoRpt) */
1701 * Transmission offset configuration for SRS.
1703 typedef struct rgSchSrsTxOffst
1705 U8 count; /*!< Number of offsets in the array */
1706 U8 offst[RGSCH_MAX_SRS_TX_OFFSET]; /*!< SRS TX offset value */
1711 * Cell Control block per cell.
1713 typedef struct rgSchSrsCfg
1715 /*ccpu00130768 - ADD - SRS CFG Present flag to enable/disable cell specific SRS*/
1716 Bool isSrsCfgPres; /*!< cell specific SRS CFG enable/disable flag */
1717 RgrSrsCfgPrd srsCfgPrdEnum; /*!< SRS configuration period (in subframes) */
1718 RgrSrsBwCfg srsBwEnum; /*!< SRS Bandwidth configuration per cell.*/
1719 RgSchSrsTxOffst srsTxOffst; /*!< Transmission offset for SRS */
1720 /*ccpu00116923 - ADD - SRS present support*/
1722 U8 srsSubFrameCfg;/*!< SRS subframe configuration index per cell.
1730 * MAC Configuration element for CRG interface.
1732 typedef struct rgSchCfgElem
1734 CmLList cfgReqLstEnt; /*!< Linked list entry for cfgReqLst */
1735 CmLteTimingInfo actvTime; /*!< Activation time to apply configuration */
1740 RgrCfgReqInfo *rgrCfgReq; /*!< Configuration request information from
1742 RgrCfgTransId transId; /*!< Transaction ID for the config request */
1743 } rgrCfg; /*!< RGR configuration information */
1749 * Configuration Control block per cell.
1751 typedef struct rgSchCfgCb
1753 CmLListCp crntRgrCfgLst; /*!< List of config requests recieved in the
1754 current TTI from RRM */
1755 CmLListCp pndngRgrCfgLst; /*!< List of pending config requests recieved in the
1756 previous TTIs from RRM */
1761 * Link of RNTIs managed by MAC.
1763 typedef struct rgSchRntiLnk
1765 U16 rnti; /*!< RNTI */
1766 /*Fix: Overcome race condition between MAC and Scheduler delete*/
1767 CmLList rntiGrdPoolLnk; /*!< Link for RNTI guard pool*/
1768 struct rgSchRntiLnk *prv; /*!< Link to previous RNTI */
1769 struct rgSchRntiLnk *nxt; /*!< Link to next RNTI */
1774 * Database of RNTIs managed by MAC.
1776 typedef struct rgSchRntiDb
1778 U16 rntiStart; /*!< Start RNTI */
1779 U16 maxRntis; /*!< Maximum number of RNTIs managed by MAC */
1781 RgSchRntiLnk *freeRnti; /*!< first free RNTI in the list */
1782 RgSchRntiLnk *lastRnti; /*!< last RNTI in the list */
1783 RgSchRntiLnk *rntiPool; /*!< Linked list of RNTIs */
1784 /*Fix:Overcome Race condition between MAC and Scheduler delete*/
1785 CmLListCp rntiGuardPool; /*!< Holds guard pool for RNTIs when deleted in
1786 Scheduler but not deleted at MAC */
1791 * Random access information per cell.
1793 typedef struct rgSchRaInfoCb
1796 U8 maxRaSize; /*!< Number of RA-RNTIs stored
1797 across radio frames */
1798 U8 lstSize; /*!< list size */
1799 CmLListCp *raReqLst; /*!< Each array elem is linked
1803 /* ccpu00132523 Doubled the array size from MAX_RARNTI because window expiry
1804 * is overlapping with newly received TACH reqs in max RAR window*/
1805 /* Array Size should be more than gap towards window start */
1806 CmLListCp raReqLst[RGSCH_RAREQ_ARRAY_SIZE]; /*!< Each array elem is linked
1808 (per max ra-rnti*2) */
1810 CmLListCp raCbLst; /*!< List of RaCbs */
1811 CmLListCp toBeSchdLst; /*!< List of RaCbs to be
1815 /** @brief This structure is part of the uplink HARQ process, this structure
1816 * encapsulates all the DRX related information.
1818 typedef struct rgSchDrxUlHqProcCb
1820 CmLList harqRTTEnt; /*!< Entry into the HARQ RTT timer list */
1821 CmLList harqRetxEnt; /*!< Entry into the harqRetxQ */
1823 U16 rttIndx; /*!< Current Index into HARQ RTT Q */
1824 U16 reTxIndx; /*!< Current Index into Re-Tx Q */
1825 U8 retxTmrReduction; /*!< Due to platform specific timing diff between
1826 UL HARQ processing and UL Scheduling, the
1827 drx retx timer may start at a later time, than
1828 actual. That delay in starting the timer is
1831 } RgSchDrxUlHqProcCb;
1837 * Uplink HARQ process information per UE
1839 struct rgSchUlHqProcCb
1842 U8 remTx; /*!< Number of remaining transmissions */
1843 RgSchUlAlloc *alloc; /*!< Uplink allocation */
1844 /* Renamed rcvdDatInd to rcvdCrcInd */
1845 Bool rcvdCrcInd; /*!< Set to true when data rcvd, false when
1847 U8 rvIdx; /*!< Redundancy version index */
1848 TknU8 rvIdxPhy; /*!< Whatever is given by PHY. To be inspected in case
1849 of NACK.Always initialised to 'not present' */
1850 CmLList reTxLnk; /*!< Retransmission List */
1851 RgSchUlRetxAlloc reTxAlloc; /*!< Retransmission allocation
1853 Bool isRetx; /*!< Awaiting retransmission */
1854 U8 procId; /*!< HARQ Process ID */
1855 U8 ulSfIdx; /*!< UL Subframe Index */
1857 /* Changes for passing iPhich at TFU*/
1858 U8 iPhich; /*!< Needed to Calculate PHICH
1859 location. For TDD only */
1862 Bool isSpsActvnHqP; /*!< Set to true when this HqP is used for
1863 UL SPS Activation */
1864 Bool isSpsOccnHqP; /*!< Set to true when this HqP is used for
1865 UL SPS Occasion TX */
1869 RgSchDrxUlHqProcCb drxCb;
1872 /* 5gtf: TODO two links are not required */
1873 CmLList lnk; /*!< To link to inUse/Free Pool */
1874 CmLteTimingInfo schdTime; /*!< SFN,SF of schd time */
1879 * Uplink HARQ entity information per UE.
1881 typedef struct rgSchUlHqCb
1883 U8 maxHqRetx; /*!< Maximum number of harq
1884 * re-transmissions */
1885 U8 numHqPrcs; /*!< Number of HARQ Processes */
1887 RgSchUlHqProcCb *hqProcCb; /*!< Uplink harq process info */
1889 RgSchUlHqProcCb hqProcCb[RGSCH_NUM_UL_HQ_PROC]; /*!< Uplink harq process info */
1892 U8 numBusyHqProcs; /*!< Total Num of Hq procs in use */
1898 CmLListCp free; /*!< List of free HARQ processes */
1899 CmLListCp inUse; /*!< List of in-use HARQ processes */
1904 * Logical channel group.
1909 * Structure to store values for Ra Preambles received values
1911 typedef struct rgSchRaPreambles
1913 U8 dedPream; /*!< Dedicated RA Preamble received */
1914 U8 preamGrpA; /*!< Randomly selected preambles in low range */
1915 U8 preamGrpB; /*!< Randomly selected preambles in high range */
1919 * @brief strutcure to store Avergae PRB usage for a given Time period in
1922 typedef struct rgSchAvgPrbDl
1924 Bool cntActive; /* Set to TRUE if counting activated */
1925 CmLteTimingInfo startTime; /*!< Start Time */
1926 U8 timePrd; /*!< Period For which meas to be done */
1927 U32 prbCount; /*!< PRB Count Updated every Per TTI */
1931 * @brief strutcure to store Avergae PRB usage for a given Time period in
1934 typedef struct rgSchAvgPrbUl
1936 Bool cntActive; /*!< Set to TRUE if counting activated */
1937 CmLteTimingInfo startTime; /*!< Start Time */
1938 U8 timePrd; /*!< Period For which meas to be done */
1939 U32 prbCount; /*!< PRB Count Updated every Per TTI */
1943 * L2 measurement control block.
1945 struct rgSchL2MeasCb
1947 CmLList measLnk; /*!< MeasCb node */
1948 LrgSchMeasReqInfo measReq; /*!< Request received for measurement */
1949 CmLteTimingInfo startTime; /*!< Time at which measurement started */
1950 RgInfPrbCfm avgPrbQciUl; /*!< Used to store result from MAC */
1951 Bool cfmRcvd; /*!< Used to check if confirm received from MAC */
1952 /*!< For average PRB usage in UL */
1953 U16 sfnCycle; /*<! Count of Num of SFN wraps */
1954 U32 dlTotalBw; /*!< Total DL Bw between meas Req and Meas Send Req */
1955 U32 ulTotalBw; /*!< Total UL Bw between meas Req and Meas Send Req */
1958 typedef struct rgSchTbCnt
1960 U32 tbTransDlTotalCnt; /*!< Total DL TB count */
1961 U32 tbTransDlFaulty; /*!< Total DL Faulty TB count */
1962 U32 tbTransUlTotalCnt; /*!< Total UL TB count */
1963 U32 tbTransUlFaulty; /*!< Total UL Faulty TB count */
1965 #endif /* LTE_L2_MEAS */
1967 * Control block to store measurement details per QCI.
1971 U8 qci; /*!< QCI of the Logical Channel */
1972 U32 dlPrbCount; /*!< Cumulative Prb Count for this QCI */
1973 U32 dlUeCount; /*!< Cumulative number of active UE's */
1974 U32 dlTotal_UeCount; /*!< Cummulative count added for every sampling
1976 U32 ulUeCount; /*!< Cumulative number of active UE's */
1977 U32 ulTotal_UeCount; /*!< Cummulative count added for every sampling
1982 /* Right now not keeping associated logical channels, searching for
1983 * associated channels needed only during config */
1984 U8 lcgId; /*!< Group ID */
1987 U8 numLch; /*!< Number fo LC's for this LCG*/
1988 RgSchUlLcCb *lcArray[RGSCH_MAX_LC_PER_UE]; /*!< Dedicated Uplink logical
1990 #endif /* LTE_L2_MEAS */
1991 /* Added support for SPS*/
1994 U8 lcId[RGR_MAX_SPS_LC];
2000 * Uplink Dedicated Logical channel control block.
2004 Bool isValid; /*!< If this struct holds valid values*/
2005 U8 lcId; /*!< Logical channel ID */
2006 U8 lcgArrIdx; /*!< Index of this LC in the LCG Array*/
2007 RgSchLcgCb *lcg; /*!< Logical channel group */
2008 RgrLchQosCfg ulQos; /*!< UL Qos parameters */
2009 /* After Merging from 2.1 to 2.2 */
2010 RgSchQciCb *qciCb; /* QCI Details for this LC */
2015 * Ul Grnt Info for Ho/Po UE in RAR.
2017 typedef struct rgSchHoPoUeGrnt
2019 U8 rapId; /*!< dedicated rapId */
2020 U8 hop; /*!< Hopping flag, set to 0 in this version */
2021 U8 rbStart; /*!< Start Resource block of allocation */
2022 U8 numRb; /*!< Number of resource blocks allocated */
2023 U8 tpc; /*!< TPC command for the uplink grant */
2024 U8 iMcsCrnt; /*!< Current MCS index of the grant */
2025 TknU16 ta; /*!< Timing Adjustment */
2026 CmLList raRspLnk; /*!< To link UE to RaRsp cont free list */
2027 /* Added support for SPS*/
2028 U16 datSz; /*!< Length of the Data */
2029 Bool cqiReqBit; /*!< Aperiodic CQI is requested or not */
2034 * Uplink SPS scheduling information per UE
2036 typedef struct rgSchCmnSpsUlUeSchdInfo
2038 U32 allocBwMask[RGSCH_SPS_ULBW_MASK_LEN]; /*!< Bitmask indicating the allocation info
2039 for the UE. Bit set at position 'x'
2040 indicates subband 'x' is allocated */
2041 U8 scaledCqi; /*!< Assumed value of CQI for transmission */
2042 U16 actvSfLstIdx; /*!< Index into cell-wide UL SPS sub-frame
2043 table during activation */
2044 CmLteTimingInfo ulSpsActvOcc; /*!< Time at which SPS is activated/reactivated
2046 CmLteTimingInfo crntUlSpsOcc;/*!< Key into the list of UL SPS active
2047 UEs: next UL SPS ocassion */
2048 RgSchUlAlloc allocInfo; /*!< Allocation information of the UE */
2049 RgSchUlAlloc *crntAlloc; /*!< Allocation pointer in the subframe */
2050 RgSchUlSf *crntAllocSf; /*!< sf in which crntAlloc was made */
2051 } RgSchCmnSpsUlUeSchdInfo;
2055 * Uplink information for SPS per UE
2057 typedef struct rgSchCmnUlUeSpsInfo
2059 CmLList actvUeLstEnt; /*!< Linked List entry for UL SPS
2061 CmLList pndngUeLstEnt;/*!< Linked List entry for UE list with
2063 activation/reactivation/release */
2064 Bool isUlSpsActv; /*!< Indicates if UE's UL SPS is
2066 U8 measGapMask[RGSCH_SPS_MG_MASK_LEN]; /*!< Indicates the UL sub-frames with
2067 ongoing measurement gap. Mask is
2069 U8 state; /*!< State of the UE: can be one of
2070 ACTV_REACTV_SENT (pdcch for
2071 (re)activation sent),REL_SENT,
2073 Bool pdcchToRetx; /*!< set to TRUE if DTX occurs at the
2074 (re)activated SPS occasion */
2075 RgSchCmnSpsUlUeSchdInfo ulSpsSchdInfo; /*!< Scheduled info for UL SPS
2078 U8 spsOccIdx; /*!< N value for nxt sps occasion */
2080 U32 packetSize; /*!< Packet size for SPS - SPS allocation*/
2081 U32 spsSduSize; /*!< SDU Size recvd on SPS Occasion*/
2082 U32 spsGrantSize; /*!< Grant size for SPS allocation */
2084 CmLteTimingInfo lastSpsDatRecvdTime; /*!< timing info on which the
2085 SPS data is recieved*/
2086 CmLListCp *spsList; /*!< Pointer to the SPS list of which
2088 U32 actPdcchCrcFailCount; /*!< Num of consecutive CRC fails for
2089 SPS Activation PDCCH */
2090 U32 crcFailCntSpsOcc; /*!< Consecutive CRC fail for SPS Occasion
2092 U32 relPdcchSntCnt; /*!< Num ber Rel PDCCH sent to UE*/
2093 #ifdef RGSCH_SPS_STATS
2099 } RgSchCmnUlUeSpsInfo;
2105 * Uplink control block for UE specific information.
2107 typedef struct rgSchUeUlCb
2109 RgSchUlLcCb lcCb[RGSCH_MAX_LC_PER_UE]; /*!< Dedicated Uplink logical channel
2111 RgSchLcgCb lcgArr[RGSCH_MAX_LCG_PER_UE]; /*!< Logical channel groups */
2112 U8 ulInactvMask; /*!< Bitmask indicating if UE is inactive for UL scheduling */
2113 CmLList ulInactvLnk; /*!< Link to the inactive UE List for UL */
2114 RgSchHoPoUeGrnt rarGrnt; /*!< UE's RAR grant Information */
2115 RgrUeTxAntSelCfg ulTxAntSel;/*!< UL Transmit antenna selection Cfg Info */
2117 /* Added periodic BSR timer */
2118 RgrUeBsrTmrCfg bsrTmrCfg; /*!< BSR timers configuraiton for the UE */
2120 /* Added support for SPS*/
2122 RgrUeSpsUlCfg ulSpsCfg; /*!< UL SPS configuration information */
2123 U8 explicitRelCnt; /*!< Number of subframes after sending
2124 release to consider it successful */
2125 U16 spsPrdcty; /*!< Shall store the SPS periodicity of the
2126 UE. Needed to round-off in case of
2128 CmLteTimingInfo relPdcchSchdTime; /*!< This field holds the scheduled time
2132 U32 nPrb; /*!< Number of resource block allocated */
2135 U8 betaHqOffst; /*!< Delta HARQ offset used in the case where HARQ
2136 feedback is multiplexed with PUSCH data. */
2137 U8 betaCqiOffst;/*!< Beta offset for CQI[0-15]. Given by RRC*/
2138 U8 betaRiOffst;/*!Beta offset for RI[0-15]. Given by RRC */
2140 U32 cqiRiSz; /*!<Size of Periodic/Aperiodic CQI or RI depending
2142 U32 betaOffstVal; /*!< beta offset of CQI or RI depending
2144 U32 maxBytesPerUePerTti; /*!< Maximum bytes that can be allocated
2145 * in 1 scheduling instance per UE */
2146 U32 minReqBytes; /*!< The buffer amount of lcg0 */
2147 U32 totalBsr; /*!< Total BSR as reported by UE (in bytes) */
2148 U32 nonLcg0Bs; /*!< Total BSR for LCG1/LCG2/LCG3 */
2149 U32 nonGbrLcgBs; /*!< Total BSR as reported by UE (in bytes) for non-GBR LCG's*/
2150 U32 effBsr; /*!< BSR yet to be satisfied in allocations */
2152 U32 cfgdAmbr; /*!< Byte rate of UE Ambr per Refresh Cycle */
2153 U32 effAmbr; /*!< Remaining Bytes of Byte rate available in a refresh Cycle */
2154 CmLteTimingInfo ulTransTime; /*!< Timing info of the latest reception of
2155 any UL data/signal from UE */
2157 RgSchCmnUlUeSpsInfo ulSpsInfo; /*!< UL SPS information for UE */
2159 Bool isUlCaEnabled; /*!< If TRUE UL CA is enabled for the UE */
2160 CmLteCellId ctrlOnServCellIdx[RGSCH_ULCTRL_RECP_DIST]; /*!<
2161 * Serving Cell Idx on which UL CTRL INFO is to
2162 * be received of all configured
2165 Bool useExtBSRSizes; /*!< If TRUE used R10 Extended BSR Size Table*/
2170 * Downlink CCCH Tx/Retx schedule information.
2172 typedef struct rgSchCcchSchdInfo
2174 U32 totBytes; /*!< Total bytes allocated */
2175 CmLList retxLnk; /*!< To link hqP to retx Queues */
2176 U8 rvIdx; /*!< Rv Index */
2177 } RgSchCcchSchdInfo;
2181 * Downlink Grant Information per UE.
2183 typedef struct rgSchDlGrnt
2185 U16 schdTime; /*!< Time at which Harq proc has been scheduled */
2186 U8 rbStrt; /*!< Starting RB of the allocation */
2187 U8 numRb; /*!< Number of RBs allocated */
2188 U8 iMcs; /*!< Index to the MCS */
2189 U8 rv; /*!< RV for HARQ (re)transmission */
2190 U8 rvIdx; /*!< RVIdx for HARQ(re)transmission */
2191 #ifdef RG_5GTF /* ToDo:: Anoop need to check for other fields required*/
2197 TfuDciFormat dciFormat; /*!< DCI format for the allocation */
2204 * Logical channel data as being scheduled by the scheduler.
2206 typedef struct rgSchLchAllocInfo
2208 U8 lcId; /*!< Logical channel ID */
2209 U32 schdData; /*!< Scheduled logical channel data */
2210 } RgSchLchAllocInfo;
2212 /** @brief This structure is part of the downlink HARQ process, this structure
2213 * encapsulates all the DRX related information.
2215 typedef struct rgSchDrxDlHqProcCb
2217 CmLList harqRTTEnt; /*!< Entry into the HARQ RTT timer list */
2218 CmLList harqRetxEnt; /*!< Entry into the harqRetxQ */
2220 U16 rttIndx; /*!< Current Index into HARQ RTT Q */
2221 U16 reTxIndx; /*!< Current Index into Re-Tx Q */
2222 U8 retxTmrReduction; /*!< Due to platform specific timing diff between
2223 DL HARQ processing and DL Scheduling, the
2224 drx retx timer may start at a later time, than
2225 actual. That delay in starting the timer is
2229 } RgSchDrxDlHqProcCb;
2231 /** @enum TfuDciFormat
2232 * This Enum has values for Harq Proc TB state.
2242 * Downlink TB information per DL HqProc.
2244 struct rgSchDlHqTbCb
2246 U8 tbIdx; /*!< Index of this TB (0/1). Initialized
2247 at HqEnt allocation */
2248 U32 tbSz; /*!< TB size scheduled for this TB */
2249 U8 txCntr; /*!< Transmission counter */
2250 U8 ndi; /*!< New Data Indicator 0 or 1*/
2251 TknU8 schdTa; /*!< TA scheduled to be sent */
2252 /* CR timer implementation changes*/
2254 U8 numLch; /*!< No. of DL Logical Channels scheduled
2256 CmLteTimingInfo timingInfo; /*!< This field holds the scheduled time */
2257 RgSchLchAllocInfo lchSchdDataArr[RGSCH_MAX_NUM_DED_LC];
2258 RgSchLchAllocInfo *lchSchdData;
2259 RgSchCcchSchdInfo ccchSchdInfo;/*!< CCCH TX/RETX scheduler Info */
2260 U8 fbkRepCntr; /*!< Counter to ANRep Feedback */
2261 U8 fbkRecpRepCntr; /*!< Counter to ANRep Feedback */
2262 CmLList anRepLnk[6]; /*!< Links for ANRep we need
2264 simultaneously hold the
2267 RgSchDlSf *crntSubfrm[6]; /*!< Pointer to subframes */
2268 U8 ackCount; /*!< Counter for ACKs */
2269 U8 isAckNackDtx; /* ACK or NACK or DTX*/
2270 U8 nackCount; /* NACK Counter */
2271 U8 dtxCount; /* DTX Counter */
2272 RgSchDlGrnt dlGrnt; /*!< Scheduler grant */
2273 Bool taSnt; /*!< TA sent or not */
2275 CmLteTimingInfo fdbkTime; /*!< Expected feedback time */
2276 U8 m; /*!< Subframe Order Index within the subframe
2277 downlink association index K */
2278 RgSchTddSfType sfType; /*!< Identifies the first Tx subframe type */
2279 U8 pucchFdbkIdx;/*!< DL subframe idx for which fdbk is expected */
2280 U8 dai; /*!< DAI associated with this TB.
2281 THis is used for F1BCS resource calulcation */
2282 #ifdef XEON_TDD_SPCL
2283 U8 initTxNumRbs;/*!< Number of Rbs Allocated in First TX */
2288 U8 numLyrs; /*!< Number of layers using which this TB is
2289 being transmitted */
2290 RgSchHqTbState state; /*!< State of this Trasport Block */
2291 RgSchDlHqProcCb *hqP; /*!< Reference to the TB container */
2292 /* Freeing up the HARQ proc blocked for
2293 * indefinite time in case of Retx */
2294 U8 cntrRetxAllocFail; /*!< Number of times allocation failed
2295 for the retransmission of this TB */
2297 TknU8 schdSCellActCe; /* !< SCell Act values and whether
2300 U32 firstSchedTime; /*!< First time when the TB was scheduled */
2301 U8 minRlcReordrTmr; /*!< Min RLC reorder timer of all LCs
2302 scheduled in this hqP*/
2308 * Downlink HARQ process information per UE.
2310 struct rgSchDlHqProcCb
2312 CmLList lnk; /*!< To link with other HARQ processes */
2313 RgSchDlHqEnt *hqE; /*!< HARQ entity */
2315 U8 txCntr; /*!< Transmission counter */
2317 U8 procId; /*!< Harq process ID */
2318 Void *sch; /*!< Cmn sched Hq control block */
2320 RgSchDlHqTbCb tbInfo[2]; /*!< TB related information for 1+1(if any) TBs */
2321 RgSchDrxDlHqProcCb drxCb; /*!< DRX control block */
2323 U8 tbCnt; /*!< Count of the number TBs being sent with a
2324 Reception Requesti */
2327 TknU16 spsN1PucchRes; /*!< N1Pucch resource for HARQ process at SPS
2328 ocassions: present only when HqP contains
2329 Data without PDCCH */
2331 /* Fix: syed having a hqP added to Lists for RB assignment rather than
2332 * a UE, as adding UE was limiting handling some scenarios */
2333 CmLList reqLnk; /*!< Link for list of UEs/RACBs to be scheduled */
2334 CmLList schdLstLnk; /*!< Link for list of scheduled/non-scheduled
2335 allocations: used by RB allocation module*/
2336 Bool hasDcch; /*!< Set to TRUE if DCCH channel is present in
2337 scheduling grant over this hqProc */
2338 Bool cwSwpEnabled; /*!< Set if CW swap enabled */
2340 U8 tpc; /*!< TPC command to be used for Secondary cell
2341 N1PUCCH resource Index*/
2345 /* Shifted from TbCb to HqCb*/
2346 RgSchPdcch *pdcch; /*!< Pdcch Allocated for this Hq TB */
2347 RgSchDlSf *subFrm; /*!< Subfrm for which this TB is assgnd */
2349 Void *emtcHqInfo;/*!< emtc specfic hq info */
2351 U8 dlDai; /*!< DL DAI assosciated with this harq proc */
2352 U8 ulDai; /*!< UL DAI assosciated with this harq proc */
2358 CmLListCp *hqPLst; /*!< pointer to either inUse of free list of hqE */
2359 TfuDciFormat prevDciFormat; /*!< Previous alloction DCI format used for ERR Ind prcessing */
2362 U32 tbSizeAtEstimate[2];
2363 U32 tbSizeAtFnlz[2];
2364 U32 tbSizeOfMvdTb[2];
2365 U32 itbsAtEstimate[2];
2371 * Downlink HARQ entity information per UE.
2375 RgSchRaCb *raCb; /*!< Parent RACB when attached to RACB */
2376 RgSchUeCb *ue; /*!< Parent UE */
2377 CmLListCp free; /*!< List of free HARQ processes */
2378 CmLListCp inUse; /*!< List of in-use HARQ processes */
2379 U8 maxHqTx; /*!< Maximum number of harq transmissions */
2380 RgSchDlHqProcCb *msg4Proc; /*!< Points to MSG4 HARQ process */
2382 /* CR timer changes*/
2383 RgSchDlHqProcCb *ccchSduProc; /*!< Points to CCCH SDU HARQ process
2384 to identify feedback for CCCH SDU
2385 transmissions done without cont res CE*/
2387 U8 numHqPrcs; /*!< Number of HARQ Processes */
2389 RgSchDlHqProcCb *procs; /*!< Downlink harq processes */
2391 RgSchDlHqProcCb procs[RGSCH_NUM_DL_HQ_PROC]; /*!< Downlink harq processes */
2393 Void *sch; /*!< Scheduler specific Info */
2395 RgSchCellCb *cell; /*Contains the pointer to coresponding CellCb*/
2401 * @enum rgSchTaState
2402 * Enumeration of time alignment states.
2404 typedef enum rgSchTaState
2406 RGSCH_TA_IDLE = 0, /*!< TA is to be scheduled */
2407 RGSCH_TA_TOBE_SCHEDULED,/*!< TA is to be scheduled */
2408 RGSCH_TA_SCHEDULED /*!< TA is scheduled */
2413 * Downlink Time alignment information per UE.
2415 typedef struct rgSchUeDlTaCb
2417 U16 cfgTaTmr; /*!< Configured TA timer value */
2418 U8 ta; /*!< TA value for UE */
2419 U8 numRemSf; /*!< Number of subframes left to apply TA */
2420 RgSchTaState state; /*!< Indicates HARQ state for TA */
2421 /*rg003.301[ccpu00121813] ADD added new var*/
2422 Bool outStndngTa; /*!< if new TA is rcvd before it gets
2424 U8 outStndngTaval; /*!< outstanding TA val */
2429 * Downlink Dedicated Logical channel control block.
2433 U8 lcId; /*!< Logical channel ID */
2435 RgSchUeCb *ue; /* UE to which this LC belongs to */
2436 /* Not validating DlQos for DCCH */
2437 CmLteLcType lcType; /* Logical channel Type*/
2438 RgSchQciCb *qciCb; /*!< Pointer to ACI Control Block */
2439 /* Added support for SPS*/
2441 RgrLchSpsCfg dlLcSpsCfg; /*!< SPS configuration for DL logical channel */
2444 U16 estRlcHdrSz; /*!< Estimated RLC header size */
2445 Bool staPduPrsnt; /*!< Indicate the status pdu present or not*/
2447 U32 staPduBo; /*!< Indicate the Status PDU BO.
2448 This amount is already included in original BO */
2449 Void *sch; /*!< Holds Scheduler Info pointer */
2450 U32 prbsReqd; /*!< PRBs reqd in DL for each UE in MUE scenario*/
2451 CmLList schdLnk; /*!< Link to ueCb inserted in toBeSchdList in DL*/
2452 U32 oldestSduArrTime; /*!< oldest SDU arrival time for this LC */
2453 CmLList lcFlowCntrlEnt; /*!<link to Lc in flow Cntrl lst */
2454 CmLList lcPdbFbkLnk; /*!<link to LC in LC flow contrl monitoring lst */
2455 Bool setMaxUlPrio; /*!<set if Poll bit is sent in the PDU */
2456 Bool setMaxDlPrio; /*!<set if there is a RLC status PDU in DL */
2462 typedef struct rgSchN1PucchResCb
2464 U16 n1PucchIdx; /* !< N1 resource */
2465 CmLList n1Lnk; /* !< Link for adding into dlsf N1 used list */
2467 typedef struct rgSchN3PucchResCb
2469 U16 n3PucchIdx; /* !< N3 resource */
2470 CmLList n3Lnk; /* !< Link for adding into dlsf N3 used list */
2471 U8 sCellIdx; /* !< Allocated by which scell */
2474 typedef struct rgSchSCellN3ResCb
2476 U8 antP0N3ResCount; /* !< Number of N3 res for antenna port 0*/
2477 U8 antP1N3ResCount; /* !< Number of N3 res for antenna port 0*/
2478 RgSchN3PucchResCb antP0N3Res[RG_SCH_MAX_NUM_N3PUCCH_PER_UE]; /* !< Antenna Port 0 N3 resources*/
2479 RgSchN3PucchResCb antP1N3Res[RG_SCH_MAX_NUM_N3PUCCH_PER_UE]; /* !< Antenna Port 1 N3 resources*/
2482 typedef struct rgSchSCellN1ResCb
2484 U8 cw1N1ResCount; /* !< Number of N1 res for CW 1*/
2485 U8 cw2N1ResCount; /* !< Number of N1 res for CW 2*/
2486 RgSchN1PucchResCb cw1N1Res[RG_SCH_MAX_NUM_N1PUCCH_PER_UE]; /* !< CW1 N1 resources*/
2487 RgSchN1PucchResCb cw2N1Res[RG_SCH_MAX_NUM_N1PUCCH_PER_UE]; /* !< CW2 N1 resources*/
2491 typedef struct rgSchN3PucchRes
2493 U16 n3PucchIdx; /* !< N3 resource */
2497 typedef struct rgSchDlHqInfo
2501 U8 numOfCells; /*!<This will be used to store number of unique cells in
2503 Bool isSCellPdschPres; /*!< Flag to indicate whether any PDSCH transmission
2504 present in secondary cell. Used for CSI/HARQ collision
2507 Bool isPuschHarqRecpPres;/*!< Flag to indicate pusch recp req is pres or not */
2508 RgrSchFrmt1b3TypEnum uciFrmtTyp; /*!< Store value of format1b or format3.
2510 U8 totalTbCnt; /*!< This will be used to store total number of TBs
2511 across all harqProcs.It will be used to identify
2512 PUCCH format type to be used in this SF*/
2513 CmLList dlSfUeLnk; /*!< list entry into dlsf->ueLst */
2515 CmLListCp hqPLst; /*!< This is a list of hq proc per DL
2516 SF which are scheduled in that SF.
2517 The number of harq procs awaiting
2518 feedback for the same subframe depends on
2519 mode TDD or FDD and max number of Carriers
2520 that can be aggregated */
2522 RgSchN3PucchRes n3ScellPucch;
2527 /** @brief This structure contains the Measurement gap configuration for an UE.
2529 typedef struct rgUeMeasGapCfg
2531 Bool isMesGapEnabled; /*!< Is Measuremnet gap enabled or disabled */
2532 U8 gapPrd; /*!< Gap period 40ms/80ms */
2533 U8 gapOffst; /*!< Gap offset - Vaue is 0 to 1*/
2537 @brief Measurement Gap related information per UE. */
2538 typedef struct rgSchUeMeasGapCb
2540 Bool isMesGapEnabled;/*!< TRUE if Measurement gap is enabled for this UE */
2541 U8 isMeasuring; /*!< Set to TRUE during measurement gap */
2542 U8 gapPrd; /*!< Measurement gap period configuration for the UE */
2543 U8 gapOffst; /*!< Measurement gap offset for the UE */
2544 CmLList measQLnk; /*!< To Link to the measurement gap list */
2545 CmLList ackNakQLnk; /*!< To Link to the ACK NACK Rep list */
2546 CmTimer measGapTmr; /*!< Timer for Measurement Gap */
2547 CmTimer measGapUlInactvTmr; /*!< UL Inactive timer for measurement gap */
2548 CmTimer measGapDlInactvTmr; /*!< DL Inactive timer for measurement gap */
2552 @brief ACK-NACK repetition related information per UE. */
2553 typedef struct rgSchUeAckNakRepCb
2555 Bool isAckNackEnabled; /*!< Is ACK/NACK Enabled*/
2556 U8 isAckNakRep; /*!< Set to TRUE during ACK-NACK repetition prd */
2557 U8 cfgRepCnt; /*!< Configured value for the repetition counter */
2558 U8 repCntr; /*!< Actual repetition counter */
2559 U16 pucchRes; /*!< PUCCH resource for repetition */
2560 CmTimer ackNakRepUlInactvTmr; /*!< UL Inactive timer for ack-nack repetition */
2561 CmTimer ackNakRepDlInactvTmr; /*!< DL Inactive timer for ack-nack repetition */
2562 CmTimer ackNakRepTmr; /*!< Timer for ack-nack repetition */
2563 CmLList ackNakRepLnk; /*!< ACK NACK repetition queue link */
2564 CmLListCp *prsntQ; /*!< Pointer to the Queue that this UE is current
2566 } RgSchUeAckNakRepCb;
2570 * UE's MIMO specific information.
2572 typedef struct rgSchUeMimoInfo
2574 RgrTxMode oldTMode; /*!< UE's Previous Transmission Mode */
2575 RgrTxMode txMode; /*!< UE's Transmission Mode */
2576 TknU32 doa; /*!< DOA indicator for this UE */
2577 Bool puschFdbkVld; /*!< True if Precoding Info in PDCCH has to be
2578 in-accordance with the latest PUSCH report */
2579 TfuDlCqiPuschInfo puschPmiInfo; /*!< PUSCH report details for explicit PMI
2580 * information to PHY during a PDSCH */
2581 RgrCodeBookRstCfg cdbkSbstRstrctn; /*!< Codebook subset restriction defined as per
2582 * 36.331 section 6.3.2. As of now, this info
2583 * is not processed by MAC. SCH shall use the
2584 * PMI reported by UE unconditionally.*/
2586 S32 txModUpChgFactor; /*!< tx mode chnage factor for step up*/
2587 S32 txModDownChgFactor; /*!< tx mode chnage factor for step
2592 /* Added changes of TFU_UPGRADE */
2595 /** @brief This structure that stores the length of Bits that
2596 * will be received over PUSCH for Aperiodic Mode 3-1.
2598 typedef struct rgSchCqiRawPuschMode31
2600 U8 wideBCqiCw0; /*!< Length of Wideband CQI Codeword 0 */
2601 U8 totLenSbDiffCqiCw0; /*!< Length of SubBand Differential CQI Codeword 0 */
2602 U8 r1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank =1*/
2603 U8 r1TotLenSbDiffCqiCw1; /*!< Length of SubBand Differential CQI Codeword 1 for Rank = 1*/
2604 U8 rg1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank > 1*/
2605 U8 rg1TotLenSbDiffCqiCw1; /*!< Length of SubBand Differential CQI Codeword 1 for Rank > 1*/
2606 U8 r1PmiBitLen; /*!< Length of PMI Bits for Rank = 1*/
2607 U8 rg1PmiBitLen; /*!< Length of PMI Bits for Rank > 1*/
2608 } RgSchCqiRawPuschMode31;
2610 /** @brief This structure that stores the length of Bits that
2611 * will be received over PUSCH for Aperiodic Mode 3-0.
2613 typedef struct rgSchCqiRawPuschMode30
2615 U8 wideBCqiCw; /*!< Length of Wideband CQI */
2616 U8 totLenSbDiffCqi; /*!< Length of SubBand Differential CQI */
2617 } RgSchCqiRawPuschMode30;
2619 /** @brief This structure that stores the length of Bits that
2620 * will be received over PUSCH for Aperiodic Mode 2-2.
2622 typedef struct rgSchCqiRawPuschMode22
2624 U8 wideBCqiCw0; /*!< Length of Wideband CQI Codeword 0 */
2625 U8 sBDiffCqiCw0; /*!< Length of SubBand Differential CQI Codeword 0 */
2626 U8 r1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank =1 */
2627 U8 r1SbDiffCqiCw1; /*!< Length of SubBand Differential CQI Codeword 1 for Rank =1*/
2628 U8 rg1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank > 1*/
2629 U8 rg1SbDiffCqiCw1; /*!< Length of SubBand Differential CQI Codeword 1 for Rank >1*/
2630 U8 posOfM; /*!< Position of M selected SubBands */
2631 U8 r1PmiBitLen; /*!< Length of PMI Bits for Rank =1*/
2632 U8 rg1PmiBitLen; /*!< Length of PMI Bits for Rank >1*/
2633 } RgSchCqiRawPuschMode22;
2635 /** @brief This structure that stores the length of Bits that
2636 * will be received over PUSCH for Aperiodic Mode 2-0.
2638 typedef struct rgSchCqiRawPuschMode20
2640 U8 wideBCqiCw; /*!< Length of Wideband CQI */
2641 U8 subBandDiffCqi; /*!< Length of SubBand Differential CQI */
2642 U8 posOfM; /*!< Position of M selected SubBands */
2643 } RgSchCqiRawPuschMode20;
2645 /** @brief This structure that stores the length of Bits that
2646 * will be received over PUSCH for Aperiodic Mode 1-2.
2648 typedef struct rgSchCqiRawPuschMode12
2650 U8 wideBCqiCw0; /*!< Length of Wideband CQI Codeword 0 */
2651 U8 r1WideBCqiCw1; /*!< Length of Wideband CQI Codeword 1 for Rank =1*/
2652 U8 rg1WideBCqiCw1; /*!< Length of Wideband CQI Codeword for Rank > 1 */
2653 U8 r1TotalPmiBitLen; /*!< Aggregate length of PMI Bits for Rank =1 */
2654 U8 rg1TotalPmiBitLen; /*!< Aggregate length of PMI Bits for Rank > 1 */
2655 } RgSchCqiRawPuschMode12;
2658 /** @brief This structure that stores the length of Bits that
2659 * will be received over PUSCH.
2661 typedef struct rgSchDlCqiRawPusch
2663 TfuDlCqiPuschMode mode; /*!< PUSCH CQI mode */
2664 TknU8 ri; /*!< Rank Indicator for TM 3,4 */
2667 RgSchCqiRawPuschMode12 mode12Info; /*!< Mode 1-2 information */
2668 RgSchCqiRawPuschMode20 mode20Info; /*!< Mode 2-0 information */
2669 RgSchCqiRawPuschMode22 mode22Info; /*!< Mode 2-2 information */
2670 RgSchCqiRawPuschMode30 mode30Info; /*!< Mode 3-0 information */
2671 RgSchCqiRawPuschMode31 mode31Info; /*!< Mode 3-1 information */
2673 } RgSchDlCqiRawPusch;
2675 typedef struct rgSchPuschRawCqiInfoPerCell
2677 U8 sCellIdx; /*!< Serving cell idx of the cell for
2679 RgSchDlCqiRawPusch puschRawCqiInfo; /*!< Raw CQI Bit Width for PUSCH */
2680 } RgSchPuschRawCqiInfoPerCell;
2682 typedef struct rgSchPuschRawCqiInfoForSCells
2684 U8 numOfCells; /* Num of cells for which Apcqi is comming*/
2685 RgSchPuschRawCqiInfoPerCell cqiBitWidth[CM_LTE_MAX_CELLS];
2686 } RgSchPuschRawCqiInfoForSCells;
2688 typedef struct rgSchPucchRawCqiInfoPerCell
2690 U8 sCellIdx; /*!< Serving cell idx of the cell for
2692 TfuDlCqiPucch pucchRawCqiInfo; /*!< Raw CQI Bit Width for PUCCH */
2693 } RgSchPucchRawCqiInfoPerCell;
2695 typedef struct rgSchUeRawCqiBitWidthInfo
2697 TfuRecpReqType type; /*!< Type indicating PUCCH or PUSCH */
2698 CmLteTimingInfo recvTime;
2701 RgSchPucchRawCqiInfoPerCell pucch;
2702 RgSchPuschRawCqiInfoForSCells pusch;
2704 } RgSchUeRawCqiBitWidthInfo;
2713 * Enum for storing the different states of a Scell
2714 * RG_SCH_SCELL_INACTIVE : SCell is added but not activate
2715 * RG_SCH_SCELL_TOBE_ACTIVATED : SCell Activation trigger condition is met
2716 Need to be scheduled.
2717 * RG_SCH_SCELL_ACTVTN_IN_PROG : Waiting for Harq feedback for the scell activation
2718 * RG_SCH_SCELL_ACTIVE : SCell is activated succesfully
2722 RG_SCH_SCELL_INACTIVE = 0, /*!<SCELL Addition/Reset */
2723 RG_SCH_SCELL_READY, /*!<SCELL Ready is reaceived or SCell is deactivated */
2724 RG_SCH_SCELL_TOBE_ACTIVATED, /*!<Activation Trigger */
2725 RG_SCH_SCELL_ACTVTN_IN_PROG, /*<!Activation CE is sent */
2726 RG_SCH_SCELL_TOBE_DEACTIVATED, /*<!Deactivation Trigger */
2727 RG_SCH_SCELL_DEACTVTN_IN_PROG, /*<!Deactivation CE is sent */
2728 RG_SCH_SCELL_ACTIVE /*<!SCell is activated */
2733 * Enum to define the value of A for Format 1B with CS
2734 * in FDD Case and for M=1 in TDD Case.
2741 RG_SCH_A_VAL_INVALID = 5
2747 * Enum to define the value of A for Format 1B with CS
2748 * in FDD Case and for M=1 in TDD Case.
2756 RG_SCH_M_VAL_INVALID = 5
2763 * Downlink UE specific SCell information.
2765 struct rgSchUeCellInfo
2767 CmHashListEnt ueLstEnt; /*!< Hash List entity for UE List */
2768 RgSchUeCb *ue; /*!< Pointer to UECB */
2770 U8 sCellIdx; /*!< Serving Cell Index */
2771 U16 sCellId; /*!< Secondary Cell Id */
2772 RgSCellStateEnum sCellState; /* !< For holding the current state of the sec cell */
2773 CmLList sCellLnk; /*!< Node for adding this UE in secondary cell */
2775 RgSchDlHqEnt *hqEnt; /*!< Downlink HARQ information for the UE */
2776 RgSchDlRbAlloc dlAllocCb; /*!< RB Allocation Info for Ded Trans/Retrans */
2777 RgSchCellCb *cell; /* !< Reference to sec Cell Cb */
2778 Void *sch; /*!< UE Specific Scheduler information */
2779 RgrUeTxModeCfg txMode; /*!< UE transmission mode in Secondary */
2781 RgSchTddANInfo *anInfo; /*!< ACK/NACK related Information */
2782 U8 nextFreeANIdx; /*!< Next Available ANInfo Index */
2785 U8 reqForCqi; /*!< set to True if Aperiodic CQI from UE is required */
2787 RgSchUeACqiCb acqiCb; /* ! < Aperiodic CQI Report Control Block*/
2788 RgSchUePCqiCb cqiCb; /*!< Periodic CQI PMI RI Control Block */
2789 TknU8 pA; /* PA value configured by RRM
2790 ref: RRC 36.331, 6.3.2, PDSCH-Config*/
2791 /* RgSchUeRawCqiBitWidthInfo rawCqiBitW[MAX_CQI_RI_RPT_BUFF]; */
2793 U8 cqiRiWritIdx; /*!< write index to be used whenever CQI/RI reception
2794 request is being filled*/
2795 U8 cqiRiReadIdx; /*!< Read index to be used whenevr CQI/RI indication
2796 is recieved from PHY*/
2797 CmTimer deactTmr; /*!< SCell deactivation timer */
2798 CmTimer actDelayTmr; /*!< SCell timer */
2810 * Downlink control block for UE specific information.
2812 typedef struct rgSchUeDlCb
2814 RgSchUeDlTaCb taCb; /*!< Downlink timing adjustment information for the
2816 RgSchDlLcCb *lcCb[RGSCH_MAX_LC_PER_UE];/*!< Dedicated Downlink logical channels in
2818 RgrUeDlCqiCfg ueDlCqiCfg; /*!< UE DL CQI config */
2819 U8 dlInactvMask; /*!< Bitmask indicating if UE is inactive for DL scheduling */
2820 RgSchCqiReqField reqForCqi; /*!< set to True if Aperiodic CQI from UE is required */
2821 Bool pCqiPrsnt; /*!< set to True if periodic CQI from UE is expected */
2822 Bool acqiResGrntd; /*!< Aperiodic CQI resources granted in RB Estimation */
2823 CmLList dlInactvLnk; /*!< Link to the inactive UE List for DL */
2825 RgrTddAckNackMode ackNackMode; /*!< ACK/NACK Bundling/ ACK/NACK Multiplexing */
2827 /* Added support for SPS*/
2829 RgrUeSpsDlCfg dlSpsCfg; /*!< DL SPS configuration information */
2830 Bool isSpsHqPInUse; /*!< Indicates if SPS HARQ procs are in use
2831 or are to be used for SPS
2833 RgSchPdcch spsOccPdcch; /*!< PDCCH information for SPS ocassion */
2838 RgSchDlHqInfo *dlSfHqInfo;
2841 /* 5GTF TODO : Hard setting number of CCs to 3 */
2842 RgSchDlHqInfo dlSfHqInfo[MAX_5GTF_CELL][RGSCH_NUM_DL_SUBFRAMES];
2844 RgSchDlHqInfo dlSfHqInfo[RGSCH_NUM_DL_SUBFRAMES];
2847 /* Moved from rgSchCmnDlUe to Here, as this shouldn't be present per cell*/
2848 U32 ambrCfgd; /*!< UE's configured AMBR scaled to Refresh Cycle */
2850 /* Added to restrict max TB Bits in case of more than one CCs for a UE */
2851 U32 aggTbBits; /*!< Aggregated Transport Block Bits this UE can receive per TTI*/
2852 CmLteTimingInfo lstSchTime; /*!< Last Time UE got Scheduled */
2860 /******************************************************************************
2861 * Start of Data declarations *
2862 ******************************************************************************/
2864 @brief Half Duplex subframtion information stored per ue. */
2866 typedef struct rgSchUeHdFddSfInfo
2868 U16 sfn; /*!< Store the sfn for updated state
2869 Default Value= 0xffff
2873 0x01= DL DATA +(OPT:CNTRL INFO)
2875 0x04= UL DATA+(OPT: CTNRL INFO)
2878 }RgSchUeHdFddSfInfo;
2881 @brief Half Duplex control related information per ue. */
2883 typedef struct rgSchUeHdFddCb
2885 RgSchUeHdFddSfInfo subfrm[RG_SCH_HDFDD_NUMSFINFO];
2888 #endif /* LTEMAC_HDFDD */
2891 /** @brief This structure is part of rgSchUeCb structure and stored DRX related
2892 * information for a UE.
2894 typedef struct rgSchDrxUeCb
2897 TknS32 cqiMask; /*!<If pres, only value supported is SETUP i.e 0 */
2899 Bool srRcvd; /*!< TRUE if SR is received from the UE. */
2900 Bool raRcvd; /*!< TRUE if Random access request is received using a
2901 dedicated preamble for this UE. */
2902 U16 onDurTmrLen; /*!< Length of onDuration Timer [1 - 200]. */
2903 U16 drxStartOffset; /*!< Value of the DRX Starting Offset [0 - 2559]. */
2904 S16 onDurExpDistance; /*!< Keeps track of actual distance */
2906 U16 drxRetransTmrLen; /*!< Length of DRX Retransmission timer [1 - 33].*/
2908 U16 inactvtyTmrLen; /*!< Length of drx-Inactivity Timer [1 - 2560]. */
2909 S16 drxInactDistance; /*!< Keeps track of actual distance */
2912 U16 longDrxCycle; /*!< Value of the DRX long cycle [10 - 2560]. */
2914 Bool isShortCycleCfgd; /*!< TRUE if short cycle is enabled. */
2915 U8 shortCycleTmrLen; /*!< Value of DRX short cycle Timer [1-16]. */
2916 U16 shortDrxCycle; /*!< Value of the DRX short cycle [2 - 640]. */
2917 S16 drxShortCycleDistance; /*!< Keeps track of actual distance */
2920 CmLList onDurationEnt; /*!< Entry into the OnDuration List. */
2921 CmLList onDurationExpEnt; /*!< Entry into the onDuration Expiry List. */
2922 CmLList inActvTmrEnt; /*!< Entry into the inactivity Timer list. */
2923 CmLList shortCycleEnt; /*!< Entry into HARQ Retransmission list. */
2925 S16 distance; /*!< Keeps track of actual distance */
2927 /* The following elements track current indices into the drxQ present at the
2928 * cell level. These indicies help in fast deletion in case of UE Delete,
2929 * otherwise it might have required a linear search. */
2930 U16 onDurIndx; /*!< The current index for onDuration Queue. */
2931 U16 onDurExpIndx; /*!< The current index for onDuration Queue. */
2932 U16 drxInactvIndx; /*!< The current index for drx-InactityTmr Queue. */
2933 U16 shortCycleIndx; /*!< The current index for Short Cycle Queue. */
2935 U8 shortCycleTmr; /*!< Counter to keep track of Short DRX Cycle. */
2936 U32 drxDlInactvMask; /*!< Downlink Mask to track InActivity */
2937 U32 drxUlInactvMask; /*!< Uplink Mask to track InActivity */
2938 U32 drxDlInactvMaskPerCell[CM_LTE_MAX_CELLS]; /*!< Downlink Mask to track InActivity per cell */
2939 U32 drxUlInactvMaskPerCell[CM_LTE_MAX_CELLS]; /*!< Uplink Mask to track InActivity per cell */
2944 /* ccpu00117452 - MOD - Changed macro name from
2945 RGR_RRM_DLPWR_CNTRL to RGR_CQI_REPT */
2947 typedef struct RgSchCqiInfo
2949 U8 cqiCount; /* To keep track of CQI reports
2951 RgrUeCqiRept cqiRept[RGR_CQIRPTS_MAXN]; /* Array to maintain CQI reports */
2957 /* LTE_ADV_FLAG_REMOVED_START */
2959 /* @brief Control block for LTE Advance Feature for UE */
2960 typedef struct rgSchLteAdvUeCb
2962 RgrLteAdvancedUeConfig rgrLteAdvUeCfg; /*< RGR Configuration of LTE Adv */
2963 Bool isCCUePHigh; /* CC user gets high power after RNTP info */
2964 } RgSchLteAdvFeatureUeCb;
2965 /* LTE_ADV_FLAG_REMOVED_END */
2967 /*<! Sizes of DCI 0/1/1A/2/2A */
2968 typedef struct rgSchUeDciSize {
2970 U8 cmnSize[TFU_DCI_FORMAT_6_2+1]; /*!< DCI 0/1A/6-0A/6-1A final size in common Search Space and scrambled by C-RNTI */
2971 U8 dedSize[TFU_DCI_FORMAT_6_2+1]; /*!< DCI 0/1/1A/2/2A/6-0A/6-1A final size in UE Search Space and scrambled by C-RNTI */
2973 U8 cmnSize[TFU_DCI_FORMAT_1A+1]; /*!< DCI 0/1A final size in common Search Space and scrambled by C-RNTI */
2974 U8 dedSize[TFU_DCI_FORMAT_2A+1]; /*!< DCI 0/1/1A/2/2A final size in UE Search Space and scrambled by C-RNTI */
2976 U8 noUlCcSize[TFU_DCI_FORMAT_2A+1]; /*!< DCI 1/1A final size in UE/Common Search Space when the cell
2977 is SCell and no corresponding UL CC configured */
2981 typedef struct rgSchPerRefreshStats {
2986 }RgSchPerRefreshStats;
2988 typedef struct rgSchLcStats
2992 U32 ueSchdOcc[CM_LTE_MAX_CELLS];
2993 U32 gbrSatisfiedCnt;
2994 Bool ignoredFirstRefresh;
2995 U32 gbrRefreshCycleCnt;
2996 U32 totGbrBytesSchd;
2997 U32 totMbrBytesSchd;
2998 U32 achvdFracDataRate;
3000 #define RGSCH_NUM_STATS_PER_REFRESH 50
3003 U32 favCellCnt[CM_LTE_MAX_CELLS];
3004 RgSchPerRefreshStats perRefresh[RGSCH_NUM_STATS_PER_REFRESH];
3007 typedef struct rgSchCqiStats
3013 typedef struct rgSchPfsStats
3015 RgSchLcStats lcStats[RGSCH_MAX_LC_PER_UE];
3016 //U32 ueSchdOcc[CM_LTE_MAX_CELLS];
3017 U32 refreshCycleCnt;
3018 RgSchCqiStats cqiStats[CM_LTE_MAX_CELLS];
3026 * UE control block for UE specific information for 5gtf.
3028 typedef struct rgSch5gtfUeCb
3030 U8 grpId; // Group Id
3031 U8 BeamId; // Beam Id of UE
3032 U8 numCC; // num Carrier configured for UE
3033 U8 mcs; // MCS configured
3034 U8 maxPrb; // Max Prb configured for UE
3035 CmLteTimingInfo nxtCqiRiOccn; /*!< Next CQI RI Occn */
3036 U16 cqiRiPer; /*!< CQI RI periodicity in SFs */
3037 U8 rank; /*!< Latest Rank Report from UE */
3043 * UE control block for UE specific information.
3047 U32 totalBo; /*!<Sum of DL BO across all logical channels*/
3048 U32 totalPrbRequired;/*!<Num of PRB reqd to satisfy DL totlBo*/
3049 /* Added support for SPS*/
3051 CmHashListEnt spsUeLstEnt; /*!< Hash List entity for UE List */
3052 U32 spsOccasionCnt; /*!< Total number of SPS occasion cnt*/
3054 #ifdef CQI_CONFBITMASK_DROP
3058 RgSchRntiLnk *rntiLnk; /*!< Link to RNTI for the UE */
3059 CmLteRnti ueId; /*!< UE identifier */
3060 RgSchUeMimoInfo mimoInfo; /*!< MIMO related information for a UE */
3061 /* Added support for SPS*/
3063 CmLteRnti spsRnti; /*!< Configured value for spsRnti if SPg
3064 is enabled for the UE */
3065 /* TODO antz - put all relPdcch related info in a struct */
3066 CmLteTimingInfo relPdcchTxTime; /*!< Time at which release pdcch is
3069 U8 relPdcchValm; /*!< 'm' for relPdcch */
3071 CmLteTimingInfo relPdcchFbkTiming;/*!< Release PDCCH feedback timing for
3072 the UE: value used by DHM */
3074 RgSchCellCb *cell; /*!< Cell to which this UE belongs */
3075 #ifdef XEON_SPECIFIC_CHANGES
3076 Void *sch; /*!< UE Specific Scheduler information */
3078 RgSchUeUlCb ul; /*!< UE Specific Uplink information */
3079 RgSchUeDlCb dl; /*!< UE Specific Downlink information */
3080 CmLteTimingInfo datIndTime;/*!< Timing info of the last received Dat
3082 CmLteTimingInfo macCeRptTime;/*!< Timing info of the last received
3083 * MAC CE (BSR/PHR) */
3084 U32 y[RGSCH_NUM_SUB_FRAMES]; /*!< 'Y' values calculated
3085 using C-RNTI and subframe
3087 present in sec 9.1.1 of
3090 CmLList taLnk; /*!< To link to the taUeLst list */
3091 CmLList dlTaLnk; /*!< To link to the Dl SCHED's taLst */
3092 CmTimer taTmr; /*!< Timer for Timing Alignment */
3093 RgSchUeMeasGapCb measGapCb; /*!< Measurement gap control block */
3094 RgSchUeAckNakRepCb ackNakRepCb; /*!< Ack-Nack Repetition control block */
3096 CmLList sCellActLnk; /*!< To link to the Dl SCHED's
3097 ScellActivation List */
3101 /* Added periodic BSR timer */
3102 CmTimer bsrTmr; /*!< BSR timer expiry handling case */
3103 /* CR timer implementation changes*/
3104 CmLList ccchSduLnk; /*!< To link raCb to the "to be
3110 U32 bo; /*!< Buffer occupancy for
3112 } dlCcchInfo; /*!< Params for DL
3116 CmTimer bsrTmr; /*!< BSR timer expiry handling case */
3118 /* Added changes of TFU_UPGRADE */
3120 CmLteUeCategory ueCatEnum;
3121 /* Moved to SCellInfo*/
3122 // RgSchUeACqiCb acqiCb; /* ! < Aperiodic CQI Report Control Block*/
3123 /* Periodic CQI/SRS/SR Report Feature */
3124 RgSchUeSrsCb srsCb; /*!< SRS Control Block*/
3125 RgSchUeSrCb srCb; /*!< SR Control Block */
3129 /* Half Duplex Feature */
3130 Bool hdFddEnbld; /*!< Half Duplex FDD is configured TRUE=1/FALSE=0 */
3131 RgSchUeHdFddCb *hdFddCb; /*!< Half Duplex Control Block */
3132 #endif /* LTEMAC_HDFDD */
3133 /* Added changes of TFU_UPGRADE */
3134 Bool isDrxEnabled; /*!< isDrx Enabled for this UE?*/
3135 RgSchDrxUeCb *drxCb; /*!< DRX control block. Allocated at time of
3136 UE configuration. */
3137 CmLList ulDrxInactvLnk; /*!<List of UE's which become inactive for UL */
3138 CmLList dlDrxInactvLnk; /*!<List of UE's which become inactive for DL */
3140 CmLList ulDrxInactvTmrLnk; /*!<List of UEs on which inactivity
3141 tmr has to be started for UL */
3142 CmLList dlDrxInactvTmrLnk; /*!<List of UEs on which inactivity
3143 tmr has to be started for DL */
3146 U8 validTxAnt; /*! < Tx Antenna selected after computing the CQI among two Antennas*/
3148 U8 cqiRiWritIdx; /*!< write index to be used whenever CQI/RI reception
3149 request is being filled*/
3150 U8 cqiRiReadIdx; /*!< Read index to be used whenevr CQI/RI indication
3151 is recieved from PHY*/
3152 RgSchUeRawCqiBitWidthInfo rawCqiBitW[MAX_CQI_RI_RPT_BUFF];
3153 U8 initNumRbs; /* No. of RBs allocated for UL Data New Transmission */
3156 /* ccpu00117452 - MOD - Changed macro name from
3157 RGR_RRM_DLPWR_CNTRL to RGR_CQI_REPT */
3159 RgrUeCqiReptCfg cqiReptCfgInfo; /* Holds static information such
3160 as configured values for DL
3165 /* ccpu00117452 - MOD - Changed macro name from
3166 RGR_RRM_DLPWR_CNTRL to RGR_CQI_REPT */
3168 RgSchCqiInfo schCqiInfo; /* This structure is place holder for
3169 keeping all CQI reporting related information */
3171 /* LTE_ADV_FLAG_REMOVED_START */
3172 RgSchLteAdvFeatureUeCb lteAdvUeCb; /* LTE-Advanced control block for UE */
3173 /* LTE_ADV_FLAG_REMOVED_END */
3177 U8 qciActiveLCs[LRG_MAX_QCI]; /* This structure has number of active LCs per
3178 Qci for this UE */ /* L2_COUNTERS */
3179 U16 ulActiveLCs; /* This is a bitmask - Each bit representing a QCI
3180 LSB - QCI 1 ... When bit is set, UE has an active
3182 U16 lastDatIndLCs; /* This is a bitmask - Each bit representing a QCI
3183 for which Data for received in UL
3184 LSB - QCI 1 ... When bit is set, UE has an active
3187 Bool isMsg4PdcchWithCrnti; /* This is to aid rgNumMsg4PdcchWithCrnti counter which counts
3188 num of PDCCH scrambled with CRNTI for CRNTI Based contention resolution */
3189 Bool isSrGrant; /*!< This is to aid Counter to check number of successful SR Grants SR_RACH_STATS*/
3190 Bool txModeTransCmplt; /*!< Flag to confirm TM Mode
3191 transition completion*/
3192 CmTimer txModeTransTmr; /*!< Timer for TxMode transition Completion */
3193 #ifdef RGSCH_SPS_STATS
3194 CmLteTimingInfo lastSpsLcBoRptTime;
3195 CmLteTimingInfo lastSpsLcSchedTime;
3199 U8 refreshOffset; /*!< UE referesh offset */
3200 U8 csgMmbrSta; /*!< CSG Membership status configured */
3202 TSL2UeStatsCb *tenbStats; /*!< UE Stats Holder */
3204 CmLListCp flowCntrlLcLst;/*!< Dedicated Downlink logical channels in UE for Flow Control*/
3205 CmLList ueFlowCntrlEnt;/*!<UE lnk to the flow control Lst*/
3207 RgSchLcgCb *repLcg;/*!<representative LCG of the UE in UL */
3208 #ifdef XEON_SPECIFIC_CHANGES
3209 CmLteTimingInfo riRecpTime; /*! To idnentify Ri wrap arround during PUSCH and
3210 PUCCH reception filling */
3213 TknU32 sCellDeactTmrVal; /* !< SCell Deactivation Timer Value */
3214 U8 f1bCsAVal; /* !< A value mentioned in table 10.12.2.1-1 of 36.213. This will tell
3215 the max number of tbs possible based on TM mode of each configured
3216 scell. It is used only for F1B with channel selection*/
3219 RgSchSCellN1ResCb n1PucchF1bResCb; /*!< N1 resouurce Cb for F1b Channel selection */
3220 RgSchSCellN3ResCb n3PucchResCb;
3221 RgrSchFrmt1b3TypEnum uciFrmtTyp; /*!< Store value of format1bcs or format3.It
3222 is updated from upper layer*/
3224 U8 numSCells; /* !< number of configured SCells */
3225 U8 cellIdToCellIdxMap[CM_LTE_MAX_CELLS]; /*!< Mapping info of Cell Id to Cell Idx */
3227 RgSchUeCellInfo *cellInfo[CM_LTE_MAX_CELLS]; /*!< DL Sec Cell Information */
3229 RgSchUePCqiCb *nPCqiCb; /*!< Pointer to Periodic Cqi CB for which next CQI is expected*/
3230 RgSchUePCqiCb *nPRiCb; /*!< Pointer to Periodic Cqi CB for which next RI is expected*/
3232 U8 remBoCnt; /*!< count of occurence when BO is not fullfilled
3234 U8 *zeroBoCnt; /*!< pointer of count of occurence when BO is
3237 Bool isScellExplicitDeAct; /*!< TRUE when SCELL deactivation timer is Infinity/Not configured */
3238 Bool allocCmnUlPdcch; /*!< If this flag is TRUE, allocate PDCCH from Common
3240 U8 simulAckNackCQIFormat3; /* !< Flag for simultanious A/N and CQI on PUCCH Format 3 */
3242 RgSchUeDciSize dciSize; /*!< DCI Sizes */
3243 RgrAccessStratumRls accessStratumRls; /*!< UE Release */
3245 RgSchPfsStats pfsStats;
3248 Bool isEmtcUe; /*!< flag to check EMTC UE */
3249 Void *emtcUeInfo; /*!< EMTC UE specific information */
3252 RgSch5gtfUeCb ue5gtfCb; /*!< UECb of 5gtf */
3259 * Configuration Information for Upper SAPs at RGU, CRG and RGR interfaces.
3261 typedef struct rgSchUpSapCfgInfo
3263 Pst sapPst; /*!< Post info associated with SAP */
3264 SpId spId; /*!< SpId associated with SAP */
3265 SuId suId; /*!< SuId associated with SAP */
3270 * Configuration Information for Lower SAP at TFU interface.
3272 typedef struct rgSchLowSapCfgInfo
3274 Pst sapPst; /*!< Post info associated with SAP */
3275 SpId spId; /*!< SpId associated with SAP */
3276 SuId suId; /*!< SuId associated with SAP */
3277 TmrCfg bndTmr; /*!< Bind Timer Value */
3278 }RgSchLowSapCfgInfo;
3282 * Control Block structure for Upper SAPs at RGU, CRG and RGR interfaces.
3284 typedef struct rgSchUpSapCb
3286 RgSchUpSapCfgInfo sapCfg; /*!< Configuration info */
3287 RgSapSta sapSta; /*!< SAP Status */
3288 RgSchCellCb *cell; /*!< Cell associated with this sap */
3293 * Control Block structure for Lower SAP at TFU interface.
3295 typedef struct rgSchLowSapCb
3297 RgSchLowSapCfgInfo sapCfg; /*!< SAP configuration info */
3298 RgSapSta sapSta; /*!< SAP Status */
3299 U8 numBndRetries; /*!< Number of Bind Retries */
3300 RgSchCellCb *cell; /*!< Cell associated with this SAP */
3301 CmTimer tmrBlk; /*!< Timer Block associated with this SAP */
3306 * structure holding Layer Manager Response information cached from control
3309 typedef struct rgSchLmResponse
3311 TranId transId; /*!< Transaction ID */
3312 Resp response; /*!< Response */
3315 /* XXX: Below structures added for PDCCH Order req for RACH Module */
3316 typedef enum sfnEnum
3323 typedef struct rgSchConfigIdx
3325 U8 configurationIndex; /* New RGR Cell cfg */
3330 typedef struct rgSchRapId
3333 CmLteTimingInfo lastAllocPRACHMaskIdx;
3336 typedef struct pdcchOrderCfg
3338 RgSchRapId rapIds[RGSCH_MAX_RAPID];
3339 RgSchConfigIdx configIdx;
3344 @brief Measurement Gap related information per cell. */
3345 typedef struct rgSchMeasGapCb
3347 CmLListCp gapPrd40Q[RG_SCH_CMN_MEAS_GAPPRD40]; /*!< Measurement Gap queue
3348 for UEs with 40 ms gap period */
3349 CmLListCp gapPrd80Q[RG_SCH_CMN_MEAS_GAPPRD80]; /*!< Measurement Gap queue
3350 for UEs with 80 ms gap period */
3354 @brief ACK-NACK repetition related information per cell. */
3355 typedef struct rgSchAckNakRepCb
3358 CmLListCp ackNakRepQ[2*RGSCH_NUM_SUB_FRAMES]; /*!< ACK NACK repetition queue */
3360 CmLListCp ackNakRepQ[RGSCH_NUM_SUB_FRAMES]; /*!< ACK NACK repetition queue */
3365 * Structure holding RBG information for the BW
3367 typedef struct rgSchBwRbgInfo
3369 U8 numRbs; /*!< Total number of RBs for which information is
3371 U8 numRbgs; /*!< Number of RBGs for the BW (rounded off to the
3372 closest RBG number */
3373 U8 rbgSize; /*!< RBG size */
3374 U8 lastRbgSize; /*!< Last RBG size : in number of RBs */
3375 U8 rbgSubsetSize[RG_SCH_NUM_RATYPE1_SUBSETS]; /*!< RBG Subset 0,1,2,3
3376 sizes: number of RBs
3379 /** @brief This structure is one element of the DRX Queue mainted per cell.
3380 * @details It is composed of a list of linked lists, each tracking a specific
3381 * timer as defined in the DRX functionality.
3383 typedef struct rgSchDrxQ
3385 CmLListCp onDurationQ; /*!< Tracks the start of onDuration Timer. */
3386 CmLListCp onDurationExpQ; /*!< Tracks the Expiry of onDuration Timer. */
3387 CmLListCp inActvTmrQ; /*!< Tracks the Expiry of drx-InactivityTimer. */
3388 CmLListCp harqRTTQ; /*!< Tracks the Expiry of HARQ RTT timer. */
3389 CmLListCp harqRetxQ; /*!< Tracks the Expiry of Re-Transmission timer. */
3390 CmLListCp shortCycleQ; /*!< Tracks the Expiry of DRX Short Cycle. */
3392 CmLListCp ulHarqRTTQ; /*!< Tracks the Expiry of HARQ RTT timer for Uplink transmission */
3393 CmLListCp ulHarqRetxQ; /*!< Tracks the Expiry of Re-Transmission timer for UPLINK. */
3397 /** @brief This structure is part of the RgSchCellCb structure and stores the
3398 * DRX related information for a cell.dfort
3399 * The cell contains a single Array of queues, wherein UEs shall be enqueued
3400 * based on configured offset and periodicity and timer values. Please note the
3401 * same queue is utilized for Long and Short DRX cycle.
3403 typedef struct rgSchDRXCellCb
3405 RgSchDrxQ drxQ[RG_SCH_MAX_DRXQ_SIZE ]; /*!< Maintains all
3406 the timers for DRX. */
3407 Bool delInUlScan; /*!< Maintains whether elements
3408 from timer queue should be
3409 removed while scanning in
3414 /* Added for SI Enhancement*/
3418 typedef struct sib1Info
3427 typedef struct siInfo
3436 @brief SI Configuration information per cell. */
3437 typedef struct rgSchSiCfgInfo
3439 Buffer *mib; /*!< MIB PDU */
3440 RgSchSib1Info sib1Info;
3441 RgSchSiInfo siInfo[RGR_MAX_NUM_SI];
3445 @brief SI Context information per SI. */
3446 typedef struct rgSchSiCtx
3448 U8 siId; /*!< SI Id */
3449 CmLteTimingInfo timeToTx; /*!< Time at which the SI for this SI
3450 context need to be scheduled.*/
3451 CmLteTimingInfo maxTimeToTx;/*!< Max Time to TX for this SI */
3452 U8 retxCntRem; /*!< SI retransmit count remaining */
3453 U16 i; /*!< Value used to calculate the Riv of SI */
3454 Bool warningSiFlag; /*!< Flag for Warning SI */
3459 @brief Contains each PDU of Warning SI */
3460 typedef struct warningSiPdu
3471 @brief warningSi node having multiple segments */
3472 typedef struct warningSiSeg
3474 /* ccpu00136659: CMAS ETWS design changes */
3475 CmLListCp segLstCp; /*!< LList of Warning SI Segments */
3476 RgSchWarningSiPdu pduNode[RGR_MAX_WARNING_SI_SEG];
3477 RgrCfgTransId transId; /*!< Transaction Id */
3481 @brief Warning SI structure per Cell. */
3482 typedef struct warningSi
3484 /* ccpu00136659: CMAS ETWS design changes */
3485 RgSchWarningSiSeg warningSiMsg;
3486 /*!< Each node contains LList of si segments. */
3487 U8 siId; /*!< Warning SI ID */
3488 U8 idx; /*!< Warning SI Idx in RgSchWarningSiInfo */
3489 }RgSchWarningSiInfo;
3492 @brief SI Array Structure for each SI */
3493 typedef struct siArray
3495 Bool isWarningSi; /*!< Flag for Warning SI */
3496 void *si; /*!< Pointer for SI */
3500 @brief SI Control BLock per Cell. */
3501 typedef struct rgSchSiCb
3503 Bool siBitMask; /*!< Bitmask to indicate which of the SI
3504 components have been updated */
3505 RgSchSiCtx siCtx; /*!< SI Context */
3506 RgrSiCfg newSiCfg; /*!< New SI Configuration, valid if the
3507 respective bit is set in bit mask
3509 S8 inWindow; /*!< counter to indicate the start of a new
3510 si window. Reset to siWinLen at the start
3512 RgSchSiCfgInfo crntSiInfo;/*!< PDUs for current modification period */
3513 RgSchSiCfgInfo newSiInfo; /*!< PDUs for next modification period */
3514 RgSchWarningSiInfo warningSi[RGR_MAX_NUM_WARNING_SI];
3515 /*!< PDUs for warning SI */
3516 RgSchSiArray siArray[RGR_MAX_NUM_SI]; /*!< Pointers for SIs */
3518 #endif /*RGR_SI_SCH */
3520 typedef struct rgSchBiInfo
3522 U16 prevBiTime; /*!< Previous BI Value in ms Calculated and
3523 Sent in Previous Response */
3524 CmLteTimingInfo biTime; /*!< Time at which previous BI sent */
3528 typedef struct rgSchQciPrbUsage
3530 U8 qci; /*!< QCI of the Logical Channel */
3531 U32 dlTotPrbUsed; /*!< total PRB used for DL within one interval*/
3532 U32 ulTotPrbUsed; /*!< total PRB used for UL within one interval*/
3537 typedef struct rgSchPrbUsage
3539 Bool prbRprtEnabld; /*!< reporting is enabled or not*/
3540 U16 rprtPeriod; /*!< reporting interval to send PRB usage to the
3541 RRM (in subframes)*/
3542 CmLteTimingInfo startTime; /*!< timing information when the summation is
3543 started in terms of sfn and subframe*/
3545 RgSchQciPrbUsage qciPrbRpts[RGINF_MAX_GBR_QCI_REPORTS]; /*!< toal
3551 /* LTE_ADV_FLAG_REMOVED_START */
3552 /* @brief Enum to differntiate the subframe */
3553 /* Donot change the value of enum member - code dependency */
3554 typedef enum rgSchAbsSfEnum
3556 RG_SCH_ABS_ENABLED_NONABS_SF = 0, /* ABS is enabled and ABS SF */
3557 RG_SCH_ABS_ENABLED_ABS_SF = 1, /* ABS is enabled and non ABS SF */
3558 RG_SCH_ABS_DISABLED = 2 /* ABS is disabled */
3561 /* @brief Control block for LTE Advance Feature */
3562 typedef struct rgSchLteAdvFeatureCb
3564 RgrSfrConfig sfrCfg; /*!< Configuration of SFR feature */
3565 RgrDsfrConfig dsfrCfg; /*!< Configuration of DSFR feature */
3566 RgrAbsConfig absCfg; /*!< Configuration of ABS feature */
3567 RgSchAbsSfEnum absDlSfInfo; /*< Flag to indicate current scheduling
3568 DL subframe is ABS subframe or not */
3571 U32 absLoadInfo[RGR_ABS_PATTERN_LEN];
3572 } RgSchLteAdvFeatureCb;
3573 /* LTE_ADV_FLAG_REMOVED_END */
3575 /*<! baseSize is the fixed sizes of the respective DCIs. If no other size
3576 * mentioned, baseSize is the final size of the DCI */
3577 typedef struct rgSchCellDciSize {
3579 U8 baseSize[TFU_DCI_FORMAT_6_2+1]; /*!< Fixed Base Size of DCI 0/1/1A/6-0A/6-1A/6-0B/6-1B/6-2 without any adjustment */
3580 U8 size[TFU_DCI_FORMAT_6_2+1]; /*!< DCI 0/1A final size in common Search Space and not scrambled by C-RNTI
3581 DCi 3/3A final sizes
3582 DCI 2/2A final sizes
3583 DCI 6-0A/6-0B final sizes
3584 DCI 6-1A/6-1B final sizes
3585 DCI 6-2 final sizes */
3587 U8 baseSize[TFU_DCI_FORMAT_1A+1]; /*!< Fixed Base Size of DCI 0/1/1A without any adjustment */
3588 U8 size[TFU_DCI_FORMAT_3A+1]; /*!< DCI 0/1A final size in common Search Space and not scrambled by C-RNTI
3589 DCi 3/3A final sizes
3590 DCI 2/2A final sizes */
3592 U8 dci0HopSize; /*!< DCI 0 Hop Size */
3597 * Cell level measurements
3599 typedef struct rgSchMeasCb
3601 U32 dlTpt; /*!< DL Bytes served in a fixed time PERIOD */
3602 U32 dlBytesCnt; /*!< DL Bytes served from start of this time period */
3603 U32 ulTpt; /*!< DL Bytes served in a fixed time PERIOD */
3604 U32 ulBytesCnt; /*!< UL Bytes served from start of this time period */
3609 * Cell level thresholds
3611 typedef struct rgSchThrsldsCb
3618 * CPU Overload control state info
3620 typedef struct rgSchCpuOvrLdCntrlCb
3625 U8 dlNxtIndxDecNumUeTti; /*!< Total DL num UE per TTI reduction instruction applied */
3626 U8 ulNxtIndxDecNumUeTti; /*!< Total UL num UE per TTI reduction instruction applied */
3627 U8 maxUeNewTxPerTti[10]; /*!< list of subframe where DL num UE per TTI reduction applied */
3628 U8 maxUeNewRxPerTti[10]; /*!< list of subframe where UL num UE per TTI reduction applied */
3629 }RgSchCpuOvrLdCntrlCb;
3633 * Cell Control block per cell.
3637 CmLteCellId cellId; /*!< Cell ID */
3638 Inst instIdx; /*!< Index of the scheduler instance */
3639 Inst macInst; /*!< Index of the MAC instance */
3640 U8 schTickDelta; /* 4UE_TTI_DELTA */
3641 Bool stopSiSch; /*!< If TRUE Bcch,Pcch Scheduling is not done */
3642 U8 stopDlSch; /*!< If TRUE DL scheduling is not done */
3643 Bool stopUlSch; /*!< If TRUE UL scheduling is not done */
3644 Bool isDlDataAllwd; /*!< FALSE for Uplink subframes */
3645 RgrDlHqCfg dlHqCfg; /*!< HARQ related configuration */
3646 RgSchRntiDb rntiDb; /*!< RNTIs DB: range of rntis to be managed by MAC */
3649 Void *sch; /*!< Common Scheduler specific information */
3650 RgSchdApis *apis; /*!< Common Scheduler APIs */
3653 Bool isCpUlExtend; /*!< Cyclic prefix : TRUE-extended/FALSE-normal */
3654 Bool isCpDlExtend; /*!< Cyclic prefix : TRUE-extended/FALSE-normal */
3655 U8 numTxAntPorts; /*!< Number of Tx antenna ports */
3656 RgrBwCfg bwCfg; /*!< Bandwidth Configuration */
3657 U8 pbchRbStart; /*!< Indicates the Start RB of the center 6 RBs of DL BW */
3658 U8 pbchRbEnd; /*!< Indicates the Start RB of the center 6 RBs of DL BW */
3659 U8 numCellRSPerSf; /*!< Indicates the number of cell specific
3660 Reference symbols in a Subframe */
3661 RgrPhichCfg phichCfg; /*!< PHICH Config Information */
3662 RgrPucchCfg pucchCfg; /*!< PUCCH Config Information */
3663 RgSchSrsCfg srsCfg; /*!< SRS Config Information */
3664 RgrRachCfg rachCfg; /*!< RACH Configuration */
3666 RgSchBiInfo biInfo; /* CELL wide BI Info */
3667 RgrSiCfg siCfg; /*!< SI Configuration */
3668 /* Added support for SPS*/
3670 RgrPuschCfg puschCfg; /*!< Cell-specific hopping configuration */
3672 RgrPreambleSetCfg macPreambleSet; /*!< Range of PDCCH Order Preamble Id's
3673 to be managed by MAC */
3674 CmLteTimingInfo crntTime; /*!< Current frame and subframe number for
3676 CmLteTimingInfo hiDci0Time; /*!< Scheduling SFN, SF for HIDCI-0 */
3677 CmLteTimingInfo hqRlsTime; /*!< SFN, SF for HARQ clean up */
3678 CmLteTimingInfo dlSfRlsTime; /*!< SFN, SF for Downlink subframe clean up*/
3679 CmLteTimingInfo dlDciTime; /*!< SFN, SF for DL control Request */
3680 CmLteTimingInfo rcpReqTime; /*!< SFN, SF for UL reception Request */
3681 RgSchCfgCfb rgCfgInfo; /*!< Control block for configuration related
3683 U8 ulCcchId; /*!< LcId for uplink CCCH */
3684 U8 dlCcchId; /*!< LcId for downlink CCCH */
3685 RgSchClcDlLcCb cmnLcCb[RGSCH_MAX_CMN_LC_CB]; /*!< BCCH/PCCH logical channel control block */
3686 CmHashListCp ueLst; /*!< Hash list of UE control
3687 blocks: RgSchUeCb */
3688 /* Added support for SPS*/
3690 CmHashListCp spsUeLst; /*!< Hash list of UE control blocks
3691 for spsRnti: RgSchUeCb */
3692 #endif /* LTEMAC_SPS */
3693 CmLListCp taUeLst; /*!< List of ueCbs having ta */
3695 /* CR timer changes*/
3696 CmLListCp ccchSduUeLst; /*!< List of ueCbs scheduled for CCCH
3698 CmLListCp contResGrdTmrLst; /*!< List of raCbs whose Guard timer is
3700 CmLListCp contResTmrLst; /*!< List of raCbs whose contention
3701 resolution timer is running */
3703 RgSchRaInfoCb raInfo; /*!< Random access related information for
3705 CmLListCp pdcchLst; /*!< List of free RgSchPdcch structures */
3707 CmTqType tq[RGSCH_UE_TQ_SIZE];
3708 U8 crntSfIdx; /*!< Current index for allocation */
3710 RgInfSfAlloc sfAllocArr[RGSCH_SF_ALLOC_SIZE]; /*!< Subframe Allocation
3711 info to be sent to MAC */
3713 RgInfSfAlloc sfAllocArr[RGSCH_NUM_SUB_FRAMES]; /*!< Subframe Allocation
3714 info to be sent to MAC */
3716 RgInfRlsHqInfo rlsHqArr[RGSCH_NUM_SUB_FRAMES]; /*!< Harq Release
3717 info to be sent to MAC */
3718 U8 crntHqIdx; /*!< Current index for Harq release info */
3719 RgSchLowSapCb *tfuSap;
3720 /* Added for sending TTI tick to RRM */
3721 #if (defined(RGR_RRM_TICK) || defined(RGR_CQI_REPT))
3722 RgSchUpSapCb *rgrSap; /*!< Pointer to the cell's RGR SAP
3725 RgSchUpSapCb *rgmSap; /*!< Pointer to the cell's RGM SAP
3728 U8 rrmTtiIndPrd; /*!< Periodicity of TTI indication from
3729 MAC towards RGR user. Range [1-255]. A
3730 value of 1 means one tick per System
3731 Frame and 2 means one tick per 2 System
3732 Frame, and so on. */
3734 PdcchOrderCfg pdcchOrdCfg;
3735 RgSchMeasGapCb measGapCb; /*!< Measurement gap control block */
3736 RgSchAckNakRepCb ackNakRepCb; /*!< Ack-Nack Repetition control block */
3738 RgSchTddRachRspLst *rachRspLst; /*!< List of awaiting RACH responses */
3739 U8 numDlSubfrms; /*!< Number of DL subframes */
3740 U8 ulDlCfgIdx; /*!< UL-DL Configuration Index */
3741 U8 ackNackFdbkArrSize; /*!< Maximum Number of Ack/Nack
3742 feedback information to be
3744 S8 tddHqSfnCycle; /*!< Counter to keep track of the
3745 number of sfn,sf wrap arounds.
3746 This is used for UL harq
3747 determination. It ranges from
3748 0 to num Ul Harq-1 */
3749 RgSchTddSplSubfrmCfg splSubfrmCfg; /*!< Special subframe configuration */
3750 Bool isDwPtsCnted; /*!< is DwPts counted as PDCCH sf */
3751 RgSchTddNpValTbl rgSchTddNpValTbl;/*!< Mapping between 'Np' and 'p' */
3752 RgSchDlSf **subFrms; /*!< DL subframes list */
3753 RgSchTddPrachRscInfo prachCfg; /*!< PRACH configuration */
3754 CmHashListCp ueTfuPendLst; /*!< Used for HARQ Ack/Nack
3756 /* TODO:: change to array of pointers */
3757 CmLListCp n1ResUsedLst[RGSCH_NUM_SUB_FRAMES]; /*!< For storing the used
3758 N1 resources for scell in case of F1B CS */
3760 RgSchDlSf *subFrms[RGSCH_NUM_DL_SUBFRAMES];
3763 RgSchDynCfiCb dynCfiCb; /*!< Dynamic CFI control block */
3764 /* Changes for MIMO feature addition */
3765 U8 noOfRbgs; /*!< Number of RBGs for this bw */
3766 U8 rbgSize; /*!< RBG Size */
3767 /* Added support for SPS*/
3769 RgSchBwRbgInfo dlBwRbgInfo; /*!< RBG information for the configured
3771 RgrSpsCellCfg spsCellCfg; /*!< SPS specific configuration for
3773 RgSchBwRbgInfo spsBwRbgInfo; /*!< RBG information for configured maximum
3777 RgSchRaPreambles raPrmbs; /*!< Different received RA preambles */
3778 RgSchAvgPrbDl avgPrbDl; /*!< PRB usage in percentage per QCI for DL */
3779 RgSchAvgPrbUl avgPrbUl; /*!< PRB usage in percentage per QCI for UL */
3780 CmLListCp l2mList; /*!< List of all L2M requests
3782 RgSchQciCb qciArray[LRG_MAX_QCI]; /*!< Array of all qci's configured
3784 Bool sndL2Meas; /*!< send L2 Meas in case no le mesurement timer is running*/
3785 RgSchTbCnt dlUlTbCnt; /*!< Count of DL and UL TB transmitteed and Faulty
3786 TB (for wich NACK is received) */
3787 #endif /* LTE_L2_MEAS */
3788 U8 ulAvailBw; /*!< Total Uplink band width available
3789 for this sub frame */
3791 RgSchPerPucchCb pCqiSrsSrLst[RG_SCH_PCQI_SRS_SR_TRINS_SIZE];
3792 /*!< To store next active Periodic CQI/PMI, RI,
3793 SRS and SR Transmission instance */
3794 #endif /* TFU_UPGRADE */
3797 CmLListCp hdFddLst; /*!< Half Duplex FDD UE list */
3798 #endif /* LTEMAC_HDFDD */
3799 RgSchDRXCellCb *drxCb; /*!< Pointer to the DRX control block shall be
3800 allocated at the time of cell configuration. */
3801 /* Added for SI Enhancement*/
3803 RgSchSiCb siCb; /*!< SI Control Block */
3804 #endif /*RGR_SI_SCH */
3805 RgSchPrbUsage prbUsage; /*!< measures average PRB usage for configured interval*/
3806 U16 t300TmrVal; /*!< t300Timer value configured in Frames */
3807 /* LTE_ADV_FLAG_REMOVED_START */
3808 TknStrOSXL rntpAggrInfo; /*!< RNTP Info */
3809 RgrLoadInfReqInfo loadInfReqInfo; /*!< Consists startRb & endRb
3810 location for which CC to
3811 be raised to P-High */
3812 RgSchLteAdvFeatureCb lteAdvCb; /*!< Control block for LTE Adv
3814 /* LTE_ADV_FLAG_REMOVED_END */
3815 U32 dlNumUeSchedPerTti[RG_MAX_NUM_UE_PER_TTI]; /*!<DL mUe/Tti histograms*/
3816 U32 ulNumUeSchedPerTti[RG_MAX_NUM_UE_PER_TTI]; /*!<UL mUe/Tti histograms*/
3817 Bool overLoadBackOffEnab; /*!< Overload Rach Backoff enable/disable */
3818 U8 overLoadBackOffval; /*!< Overload Rach BackOff value */
3819 U8 refreshUeCnt[RGSCH_MAX_REFRESH_OFFSET]; /*! To maintain number of UE refreshed per subframe */
3820 U8 minDlResNonCsg; /*!< Minimum DL resources reserved for Non CSG UEs */
3821 U8 minUlResNonCsg; /*!< Minimum UL resources reserved for CSG UEs */
3822 Bool isAutoCfgModeEnb; /*!< Indicates Auto config of TM mode is enabled or
3823 disabled. True - Enabled, False - Disabled */
3824 CmLListCp lcMonitorLst; /*LC Lst used for flow cntrl */
3825 U32 prbCnt; /*!<PRB usage in flow control interval*/
3826 U32 maxPrbCnt; /*!<Max PRB cnt after which Flow Cntrl
3828 RgSchCpuOvrLdCntrlCb cpuOvrLdCntrl; /*!< CPU Overload control state info */
3829 RgSchMeasCb measurements; /*!< Cell level measurements */
3830 RgSchThrsldsCb thresholds; /*!< Cell level thresholds */
3832 TSL2CellStatsCb *tenbStats; /*!< CELL Stats Holder */
3834 RgSchCellDciSize dciSize;
3836 CmLListCp sCellUeLst; /*!< List of UEs for which this cell is secondary cell*/
3837 Bool isPucchFormat3Sptd;
3845 /* TODO:: Below members need to be moved
3846 * to emtc specific files and have void *
3850 RgSchRntiDb emtcRntiDb; /*!< RNTIs DB: range of rntis to be managed by MAC */
3852 RgSchIotResMngmtCb resMngmt;
3854 RgSch5gtfCellCb cell5gtfCb;
3860 * Structure holding LTE MAC's General Configuration information.
3862 typedef struct rgSchGenCb
3864 U8 tmrRes; /*!< Timer resolution */
3865 RgSchLmResponse *bndCfmResp; /*!< Respones value for Bind Confirm */
3866 RgSchLmResponse ustaResp; /*!< Respones value for Alarms */
3867 U8 startCellId; /*!< Starting Cell Id */
3869 Bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
3870 of RLC control BO and SRB BO on
3871 PCell. val 0 means don't force*/
3872 Bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
3877 /* 5GTF Dynamic TDD Specific defines */
3879 /* Number of subframes information managed */
3880 #define RG_SCH_DYNTDD_MAX_SFINFO 20
3882 /* Subframe Types */
3883 #define RG_SCH_DYNTDD_NOTDEF 0
3884 #define RG_SCH_DYNTDD_DLC_DLD 1
3885 #define RG_SCH_DYNTDD_DLC_DLD_ULC 2
3886 #define RG_SCH_DYNTDD_DLC_ULD 3
3887 #define RG_SCH_DYNTDD_DLC_ULD_ULC 4
3889 /* Mark the subframe */
3890 #define RG_SCH_DYN_TDD_MARKTYPE(_dynTdd, _sfi, _state)\
3892 (_dynTdd)->sfInfo[(_sfi)].sfType = _state;\
3895 /* Mark sfi as UL Subframe */
3896 #define RG_SCH_DYN_TDD_MARKTYPE_UL(_dynTdd, _sfi)\
3898 RG_SCH_DYN_TDD_MARKTYPE(_dynTdd, _sfi, RG_SCH_DYNTDD_DLC_ULD);\
3901 /* Mark sfi as DL Subframe */
3902 #define RG_SCH_DYN_TDD_MARKTYPE_DL(_dynTdd, _sfi)\
3904 RG_SCH_DYN_TDD_MARKTYPE(_dynTdd, _sfi, RG_SCH_DYNTDD_DLC_DLD);\
3907 /* Get SFI and SFN from given time and subframe offset */
3908 #define RG_SCH_DYN_TDD_GET_SFIDX(_sfi, _crntSfIdx, _offset)\
3909 (_sfi) = (_crntSfIdx + _offset)% RG_SCH_DYNTDD_MAX_SFINFO
3912 @brief Dynamic TDD subframe type. */
3914 typedef struct rgSchDynTddSfType
3916 U8 sfType; /*!< 0= NOT Defined
3917 1= DL Cntrl + DL Data
3918 2= DL Cntrl + DL Data + UL Cntrl
3919 3= DL Cntrl + UL Data
3920 4= DL Cntrl + UL Data + UL Cntrl
3925 @brief Dynamic TDD control Block */
3927 typedef struct rgSchDynTddCb
3929 Bool isDynTddEnbld; /*!< Is dynamic TDD enabled */
3930 U8 crntDTddSfIdx; /*!< Pivot Index corresponding
3931 cell's current subframe */
3932 RgSchDynTddSfType sfInfo[RG_SCH_DYNTDD_MAX_SFINFO];
3939 * Global Control block for LTE-MAC.
3943 TskInit rgSchInit; /*!< Task Init info */
3944 RgSchGenCb genCfg; /*!< General Config info */
3945 U8 numSaps; /*!< Num RGR Saps = Num TFU Saps */
3946 RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
3947 RgSchLowSapCb *tfuSap; /*!< TFU SAP Control Block */
3948 RgSchUpSapCb *rgmSap; /*!< TFU SAP Control Block */
3949 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
3950 CmTqType tmrTq[RGSCH_TQ_SIZE]; /*!< Timer Task Queue */
3951 U8 rgSchDlDelta; /* 4UE_TTI_DELTA */
3954 RgSchCellCb *cells[CM_LTE_MAX_CELLS]; /* Array to store cellCb ptr */
3955 RgrSchedEnbCfg rgrSchedEnbCfg; /*!< eNB level RR/PFS Config */
3956 Void *rgSchEnbPfsDl; /*!< eNB level PFS DL Block */
3960 RgSchDynTddCb rgSchDynTdd; /*!< Dynamic TDD Control Block */
3964 /* Declaration for scheduler control blocks */
3965 EXTERN RgSchCb rgSchCb[RGSCH_MAX_INST];
3968 * Data structures for RAM
3973 * Random Access Req Info to be stored in cellCb.
3975 typedef struct rgSchRaReqInfo
3977 CmLList raReqLstEnt; /*!< Linked list entity for RaReq List */
3978 CmLteTimingInfo timingInfo; /*!< RACHO: Time of RaReq Reception */
3979 RgTfuRaReqInfo raReq; /*!< Random Access Request Information */
3980 RgSchUeCb *ue; /*!< UECB if RAP ID is a dedicated one */
3984 * @enum rgSchRaState
3985 * Enumeration of random access states.
3987 typedef enum rgSchRaState
3989 RGSCH_RA_MSG3_PENDING, /*!< Msg3 reception pending */
3990 RGSCH_RA_MSG4_PENDING, /*!< Msg4 transmission pending */
3991 RGSCH_RA_MSG4_DONE /*!< Msg4 transmission successful */
3996 * Control block for Random Access.
4000 CmLList raCbLnk; /*!< To link to the raCb list */
4001 CmLList schdLnk; /*!< To link raCb to the "to be scheduled"
4003 CmLteRnti tmpCrnti; /*!< Temporary C-RNTI */
4004 CmLteTimingInfo timingInfo; /*!< Timing information */
4005 RgSchRntiLnk *rntiLnk; /*!< Link to RNTI for raCb */
4006 RgSchRaState raState; /*!< Random access state */
4009 U32 bo; /*!< Buffer occupancy for CCCH */
4010 } dlCcchInfo; /*!< Params for DL CCCH */
4011 U8 msg3HqProcId; /*!< Msg3 Harq Process ID */
4012 /*ccpu00128820 - DEL - msg3HqProcRef is delete for Msg3 alloc double delete issue*/
4013 RgSchUlHqProcCb msg3HqProc; /*!< msg3HqProcRef points to this initially */
4014 RgSchUeCb *ue; /*!< NULL initially */
4015 Bool toDel; /*!< To delete this RaCb after msg4 reject */
4016 TknU8 phr; /*!< To store the PHR, if received along with
4018 CmLList rspLnk; /*!< Used to link RACB to a frame for resp */
4019 U8 rapId; /*!< RAP ID */
4020 TknU16 ta; /*!< Timing Adjustment */
4021 RgSchUlGrnt msg3Grnt; /*!< Msg3 grant as given by the UL Sched */
4022 U32 y[RGSCH_NUM_SUB_FRAMES]; /*!< y values using tmpCrnti by DLSCHED */
4023 RgSchDlHqEnt *dlHqE; /*!< DL HARQ module */
4024 U8 ccchCqi; /*!< DL Cqi obtained from RaReq and Used for CCCH */
4025 RgSchDlRbAlloc rbAllocInfo; /*!< RB Allocation Info for MSG4 Trans/Retrans */
4026 /* PHR handling for MSG3 */
4027 CmLteTimingInfo msg3AllocTime; /*!< Allocation time for msg3 grant */
4029 /* CR timer changes*/
4030 CmLList contResTmrLnk; /*!< To link raCb to the
4031 Guard Timer/Contention Resolution timer list*/
4032 CmLteTimingInfo expiryTime; /*!< Expiry time for Guard/Contention
4033 Resolution timers */
4035 U32 ccchSduBo; /*!<To store CCCH SDU BO if it arrives while
4036 ContRes CE is transmitting or retransmitting*/
4039 Bool isEmtcRaCb; /*!< 0 - Normal, 1 - EMTC */
4046 * Carries the Error information.
4050 U8 errType; /*!< Error Type */
4051 U16 errCause; /*!< Cause of Error */
4054 /* Global Variables */
4058 EXTERN U8 rgSchTddSpsDlMaxRetxTbl[RGSCH_MAX_TDD_UL_DL_CFG];
4060 typedef U8 RgSchTddUlDlSubfrmTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4061 EXTERN RgSchTddUlDlSubfrmTbl rgSchTddUlDlSubfrmTbl;
4063 typedef struct rgSchTddSplSubfrmInfo RgSchTddSplSubfrmInfoTbl[RGSCH_MAX_TDD_SPL_SUBFRM_CFG];
4064 EXTERN RgSchTddSplSubfrmInfoTbl rgSchTddSplSubfrmInfoTbl;
4066 typedef struct rgSchTddDlAscSetIdxK RgSchTddDlAscSetIdxKTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4067 EXTERN RgSchTddDlAscSetIdxKTbl rgSchTddDlAscSetIdxKTbl;
4069 EXTERN RgSchTddDlAscSetIdxKTbl rgSchTddDlHqPucchResCalTbl;
4071 typedef U8 RgSchTddPhichMValTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4072 EXTERN RgSchTddPhichMValTbl rgSchTddPhichMValTbl;
4074 typedef U8 RgSchTddKPhichTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4075 EXTERN RgSchTddKPhichTbl rgSchTddKPhichTbl;
4077 typedef RgSchTddPhichOffInfo RgSchTddPhichOffInfoTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4079 typedef U8 RgSchTddUlAscIdxKDashTbl[RGSCH_MAX_TDD_UL_DL_CFG-1][RGSCH_NUM_SUB_FRAMES];
4080 EXTERN RgSchTddUlAscIdxKDashTbl rgSchTddUlAscIdxKDashTbl;
4083 typedef U8 RgSchTddInvDlAscSetIdxTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4084 EXTERN RgSchTddInvDlAscSetIdxTbl rgSchTddInvDlAscSetIdxTbl;
4087 typedef U8 RgSchTddPuschTxKTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4088 EXTERN RgSchTddPuschTxKTbl rgSchTddPuschTxKTbl;
4090 typedef U8 RgSchTddUlNumHarqProcTbl[RGSCH_MAX_TDD_UL_DL_CFG];
4091 EXTERN RgSchTddUlNumHarqProcTbl rgSchTddUlNumHarqProcTbl;
4093 typedef U8 RgSchTddDlNumHarqProcTbl[RGSCH_MAX_TDD_UL_DL_CFG];
4094 EXTERN RgSchTddDlNumHarqProcTbl rgSchTddDlNumHarqProcTbl;
4096 /* Number of ACK/NACK Feedback to be stored based on UL-DL Configuration Index */
4097 typedef U8 RgSchTddANFdbkMapTbl[RGSCH_MAX_TDD_UL_DL_CFG];
4098 EXTERN RgSchTddANFdbkMapTbl rgSchTddANFdbkMapTbl;
4100 /* Number of UL subframes */
4101 typedef RgSchTddSubfrmInfo RgSchTddMaxUlSubfrmTbl[RGSCH_MAX_TDD_UL_DL_CFG];
4102 EXTERN RgSchTddMaxUlSubfrmTbl rgSchTddMaxUlSubfrmTbl;
4104 /* Number of UL subframes */
4105 typedef U8 RgSchTddNumUlSubfrmTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4106 EXTERN RgSchTddNumUlSubfrmTbl rgSchTddNumUlSubfrmTbl;
4108 /* Number of low UL subframes Indices*/
4109 typedef U8 RgSchTddLowUlSubfrmIdxTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4110 EXTERN RgSchTddLowUlSubfrmIdxTbl rgSchTddLowUlSubfrmIdxTbl;
4112 /* Number of high UL subframes Indices*/
4113 typedef U8 RgSchTddHighUlSubfrmIdxTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4114 EXTERN RgSchTddHighUlSubfrmIdxTbl rgSchTddHighUlSubfrmIdxTbl;
4116 /* Number of low DL subframes Indices*/
4117 typedef U8 RgSchTddLowDlSubfrmIdxTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4118 EXTERN RgSchTddLowDlSubfrmIdxTbl rgSchTddLowDlSubfrmIdxTbl;
4120 /* Number of high DL subframes Indices*/
4121 typedef U8 RgSchTddHighDlSubfrmIdxTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4122 EXTERN RgSchTddHighDlSubfrmIdxTbl rgSchTddHighDlSubfrmIdxTbl;
4124 /* Number of DL subframes and Special subframes with DwPTS */
4125 typedef U8 RgSchTddNumDlSubfrmTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4126 EXTERN RgSchTddNumDlSubfrmTbl rgSchTddNumDlSubfrmTbl;
4128 /* Number of DL subframes and Special subframes with DwPTS */
4129 typedef RgSchTddSubfrmInfo RgSchTddMaxDlSubfrmTbl[RGSCH_MAX_TDD_UL_DL_CFG];
4130 EXTERN RgSchTddMaxDlSubfrmTbl rgSchTddMaxDlSubfrmTbl;
4132 typedef U8 RgSchTddMsg3SubfrmTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4133 EXTERN RgSchTddMsg3SubfrmTbl rgSchTddMsg3SubfrmTbl;
4135 typedef RgSchTddMsg3SubfrmTbl RgSchTddSpsUlRsrvTbl;
4136 EXTERN RgSchTddMsg3SubfrmTbl rgSchTddSpsUlRsrvTbl;
4139 typedef U8 RgSchTddRlsDlSubfrmTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4140 EXTERN RgSchTddRlsDlSubfrmTbl rgSchTddRlsDlSubfrmTbl;
4143 EXTERN U8 rgSchTddPucchTxTbl[RGSCH_MAX_TDD_UL_DL_CFG][RGSCH_NUM_SUB_FRAMES];
4147 EXTERN RgSchCellCb* rgSchUtlGetCellCb ARGS((
4152 EXTERN Void rgSCHSCellDlUeReset ARGS((
4157 EXTERN Void rgSCHSCellDlLcCfg ARGS((
4163 EXTERN Void rgSCHSCellDlLcDel ARGS((
4169 EXTERN Void rgSCHSCellDlDedBoUpd ARGS((
4175 EXTERN Void rgSCHSCellSchdActDeactCe ARGS((
4177 RgSchDlHqTbCb *tbInfo
4180 EXTERN Void rgSCHSCellAddToActDeactLst ARGS((
4185 EXTERN Void rgSCHSCellRmvFrmActLst ARGS((
4189 EXTERN S16 rgSCHSCellIsActive ARGS((
4196 EXTERN Void rgSCHSCellHndlFdbkInd ARGS((
4197 RgSchDlHqProcCb *hqP,
4200 Bool maxHqRetxReached
4203 EXTERN Void rgSCHSCellDeactTmrExpry ARGS((
4204 RgSchUeCellInfo *sCell
4207 EXTERN S16 rgSCHSCellTrigActDeact ARGS((
4214 EXTERN S16 rgSCHSCellDelUe ARGS((
4215 RgSchCellCb *cellCb,
4219 EXTERN Bool rgSCHIsActvReqd ARGS ((
4224 EXTERN Void rgSCHSCellSelectAndActDeAct ARGS ((
4230 EXTERN S16 rgSCHSCellPCqiCfg ARGS((
4231 RgSchCellCb *priCellCb,
4232 RgSchCellCb *secCellCb,
4234 RgrUePrdDlCqiCfg *cqiCfg,
4235 CmLteUeCategory ueCat,
4239 EXTERN Void rgSCHUtlSndUeSCellDel2Mac ARGS ((
4244 EXTERN U8 rgSCHUtlGetMaxTbSupp ARGS ((
4249 /* APIs exposed by TMR module */
4250 EXTERN Void rgSCHTmrStartTmr ARGS((
4251 RgSchCellCb *cellCb,
4256 EXTERN Void rgSCHTmrStopTmr ARGS((
4257 RgSchCellCb *cellCb,
4261 EXTERN Void rgSCHTmrProcTmr ARGS((
4265 /* APIs exposed by TOM */
4267 EXTERN S16 rgSCHTomRaReqInd ARGS((
4269 TfuRaReqIndInfo *raReqInd));
4271 EXTERN S16 rgSCHTomPucchDeltaPwrInd ARGS((
4273 TfuPucchDeltaPwrIndInfo *pucchDeltaPwr));
4275 EXTERN S16 rgSCHTomUlCqiInd ARGS((
4277 TfuUlCqiIndInfo *ulCqiInd));
4279 EXTERN S16 rgSCHTomSrInd ARGS((
4281 TfuSrIndInfo *srInd));
4283 EXTERN S16 rgSCHTomDlCqiInd ARGS((
4285 TfuDlCqiIndInfo *dlCqiInd));
4286 /* Added changes of TFU_UPGRADE */
4288 EXTERN S16 rgSCHTomRawCqiInd ARGS
4291 TfuRawCqiIndInfo* rawCqiInd
4294 EXTERN S16 rgSCHTomSrsInd ARGS
4297 TfuSrsIndInfo* srsInd
4302 EXTERN S16 rgSCHTomDoaInd ARGS((
4304 TfuDoaIndInfo *doaInd));
4305 EXTERN S16 rgSCHTomCrcInd ARGS((
4307 TfuCrcIndInfo *crcInd));
4309 EXTERN Void rgSCHTomTtiInd ARGS((
4310 TfuTtiIndInfo *ttiInd,
4313 EXTERN S16 rgSCHTomHarqAckInd ARGS((
4315 TfuHqIndInfo *harqAckInd));
4317 EXTERN S16 rgSCHTomTimingAdvInd ARGS((
4319 TfuTimingAdvIndInfo *timingAdvInd));
4323 * APIs exposed by LMM
4325 EXTERN S16 schActvInit ARGS((Ent entity, Inst inst, Region
4326 region, Reason reason));
4327 EXTERN S16 rgSCHLmmStartTmr ARGS ((Inst instId, S16 tmrEvnt,
4328 U32 tmrVal, PTR cb));
4329 EXTERN S16 rgSCHLmmStopTmr ARGS((Inst instId, S16 tmrEvnt, PTR cb));
4330 EXTERN S16 rgSCHLmmTmrExpiry ARGS((PTR cb, S16 tmrEvnt));
4331 /* This function invokes a Control Confirmation to the LM from scheduler. */
4332 EXTERN S16 rgSCHLmmBndCfm ARGS((Pst *pst, SuId suId, U8 status));
4333 EXTERN S16 schActvTmr ARGS((Ent entity, Inst inst));
4334 /* To send a Unsolicited Status Indication to Layer Manager */
4335 EXTERN S16 rgSCHLmmStaInd ARGS((Inst instId, U16 category, U16 event,
4336 U16 cause, RgUstaDgn *dgn));
4337 EXTERN S16 schActvTsk ARGS((Pst *pst, Buffer *mBuf));
4338 EXTERN Void rgSCHLmmFillCfmPst ARGS((Pst *reqPst,Pst *cfmPst,RgMngmt *cfm));
4339 EXTERN U16 rgSCHLmmInstCfg ARGS((RgCfg *cfg, Inst inst));
4340 EXTERN Void printSchCellInfo ARGS((Void));
4341 EXTERN Void rgSCHLmmGenCntrl ARGS((RgMngmt *cntrl,RgMngmt *cfm,Pst *cfmPst));
4342 EXTERN Void rgSCHLmmSapCntrl ARGS((RgMngmt *cntrl,RgMngmt *cfm,Pst *cfmPst));
4345 EXTERN S16 rgSCHCfgEmtcCellCfg ARGS ((RgSchCellCb *cell,
4346 RgrEmtcCellCfg *emtcCellCfg));
4347 EXTERN S16 rgSCHCfgVldtRgrEmtcCellCfg ARGS ((RgrCellCfg *cellCfg));
4349 EXTERN PUBLIC Void rgSchTomTtiEmtcSched ARGS((RgSchCellCb *cell));
4350 EXTERN S16 rgSCHCfgVldtEmtcUeCfg ARGS((RgSchCellCb *cell, RgrUeEmtcCfg *emtcUeCfg));
4351 EXTERN S16 rgSCHUtlUpdUeEmtcInfo ARGS((RgSchCellCb *cell, RgrUeCfg *ueCfg, RgSchUeCb *ueCb));
4352 EXTERN S16 rgSCHEmtcCellDel ARGS((RgSchCellCb *cell));
4353 EXTERN S16 rgSCHEmtcUeDel ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
4354 EXTERN S16 rgSCHEmtcHdFddUeCfg ARGS((RgSchCellCb *cellCb,RgSchUeCb *ueCb,Bool hdFddEnbl));
4358 * APIs exposed by CFG module
4360 EXTERN S16 rgSCHCfgVldtRgrCellCfg ARGS((Inst inst, RgrCellCfg *cellCfg,
4361 RgSchCellCb *cell, RgSchErrInfo *errInfo));
4362 EXTERN S16 rgSCHCfgRgrCellCfg ARGS((RgSchCb *instCb, SpId spId,
4363 RgrCellCfg *cellCfg, RgSchErrInfo *errInfo));
4364 EXTERN S16 rgSCHCfgRgrSchedEnbCfg ARGS((Inst inst, SpId spId,
4365 RgrSchedEnbCfg *schedEnbCfg, RgSchErrInfo *errInfo));
4366 EXTERN S16 rgSCHCfgVldtRgrCellRecfg ARGS((Inst inst, RgrCellRecfg *cellRecfg,
4367 RgSchCellCb **cell, RgSchErrInfo *errInfo));
4368 EXTERN S16 rgSCHCfgRgrCellRecfg ARGS((RgSchCellCb *cell, RgrCellRecfg *cellRecfg,
4369 RgSchErrInfo *errInfo));
4371 EXTERN S16 rgSCHCfgVldtRgrUeCfg ARGS((Inst inst, RgrUeCfg *ueCfg,
4372 RgSchCellCb **cell, RgSchErrInfo *errInfo));
4373 EXTERN S16 rgSCHCfgRgrUeCfg ARGS((RgSchCellCb *cell, RgrUeCfg *ueCfg,
4374 RgSchErrInfo *errInfo));
4375 EXTERN S16 rgSCHCfgVldtRgrUeRecfg ARGS((Inst inst, RgrUeRecfg *ueRecfg,
4376 RgSchCellCb **cell, RgSchUeCb **ue, RgSchErrInfo *errInfo));
4377 EXTERN S16 rgSCHCfgRgrUeRecfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue, RgrUeRecfg
4378 *ueRecfg, RgSchErrInfo *errInfo));
4380 EXTERN S16 rgSCHCfgVldtRgrLcCfg ARGS((Inst inst, RgrLchCfg *lcCfg,
4381 RgSchCellCb **cell, RgSchUeCb **ue, RgSchErrInfo *errInfo));
4382 EXTERN S16 rgSCHCfgRgrLchCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4383 RgrLchCfg *lcCfg, RgSchErrInfo *errInfo));
4384 EXTERN S16 rgSCHCfgVldtRgrLchRecfg ARGS((Inst inst, RgrLchRecfg *lcRecfg,
4385 RgSchCellCb **cell, RgSchUeCb **ue, RgSchDlLcCb **dlLc,
4386 RgSchErrInfo *errInfo));
4387 EXTERN S16 rgSCHCfgRgrLchRecfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4388 RgSchDlLcCb *dlLc, RgrLchRecfg *lcRecfg, RgSchErrInfo *errInfo));
4390 EXTERN S16 rgSCHCfgVldtRgrLcgRecfg ARGS ((Inst inst,RgrLcgRecfg *lcgRecfg,
4391 RgSchCellCb *cell,RgSchUeCb **ue,RgSchErrInfo *errInfo ));
4392 EXTERN S16 rgSCHCfgVldtRgrLcgCfg ARGS ((Inst inst,RgrLcgCfg *lcgCfg,
4393 RgSchCellCb **cell,RgSchUeCb **ue,RgSchErrInfo *errInfo ));
4394 EXTERN S16 rgSCHCfgVldtRgrSchedEnbCfg ARGS ((Inst inst,
4395 RgrSchedEnbCfg *schedEnbCfg, RgSchErrInfo *errInfo ));
4396 EXTERN S16 rgSCHCfgRgrLcgCfg ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
4397 RgrLcgCfg *lcgCfg,RgSchErrInfo *errInfo ));
4398 EXTERN S16 rgSCHCfgRgrLcgRecfg ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
4399 RgrLcgRecfg *lcgRecfg,RgSchErrInfo *errInfo));
4401 EXTERN S16 rgSCHCfgVldtRgrUeReset ARGS((Inst inst, RgrRst *reset, RgSchCellCb *cell,
4402 RgSchUeCb **ue,RgSchErrInfo *errInfo));
4403 EXTERN S16 rgSCHCfgRgrUeReset ARGS((RgSchCellCb *cell,RgSchUeCb *ue,RgrRst *reset,
4404 RgSchErrInfo *errInfo));
4406 EXTERN S16 rgSCHCfgRgrCellDel ARGS((RgSchCellCb *cell, RgrDel *cellDelInfo,
4407 RgSchErrInfo *errInfo));
4408 EXTERN S16 rgSCHCfgRgrUeDel ARGS((RgSchCellCb *cell, RgrDel *ueDelInfo,
4409 RgSchErrInfo *errInfo));
4410 EXTERN S16 rgSCHCfgRgrLcDel ARGS((RgSchCellCb *cell, RgrDel *lcDelInfo,
4411 RgSchErrInfo *errInfo));
4412 EXTERN S16 rgSCHCfgRgrLcgDel ARGS ((RgSchCellCb *cell,RgrDel *lcDelInfo,
4413 RgSchErrInfo *errInfo));
4414 EXTERN Void rgSCHCfgFreeCellCb ARGS((RgSchCellCb *cell));
4415 /* Added for SI Enhancement*/
4417 EXTERN S16 rgSCHCfgVldtRgrSiCfg ARGS(( Inst inst, RgrSiCfgReqInfo *siCfg,
4418 RgSchCellCb *cell, RgSchErrInfo *errInfo));
4419 EXTERN S16 rgSCHGomHndlSiCfg ARGS(( Region reg, Pool pool,
4420 RgSchCb *instCb, SpId spId,
4421 RgrCfgTransId transId, RgrSiCfgReqInfo *cfgReqInfo));
4422 EXTERN S16 rgSCHUtlRgrSiCfgCfm ARGS ((Inst inst, SpId spId,
4423 RgrCfgTransId transId,U8 status));
4425 EXTERN S16 rgSCHGomHndlWarningSiCfg ARGS(( Region reg, Pool pool,
4426 RgSchCb *instCb, SpId spId, RgrCfgTransId transId,
4427 RgrWarningSiCfgReqInfo *warningSiCfgReqInfo));
4429 EXTERN Void rgSCHGomHndlWarningSiStopReq ARGS(( Region reg, Pool pool,
4430 RgSchCb *instCb, U8 siId,
4431 RgrCfgTransId transId, SpId spId));
4433 EXTERN S16 rgSCHUtlRgrWarningSiCfgCfm ARGS ((Inst inst, SpId spId, U8 siId,
4434 RgrCfgTransId transId,U8 status));
4435 #endif /* RGR_SI_SCH */
4436 /* LTE_ADV_FLAG_REMOVED_START */
4437 EXTERN S16 rgSchDSFRRntpInfoInit ARGS ((TknStrOSXL *rntpPtr, RgSchCellCb *cell,
4439 EXTERN S16 rgSchDSFRRntpInfoFree ARGS ((TknStrOSXL *rntpPtr, RgSchCellCb *cell,
4441 EXTERN S16 rgSchUpdtRNTPInfo ARGS ((RgSchCellCb *cell, RgSchDlSf *sf,
4442 RgrLoadInfReqInfo *loadInfReq));
4443 EXTERN S16 rgSCHCfgVldtRgrLoadInf ARGS(( Inst inst, RgrLoadInfReqInfo *loadInfReq,
4444 RgSchCellCb *cell, RgSchErrInfo *errInfo));
4445 EXTERN S16 rgSCHGomHndlLoadInf ARGS(( Region reg, Pool pool,
4446 RgSchCb *instCb, SpId spId,
4447 RgrCfgTransId transId, RgrLoadInfReqInfo *cfgReqInfo));
4448 /* LTE_ADV_FLAG_REMOVED_END */
4451 * APIs exposed by GOM module
4453 EXTERN S16 rgSCHGomHndlCfg ARGS((Region reg, Pool pool, RgSchCb *instCb, SpId spId,
4454 RgrCfgTransId transId, RgrCfgReqInfo *cfgReqInfo));
4455 EXTERN S16 rgSCHGomTtiHndlr ARGS((RgSchCellCb *cell, SpId spId));
4459 * APIs exposed by RAM module
4461 EXTERN S16 rgSCHRamVldtUeCfg ARGS((
4465 EXTERN S16 rgSCHRamProcRaReq ARGS((U8 raReqCnt, RgSchCellCb *cell, CmLteRnti raRnti,
4466 TfuRachInfo *raReqInd,
4467 CmLteTimingInfo timingInfo,
4469 RgSchErrInfo *err));
4470 EXTERN S16 rgSCHRamCreateRaCb ARGS((RgSchCellCb *cell, RgSchRaCb **raCb,
4471 RgSchErrInfo *err));
4472 EXTERN S16 rgSCHRamRgrUeCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4473 RgSchRaCb *raCb, RgSchErrInfo *err));
4474 EXTERN S16 rgSCHRamProcMsg3 ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4475 RgSchRaCb *raCb, RgInfUeDatInd *pdu,
4476 RgSchErrInfo *err));
4477 EXTERN S16 rgSCHRamUpdtBo ARGS((RgSchCellCb *cell, RgSchRaCb *raCb,
4478 RgInfCmnBoRpt *staRsp));
4479 EXTERN S16 rgSCHRamMsg3DatInd ARGS((RgSchRaCb *raCb));
4480 EXTERN S16 rgSCHRamMsg3FailureInd ARGS((RgSchRaCb *raCb));
4481 EXTERN S16 rgSCHRamMsg4FdbkInd ARGS((RgSchRaCb *raCb));
4482 EXTERN S16 rgSCHRamMsg4Done ARGS((RgSchCellCb *cell, RgSchRaCb *raCb));
4483 EXTERN S16 rgSCHRamDelRaCb ARGS((RgSchCellCb *cell, RgSchRaCb *raCb,
4485 EXTERN S16 rgSCHRamFreeCell ARGS((RgSchCellCb *cell));
4486 EXTERN S16 rgSCHRamTtiHndlr ARGS((RgSchCellCb *cell));
4487 EXTERN Void rgSCHCmnUlSch ARGS((RgSchCellCb *cell));
4488 EXTERN Void rgSCHCmnDlCommonChSch ARGS ((RgSchCellCb *cell));
4490 /* Added periodic BSR timer */
4491 EXTERN S16 rgSCHCmnBsrTmrExpry ARGS(( RgSchUeCb *ueCb));
4494 EXTERN S16 rgSCHRamDelRaReq ARGS((RgSchCellCb *cell,
4495 CmLteTimingInfo timingInfo,
4498 EXTERN S16 rgSCHRamAddToRaInfoSchdLst(RgSchCellCb *cell, RgSchRaCb *raCb);
4500 EXTERN S16 rgSCHRamRmvFrmRaInfoSchdLst(RgSchCellCb *cell, RgSchRaCb *raCb);
4502 /* APIs exposed by UHM */
4503 /* Added for Uplink Adaptive retransmission */
4504 EXTERN Void rgSCHUhmNonadapRetx ARGS((RgSchUlHqProcCb *hqProc));
4505 EXTERN S16 rgSCHUhmHqEntInit ARGS ((RgSchCellCb *cellCb, RgSchUeCb *ueCb));
4506 #ifndef MAC_SCH_STATS
4507 EXTERN Void rgSCHUhmProcDatInd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4508 CmLteTimingInfo frm));
4509 #else /* MAC_SCH_STATS */
4510 EXTERN Void rgSCHUhmProcDatInd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4511 CmLteTimingInfo frm, U8 cqi));
4513 EXTERN Void rgSCHUhmProcMsg3DatInd ARGS((RgSchUlHqProcCb *hqProc));
4514 EXTERN Void rgSCHUhmProcMsg3Failure ARGS((RgSchUlHqProcCb *hqProc));
4515 #ifndef MAC_SCH_STATS
4516 EXTERN Void rgSCHUhmProcHqFailure ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4517 CmLteTimingInfo frm, TknU8 rv));
4518 #else /* MAC_SCH_STATS */
4519 EXTERN Void rgSCHUhmProcHqFailure ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4520 CmLteTimingInfo frm, TknU8 rv, U8 cqi));
4522 EXTERN RgSchUlHqProcCb* rgSCHUhmGetUlHqProc ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4524 EXTERN Void rgSCHUhmNewTx ARGS((RgSchUlHqProcCb *hqProc, U8 maxHqRetx,
4525 RgSchUlAlloc *alloc));
4526 EXTERN Void rgSCHUhmFreeProc ARGS((RgSchUlHqProcCb *hqProc,
4527 RgSchCellCb *cell));
4528 EXTERN Void rgSCHUhmRetx ARGS((RgSchUlHqProcCb *hqProc, RgSchUlAlloc *alloc));
4529 EXTERN Void rgSCHUhmRgrUeCfg ARGS(( RgSchCellCb *cellCb, RgSchUeCb *ueCb,
4531 EXTERN Void rgSCHUhmRgrUeRecfg ARGS(( RgSchCellCb *cellCb, RgSchUeCb *ueCb,
4532 RgrUeRecfg *ueRecfg));
4533 EXTERN Void rgSCHUhmFreeUe ARGS(( RgSchCellCb *cellCb, RgUeUlHqCb *hqEnt));
4534 EXTERN S16 rgSCHUhmAppendPhich ARGS(( RgSchCellCb *cellCb,
4535 CmLteTimingInfo frm, U8 idx));
4537 /* APIs exposed by DBM */
4538 EXTERN S16 rgSCHDbmInitCell ARGS((RgSchCellCb *cellCb));
4539 EXTERN S16 rgSCHDbmDeInitUeCbLst ARGS(( RgSchCellCb *cellCb));
4541 EXTERN S16 rgSCHDbmDeInitUeTfuPendLst ARGS(( RgSchCellCb *cellCb));
4543 EXTERN S16 rgSCHDbmInsUeCb ARGS(( RgSchCellCb *cellCb, RgSchUeCb *ueCb));
4544 EXTERN RgSchUeCb* rgSCHDbmGetUeCb ARGS(( RgSchCellCb *cellCb, CmLteRnti ueId));
4545 EXTERN RgSchUeCb* rgSCHDbmGetNextUeCb ( RgSchCellCb *cellCb, RgSchUeCb *ueCb);
4546 EXTERN S16 rgSCHDbmDelUeCb ARGS(( RgSchCellCb *cellCb, RgSchUeCb *ueCb));
4548 EXTERN S16 rgSCHDbmDelL2MUe ARGS(( RgSchCellCb *cellCb, RgSchUeCb *ueCb));
4550 EXTERN S16 rgSCHDbmInitUe ARGS((RgSchUeCb *ueCb));
4551 EXTERN Void rgSCHDbmInsDlDedLcCb ARGS((RgSchUeCb *ueCb, RgSchDlLcCb *dlLcCb));
4552 EXTERN Void rgSCHDbmDelDlDedLcCb ARGS((RgSchUeCb *ueCb, RgSchDlLcCb *dlLcCb));
4553 EXTERN RgSchDlLcCb* rgSCHDbmGetDlDedLcCb ARGS(( RgSchUeCb *ueCb, CmLteLcId idx));
4554 EXTERN RgSchDlLcCb* rgSCHDbmGetFirstDlDedLcCb ARGS((RgSchUeCb *ueCbb));
4555 EXTERN RgSchDlLcCb* rgSCHDbmGetNextDlDedLcCb ARGS((RgSchUeCb *ueCb, RgSchDlLcCb *lcCb));
4556 EXTERN RgSchClcDlLcCb* rgSCHDbmGetCmnLcCb ARGS(( RgSchCellCb *cellCb, CmLteLcId lcId));
4557 EXTERN RgSchClcDlLcCb* rgSCHDbmGetBcchOnBch ARGS(( RgSchCellCb *cellCb ));
4558 EXTERN RgSchClcDlLcCb* rgSCHDbmGetFirstBcchOnDlsch ARGS(( RgSchCellCb *cellCb));
4559 EXTERN RgSchClcDlLcCb* rgSCHDbmGetSecondBcchOnDlsch ARGS(( RgSchCellCb *cellCb));
4560 EXTERN RgSchClcDlLcCb* rgSCHDbmGetPcch ARGS(( RgSchCellCb *cellCb));
4561 EXTERN Void rgSCHDbmInsBcchOnBch ARGS(( RgSchCellCb *cellCb, RgSchClcDlLcCb *cmnDlLcCb));
4562 EXTERN Void rgSCHDbmInsBcchOnDlsch ARGS(( RgSchCellCb *cellCb, RgSchClcDlLcCb *cmnDlLcCb));
4563 EXTERN Void rgSCHDbmInsPcch ARGS(( RgSchCellCb *cellCb, RgSchClcDlLcCb *cmnDlLcCb));
4565 EXTERN Void rgSCHDbmInitCmnLcBoLst ARGS(( RgSchClcDlLcCb *cmnDlLcCb));
4566 EXTERN Void rgSCHDbmInsCmnLcBoRpt ARGS(( RgSchClcDlLcCb *cmnDlLcCb,
4567 RgSchClcBoRpt *cmnBoRpt));
4568 EXTERN RgSchRaCb* rgSCHDbmGetRaCb ARGS(( RgSchCellCb *cellCb, CmLteRnti key));
4569 EXTERN Void rgSCHDbmInsCrntRgrCfgElem ARGS(( RgSchCellCb *cellCb,
4570 RgSchCfgElem *cfgElem));
4571 EXTERN Void rgSCHDbmInsPndngRgrCfgElem ARGS(( RgSchCellCb *cellCb,
4572 RgSchCfgElem *cfgElem));
4573 EXTERN RgSchCfgElem* rgSCHDbmGetNextCrntRgrCfgElem ARGS(( RgSchCellCb *cellCb,
4574 RgSchCfgElem *cfgElem));
4575 EXTERN RgSchCfgElem* rgSCHDbmGetNextPndngRgrCfgElem ARGS(( RgSchCellCb *cellCb,
4576 RgSchCfgElem *cfgElem));
4577 EXTERN RgSchCfgElem* rgSCHDbmGetPndngRgrCfgElemByKey ARGS(( RgSchCellCb *cellCb,
4578 CmLteTimingInfo key));
4579 EXTERN RgSchCfgElem* rgSCHDbmDelCrntRgrCfgElem ARGS(( RgSchCellCb *cellCb,
4580 RgSchCfgElem *cfgElem));
4581 EXTERN RgSchCfgElem* rgSCHDbmDelPndngRgrCfgElem ARGS(( RgSchCellCb *cellCb,
4582 RgSchCfgElem *cfgElem));
4584 EXTERN S16 rgSCHDbmRntiDbInit ARGS(( RgSchCellCb *cellCb, U16 rntiStart, U16 maxRntis));
4585 EXTERN Void rgSCHDbmRntiDbDeInit ARGS(( RgSchCellCb *cellCb));
4586 EXTERN RgSchRntiLnk* rgSCHDbmGetRnti ARGS(( RgSchCellCb *cellCb));
4587 EXTERN Void rgSCHDbmRlsRnti ARGS(( RgSchCellCb *cellCb, RgSchRntiLnk *rntiLnk));
4588 /* Fix : syed HO UE does not have a valid ue->rntiLnk */
4589 EXTERN Void rgSCHUtlIndRntiRls2Mac ARGS(( RgSchCellCb *cell, CmLteRnti rnti,
4590 Bool ueIdChng, CmLteRnti newRnti));
4592 /*rg008.201 - Added support for SPS*/
4594 EXTERN S16 rgSCHDbmDeInitSpsUeCbLst ARGS((RgSchCellCb *cellCb));
4595 EXTERN S16 rgSCHDbmInsSpsUeCb ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb));
4596 EXTERN RgSchUeCb* rgSCHDbmGetSpsUeCb ARGS((RgSchCellCb *cellCb, CmLteRnti ueId));
4597 EXTERN RgSchUeCb* rgSCHDbmGetNextSpsUeCb ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb));
4598 EXTERN S16 rgSCHDbmDelSpsUeCb ARGS((RgSchCellCb *cellCb,RgSchUeCb *ueCb));
4599 #endif /* LTEMAC_SPS */
4605 EXTERN S16 rgSchL2mMeasReq ARGS ((
4607 LrgSchMeasReqInfo *measInfo,
4609 EXTERN S16 RgSchMacL2MeasSend ARGS
4612 RgInfL2MeasSndReq *measInfo
4615 EXTERN S16 RgSchMacL2MeasStop ARGS
4618 RgInfL2MeasStopReq *measInfo
4620 #endif /* LTE_L2_MEAS */
4624 /* LTE_ADV_FLAG_REMOVED_START */
4625 EXTERN S16 rgSchSFRTotalPoolInit ARGS((RgSchCellCb *cell, RgSchDlSf *sf));
4626 /* LTE_ADV_FLAG_REMOVED_END */
4627 EXTERN Void rgSCHDhmHqPAdd2FreeLst ARGS (( RgSchDlHqProcCb *hqP));
4628 EXTERN Void rgSCHDhmHqPAdd2InUseLst ARGS (( RgSchDlHqProcCb *hqP));
4629 EXTERN Void rgSCHDhmHqPDelFrmFreeLst ARGS (( RgSchDlHqProcCb *hqP));
4630 EXTERN Void rgSCHDhmHqPDelFrmInUseLst ARGS (( RgSchDlHqProcCb *hqP));
4632 EXTERN RgSchDlHqEnt *rgSCHDhmHqEntInit ARGS((RgSchCellCb *cell));
4633 EXTERN S16 rgSCHDhmGetAvlHqProc ARGS((RgSchCellCb *cell, RgSchUeCb *ue, CmLteTimingInfo timingInfo,
4634 RgSchDlHqProcCb **hqP));
4635 EXTERN Void rgSCHDhmHqRetx ARGS((RgSchDlHqEnt *hqE, CmLteTimingInfo timeInfo,
4636 RgSchDlHqProcCb *hqP));
4637 EXTERN RgSchDlHqProcCb * rgSCHDhmLastSchedHqProc ARGS((RgSchDlHqEnt *hqE));
4638 /* CR timer changes*/
4639 EXTERN S16 rgSCHDhmGetCcchSduHqProc ARGS((RgSchUeCb *ueCb, CmLteTimingInfo timeInfo,
4640 RgSchDlHqProcCb **hqP));
4641 EXTERN S16 rgSCHDhmGetMsg4HqProc ARGS((RgSchRaCb *raCb, CmLteTimingInfo timeInfo));
4642 EXTERN Void rgSCHDhmRlsHqProc ARGS((RgSchDlHqProcCb *hqP));
4643 /* ccpu00118350 : Correcting NDI manipulation of Harq */
4644 EXTERN Void rgSCHDhmRlsHqpTb ARGS((RgSchDlHqProcCb *hqP, U8 tbIdx, Bool togNdi));
4645 EXTERN Void rgSCHUtlDlHqPTbAddToTx ARGS((RgSchDlSf *subFrm,
4646 RgSchDlHqProcCb *hqP, U8 tbIdx ));
4647 EXTERN Void rgSCHDhmHqTbRetx ARGS(( RgSchDlHqEnt *hqE,
4648 CmLteTimingInfo timingInfo, RgSchDlHqProcCb *hqP, U8 tbIdx));
4649 EXTERN Void rgSCHUtlDlHqPTbAddToTx ARGS((RgSchDlSf *subFrm,
4650 RgSchDlHqProcCb *hqP, U8 tbIdx ));
4651 EXTERN Void rgSCHDhmHqTbRetx ARGS(( RgSchDlHqEnt *hqE,
4652 CmLteTimingInfo timingInfo, RgSchDlHqProcCb *hqP, U8 tbIdx));
4654 EXTERN S16 rgSCHDhmGetHqProcFrmId ARGS((RgSchCellCb *cell, RgSchUeCb *ue, U8 idx,
4655 RgSchDlHqProcCb **hqP));
4657 /* Changes for MIMO feature addition */
4658 EXTERN Void rgSCHDhmSchdTa ARGS((RgSchUeCb *ueCb, RgSchDlHqTbCb *tbInfo));
4659 EXTERN S16 rgSCHDhmHqFdbkInd ARGS((Void *cb, U8 cbType, RgSchCellCb *cellCb,
4660 CmLteTimingInfo timingInfo, RgTfuHqInfo *fdbk, RgInfRlsHqInfo
4661 *rlsHqBufs,RgSchErrInfo *err));
4663 EXTERN S16 rgSCHDhmEmtcHqFdbkInd ARGS((Void *cb, U8 cbType, RgSchCellCb *cellCb,
4664 CmLteTimingInfo timingInfo, RgTfuHqInfo *fdbk, RgInfRlsHqInfo
4665 *rlsHqBufs,RgSchErrInfo *err));
4666 EXTERN PUBLIC S16 rgSCHUtlAddToResLst
4673 EXTERN S16 rgSCHDhmPrcFdbkForTb(RgSchCellCb *cell,RgSchUeCb *ue,
4674 RgSchDlHqProcCb *hqP,RgSchDlSf *sf,Bool isMsg4,
4675 U16 rnti,U8 tbCnt,CmLteTimingInfo timingInfo, U8 isAck,
4676 RgInfRlsHqInfo *rlsHqBufs,RgSchErrInfo *err
4679 EXTERN Void rgSCHDhmRgrUeCfg ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb,
4680 RgrUeCfg *ueCfg, RgSchErrInfo *err));
4681 EXTERN Void rgSCHDhmRgrUeRecfg ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb,
4682 RgrUeRecfg *ueCfg, RgSchErrInfo *err));
4683 EXTERN Void rgSCHDhmRgrCellCfg ARGS((RgSchCellCb *cellCb, RgrCellCfg *cellCfg,
4684 RgSchErrInfo *err));
4685 EXTERN Void rgSCHDhmRgrCellRecfg ARGS((RgSchCellCb *cellCb, RgrCellRecfg
4686 *cellRecfg, RgSchErrInfo *err));
4687 EXTERN Void rgSCHDhmFreeUe ARGS((RgSchUeCb *ueCb));
4688 EXTERN Void rgSCHDhmUpdTa ARGS((RgSchCellCb *cellCb, RgSchUeCb *ueCb, U8 ta));
4689 EXTERN Void rgSCHDhmProcTAExp ARGS((RgSchUeCb *ue));
4690 /* Changes for MIMO feature addition */
4691 EXTERN S16 rgSCHDhmAddLcData ARGS((Inst inst, RgSchLchAllocInfo *lchData,
4692 RgSchDlHqTbCb *tbInfo));
4693 EXTERN S16 rgSCHDhmRlsDlsfHqProc ARGS((RgSchCellCb *cellCb, CmLteTimingInfo
4697 EXTERN S16 rgSCHDhmTddRlsSubFrm ARGS((RgSchCellCb *cell, CmLteTimingInfo uciTimingInfo));
4698 EXTERN S16 rgSCHCfgVldtTddDrxCycCfg ARGS((RgSchCellCb *cell, U16 drxCycle,
4699 U8 onDurTmr, U16 offSet));
4701 /* Added support for SPS*/
4703 EXTERN S16 rgSCHDhmGetHqProcFrmId ARGS((
4707 RgSchDlHqProcCb **hqP
4709 #endif /* LTEMAC_SPS */
4710 /* Freeing up the HARQ proc blocked for
4711 * indefinite time in case of Retx */
4712 EXTERN S16 rgSCHDhmDlRetxAllocFail ARGS((
4714 RgSchDlHqProcCb *proc
4716 /* MS_WORKAROUND for ccpu00122893 temp fix Incorrect HqProc release was done instead of
4717 * a Harq Entity reset. Fixing the same */
4718 EXTERN Void rgSCHDhmHqEntReset ARGS((
4721 /* Measurement GAP and ACK NACK */
4723 EXTERN S16 rgSCHMeasGapANRepUeCfg ARGS((
4728 EXTERN S16 rgSCHMeasGapANRepUeRecfg ARGS((
4733 /* ccpu00133470- Added extra argument to identify UE DEL*/
4734 EXTERN Void rgSCHMeasGapANRepUeDel ARGS((
4739 EXTERN S16 rgSCHMeasGapANRepTtiHndl ARGS((
4742 EXTERN S16 rgSCHMeasGapANRepGetDlInactvUe ARGS((
4744 CmLListCp *dlInactvUeLst
4746 EXTERN S16 rgSCHMeasGapANRepGetUlInactvUe ARGS((
4748 CmLListCp *ulInactvUeLst
4750 EXTERN Void rgSCHMeasGapANRepDlInactvTmrExpry ARGS((
4754 EXTERN Void rgSCHMeasGapANRepUlInactvTmrExpry ARGS((
4758 EXTERN Void rgSCHMeasGapANRepTmrExpry ARGS((
4761 EXTERN Void rgSCHAckNakRepTmrExpry ARGS((
4764 EXTERN Void rgSCHAckNakRepSndHqFbkRcpReq ARGS((
4767 CmLteTimingInfo timingInfo));
4769 EXTERN Void rgSCHAckNakRepAddToQ ARGS((
4771 RgSchDlSf *crntDlSf));
4777 EXTERN Void rgSCHUtlHdlCrcInd ARGS((
4780 CmLteTimingInfo timingInfo
4785 EXTERN S16 rgSCHUtlValidateMeasReq ARGS ((RgSchCellCb *cellCb,
4786 LrgSchMeasReqInfo *schL2MeasInfo,
4789 EXTERN S16 rgSchL2mSndCfm ARGS((Pst *pst,
4790 RgSchL2MeasCb *measCb,
4791 LrgSchMeasReqInfo *measInfo,
4794 EXTERN S16 rgSchFillL2MeasCfm ARGS((
4796 RgSchL2MeasCb *measCb,
4797 LrgSchMeasCfmInfo *cfm,
4800 EXTERN Void rgSchL2mFillCfmPst ARGS((
4803 LrgSchMeasReqInfo *measInfo
4805 EXTERN S16 rgSCHL2Meas ARGS((
4809 #endif /* LTE_L2_MEAS */
4810 /* Added changes of TFU_UPGRADE */
4812 EXTERN F64 rgSCHUtlPower ARGS
4818 EXTERN U32 rgSCHUtlParse ARGS
4826 EXTERN U8 rgSCHUtlFindDist ARGS
4832 EXTERN Bool rgSCHUtlPdcchAvail ARGS((RgSchCellCb *cell, RgSchPdcchInfo
4833 *pdcchInfo, CmLteAggrLvl aggrLvl, RgSchPdcch **pdcch));
4834 EXTERN Void rgSCHUtlPdcchPut ARGS((RgSchCellCb *cell, RgSchPdcchInfo *pdcchInfo,
4835 RgSchPdcch *pdcch));
4837 /* Changes for passing iPhich at TFU interface*/
4838 EXTERN S16 rgSCHUtlAddPhich ARGS((RgSchCellCb *cellCb, CmLteTimingInfo frm,
4839 U8 hqFeedBack, U8 nDmrs, U8 rbStart, U8 iPhich));
4841 EXTERN S16 rgSCHUtlAddPhich ARGS((RgSchCellCb *cellCb, CmLteTimingInfo frm,
4842 U8 hqFeedBack, U8 nDmrs, U8 rbStart,Bool isForMsg3));
4844 EXTERN RgSchDlSf* rgSCHUtlSubFrmGet ARGS((RgSchCellCb *cell,
4845 CmLteTimingInfo frm));
4846 EXTERN Void rgSCHUtlSubFrmPut ARGS((RgSchCellCb *cell, RgSchDlSf *sf));
4847 EXTERN U8 rgSCHUtlLog32bitNbase2 ARGS((U32 n));
4848 /* Added support for SPS*/
4852 EXTERN RgSchDlHqProcCb * rgSCHDhmSpsDlGetHqProc ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4853 CmLteTimingInfo timingInfo));
4856 EXTERN U8 rgSCHUtlCalcNCce ARGS((U8 bw, RgrPhichNg ng, U8 cfi, U8 mPhich,
4857 U8 numAntna, Bool isEcp));
4859 EXTERN U8 rgSCHUtlCalcNCce ARGS((U8 bw, RgrPhichNg ng, U8 cfi, U8 numAntna, Bool
4863 /* Changes for passing iPhich at TFU interface*/
4864 EXTERN S16 rgSCHUtlGetPhichInfo ARGS((RgSchUlHqProcCb *hqProc, U8 *rbStartRef,
4865 U8 *nDmrsRef, U8 *iPhich));
4867 EXTERN S16 rgSCHUtlGetPhichInfo ARGS((RgSchUlHqProcCb *hqProc, U8 *rbStartRef,
4870 /* Added changes of TFU_UPGRADE */
4872 /* To include the length and ModOrder in DataRecp Req. */
4873 /* Updating NDI and HARQ proc Id */
4874 EXTERN S16 rgSCHUtlAllocRcptInfo ARGS((RgSchUlAlloc *alloc, CmLteRnti *rnti,
4875 U8 *iMcsRef, U8 *rbStartRef, U8 *numRbRef, U8 *rvRef, U16 *size,
4876 TfuModScheme *modType,Bool *isRtx,
4881 EXTERN S16 rgSCHUtlAllocRcptInfo ARGS((
4883 RgSchUlAlloc *alloc,
4884 CmLteTimingInfo *timeInfo,
4885 TfuUeUlSchRecpInfo *recpReq
4887 #endif /* TFU_UPGRADE */
4889 EXTERN S16 rgSCHUtlRgrCellCfg ARGS((RgSchCellCb *cell, RgrCellCfg *cellCfg,
4890 RgSchErrInfo *errInfo));
4891 EXTERN S16 rgSCHUtlRgrCellRecfg ARGS((RgSchCellCb *cell, RgrCellRecfg *recfg,
4892 RgSchErrInfo *errInfo));
4893 EXTERN S16 rgSCHUtlFreeCell ARGS((RgSchCellCb *cell));
4894 EXTERN S16 rgSCHUtlRgrUeCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4895 RgrUeCfg *cfg, RgSchErrInfo *err));
4896 EXTERN S16 rgSCHUtlRgrLcCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4897 RgSchDlLcCb *dl, RgrLchCfg *cfg,RgSchErrInfo *errInfo));
4898 EXTERN S16 rgSCHUtlRgrLcDel ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4899 CmLteLcId lcId, U8 lcgId));
4900 EXTERN S16 rgSCHUtlRgrLcRecfg ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
4901 RgSchDlLcCb *dlLc,RgrLchRecfg *recfg,RgSchErrInfo *err));
4902 EXTERN S16 rgSCHUtlRgrLcgCfg ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
4903 RgrLcgCfg *cfg,RgSchErrInfo *errInfo));
4904 EXTERN S16 rgSCHUtlRgrLcgRecfg ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
4905 RgrLcgRecfg *recfg,RgSchErrInfo *err));
4906 EXTERN Void rgSCHUtlRgrLcgDel ARGS ((RgSchCellCb *cell,RgSchUeCb *ue,
4908 EXTERN Void rgSCHUtlDlCqiInd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4909 TfuDlCqiRpt *dlCqiInd, CmLteTimingInfo timingInfo));
4911 /* Added changes of TFU_UPGRADE */
4913 EXTERN Void rgSCHUtlRawCqiInd ARGS
4917 TfuRawCqiRpt* rawCqiRpt,
4918 CmLteTimingInfo timingInfo
4921 EXTERN Void rgSCHUtlSrsInd ARGS
4926 CmLteTimingInfo timingInfo
4928 EXTERN S16 rgSCHUtlGetCfgPerOff ARGS
4937 EXTERN Void rgSCHUtlDoaInd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4938 TfuDoaRpt *doaInd));
4939 EXTERN Void rgSCHUtlDlTARpt ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
4940 /* Changes for MIMO feature addition */
4941 EXTERN Void rgSCHUtlDlRlsSubFrm ARGS((RgSchCellCb *cell, CmLteTimingInfo subFrm));
4942 EXTERN Void rgSCHUtlDlProcAddToRetx ARGS((RgSchCellCb *cell,
4943 RgSchDlHqProcCb *hqP));
4944 EXTERN S16 rgSCHUtlRegSch ARGS((U8 schIdx, RgSchdApis *apis));
4945 EXTERN Void rgSCHUtlDlHqProcAddToTx ARGS((RgSchDlSf *subFrm, RgSchDlHqProcCb *hqP));
4946 /* Changes for MIMO feature addition */
4947 EXTERN Void rgSCHUtlDlHqPTbRmvFrmTx ARGS((RgSchDlSf *subFrm,
4948 RgSchDlHqProcCb *hqP, U8 tbIdx, Bool isRepeating));
4949 EXTERN S16 rgSCHUtlRgrUeRecfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4950 RgrUeRecfg *recfg, RgSchErrInfo *err));
4951 EXTERN Void rgSCHUtlFreeDlLc ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4952 RgSchDlLcCb *dlLc));
4953 EXTERN Void rgSCHUtlFreeUlLc ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4954 RgSchUlLcCb *ulLc));
4955 EXTERN Void rgSCHUtlFreeUe ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
4956 EXTERN Void rgSCHUtlDlDedBoUpd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4959 EXTERN S16 rgSCHUtlUpdUlHqProc ARGS((RgSchCellCb *cell, RgSchUlHqProcCb *curProc,
4960 RgSchUlHqProcCb *oldProc));
4962 /* PHR handling for MSG3 */
4963 EXTERN Void rgSCHUtlRecMsg3Alloc ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4965 EXTERN S16 rgSCHUtlContResUlGrant ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4966 RgSchErrInfo *err));
4967 EXTERN S16 rgSCHUtlSrRcvd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4968 CmLteTimingInfo, RgSchErrInfo *err));
4969 EXTERN Void rgSCHUtlUpdBsrShort ARGS((RgSchCellCb *cell, RgSchUeCb *ue, U8 lcgId,
4970 U8 bsr, RgSchErrInfo *err));
4971 EXTERN Void rgSCHUtlUpdBsrTrunc ARGS((RgSchCellCb *cell, RgSchUeCb *ue, U8 lcgId,
4972 U8 bsr, RgSchErrInfo *err));
4973 EXTERN Void rgSCHUtlUpdBsrLong ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4974 U8 bsr1,U8 bsr2,U8 bsr3,U8 bsr4, RgSchErrInfo *err));
4975 EXTERN S16 rgSCHUtlUpdPhr ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
4976 U8 phr, RgSchErrInfo *err));
4977 EXTERN S16 rgSCHUtlUpdExtPhr ARGS(( RgSchCellCb *cell, RgSchUeCb *ue,
4978 RgInfExtPhrCEInfo * extPhr, RgSchErrInfo *err));
4979 EXTERN S16 rgSCHUtlDataRcvd ARGS((RgSchCellCb *cell, RgSchUeCb *ue, U8 numLc,
4980 RgSchUlLcCb *lcArr[], U16 bytesArr[], RgSchErrInfo *err));
4981 EXTERN Void rgSCHUtlUlCqiInd ARGS(( RgSchCellCb *cell, RgSchUeCb *ue,
4982 TfuUlCqiRpt *ulCqiInfo));
4983 EXTERN Void rgSCHUtlPucchDeltaPwrInd ARGS(( RgSchCellCb *cell, RgSchUeCb *ue,
4985 EXTERN Void rgSCHUtlUeReset ARGS(( RgSchCellCb *cell, RgSchUeCb *ue));
4986 EXTERN Void rgSCHUtlUlHqProcForUe ARGS((RgSchCellCb *cell, CmLteTimingInfo frm,
4987 RgSchUeCb *ue, RgSchUlHqProcCb **procRef));
4988 EXTERN RgSchUlAlloc *rgSCHUtlFirstRcptnReq ARGS((RgSchCellCb *cell));
4989 EXTERN RgSchUlAlloc *rgSCHUtlNextRcptnReq ARGS((RgSchCellCb *cell,
4990 RgSchUlAlloc *alloc));
4991 EXTERN RgSchUlAlloc *rgSCHUtlFirstHqFdbkAlloc ARGS((RgSchCellCb *cell, U8 idx));
4992 EXTERN RgSchUlAlloc *rgSCHUtlNextHqFdbkAlloc ARGS((RgSchCellCb *cell,
4993 RgSchUlAlloc *alloc, U8 idx));
4994 EXTERN S16 rgSCHUtlTfuBndReq ARGS((Inst inst, SuId suId, SpId spId));
4995 EXTERN S16 rgSCHUtlTfuUBndReq ARGS((Inst inst, RgSchLowSapCfgInfo sapCfg, Reason reason));
4997 EXTERN S16 rgSCHEmtcUtlResetSfAlloc ARGS((RgInfSfAlloc *sfAlloc,
4998 Bool resetCmnLcInfo, Bool restAlloc));
5000 EXTERN S16 rgSCHUtlResetSfAlloc ARGS((RgInfSfAlloc *sfAlloc,
5001 Bool resetCmnLcInfo, Bool restAlloc));
5002 EXTERN S16 rgSCHUtlGetSfAlloc ARGS((RgSchCellCb *cell));
5003 EXTERN S16 rgSCHUtlPutSfAlloc ARGS((RgSchCellCb *cell));
5004 EXTERN S16 rgSCHUtlAllocSBuf ARGS((Inst inst, Data **pData, Size size));
5005 /* ccpu00117052 - MOD - Passing double pointer
5006 for proper NULLP assignment*/
5007 EXTERN Void rgSCHUtlFreeSBuf ARGS((Inst inst, Data **data, Size size));
5008 EXTERN Void rgSCHUtlFillDgnParams ARGS((Inst inst, RgUstaDgn *dgn,U8 dgnType));
5009 EXTERN Void rgSCHUtlGetPstToLyr ARGS((Pst *pst,RgSchCb *schCb,Inst macInst));
5010 EXTERN S16 rgSCHUtlFillRgInfCmnLcInfo ARGS((RgSchDlSf *sf,RgInfSfAlloc *sfAlloc,
5011 CmLteLcId lcId, Bool sendInd));
5012 EXTERN S16 rgSCHUtlFillRgInfRarInfo ARGS((RgSchDlSf *sf,RgInfSfAlloc *sfAlloc,RgSchCellCb *cell));
5013 EXTERN S16 rgSCHUtlFillPdschDciInfo ARGS((TfuPdschDciInfo *pdschDci,TfuDciInfo
5016 EXTERN Void rgSCHUtlFillRgInfUeInfo ARGS((RgSchDlSf*, RgSchCellCb *cell, CmLListCp *dlDrxInactvTmrLst,
5017 CmLListCp *dlInActvLst, CmLListCp *ulInActvLst));
5019 EXTERN S16 rgSCHUtlUpdSch ARGS((RgInfSfDatInd *subfrmInfo, RgSchCellCb *cellCb,
5020 RgSchUeCb *ueCb, RgInfUeDatInd *pdu,RgSchErrInfo *err));
5021 EXTERN S16 rgSCHUtlHndlCcchBoUpdt ARGS((RgSchCellCb *cell,RgInfCmnBoRpt *boRpt));
5022 EXTERN S16 rgSCHUtlHndlBcchPcchBoUpdt ARGS((RgSchCellCb *cell,RgInfCmnBoRpt
5024 EXTERN S16 rgSCHUtlRgrBndCfm ARGS ((Inst inst, SuId suId,U8 status));
5025 /* Added for sending TTI tick to RRM */
5027 EXTERN S16 rgSCHUtlRgrTtiInd ARGS ((RgSchCellCb *cell, RgrTtiIndInfo *ttiInd));
5029 EXTERN S16 rgSCHUtlRgrCfgCfm ARGS ((Inst inst, SpId spId,
5030 RgrCfgTransId transId,U8 status));
5031 EXTERN S16 rgSCHUtlProcMsg3 ARGS((RgInfSfDatInd *subfrmInfo, RgSchCellCb *cellCb,
5032 RgSchUeCb *ueCb, CmLteRnti rnti,RgInfUeDatInd *pdu,
5033 RgSchErrInfo *err ));
5035 EXTERN S16 rgSCHUtlTfuGrpPwrCntrlReq ARGS((Inst inst,S16 sapId,
5036 TfuGrpPwrCntrlReqInfo *grpPwrCntrlReq));
5038 EXTERN S16 rgSCHUtlTfuCntrlReq ARGS((Inst inst, S16 sapId,
5039 TfuCntrlReqInfo *cntrlReq));
5040 EXTERN S16 rgSCHUtlTfuRecpReq ARGS((Inst inst, S16 sapId,
5041 TfuRecpReqInfo *recpReq));
5042 EXTERN S16 rgSCHUtlValidateTfuSap ARGS((Inst inst,SuId suId));
5043 EXTERN S16 rgSCHUtlAllocEventMem ARGS((Inst inst,Ptr *memPtr,Size memSize));
5044 EXTERN S16 rgSCHUtlGetEventMem ARGS((Ptr *ptr,Size len,Ptr memCpa));
5045 EXTERN S16 rgSCHUtlGetRlsHqAlloc ARGS((RgSchCellCb *cell));
5046 EXTERN S16 rgSCHUtlPutRlsHqAlloc ARGS((RgSchCellCb *cell));
5048 EXTERN S16 rgSCHUtlDlActvtUe ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
5049 EXTERN S16 rgSCHUtlUlActvtUe ARGS((RgSchCellCb *cell, RgSchUeCb *ue));
5050 EXTERN Void rgSCHUtlHdlUlTransInd ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
5051 CmLteTimingInfo timingInfo));
5053 EXTERN Void rgSCHUtlUpdACqiTrigWt ARGS((RgSchUeCb *ue,RgSchUeCellInfo *sCellInfo, U8 isAck));
5055 /* Nprb indication at PHY for common Ch */
5056 /* Corrected allocation for common channels */
5057 EXTERN PUBLIC S32 rgSCHUtlGetAllwdCchTbSz ARGS((U32 bo, U8 *nPrb, U8 *mcs
5059 /* CR timer changes*/
5060 EXTERN PUBLIC S16 rgSCHUtlUpdtBo ARGS((RgSchCellCb *cell,
5061 RgInfCmnBoRpt *staRsp));
5062 EXTERN PUBLIC S16 rgSCHUtlAddUeToCcchSduLst ARGS(
5066 EXTERN PUBLIC S16 rgSCHUtlAddUeToEmtcCcchSduLst ARGS(
5070 EXTERN S16 rgSCHRamRmvFrmEmtcRaInfoSchdLst ARGS((RgSchCellCb *cell, RgSchRaCb *raCb));
5071 EXTERN Void rgSCHRamEmtcDelRaCb ARGS((RgSchCellCb *cell, RgSchRaCb *raCb));
5072 EXTERN S16 rgSCHRamEmtcUpdtBo ARGS((RgSchCellCb *cell, RgSchRaCb *raCb,
5073 RgInfCmnBoRpt *staRsp));
5075 /* Added for SI Enhancement*/
5077 EXTERN Void rgSCHUtlPutSiInfo ARGS((RgSchCellCb *cell));
5078 EXTERN Void rgSCHUtlFreeWarningSiSeg ARGS((Region reg,Pool pool,
5079 CmLListCp *siPduLst));
5080 EXTERN Void rgSCHUtlFreeWarningSiPdu ARGS((RgSchCellCb *cell));
5081 EXTERN Buffer *rgSCHUtlGetWarningSiPdu ARGS((RgSchCellCb *cell));
5082 EXTERN S16 rgSCHUtlGetMcsAndNPrb ARGS((RgSchCellCb *cell, U8 *nPrb, U8 *mcs, MsgLen *msgLen));
5083 EXTERN S16 rgSCHUtlCalMcsAndNPrb ARGS((RgSchCellCb *cell, U8 cfgType, MsgLen msgLen, U8 siId));
5084 #endif/*RGR_SI_SCH*/
5087 EXTERN S16 rgSCHUtlAllocUeANFdbkInfo ARGS((RgSchUeCb *ue,U8 servCellIdx));
5088 EXTERN Void rgSCHUtlDelUeANFdbkInfo ARGS((RgSchUeCb *ue,U8 servCellIdx));
5089 EXTERN S16 rgSCHUtlInitUeANFdbkInfo ARGS((RgSchTddANInfo *anInfo));
5090 EXTERN RgSchTddANInfo* rgSCHUtlGetUeANFdbkInfo ARGS((RgSchUeCb *ueCb, CmLteTimingInfo *timeInfo,U8 servCellIdx));
5091 EXTERN U8 rgSCHUtlGetDlSfIdx ARGS((RgSchCellCb *cell, CmLteTimingInfo *timeInfo));
5092 EXTERN Void rgSCHUtlPrachCfgInit ARGS((RgSchCellCb *cell, RgrCellCfg *cellCfg ));
5093 EXTERN Void rgSCHUtlGetNxtDlSfInfo ARGS((CmLteTimingInfo curDlTime, RgSchCellCb *cell, RgSchDlSf *dlSf, RgSchDlSf **nxtDlsf, CmLteTimingInfo *nxtDlTime));
5094 EXTERN Void rgSCHUtlGetPrevDlSfInfo ARGS((RgSchCellCb * cell, CmLteTimingInfo curDlTime, CmLteTimingInfo *prevDlTime, U8 *numSubfrm));
5096 EXTERN Void rgSCHCmnDlSch ARGS
5100 EXTERN Void rgSCHCmnSndCnsldtInfo ARGS
5104 EXTERN Void rgSCHCmnCnsldtSfAlloc ARGS
5109 /* Added support for SPS*/
5110 EXTERN Void rgSCHCmnDlAllocFnlz ARGS
5116 EXTERN Void rgSCHUtlDlRelPdcchFbk ARGS((
5122 EXTERN Void rgSCHUtlDlProcAck ARGS((
5124 RgSchDlHqProcCb *hqP
5126 EXTERN S16 rgSCHUtlSpsRelInd ARGS((
5127 RgSchCellCb *cellCb,
5132 EXTERN Void rgSCHCmnDlSch ARGS
5137 EXTERN S16 rgSCHUtlSpsActInd ARGS((
5138 RgSchCellCb *cellCb,
5143 EXTERN Void rgSCHUtlHdlCrcFailInd ARGS((
5146 CmLteTimingInfo timingInfo
5149 EXTERN Void rgSCHUtlHdlCrntiCE ARGS((
5154 #endif /* LTEMAC_SPS*/
5156 /******* </AllocHolesMemMgmnt>: START *****/
5157 EXTERN S16 rgSCHUtlUlSfInit ARGS((
5163 EXTERN Void rgSCHUtlUlSfDeinit ARGS((
5167 EXTERN RgSchUlAlloc *rgSCHUtlUlAllocGetHole ARGS((
5172 EXTERN RgSchUlAlloc *rgSCHUtlUlAllocGetCompHole ARGS((
5176 EXTERN RgSchUlAlloc *rgSCHUtlUlAllocGetPartHole ARGS((
5181 EXTERN Void rgSCHUtlUlAllocRls ARGS((
5186 /* UL_ALLOC_ENHANCEMENT */
5187 EXTERN Void rgSCHUtlUlAllocRelease ARGS((
5190 EXTERN RgSchUlAlloc *rgSCHUtlUlAllocFirst ARGS((
5193 EXTERN RgSchUlAlloc *rgSCHUtlUlAllocNxt ARGS((
5197 EXTERN RgSchUlHole *rgSCHUtlUlHoleFirst ARGS((
5200 EXTERN RgSchUlHole *rgSCHUtlUlHoleNxt ARGS((
5204 EXTERN RgSchUlAlloc *rgSCHUtlUlAllocGetAdjNxt ARGS((
5208 EXTERN RgSchUlAlloc *rgSCHUtlUlAllocGetFirst ARGS((
5211 EXTERN Void rgSCHUtlUlHoleAddAlloc ARGS((
5215 /* UL_ALLOC_ENHANCEMENT */
5216 EXTERN Void rgSCHUtlUlHoleAddAllocation ARGS((
5220 EXTERN Void rgSCHUtlUlHoleJoin ARGS((
5226 EXTERN Void rgSCHUtlUlHoleExtndRight ARGS((
5231 EXTERN Void rgSCHUtlUlHoleExtndLeft ARGS((
5236 EXTERN Void rgSCHUtlUlHoleNew ARGS((
5240 EXTERN Void rgSCHUtlUlHoleUpdAllocLnks ARGS((
5242 RgSchUlAlloc *prvAlloc,
5243 RgSchUlAlloc *nxtAlloc
5245 EXTERN Void rgSCHUtlUlHoleIns ARGS((
5249 EXTERN Void rgSCHUtlUlHoleIncr ARGS((
5253 EXTERN Void rgSCHUtlUlHoleDecr ARGS((
5257 EXTERN Void rgSCHUtlUlHoleRls ARGS((
5261 EXTERN S16 rgSCHUtlUlAllocMemInit ARGS((
5263 RgSchUlAllocMem *mem,
5266 EXTERN Void rgSCHUtlUlAllocMemDeinit ARGS((
5268 RgSchUlAllocMem *mem
5270 EXTERN S16 rgSCHUtlUlHoleMemInit ARGS((
5272 RgSchUlHoleMem *mem,
5274 RgSchUlHole **holeRef
5276 EXTERN Void rgSCHUtlUlHoleMemDeinit ARGS((
5280 EXTERN RgSchUlAlloc *rgSCHUtlUlAllocMemGet ARGS((
5281 RgSchUlAllocMem *mem
5283 EXTERN Void rgSCHUtlUlAllocMemRls ARGS((
5284 RgSchUlAllocMem *mem,
5287 EXTERN RgSchUlHole *rgSCHUtlUlHoleMemGet ARGS((
5290 EXTERN Void rgSCHUtlUlHoleMemRls ARGS((
5291 RgSchUlHoleMem *mem,
5294 EXTERN RgSchUlAlloc *rgSCHUtlUlGetSpfcAlloc ARGS((
5299 /******* </AllocHolesMemMgmnt>: END *****/
5301 /* DRX function declarations */
5302 EXTERN S16 rgSCHDrxCellCfg ARGS((RgSchCellCb *cell, RgrCellCfg *cellCfg));
5303 EXTERN Void rgSCHDrxCellDel ARGS((RgSchCellCb *cell));
5304 EXTERN S16 rgSCHDrxUeCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
5307 EXTERN S16 rgSCHDrxUeReCfg ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
5308 RgrUeRecfg *ueCfg));
5310 EXTERN S16 rgSCHDrxUeDel ARGS((RgSchCellCb *cell,RgSchUeCb *ue));
5311 EXTERN Void rgSCHDrxTtiInd ARGS ((RgSchCellCb *cell));
5313 EXTERN S16 rgSCHDrxSfAlloc ARGS ((RgSchCellCb *cellCb, RgSchDlSf
5315 EXTERN S16 rgSCHDrxDlTrnsFail ARGS((RgSchCellCb *cell, RgSchDlHqProcCb
5317 EXTERN Void rgSCHDrxDedRa ARGS((RgSchCellCb *cellCb, RgSchUeCb* ueCb));
5318 EXTERN S16 rgSCHDrxSrInd ARGS((RgSchCellCb *cell,RgSchUeCb *ue));
5320 EXTERN Void rgSCHDrxStrtInActvTmr ARGS((RgSchCellCb *cell,
5323 EXTERN S16 rgSCHUtlGetDrxSchdUesInDl ARGS((RgSchCellCb *cellCb,
5325 RgSchDlHqProcCb *dlHq,
5326 RgInfUeAlloc *allocInfo,
5327 CmLListCp *dlDrxInactvTmrLst,
5328 CmLListCp *dlInActvLst,
5329 CmLListCp *ulInActvLst));
5330 EXTERN Void rgSCHDrxStartHarqRTTTmr ARGS((RgSchCellCb *cell,
5331 RgSchDlHqProcCb *hqP,
5333 EXTERN Void rgSCHDrxUeHqReset ARGS((RgSchCellCb *cell,
5340 EXTERN CONSTANT PUBLIC RgSchTddCellSpSrsSubfrmTbl rgSchTddCellSpSrsSubfrmTbl;
5342 EXTERN CONSTANT PUBLIC RgSchFddCellSpSrsSubfrmTbl rgSchFddCellSpSrsSubfrmTbl;
5347 EXTERN S16 rgSCHHdFddUeCfg ARGS((
5348 RgSchCellCb *cellCb,
5351 EXTERN S16 rgSCHHdFddUeDel ARGS((
5352 RgSchCellCb *cellCb,
5354 EXTERN Void rgSCHCmnHdFddPtUlMrk ARGS((
5355 RgSchCellCb *cellCb));
5356 EXTERN Void rgSCHCmnHdFddChkUlAllow ARGS((
5357 RgSchCellCb *cellCb,
5360 EXTERN Void rgSCHCmnHdFddChkDlAllow ARGS((
5361 RgSchCellCb *cellCb,
5364 EXTERN Void rgSCHCmnHdFddChkNackAllow ARGS((
5365 RgSchCellCb *cellCb,
5367 CmLteTimingInfo timInfo,
5369 EXTERN Void rgSCHCmnHdFddUpdULMark ARGS((
5370 RgSchCellCb *cellCb,
5372 EXTERN Void rgSCHCmnHdFddUpdDLMark ARGS((
5373 RgSchCellCb *cellCb,
5375 EXTERN Void rgSCHHdFddGetSfn ARGS((
5377 CmLteTimingInfo timeInfo,
5379 #endif /* ifdef LTEMAC_HDFDD */
5381 /* ccpu00117452 - MOD - Changed macro name from
5382 RGR_RRM_DLPWR_CNTRL to RGR_CQI_REPT */
5384 PUBLIC S16 rgSCHUtlRgrStaInd ARGS((
5386 RgrStaIndInfo *rgrSta
5389 PUBLIC S16 rgSCHUtlFillSndStaInd ARGS((
5392 RgrStaIndInfo *staInfo,
5395 #endif /* End of RGR_CQI_REPT */
5396 PUBLIC S16 rgSCHUtlRgrUeStaInd ARGS((
5398 RgrUeStaIndInfo *rgrUeSta
5401 PUBLIC S16 rgSCHUtlFillSndUeStaInd ARGS((
5404 RgrUeStaIndInfo *ueStaInfo
5408 /* LTE_ADV_FLAG_REMOVED_START */
5409 PUBLIC S16 rgSCHUtlRgrLoadInfInd ARGS((
5411 RgrLoadInfIndInfo *rgrLoadInf
5413 /* LTE_ADV_FLAG_REMOVED_END */
5416 PUBLIC TfuAckNackMode rgSchUtlGetFdbkMode ARGS((
5417 RgrSchFrmt1b3TypEnum fdbkType
5420 EXTERN TfuAckNackMode rgSchUtlGetFdbkMode ARGS((
5421 RgrSchFrmt1b3TypEnum fdbkType
5424 #endif /*TFU_UPGRADE */
5425 #endif /* LTE_ADV */
5427 PUBLIC Void rgSCHUtlRlsRnti ARGS((
5428 RgSchCellCb *cellCb,
5429 RgSchRntiLnk *rntiLnk,
5433 PUBLIC S16 rgSCHUtlRgmBndCfm ARGS((
5438 PUBLIC Void rgSCHDhmDelHqEnt ARGS((
5442 PUBLIC Void rgSCHDhmAssgnUeHqEntFrmRaCb ARGS((
5446 PUBLIC Void rgSCHUtlReTxTa ARGS((
5447 RgSchCellCb *cellCb,
5449 /* LTE_ADV_FLAG_REMOVED_START */
5450 PUBLIC Void rgSchSFRTotalPoolFree ARGS((
5451 RgSchSFRTotalPoolInfo *sfrTotalPoolInfo,
5452 RgSchCellCb *cell));
5453 PUBLIC Void rgSchDSFRPwrCheck ARGS((
5455 Bool *isAllUePwrHigh));
5456 /* LTE_ADV_FLAG_REMOVED_END */
5458 PUBLIC S16 rgSCHUtlUpdAvgPrbUsage ARGS((
5462 PUBLIC U8 rgSchUtlCfg0ReTxIdx ARGS((
5464 CmLteTimingInfo phichTime,
5468 EXTERN S16 rgSCHUtlBuildNSendLcgReg ARGS((
5475 EXTERN Void rgSCHUtlPdcchInit ARGS((
5479 EXTERN Void rgSCHDynCfiReCfg ARGS((
5483 PUBLIC Void rgSchUtlCalcTotalPrbReq ARGS((RgSchCellCb *cell,
5487 EXTERN U8 rgSchUtlGetNumSbs ARGS((
5493 EXTERN U8 rgSchUtlSortInsUeLst ARGS((
5499 EXTERN S16 rgSCHUtlResetCpuOvrLdState ARGS((
5503 EXTERN Void rgSCHUtlCpuOvrLdAdjItbsCap ARGS((
5507 EXTERN S16 rgSCHTomUtlPcqiSbCalcBpIdx ARGS((
5508 CmLteTimingInfo crntTimInfo,
5510 RgSchUePCqiCb *cqiCb
5514 EXTERN S16 rgSCHUtlSCellHndlCqiCollsn ARGS((
5515 RgSchUePCqiCb *cqiCb
5518 EXTERN S16 rgSCHUtlSCellHndlRiCollsn ARGS((
5519 RgSchUePCqiCb *cqiCb
5523 #endif/*TFU_UPGRADE*/
5525 EXTERN Void rgSCHTomUtlGetTrigSet ARGS((
5532 EXTERN Void rgSCHUtlUpdUeDciSize ARGS((
5537 EXTERN Void rgSCHUtlCalcDciSizes ARGS((
5541 EXTERN Void rgSchCmnPreDlSch ARGS ((
5544 RgSchCellCb **cellLst
5547 EXTERN Void rgSchCmnPstDlSch ARGS ((
5551 EXTERN PUBLIC U8 rgSCHCmnGetBiIndex ARGS ((
5558 #endif /* __cplusplus */
5559 #endif /* __SCH__ */
5562 /**********************************************************************
5564 **********************************************************************/