1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 /* header include files -- defines (.h) */
21 #include "common_def.h"
24 #include "du_app_mac_inf.h"
25 #include "mac_sch_interface.h"
26 #include "lwr_mac_upr_inf.h"
31 #include "fapi_vendor_extension.h"
36 #include "lwr_mac_fsm.h"
37 #include "lwr_mac_phy.h"
38 #include "mac_utils.h"
40 #define MIB_SFN_BITMASK 0xFC
41 #define PDCCH_PDU_TYPE 0
42 #define PDSCH_PDU_TYPE 1
43 #define SSB_PDU_TYPE 3
44 #define PRACH_PDU_TYPE 0
45 #define PUSCH_PDU_TYPE 1
46 #define PUCCH_PDU_TYPE 2
48 #define SET_MSG_LEN(x, size) x += size
50 /* Global variables */
53 uint8_t UnrestrictedSetNcsTable[MAX_ZERO_CORR_CFG_IDX];
54 void fapiMacConfigRsp(uint16_t cellId);
55 uint16_t sendTxDataReq(SlotTimingInfo currTimingInfo, MacDlSlot *dlSlot, p_fapi_api_queue_elem_t prevElem);
56 uint16_t fillUlTtiReq(SlotTimingInfo currTimingInfo, p_fapi_api_queue_elem_t prevElem);
57 uint16_t fillUlDciReq(SlotTimingInfo currTimingInfo, p_fapi_api_queue_elem_t prevElem);
58 uint8_t lwr_mac_procStopReqEvt(SlotTimingInfo slotInfo, p_fapi_api_queue_elem_t prevElem);
60 void lwrMacLayerInit(Region region, Pool pool)
66 memset(&lwrMacCb, 0, sizeof(LwrMacCb));
67 lwrMacCb.region = region;
69 lwrMacCb.clCfgDone = TRUE;
71 lwrMacCb.phyState = PHY_STATE_IDLE;
74 /* Initializing WLS free mem list */
75 lwrMacCb.phySlotIndCntr = 1;
76 for(idx = 0; idx < WLS_MEM_FREE_PRD; idx++)
78 cmLListInit(&wlsBlockToFreeList[idx]);
83 /*******************************************************************
85 * @brief Handles Invalid Request Event
89 * Function : lwr_mac_procInvalidEvt
92 * - Displays the PHY state when the invalid event occurs
95 * @return ROK - success
98 * ****************************************************************/
99 uint8_t lwr_mac_procInvalidEvt(void *msg)
101 #ifdef CALL_FLOW_DEBUG_LOG
102 DU_LOG("\nCall Flow: ENTMAC -> ENTLWRMAC : INVALID_EVENT\n");
104 DU_LOG("\nERROR --> LWR_MAC: Error Indication Event[%d] received in state [%d]", lwrMacCb.event, lwrMacCb.phyState);
109 /*******************************************************************
111 * @brief Fills FAPI message header
115 * Function : fillMsgHeader
118 * -Fills FAPI message header
120 * @params[in] Pointer to header
126 * ****************************************************************/
127 void fillMsgHeader(fapi_msg_t *hdr, uint16_t msgType, uint16_t msgLen)
129 memset(hdr, 0, sizeof(fapi_msg_t));
130 hdr->msg_id = msgType;
131 hdr->length = msgLen;
134 /*******************************************************************
136 * @brief Fills FAPI Config Request message header
140 * Function : fillTlvs
143 * -Fills FAPI Config Request message header
145 * @params[in] Pointer to TLV
152 * ****************************************************************/
153 void fillTlvs(fapi_uint32_tlv_t *tlv, uint16_t tag, uint16_t length,
154 uint32_t value, uint32_t *msgLen)
157 tlv->tl.length = length;
159 *msgLen = *msgLen + sizeof(tag) + sizeof(length) + length;
161 /*******************************************************************
163 * @brief fills the cyclic prefix by comparing the bitmask
167 * Function : fillCyclicPrefix
170 * -checks the value with the bitmask and
171 * fills the cellPtr's cyclic prefix.
173 * @params[in] Pointer to ClCellParam
174 * Value to be compared
177 ********************************************************************/
178 void fillCyclicPrefix(uint8_t value, ClCellParam **cellPtr)
180 if((value & FAPI_NORMAL_CYCLIC_PREFIX_MASK) == FAPI_NORMAL_CYCLIC_PREFIX_MASK)
182 (*cellPtr)->cyclicPrefix = NORMAL_CYCLIC_PREFIX_MASK;
184 else if((value & FAPI_EXTENDED_CYCLIC_PREFIX_MASK) == FAPI_EXTENDED_CYCLIC_PREFIX_MASK)
186 (*cellPtr)->cyclicPrefix = EXTENDED_CYCLIC_PREFIX_MASK;
190 (*cellPtr)->cyclicPrefix = INVALID_VALUE;
194 /*******************************************************************
196 * @brief fills the subcarrier spacing of Downlink by comparing the bitmask
200 * Function : fillSubcarrierSpaceDl
203 * -checks the value with the bitmask and
204 * fills the cellPtr's subcarrier spacing in DL
206 * @params[in] Pointer to ClCellParam
207 * Value to be compared
210 * ****************************************************************/
212 void fillSubcarrierSpaceDl(uint8_t value, ClCellParam **cellPtr)
214 if((value & FAPI_15KHZ_MASK) == FAPI_15KHZ_MASK)
216 (*cellPtr)->supportedSubcarrierSpacingDl = SPACING_15_KHZ;
218 else if((value & FAPI_30KHZ_MASK) == FAPI_30KHZ_MASK)
220 (*cellPtr)->supportedSubcarrierSpacingDl = SPACING_30_KHZ;
222 else if((value & FAPI_60KHZ_MASK) == FAPI_60KHZ_MASK)
224 (*cellPtr)->supportedSubcarrierSpacingDl = SPACING_60_KHZ;
226 else if((value & FAPI_120KHZ_MASK) == FAPI_120KHZ_MASK)
228 (*cellPtr)->supportedSubcarrierSpacingDl = SPACING_120_KHZ;
232 (*cellPtr)->supportedSubcarrierSpacingDl = INVALID_VALUE;
236 /*******************************************************************
238 * @brief fills the downlink bandwidth by comparing the bitmask
242 * Function : fillBandwidthDl
245 * -checks the value with the bitmask and
246 * -fills the cellPtr's DL Bandwidth
248 * @params[in] Pointer to ClCellParam
249 * Value to be compared
252 * ****************************************************************/
254 void fillBandwidthDl(uint16_t value, ClCellParam **cellPtr)
256 if((value & FAPI_5MHZ_BW_MASK) == FAPI_5MHZ_BW_MASK)
258 (*cellPtr)->supportedBandwidthDl = BW_5MHZ;
260 else if((value & FAPI_10MHZ_BW_MASK) == FAPI_10MHZ_BW_MASK)
262 (*cellPtr)->supportedBandwidthDl = BW_10MHZ;
264 else if((value & FAPI_15MHZ_BW_MASK) == FAPI_15MHZ_BW_MASK)
266 (*cellPtr)->supportedBandwidthDl = BW_15MHZ;
268 else if((value & FAPI_20MHZ_BW_MASK) == FAPI_20MHZ_BW_MASK)
270 (*cellPtr)->supportedBandwidthDl = BW_20MHZ;
272 else if((value & FAPI_40MHZ_BW_MASK) == FAPI_40MHZ_BW_MASK)
274 (*cellPtr)->supportedBandwidthDl = BW_40MHZ;
276 else if((value & FAPI_50MHZ_BW_MASK) == FAPI_50MHZ_BW_MASK)
278 (*cellPtr)->supportedBandwidthDl = BW_50MHZ;
280 else if((value & FAPI_60MHZ_BW_MASK) == FAPI_60MHZ_BW_MASK)
282 (*cellPtr)->supportedBandwidthDl = BW_60MHZ;
284 else if((value & FAPI_70MHZ_BW_MASK) == FAPI_70MHZ_BW_MASK)
286 (*cellPtr)->supportedBandwidthDl = BW_70MHZ;
288 else if((value & FAPI_80MHZ_BW_MASK) == FAPI_80MHZ_BW_MASK)
290 (*cellPtr)->supportedBandwidthDl = BW_80MHZ;
292 else if((value & FAPI_90MHZ_BW_MASK) == FAPI_90MHZ_BW_MASK)
294 (*cellPtr)->supportedBandwidthDl = BW_90MHZ;
296 else if((value & FAPI_100MHZ_BW_MASK) == FAPI_100MHZ_BW_MASK)
298 (*cellPtr)->supportedBandwidthDl = BW_100MHZ;
300 else if((value & FAPI_200MHZ_BW_MASK) == FAPI_200MHZ_BW_MASK)
302 (*cellPtr)->supportedBandwidthDl = BW_200MHZ;
304 else if((value & FAPI_400MHZ_BW_MASK) == FAPI_400MHZ_BW_MASK)
306 (*cellPtr)->supportedBandwidthDl = BW_400MHZ;
310 (*cellPtr)->supportedBandwidthDl = INVALID_VALUE;
314 /*******************************************************************
316 * @brief fills the subcarrier spacing of Uplink by comparing the bitmask
320 * Function : fillSubcarrierSpaceUl
323 * -checks the value with the bitmask and
324 * -fills cellPtr's subcarrier spacing in UL
326 * @params[in] Pointer to ClCellParam
327 * Value to be compared
330 * ****************************************************************/
332 void fillSubcarrierSpaceUl(uint8_t value, ClCellParam **cellPtr)
334 if((value & FAPI_15KHZ_MASK) == FAPI_15KHZ_MASK)
336 (*cellPtr)->supportedSubcarrierSpacingsUl = SPACING_15_KHZ;
338 else if((value & FAPI_30KHZ_MASK) == FAPI_30KHZ_MASK)
340 (*cellPtr)->supportedSubcarrierSpacingsUl = SPACING_30_KHZ;
342 else if((value & FAPI_60KHZ_MASK) == FAPI_60KHZ_MASK)
344 (*cellPtr)->supportedSubcarrierSpacingsUl = SPACING_60_KHZ;
346 else if((value & FAPI_120KHZ_MASK) == FAPI_120KHZ_MASK)
348 (*cellPtr)->supportedSubcarrierSpacingsUl = SPACING_120_KHZ;
352 (*cellPtr)->supportedSubcarrierSpacingsUl = INVALID_VALUE;
356 /*******************************************************************
358 * @brief fills the uplink bandwidth by comparing the bitmask
362 * Function : fillBandwidthUl
365 * -checks the value with the bitmask and
366 * fills the cellPtr's UL Bandwidth
370 * @params[in] Pointer to ClCellParam
371 * Value to be compared
375 * ****************************************************************/
377 void fillBandwidthUl(uint16_t value, ClCellParam **cellPtr)
379 if((value & FAPI_5MHZ_BW_MASK) == FAPI_5MHZ_BW_MASK)
381 (*cellPtr)->supportedBandwidthUl = BW_5MHZ;
383 else if((value & FAPI_10MHZ_BW_MASK) == FAPI_10MHZ_BW_MASK)
385 (*cellPtr)->supportedBandwidthUl = BW_10MHZ;
387 else if((value & FAPI_15MHZ_BW_MASK) == FAPI_15MHZ_BW_MASK)
389 (*cellPtr)->supportedBandwidthUl = BW_15MHZ;
391 else if((value & FAPI_20MHZ_BW_MASK) == FAPI_20MHZ_BW_MASK)
393 (*cellPtr)->supportedBandwidthUl = BW_20MHZ;
395 else if((value & FAPI_40MHZ_BW_MASK) == FAPI_40MHZ_BW_MASK)
397 (*cellPtr)->supportedBandwidthUl = BW_40MHZ;
399 else if((value & FAPI_50MHZ_BW_MASK) == FAPI_50MHZ_BW_MASK)
401 (*cellPtr)->supportedBandwidthUl = BW_50MHZ;
403 else if((value & FAPI_60MHZ_BW_MASK) == FAPI_60MHZ_BW_MASK)
405 (*cellPtr)->supportedBandwidthUl = BW_60MHZ;
407 else if((value & FAPI_70MHZ_BW_MASK) == FAPI_70MHZ_BW_MASK)
409 (*cellPtr)->supportedBandwidthUl = BW_70MHZ;
411 else if((value & FAPI_80MHZ_BW_MASK) == FAPI_80MHZ_BW_MASK)
413 (*cellPtr)->supportedBandwidthUl = BW_80MHZ;
415 else if((value & FAPI_90MHZ_BW_MASK) == FAPI_90MHZ_BW_MASK)
417 (*cellPtr)->supportedBandwidthUl = BW_90MHZ;
419 else if((value & FAPI_100MHZ_BW_MASK) == FAPI_100MHZ_BW_MASK)
421 (*cellPtr)->supportedBandwidthUl = BW_100MHZ;
423 else if((value & FAPI_200MHZ_BW_MASK) == FAPI_200MHZ_BW_MASK)
425 (*cellPtr)->supportedBandwidthUl = BW_200MHZ;
427 else if((value & FAPI_400MHZ_BW_MASK) == FAPI_400MHZ_BW_MASK)
429 (*cellPtr)->supportedBandwidthUl = BW_400MHZ;
433 (*cellPtr)->supportedBandwidthUl = INVALID_VALUE;
436 /*******************************************************************
438 * @brief fills the CCE maping by comparing the bitmask
442 * Function : fillCCEmaping
445 * -checks the value with the bitmask and
446 * fills the cellPtr's CCE Mapping Type
449 * @params[in] Pointer to ClCellParam
450 * Value to be compared
453 * ****************************************************************/
455 void fillCCEmaping(uint8_t value, ClCellParam **cellPtr)
457 if ((value & FAPI_CCE_MAPPING_INTERLEAVED_MASK) == FAPI_CCE_MAPPING_INTERLEAVED_MASK)
459 (*cellPtr)->cceMappingType = CCE_MAPPING_INTERLEAVED_MASK;
461 else if((value & FAPI_CCE_MAPPING_INTERLEAVED_MASK) == FAPI_CCE_MAPPING_NONINTERLVD_MASK)
463 (*cellPtr)->cceMappingType = CCE_MAPPING_NONINTERLVD_MASK;
467 (*cellPtr)->cceMappingType = INVALID_VALUE;
471 /*******************************************************************
473 * @brief fills the PUCCH format by comparing the bitmask
477 * Function : fillPucchFormat
480 * -checks the value with the bitmask and
481 * fills the cellPtr's pucch format
484 * @params[in] Pointer to ClCellParam
485 * Value to be compared
488 * ****************************************************************/
490 void fillPucchFormat(uint8_t value, ClCellParam **cellPtr)
492 if((value & FAPI_FORMAT_0_MASK) == FAPI_FORMAT_0_MASK)
494 (*cellPtr)->pucchFormats = FORMAT_0;
496 else if((value & FAPI_FORMAT_1_MASK) == FAPI_FORMAT_1_MASK)
498 (*cellPtr)->pucchFormats = FORMAT_1;
500 else if((value & FAPI_FORMAT_2_MASK) == FAPI_FORMAT_2_MASK)
502 (*cellPtr)->pucchFormats = FORMAT_2;
504 else if((value & FAPI_FORMAT_3_MASK) == FAPI_FORMAT_3_MASK)
506 (*cellPtr)->pucchFormats = FORMAT_3;
508 else if((value & FAPI_FORMAT_4_MASK) == FAPI_FORMAT_4_MASK)
510 (*cellPtr)->pucchFormats = FORMAT_4;
514 (*cellPtr)->pucchFormats = INVALID_VALUE;
518 /*******************************************************************
520 * @brief fills the PDSCH Mapping Type by comparing the bitmask
524 * Function : fillPdschMappingType
527 * -checks the value with the bitmask and
528 * fills the cellPtr's PDSCH MappingType
530 * @params[in] Pointer to ClCellParam
531 * Value to be compared
534 * ****************************************************************/
536 void fillPdschMappingType(uint8_t value, ClCellParam **cellPtr)
538 if((value & FAPI_PDSCH_MAPPING_TYPE_A_MASK) == FAPI_PDSCH_MAPPING_TYPE_A_MASK)
540 (*cellPtr)->pdschMappingType = MAPPING_TYPE_A;
542 else if((value & FAPI_PDSCH_MAPPING_TYPE_B_MASK) == FAPI_PDSCH_MAPPING_TYPE_B_MASK)
544 (*cellPtr)->pdschMappingType = MAPPING_TYPE_B;
548 (*cellPtr)->pdschMappingType = INVALID_VALUE;
552 /*******************************************************************
554 * @brief fills the PDSCH Allocation Type by comparing the bitmask
558 * Function : fillPdschAllocationType
561 * -checks the value with the bitmask and
562 * fills the cellPtr's PDSCH AllocationType
564 * @params[in] Pointer to ClCellParam
565 * Value to be compared
568 * ****************************************************************/
570 void fillPdschAllocationType(uint8_t value, ClCellParam **cellPtr)
572 if((value & FAPI_PDSCH_ALLOC_TYPE_0_MASK) == FAPI_PDSCH_ALLOC_TYPE_0_MASK)
574 (*cellPtr)->pdschAllocationTypes = ALLOCATION_TYPE_0;
576 else if((value & FAPI_PDSCH_ALLOC_TYPE_1_MASK) == FAPI_PDSCH_ALLOC_TYPE_1_MASK)
578 (*cellPtr)->pdschAllocationTypes = ALLOCATION_TYPE_1;
582 (*cellPtr)->pdschAllocationTypes = INVALID_VALUE;
586 /*******************************************************************
588 * @brief fills the PDSCH PRB Mapping Type by comparing the bitmask
592 * Function : fillPrbMappingType
595 * -checks the value with the bitmask and
596 * fills the cellPtr's PRB Mapping Type
598 * @params[in] Pointer to ClCellParam
599 * Value to be compared
602 ******************************************************************/
603 void fillPrbMappingType(uint8_t value, ClCellParam **cellPtr)
605 if((value & FAPI_PDSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK) == FAPI_PDSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK)
607 (*cellPtr)->pdschVrbToPrbMapping = VRB_TO_PRB_MAP_NON_INTLV;
609 else if((value & FAPI_PDSCH_VRB_TO_PRB_MAP_INTLVD_MASK) == FAPI_PDSCH_VRB_TO_PRB_MAP_INTLVD_MASK)
611 (*cellPtr)->pdschVrbToPrbMapping = VRB_TO_PRB_MAP_INTLVD;
615 (*cellPtr)->pdschVrbToPrbMapping = INVALID_VALUE;
619 /*******************************************************************
621 * @brief fills the PDSCH DmrsConfig Type by comparing the bitmask
625 * Function : fillPdschDmrsConfigType
628 * -checks the value with the bitmask and
629 * fills the cellPtr's DmrsConfig Type
631 * @params[in] Pointer to ClCellParam
632 * Value to be compared
635 ******************************************************************/
637 void fillPdschDmrsConfigType(uint8_t value, ClCellParam **cellPtr)
639 if((value & FAPI_PDSCH_DMRS_CONFIG_TYPE_1_MASK) == FAPI_PDSCH_DMRS_CONFIG_TYPE_1_MASK)
641 (*cellPtr)->pdschDmrsConfigTypes = DMRS_CONFIG_TYPE_1;
643 else if((value & FAPI_PDSCH_DMRS_CONFIG_TYPE_2_MASK) == FAPI_PDSCH_DMRS_CONFIG_TYPE_2_MASK)
645 (*cellPtr)->pdschDmrsConfigTypes = DMRS_CONFIG_TYPE_2;
649 (*cellPtr)->pdschDmrsConfigTypes = INVALID_VALUE;
653 /*******************************************************************
655 * @brief fills the PDSCH DmrsLength by comparing the bitmask
659 * Function : fillPdschDmrsLength
662 * -checks the value with the bitmask and
663 * fills the cellPtr's PdschDmrsLength
665 * @params[in] Pointer to ClCellParam
666 * Value to be compared
669 ******************************************************************/
670 void fillPdschDmrsLength(uint8_t value, ClCellParam **cellPtr)
672 if(value == FAPI_PDSCH_DMRS_MAX_LENGTH_1)
674 (*cellPtr)->pdschDmrsMaxLength = DMRS_MAX_LENGTH_1;
676 else if(value == FAPI_PDSCH_DMRS_MAX_LENGTH_2)
678 (*cellPtr)->pdschDmrsMaxLength = DMRS_MAX_LENGTH_2;
682 (*cellPtr)->pdschDmrsMaxLength = INVALID_VALUE;
686 /*******************************************************************
688 * @brief fills the PDSCH Dmrs Additional Pos by comparing the bitmask
692 * Function : fillPdschDmrsAddPos
695 * -checks the value with the bitmask and
696 * fills the cellPtr's Pdsch DmrsAddPos
698 * @params[in] Pointer to ClCellParam
699 * Value to be compared
702 ******************************************************************/
704 void fillPdschDmrsAddPos(uint8_t value, ClCellParam **cellPtr)
706 if((value & FAPI_DMRS_ADDITIONAL_POS_0_MASK) == FAPI_DMRS_ADDITIONAL_POS_0_MASK)
708 (*cellPtr)->pdschDmrsAdditionalPos = DMRS_ADDITIONAL_POS_0;
710 else if((value & FAPI_DMRS_ADDITIONAL_POS_1_MASK) == FAPI_DMRS_ADDITIONAL_POS_1_MASK)
712 (*cellPtr)->pdschDmrsAdditionalPos = DMRS_ADDITIONAL_POS_1;
714 else if((value & FAPI_DMRS_ADDITIONAL_POS_2_MASK) == FAPI_DMRS_ADDITIONAL_POS_2_MASK)
716 (*cellPtr)->pdschDmrsAdditionalPos = DMRS_ADDITIONAL_POS_2;
718 else if((value & FAPI_DMRS_ADDITIONAL_POS_3_MASK) == FAPI_DMRS_ADDITIONAL_POS_3_MASK)
720 (*cellPtr)->pdschDmrsAdditionalPos = DMRS_ADDITIONAL_POS_3;
724 (*cellPtr)->pdschDmrsAdditionalPos = INVALID_VALUE;
728 /*******************************************************************
730 * @brief fills the Modulation Order in DL by comparing the bitmask
734 * Function : fillModulationOrderDl
737 * -checks the value with the bitmask and
738 * fills the cellPtr's ModulationOrder in DL.
740 * @params[in] Pointer to ClCellParam
741 * Value to be compared
744 ******************************************************************/
745 void fillModulationOrderDl(uint8_t value, ClCellParam **cellPtr)
749 (*cellPtr)->supportedMaxModulationOrderDl = MOD_QPSK;
753 (*cellPtr)->supportedMaxModulationOrderDl = MOD_16QAM;
757 (*cellPtr)->supportedMaxModulationOrderDl = MOD_64QAM;
761 (*cellPtr)->supportedMaxModulationOrderDl = MOD_256QAM;
765 (*cellPtr)->supportedMaxModulationOrderDl = INVALID_VALUE;
769 /*******************************************************************
771 * @brief fills the PUSCH DmrsConfig Type by comparing the bitmask
775 * Function : fillPuschDmrsConfigType
778 * -checks the value with the bitmask and
779 * fills the cellPtr's PUSCH DmrsConfigType
781 * @params[in] Pointer to ClCellParam
782 * Value to be compared
785 ******************************************************************/
787 void fillPuschDmrsConfig(uint8_t value, ClCellParam **cellPtr)
789 if((value & FAPI_PUSCH_DMRS_CONFIG_TYPE_1_MASK) == FAPI_PUSCH_DMRS_CONFIG_TYPE_1_MASK)
791 (*cellPtr)->puschDmrsConfigTypes = DMRS_CONFIG_TYPE_1;
793 else if((value & FAPI_PUSCH_DMRS_CONFIG_TYPE_2_MASK) == FAPI_PUSCH_DMRS_CONFIG_TYPE_2_MASK)
795 (*cellPtr)->puschDmrsConfigTypes = DMRS_CONFIG_TYPE_2;
799 (*cellPtr)->puschDmrsConfigTypes = INVALID_VALUE;
803 /*******************************************************************
805 * @brief fills the PUSCH DmrsLength by comparing the bitmask
809 * Function : fillPuschDmrsLength
812 * -checks the value with the bitmask and
813 * fills the cellPtr's PUSCH DmrsLength
815 * @params[in] Pointer to ClCellParam
816 * Value to be compared
819 ******************************************************************/
821 void fillPuschDmrsLength(uint8_t value, ClCellParam **cellPtr)
823 if(value == FAPI_PUSCH_DMRS_MAX_LENGTH_1)
825 (*cellPtr)->puschDmrsMaxLength = DMRS_MAX_LENGTH_1;
827 else if(value == FAPI_PUSCH_DMRS_MAX_LENGTH_2)
829 (*cellPtr)->puschDmrsMaxLength = DMRS_MAX_LENGTH_2;
833 (*cellPtr)->puschDmrsMaxLength = INVALID_VALUE;
837 /*******************************************************************
839 * @brief fills the PUSCH Dmrs Additional position by comparing the bitmask
843 * Function : fillPuschDmrsAddPos
846 * -checks the value with the bitmask and
847 * fills the cellPtr's PUSCH DmrsAddPos
849 * @params[in] Pointer to ClCellParam
850 * Value to be compared
853 ******************************************************************/
855 void fillPuschDmrsAddPos(uint8_t value, ClCellParam **cellPtr)
857 if((value & FAPI_DMRS_ADDITIONAL_POS_0_MASK) == FAPI_DMRS_ADDITIONAL_POS_0_MASK)
859 (*cellPtr)->puschDmrsAdditionalPos = DMRS_ADDITIONAL_POS_0;
861 else if((value & FAPI_DMRS_ADDITIONAL_POS_1_MASK) == FAPI_DMRS_ADDITIONAL_POS_1_MASK)
863 (*cellPtr)->puschDmrsAdditionalPos = DMRS_ADDITIONAL_POS_1;
865 else if((value & FAPI_DMRS_ADDITIONAL_POS_2_MASK) == FAPI_DMRS_ADDITIONAL_POS_2_MASK)
867 (*cellPtr)->puschDmrsAdditionalPos = DMRS_ADDITIONAL_POS_2;
869 else if((value & FAPI_DMRS_ADDITIONAL_POS_3_MASK) == FAPI_DMRS_ADDITIONAL_POS_3_MASK)
871 (*cellPtr)->puschDmrsAdditionalPos = DMRS_ADDITIONAL_POS_3;
875 (*cellPtr)->puschDmrsAdditionalPos = INVALID_VALUE;
879 /*******************************************************************
881 * @brief fills the PUSCH Mapping Type by comparing the bitmask
885 * Function : fillPuschMappingType
888 * -checks the value with the bitmask and
889 * fills the cellPtr's PUSCH MappingType
891 * @params[in] Pointer to ClCellParam
892 * Value to be compared
895 ******************************************************************/
897 void fillPuschMappingType(uint8_t value, ClCellParam **cellPtr)
899 if((value & FAPI_PUSCH_MAPPING_TYPE_A_MASK) == FAPI_PUSCH_MAPPING_TYPE_A_MASK)
901 (*cellPtr)->puschMappingType = MAPPING_TYPE_A;
903 else if((value & FAPI_PUSCH_MAPPING_TYPE_B_MASK) == FAPI_PUSCH_MAPPING_TYPE_B_MASK)
905 (*cellPtr)->puschMappingType = MAPPING_TYPE_B;
909 (*cellPtr)->puschMappingType = INVALID_VALUE;
913 /*******************************************************************
915 * @brief fills the PUSCH Allocation Type by comparing the bitmask
919 * Function : fillPuschAllocationType
922 * -checks the value with the bitmask and
923 * fills the cellPtr's PUSCH AllocationType
925 * @params[in] Pointer to ClCellParam
926 * Value to be compared
929 ******************************************************************/
931 void fillPuschAllocationType(uint8_t value, ClCellParam **cellPtr)
933 if((value & FAPI_PUSCH_ALLOC_TYPE_0_MASK) == FAPI_PUSCH_ALLOC_TYPE_0_MASK)
935 (*cellPtr)->puschAllocationTypes = ALLOCATION_TYPE_0;
937 else if((value & FAPI_PUSCH_ALLOC_TYPE_0_MASK) == FAPI_PUSCH_ALLOC_TYPE_0_MASK)
939 (*cellPtr)->puschAllocationTypes = ALLOCATION_TYPE_1;
943 (*cellPtr)->puschAllocationTypes = INVALID_VALUE;
947 /*******************************************************************
949 * @brief fills the PUSCH PRB Mapping Type by comparing the bitmask
953 * Function : fillPuschPrbMappingType
956 * -checks the value with the bitmask and
957 * fills the cellPtr's PUSCH PRB MApping Type
959 * @params[in] Pointer to ClCellParam
960 * Value to be compared
963 ******************************************************************/
965 void fillPuschPrbMappingType(uint8_t value, ClCellParam **cellPtr)
967 if((value & FAPI_PUSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK) == FAPI_PUSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK)
969 (*cellPtr)->puschVrbToPrbMapping = VRB_TO_PRB_MAP_NON_INTLV;
971 else if((value & FAPI_PUSCH_VRB_TO_PRB_MAP_INTLVD_MASK) == FAPI_PUSCH_VRB_TO_PRB_MAP_INTLVD_MASK)
973 (*cellPtr)->puschVrbToPrbMapping = VRB_TO_PRB_MAP_INTLVD;
977 (*cellPtr)->puschVrbToPrbMapping = INVALID_VALUE;
981 /*******************************************************************
983 * @brief fills the Modulation Order in Ul by comparing the bitmask
987 * Function : fillModulationOrderUl
990 * -checks the value with the bitmask and
991 * fills the cellPtr's Modualtsion Order in UL.
993 * @params[in] Pointer to ClCellParam
994 * Value to be compared
997 ******************************************************************/
999 void fillModulationOrderUl(uint8_t value, ClCellParam **cellPtr)
1003 (*cellPtr)->supportedModulationOrderUl = MOD_QPSK;
1007 (*cellPtr)->supportedModulationOrderUl = MOD_16QAM;
1011 (*cellPtr)->supportedModulationOrderUl = MOD_64QAM;
1015 (*cellPtr)->supportedModulationOrderUl = MOD_256QAM;
1019 (*cellPtr)->supportedModulationOrderUl = INVALID_VALUE;
1023 /*******************************************************************
1025 * @brief fills the PUSCH Aggregation Factor by comparing the bitmask
1029 * Function : fillPuschAggregationFactor
1032 * -checks the value with the bitmask and
1033 * fills the cellPtr's PUSCH Aggregation Factor
1035 * @params[in] Pointer to ClCellParam
1036 * Value to be compared
1039 ******************************************************************/
1041 void fillPuschAggregationFactor(uint8_t value, ClCellParam **cellPtr)
1043 if((value & FAPI_FORMAT_0_MASK) == FAPI_FORMAT_0_MASK)
1045 (*cellPtr)->puschAggregationFactor = AGG_FACTOR_1;
1047 else if((value & FAPI_FORMAT_1_MASK) == FAPI_FORMAT_1_MASK)
1049 (*cellPtr)->puschAggregationFactor = AGG_FACTOR_2;
1051 else if((value & FAPI_FORMAT_2_MASK) == FAPI_FORMAT_2_MASK)
1053 (*cellPtr)->puschAggregationFactor = AGG_FACTOR_4;
1055 else if((value & FAPI_FORMAT_3_MASK) == FAPI_FORMAT_3_MASK)
1057 (*cellPtr)->puschAggregationFactor = AGG_FACTOR_8;
1061 (*cellPtr)->puschAggregationFactor = INVALID_VALUE;
1065 /*******************************************************************
1067 * @brief fills the PRACH Long Format by comparing the bitmask
1071 * Function : fillPrachLongFormat
1074 * -checks the value with the bitmask and
1075 * fills the cellPtr's PRACH Long Format
1077 * @params[in] Pointer to ClCellParam
1078 * Value to be compared
1081 ******************************************************************/
1083 void fillPrachLongFormat(uint8_t value, ClCellParam **cellPtr)
1085 if((value & FAPI_PRACH_LF_FORMAT_0_MASK) == FAPI_PRACH_LF_FORMAT_0_MASK)
1087 (*cellPtr)->prachLongFormats = FORMAT_0;
1089 else if((value & FAPI_PRACH_LF_FORMAT_1_MASK) == FAPI_PRACH_LF_FORMAT_1_MASK)
1091 (*cellPtr)->prachLongFormats = FORMAT_1;
1093 else if((value & FAPI_PRACH_LF_FORMAT_2_MASK) == FAPI_PRACH_LF_FORMAT_2_MASK)
1095 (*cellPtr)->prachLongFormats = FORMAT_2;
1097 else if((value & FAPI_PRACH_LF_FORMAT_3_MASK) == FAPI_PRACH_LF_FORMAT_3_MASK)
1099 (*cellPtr)->prachLongFormats = FORMAT_3;
1103 (*cellPtr)->prachLongFormats = INVALID_VALUE;
1107 /*******************************************************************
1109 * @brief fills the PRACH Short Format by comparing the bitmask
1113 * Function : fillPrachShortFormat
1116 * -checks the value with the bitmask and
1117 * fills the cellPtr's PRACH ShortFormat
1119 * @params[in] Pointer to ClCellParam
1120 * Value to be compared
1123 ******************************************************************/
1125 void fillPrachShortFormat(uint8_t value, ClCellParam **cellPtr)
1127 if((value & FAPI_PRACH_SF_FORMAT_A1_MASK) == FAPI_PRACH_SF_FORMAT_A1_MASK)
1129 (*cellPtr)->prachShortFormats = SF_FORMAT_A1;
1131 else if((value & FAPI_PRACH_SF_FORMAT_A2_MASK) == FAPI_PRACH_SF_FORMAT_A2_MASK)
1133 (*cellPtr)->prachShortFormats = SF_FORMAT_A2;
1135 else if((value & FAPI_PRACH_SF_FORMAT_A3_MASK) == FAPI_PRACH_SF_FORMAT_A3_MASK)
1137 (*cellPtr)->prachShortFormats = SF_FORMAT_A3;
1139 else if((value & FAPI_PRACH_SF_FORMAT_B1_MASK) == FAPI_PRACH_SF_FORMAT_B1_MASK)
1141 (*cellPtr)->prachShortFormats = SF_FORMAT_B1;
1143 else if((value & FAPI_PRACH_SF_FORMAT_B2_MASK) == FAPI_PRACH_SF_FORMAT_B2_MASK)
1145 (*cellPtr)->prachShortFormats = SF_FORMAT_B2;
1147 else if((value & FAPI_PRACH_SF_FORMAT_B3_MASK) == FAPI_PRACH_SF_FORMAT_B3_MASK)
1149 (*cellPtr)->prachShortFormats = SF_FORMAT_B3;
1151 else if((value & FAPI_PRACH_SF_FORMAT_B4_MASK) == FAPI_PRACH_SF_FORMAT_B4_MASK)
1153 (*cellPtr)->prachShortFormats = SF_FORMAT_B4;
1155 else if((value & FAPI_PRACH_SF_FORMAT_C0_MASK) == FAPI_PRACH_SF_FORMAT_C0_MASK)
1157 (*cellPtr)->prachShortFormats = SF_FORMAT_C0;
1159 else if((value & FAPI_PRACH_SF_FORMAT_C2_MASK) == FAPI_PRACH_SF_FORMAT_C2_MASK)
1161 (*cellPtr)->prachShortFormats = SF_FORMAT_C2;
1165 (*cellPtr)->prachShortFormats = INVALID_VALUE;
1169 /*******************************************************************
1171 * @brief fills the Fd Occasions Type by comparing the bitmask
1175 * Function : fillFdOccasions
1178 * -checks the value with the bitmask and
1179 * fills the cellPtr's Fd Occasions
1181 * @params[in] Pointer to ClCellParam
1182 * Value to be compared
1185 ******************************************************************/
1187 void fillFdOccasions(uint8_t value, ClCellParam **cellPtr)
1191 (*cellPtr)->maxPrachFdOccasionsInASlot = PRACH_FD_OCC_IN_A_SLOT_1;
1195 (*cellPtr)->maxPrachFdOccasionsInASlot = PRACH_FD_OCC_IN_A_SLOT_2;
1199 (*cellPtr)->maxPrachFdOccasionsInASlot = PRACH_FD_OCC_IN_A_SLOT_4;
1203 (*cellPtr)->maxPrachFdOccasionsInASlot = PRACH_FD_OCC_IN_A_SLOT_8;
1207 (*cellPtr)->maxPrachFdOccasionsInASlot = INVALID_VALUE;
1211 /*******************************************************************
1213 * @brief fills the RSSI Measurement by comparing the bitmask
1217 * Function : fillRssiMeas
1220 * -checks the value with the bitmask and
1221 * fills the cellPtr's RSSI Measurement report
1223 * @params[in] Pointer to ClCellParam
1224 * Value to be compared
1227 ******************************************************************/
1229 void fillRssiMeas(uint8_t value, ClCellParam **cellPtr)
1231 if((value & FAPI_RSSI_REPORT_IN_DBM_MASK) == FAPI_RSSI_REPORT_IN_DBM_MASK)
1233 (*cellPtr)->rssiMeasurementSupport = RSSI_REPORT_DBM;
1235 else if((value & FAPI_RSSI_REPORT_IN_DBFS_MASK) == FAPI_RSSI_REPORT_IN_DBFS_MASK)
1237 (*cellPtr)->rssiMeasurementSupport = RSSI_REPORT_DBFS;
1241 (*cellPtr)->rssiMeasurementSupport = INVALID_VALUE;
1245 /*******************************************************************
1247 * @brief Returns the TLVs value
1251 * Function : getParamValue
1254 * -return TLVs value
1257 * @return ROK - temp
1260 * ****************************************************************/
1262 uint32_t getParamValue(fapi_uint16_tlv_t *tlv, uint16_t type)
1265 posPtr = &tlv->tl.tag;
1266 posPtr += sizeof(tlv->tl.tag);
1267 posPtr += sizeof(tlv->tl.length);
1268 /*TO DO: malloc to SSI memory */
1269 if(type == FAPI_UINT_8)
1271 return(*(uint8_t *)posPtr);
1273 else if(type == FAPI_UINT_16)
1275 return(*(uint16_t *)posPtr);
1277 else if(type == FAPI_UINT_32)
1279 return(*(uint32_t *)posPtr);
1283 DU_LOG("\nERROR --> LWR_MAC: Value Extraction failed" );
1289 /*******************************************************************
1291 * @brief Modifes the received mibPdu to uint32 bit
1292 * and stores it in MacCellCfg
1296 * Function : setMibPdu
1301 * @params[in] Pointer to mibPdu
1302 * pointer to modified value
1303 ******************************************************************/
1304 void setMibPdu(uint8_t *mibPdu, uint32_t *val, uint16_t sfn)
1306 *mibPdu |= (((uint8_t)(sfn << 2)) & MIB_SFN_BITMASK);
1307 *val = (mibPdu[0] << 24 | mibPdu[1] << 16 | mibPdu[2] << 8);
1308 DU_LOG("\nDEBUG --> LWR_MAC: MIB PDU %x", *val);
1311 /*******************************************************************
1313 * @brief Sends FAPI Param req to PHY
1317 * Function : lwr_mac_procParamReqEvt
1320 * -Sends FAPI Param req to PHY
1323 * @return ROK - success
1326 * ****************************************************************/
1328 uint8_t lwr_mac_procParamReqEvt(void *msg)
1331 #ifdef CALL_FLOW_DEBUG_LOG
1332 DU_LOG("\nCall Flow: ENTMAC -> ENTLWRMAC : PARAM_REQ\n");
1335 /* startGuardTimer(); */
1336 fapi_param_req_t *paramReq = NULL;
1337 fapi_msg_header_t *msgHeader;
1338 p_fapi_api_queue_elem_t paramReqElem;
1339 p_fapi_api_queue_elem_t headerElem;
1341 LWR_MAC_ALLOC(paramReqElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_param_req_t)));
1342 if(paramReq != NULL)
1344 FILL_FAPI_LIST_ELEM(paramReqElem, NULLP, FAPI_PARAM_REQUEST, 1, \
1345 sizeof(fapi_tx_data_req_t));
1346 paramReq = (fapi_param_req_t *)(paramReqElem +1);
1347 memset(paramReq, 0, sizeof(fapi_param_req_t));
1348 fillMsgHeader(¶mReq->header, FAPI_PARAM_REQUEST, sizeof(fapi_param_req_t));
1350 /* Fill message header */
1351 LWR_MAC_ALLOC(headerElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_msg_header_t)));
1354 DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for param req header");
1355 LWR_MAC_FREE(paramReqElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_param_req_t)));
1358 FILL_FAPI_LIST_ELEM(headerElem, paramReqElem, FAPI_VENDOR_MSG_HEADER_IND, 1, \
1359 sizeof(fapi_msg_header_t));
1360 msgHeader = (fapi_msg_header_t *)(headerElem + 1);
1361 msgHeader->num_msg = 1;
1362 msgHeader->handle = 0;
1364 DU_LOG("\nDEBUG --> LWR_MAC: Sending Param Request to Phy");
1365 LwrMacSendToL1(headerElem);
1369 DU_LOG("\nERROR --> LWR_MAC: Failed to allocate memory for Param Request");
1376 /*******************************************************************
1378 * @brief Sends FAPI Param Response to MAC via PHY
1382 * Function : lwr_mac_procParamRspEvt
1385 * -Sends FAPI Param rsp to MAC via PHY
1388 * @return ROK - success
1391 * ****************************************************************/
1393 uint8_t lwr_mac_procParamRspEvt(void *msg)
1396 /* stopGuardTimer(); */
1398 uint32_t encodedVal;
1399 fapi_param_resp_t *paramRsp;
1400 ClCellParam *cellParam = NULLP;
1402 paramRsp = (fapi_param_resp_t *)msg;
1403 DU_LOG("\nINFO --> LWR_MAC: Received EVENT[%d] at STATE[%d]", lwrMacCb.event, lwrMacCb.phyState);
1405 if(paramRsp != NULLP)
1407 MAC_ALLOC(cellParam, sizeof(ClCellParam));
1408 if(cellParam != NULLP)
1410 DU_LOG("\nDEBUG --> LWR_MAC: Filling TLVS into MAC API");
1411 if(paramRsp->error_code == MSG_OK)
1413 for(index = 0; index < paramRsp->number_of_tlvs; index++)
1415 switch(paramRsp->tlvs[index].tl.tag)
1417 case FAPI_RELEASE_CAPABILITY_TAG:
1418 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_16);
1419 if(encodedVal != RFAILED && (encodedVal & RELEASE_15) == RELEASE_15)
1421 cellParam->releaseCapability = RELEASE_15;
1425 case FAPI_PHY_STATE_TAG:
1426 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1427 if(encodedVal != RFAILED && encodedVal != lwrMacCb.phyState)
1429 DU_LOG("\nERROR --> PhyState mismatch [%d][%d]", lwrMacCb.phyState, lwrMacCb.event);
1434 case FAPI_SKIP_BLANK_DL_CONFIG_TAG:
1435 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1436 if(encodedVal != RFAILED && encodedVal != 0)
1438 cellParam->skipBlankDlConfig = SUPPORTED;
1442 cellParam->skipBlankDlConfig = NOT_SUPPORTED;
1446 case FAPI_SKIP_BLANK_UL_CONFIG_TAG:
1447 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1448 if(encodedVal != RFAILED && encodedVal != 0)
1450 cellParam->skipBlankUlConfig = SUPPORTED;
1454 cellParam->skipBlankUlConfig = NOT_SUPPORTED;
1458 case FAPI_NUM_CONFIG_TLVS_TO_REPORT_TYPE_TAG:
1459 cellParam->numTlvsToReport = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_16);
1462 case FAPI_CYCLIC_PREFIX_TAG:
1463 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1464 if(encodedVal != RFAILED)
1466 fillCyclicPrefix(encodedVal, &cellParam);
1470 case FAPI_SUPPORTED_SUBCARRIER_SPACING_DL_TAG:
1471 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1472 if(encodedVal != RFAILED)
1474 fillSubcarrierSpaceDl(encodedVal, &cellParam);
1478 case FAPI_SUPPORTED_BANDWIDTH_DL_TAG:
1479 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_16);
1480 if(encodedVal != RFAILED)
1482 fillBandwidthDl(encodedVal, &cellParam);
1486 case FAPI_SUPPORTED_SUBCARRIER_SPACING_UL_TAG:
1487 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1488 if(encodedVal != RFAILED)
1490 fillSubcarrierSpaceUl(encodedVal, &cellParam);
1494 case FAPI_SUPPORTED_BANDWIDTH_UL_TAG:
1495 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_16);
1496 if(encodedVal != RFAILED)
1498 fillBandwidthUl(encodedVal, &cellParam);
1502 case FAPI_CCE_MAPPING_TYPE_TAG:
1503 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1504 if(encodedVal != RFAILED)
1506 fillCCEmaping(encodedVal, &cellParam);
1510 case FAPI_CORESET_OUTSIDE_FIRST_3_OFDM_SYMS_OF_SLOT_TAG:
1511 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1512 if(encodedVal != RFAILED && encodedVal != 0)
1514 cellParam->coresetOutsideFirst3OfdmSymsOfSlot = SUPPORTED;
1518 cellParam->coresetOutsideFirst3OfdmSymsOfSlot = NOT_SUPPORTED;
1522 case FAPI_PRECODER_GRANULARITY_CORESET_TAG:
1523 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1524 if(encodedVal != RFAILED && encodedVal != 0)
1526 cellParam->precoderGranularityCoreset = SUPPORTED;
1530 cellParam->precoderGranularityCoreset = NOT_SUPPORTED;
1534 case FAPI_PDCCH_MU_MIMO_TAG:
1535 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1536 if(encodedVal != RFAILED && encodedVal != 0)
1538 cellParam->pdcchMuMimo = SUPPORTED;
1542 cellParam->pdcchMuMimo = NOT_SUPPORTED;
1546 case FAPI_PDCCH_PRECODER_CYCLING_TAG:
1547 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1548 if(encodedVal != RFAILED && encodedVal != 0)
1550 cellParam->pdcchPrecoderCycling = SUPPORTED;
1554 cellParam->pdcchPrecoderCycling = NOT_SUPPORTED;
1558 case FAPI_MAX_PDCCHS_PER_SLOT_TAG:
1559 cellParam->maxPdcchsPerSlot = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1562 case FAPI_PUCCH_FORMATS_TAG:
1563 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1564 if(encodedVal != RFAILED)
1566 fillPucchFormat(encodedVal, &cellParam);
1570 case FAPI_MAX_PUCCHS_PER_SLOT_TAG:
1571 cellParam->maxPucchsPerSlot = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1574 case FAPI_PDSCH_MAPPING_TYPE_TAG:
1575 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1576 if(encodedVal != RFAILED)
1578 fillPdschMappingType(encodedVal, &cellParam);
1582 case FAPI_PDSCH_ALLOCATION_TYPES_TAG:
1583 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1584 if(encodedVal != RFAILED)
1586 fillPdschAllocationType(encodedVal, &cellParam);
1590 case FAPI_PDSCH_VRB_TO_PRB_MAPPING_TAG:
1591 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1592 if(encodedVal != RFAILED)
1594 fillPrbMappingType(encodedVal, &cellParam);
1598 case FAPI_PDSCH_CBG_TAG:
1599 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1600 if(encodedVal != RFAILED && encodedVal != 0)
1602 cellParam->pdschCbg = SUPPORTED;
1606 cellParam->pdschCbg = NOT_SUPPORTED;
1610 case FAPI_PDSCH_DMRS_CONFIG_TYPES_TAG:
1611 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1612 if(encodedVal != RFAILED)
1614 fillPdschDmrsConfigType(encodedVal, &cellParam);
1618 case FAPI_PDSCH_DMRS_MAX_LENGTH_TAG:
1619 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1620 if(encodedVal != RFAILED)
1622 fillPdschDmrsLength(encodedVal, &cellParam);
1626 case FAPI_PDSCH_DMRS_ADDITIONAL_POS_TAG:
1627 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1628 if(encodedVal != RFAILED)
1630 fillPdschDmrsAddPos(encodedVal, &cellParam);
1634 case FAPI_MAX_PDSCHS_TBS_PER_SLOT_TAG:
1635 cellParam->maxPdschsTBsPerSlot = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1638 case FAPI_MAX_NUMBER_MIMO_LAYERS_PDSCH_TAG:
1639 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1640 if(encodedVal != RFAILED && encodedVal < FAPI_MAX_NUMBERMIMO_LAYERS_PDSCH)
1642 cellParam->maxNumberMimoLayersPdsch = encodedVal;
1646 case FAPI_SUPPORTED_MAX_MODULATION_ORDER_DL_TAG:
1647 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1648 if(encodedVal != RFAILED)
1650 fillModulationOrderDl(encodedVal, &cellParam);
1654 case FAPI_MAX_MU_MIMO_USERS_DL_TAG:
1655 cellParam->maxMuMimoUsersDl = \
1656 getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1659 case FAPI_PDSCH_DATA_IN_DMRS_SYMBOLS_TAG:
1660 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1661 if(encodedVal != RFAILED && encodedVal != 0)
1663 cellParam->pdschDataInDmrsSymbols = SUPPORTED;
1667 cellParam->pdschDataInDmrsSymbols = NOT_SUPPORTED;
1671 case FAPI_PREMPTIONSUPPORT_TAG:
1672 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1673 if(encodedVal != RFAILED && encodedVal != 0)
1675 cellParam->premptionSupport = SUPPORTED;
1679 cellParam->premptionSupport = NOT_SUPPORTED;
1683 case FAPI_PDSCH_NON_SLOT_SUPPORT_TAG:
1684 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1685 if(encodedVal != RFAILED && encodedVal != 0)
1687 cellParam->pdschNonSlotSupport = SUPPORTED;
1691 cellParam->pdschNonSlotSupport = NOT_SUPPORTED;
1695 case FAPI_UCI_MUX_ULSCH_IN_PUSCH_TAG:
1696 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1697 if(encodedVal != RFAILED && encodedVal != 0)
1699 cellParam->uciMuxUlschInPusch = SUPPORTED;
1703 cellParam->uciMuxUlschInPusch = NOT_SUPPORTED;
1707 case FAPI_UCI_ONLY_PUSCH_TAG:
1708 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1709 if(encodedVal != RFAILED && encodedVal != 0)
1711 cellParam->uciOnlyPusch = SUPPORTED;
1715 cellParam->uciOnlyPusch = NOT_SUPPORTED;
1719 case FAPI_PUSCH_FREQUENCY_HOPPING_TAG:
1720 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1721 if(encodedVal != RFAILED && encodedVal != 0)
1723 cellParam->puschFrequencyHopping = SUPPORTED;
1727 cellParam->puschFrequencyHopping = NOT_SUPPORTED;
1731 case FAPI_PUSCH_DMRS_CONFIG_TYPES_TAG:
1732 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1733 if(encodedVal != RFAILED)
1735 fillPuschDmrsConfig(encodedVal, &cellParam);
1739 case FAPI_PUSCH_DMRS_MAX_LEN_TAG:
1740 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1741 if(encodedVal != RFAILED)
1743 fillPuschDmrsLength(encodedVal, &cellParam);
1747 case FAPI_PUSCH_DMRS_ADDITIONAL_POS_TAG:
1748 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1749 if(encodedVal != RFAILED)
1751 fillPuschDmrsAddPos(encodedVal, &cellParam);
1755 case FAPI_PUSCH_CBG_TAG:
1756 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1757 if(encodedVal != RFAILED && encodedVal != 0)
1759 cellParam->puschCbg = SUPPORTED;
1763 cellParam->puschCbg = NOT_SUPPORTED;
1767 case FAPI_PUSCH_MAPPING_TYPE_TAG:
1768 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1769 if(encodedVal != RFAILED)
1771 fillPuschMappingType(encodedVal, &cellParam);
1775 case FAPI_PUSCH_ALLOCATION_TYPES_TAG:
1776 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1777 if(encodedVal != RFAILED)
1779 fillPuschAllocationType(encodedVal, &cellParam);
1783 case FAPI_PUSCH_VRB_TO_PRB_MAPPING_TAG:
1784 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1785 if(encodedVal != RFAILED)
1787 fillPuschPrbMappingType(encodedVal, &cellParam);
1791 case FAPI_PUSCH_MAX_PTRS_PORTS_TAG:
1792 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1793 if(encodedVal != RFAILED && encodedVal < FAPI_PUSCH_MAX_PTRS_PORTS_UB)
1795 cellParam->puschMaxPtrsPorts = encodedVal;
1799 case FAPI_MAX_PDUSCHS_TBS_PER_SLOT_TAG:
1800 cellParam->maxPduschsTBsPerSlot = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1803 case FAPI_MAX_NUMBER_MIMO_LAYERS_NON_CB_PUSCH_TAG:
1804 cellParam->maxNumberMimoLayersNonCbPusch = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1807 case FAPI_SUPPORTED_MODULATION_ORDER_UL_TAG:
1808 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1809 if(encodedVal != RFAILED)
1811 fillModulationOrderUl(encodedVal, &cellParam);
1815 case FAPI_MAX_MU_MIMO_USERS_UL_TAG:
1816 cellParam->maxMuMimoUsersUl = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1819 case FAPI_DFTS_OFDM_SUPPORT_TAG:
1820 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1821 if(encodedVal != RFAILED && encodedVal != 0)
1823 cellParam->dftsOfdmSupport = SUPPORTED;
1827 cellParam->dftsOfdmSupport = NOT_SUPPORTED;
1831 case FAPI_PUSCH_AGGREGATION_FACTOR_TAG:
1832 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1833 if(encodedVal != RFAILED)
1835 fillPuschAggregationFactor(encodedVal, &cellParam);
1839 case FAPI_PRACH_LONG_FORMATS_TAG:
1840 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1841 if(encodedVal != RFAILED)
1843 fillPrachLongFormat(encodedVal, &cellParam);
1847 case FAPI_PRACH_SHORT_FORMATS_TAG:
1848 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1849 if(encodedVal != RFAILED)
1851 fillPrachShortFormat(encodedVal, &cellParam);
1855 case FAPI_PRACH_RESTRICTED_SETS_TAG:
1856 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1857 if(encodedVal != RFAILED && encodedVal != 0)
1859 cellParam->prachRestrictedSets = SUPPORTED;
1863 cellParam->prachRestrictedSets = NOT_SUPPORTED;
1867 case FAPI_MAX_PRACH_FD_OCCASIONS_IN_A_SLOT_TAG:
1868 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1869 if(encodedVal != RFAILED)
1871 fillFdOccasions(encodedVal, &cellParam);
1875 case FAPI_RSSI_MEASUREMENT_SUPPORT_TAG:
1876 encodedVal = getParamValue(¶mRsp->tlvs[index], FAPI_UINT_8);
1877 if(encodedVal != RFAILED)
1879 fillRssiMeas(encodedVal, &cellParam);
1883 //DU_LOG("\nERROR --> Invalid value for TLV[%x] at index[%d]", paramRsp->tlvs[index].tl.tag, index);
1887 MAC_FREE(cellParam, sizeof(ClCellParam));
1888 sendToLowerMac(FAPI_CONFIG_REQUEST, 0, (void *)NULL);
1893 DU_LOG("\nERROR --> LWR_MAC: Invalid error code %d", paramRsp->error_code);
1899 DU_LOG("\nERROR --> LWR_MAC: Failed to allocate memory for cell param");
1905 DU_LOG("\nERROR --> LWR_MAC: Param Response received from PHY is NULL");
1913 #ifdef INTEL_TIMER_MODE
1914 uint8_t lwr_mac_procIqSamplesReqEvt(void *msg)
1916 void * wlsHdlr = NULLP;
1917 fapi_msg_header_t *msgHeader;
1918 fapi_vendor_ext_iq_samples_req_t *iqSampleReq;
1919 p_fapi_api_queue_elem_t headerElem;
1920 p_fapi_api_queue_elem_t iqSampleElem;
1921 char filename[100] = "/root/intel/FlexRAN/testcase/ul/mu0_20mhz/2/uliq00_prach_tst2.bin";
1923 uint8_t buffer[] ={0,0,0,0,0,2,11,0,212,93,40,0,20,137,38,0,20,0,20,0,0,8,0,8,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0,2,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,128,1,0,0,0,0,0,0,1,0,2,0,0,0,0,0,0,0,1,0};
1925 size_t bufferSize = sizeof(buffer) / sizeof(buffer[0]);
1927 /* Fill IQ sample req */
1928 mtGetWlsHdl(&wlsHdlr);
1929 //iqSampleElem = (p_fapi_api_queue_elem_t)WLS_Alloc(wlsHdlr, \
1930 (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_ext_iq_samples_req_t)));
1931 LWR_MAC_ALLOC(iqSampleElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_ext_iq_samples_req_t)));
1934 DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for IQ sample req");
1937 FILL_FAPI_LIST_ELEM(iqSampleElem, NULLP, FAPI_VENDOR_EXT_UL_IQ_SAMPLES, 1, \
1938 sizeof(fapi_vendor_ext_iq_samples_req_t));
1940 iqSampleReq = (fapi_vendor_ext_iq_samples_req_t *)(iqSampleElem + 1);
1941 memset(iqSampleReq, 0, sizeof(fapi_vendor_ext_iq_samples_req_t));
1942 fillMsgHeader(&iqSampleReq->header, FAPI_VENDOR_EXT_UL_IQ_SAMPLES, \
1943 sizeof(fapi_vendor_ext_iq_samples_req_t));
1945 iqSampleReq->iq_samples_info.carrNum = 0;
1946 iqSampleReq->iq_samples_info.numSubframes = 40;
1947 iqSampleReq->iq_samples_info.nIsRadioMode = 0;
1948 iqSampleReq->iq_samples_info.timerModeFreqDomain = 0;
1949 iqSampleReq->iq_samples_info.phaseCompensationEnable = 0;
1950 iqSampleReq->iq_samples_info.startFrameNum = 0;
1951 iqSampleReq->iq_samples_info.startSlotNum = 0;
1952 iqSampleReq->iq_samples_info.startSymNum = 0;
1953 strncpy(iqSampleReq->iq_samples_info.filename_in_ul_iq[0], filename, 100);
1954 memcpy(iqSampleReq->iq_samples_info.buffer, buffer, bufferSize);
1956 /* TODO : Fill remaining parameters */
1958 /* Fill message header */
1959 LWR_MAC_ALLOC(headerElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_msg_header_t)));
1962 DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for FAPI header in lwr_mac_procIqSamplesReqEvt");
1965 FILL_FAPI_LIST_ELEM(headerElem, iqSampleElem, FAPI_VENDOR_MSG_HEADER_IND, 1, \
1966 sizeof(fapi_msg_header_t));
1967 msgHeader = (fapi_msg_header_t *)(headerElem + 1);
1968 msgHeader->num_msg = 1;
1969 msgHeader->handle = 0;
1971 DU_LOG("\nINFO --> LWR_MAC: Sending IQ Sample request to Phy");
1972 LwrMacSendToL1(headerElem);
1977 /*******************************************************************
1979 * @brief Sends FAPI Config req to PHY
1983 * Function : lwr_mac_procConfigReqEvt
1986 * -Sends FAPI Config Req to PHY
1989 * @return ROK - success
1992 * ****************************************************************/
1994 uint8_t lwr_mac_procConfigReqEvt(void *msg)
1997 #ifdef CALL_FLOW_DEBUG_LOG
1998 DU_LOG("\nCall Flow: ENTMAC -> ENTLWRMAC : CONFIG_REQ\n");
2001 uint8_t slotIdx = 0;
2002 uint8_t symbolIdx =0;
2005 uint16_t *cellId =NULLP;
2006 uint16_t cellIdx =0;
2007 uint32_t msgLen = 0;
2009 MacCellCfg macCfgParams;
2010 fapi_vendor_msg_t *vendorMsg;
2011 fapi_config_req_t *configReq;
2012 fapi_msg_header_t *msgHeader;
2013 p_fapi_api_queue_elem_t headerElem;
2014 p_fapi_api_queue_elem_t vendorMsgQElem;
2015 p_fapi_api_queue_elem_t cfgReqQElem;
2017 DU_LOG("\nINFO --> LWR_MAC: Received EVENT[%d] at STATE[%d]", lwrMacCb.event, \
2020 cellId = (uint16_t *)msg;
2021 GET_CELL_IDX(*cellId, cellIdx);
2022 macCfgParams = macCb.macCell[cellIdx]->macCellCfg;
2024 /* Fill Cell Configuration in lwrMacCb */
2025 memset(&lwrMacCb.cellCb[lwrMacCb.numCell], 0, sizeof(LwrMacCellCb));
2026 lwrMacCb.cellCb[lwrMacCb.numCell].cellId = macCfgParams.cellId;
2027 lwrMacCb.cellCb[lwrMacCb.numCell].phyCellId = macCfgParams.phyCellId;
2030 /* Allocte And fill Vendor msg */
2031 LWR_MAC_ALLOC(vendorMsgQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
2034 DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in config req");
2037 FILL_FAPI_LIST_ELEM(vendorMsgQElem, NULLP, FAPI_VENDOR_MESSAGE, 1, sizeof(fapi_vendor_msg_t));
2038 vendorMsg = (fapi_vendor_msg_t *)(vendorMsgQElem + 1);
2039 fillMsgHeader(&vendorMsg->header, FAPI_VENDOR_MESSAGE, sizeof(fapi_vendor_msg_t));
2040 vendorMsg->config_req_vendor.hopping_id = 0;
2041 vendorMsg->config_req_vendor.carrier_aggregation_level = 0;
2042 vendorMsg->config_req_vendor.group_hop_flag = 0;
2043 vendorMsg->config_req_vendor.sequence_hop_flag = 0;
2044 vendorMsg->start_req_vendor.sfn = 0;
2045 vendorMsg->start_req_vendor.slot = 0;
2046 vendorMsg->start_req_vendor.mode = 4;
2048 vendorMsg->start_req_vendor.count = 0;
2049 vendorMsg->start_req_vendor.period = 1;
2051 /* Fill FAPI config req */
2052 LWR_MAC_ALLOC(cfgReqQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_config_req_t)));
2055 DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for config req");
2056 LWR_MAC_ALLOC(vendorMsgQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
2059 FILL_FAPI_LIST_ELEM(cfgReqQElem, vendorMsgQElem, FAPI_CONFIG_REQUEST, 1, \
2060 sizeof(fapi_config_req_t));
2062 configReq = (fapi_config_req_t *)(cfgReqQElem + 1);
2063 memset(configReq, 0, sizeof(fapi_config_req_t));
2064 fillMsgHeader(&configReq->header, FAPI_CONFIG_REQUEST, sizeof(fapi_config_req_t));
2065 configReq->number_of_tlvs = 25;
2066 msgLen = sizeof(configReq->number_of_tlvs);
2068 if(macCfgParams.dlCarrCfg.pres)
2070 fillTlvs(&configReq->tlvs[index++], FAPI_DL_BANDWIDTH_TAG, \
2071 sizeof(uint32_t), macCfgParams.dlCarrCfg.bw, &msgLen);
2072 fillTlvs(&configReq->tlvs[index++], FAPI_DL_FREQUENCY_TAG, \
2073 sizeof(uint32_t), macCfgParams.dlCarrCfg.freq, &msgLen);
2074 /* Due to bug in Intel FT code, commenting TLVs that are are not
2075 * needed to avoid error. Must be uncommented when FT bug is fixed */
2076 //fillTlvs(&configReq->tlvs[index++], FAPI_DL_K0_TAG, \
2077 sizeof(uint16_t), macCfgParams.dlCarrCfg.k0[0], &msgLen);
2078 //fillTlvs(&configReq->tlvs[index++], FAPI_DL_GRIDSIZE_TAG, \
2079 sizeof(uint16_t), macCfgParams.dlCarrCfg.gridSize[0], &msgLen);
2080 fillTlvs(&configReq->tlvs[index++], FAPI_NUM_TX_ANT_TAG, \
2081 sizeof(uint16_t), macCfgParams.dlCarrCfg.numAnt, &msgLen);
2083 if(macCfgParams.ulCarrCfg.pres)
2085 fillTlvs(&configReq->tlvs[index++], FAPI_UPLINK_BANDWIDTH_TAG, \
2086 sizeof(uint32_t), macCfgParams.ulCarrCfg.bw, &msgLen);
2087 fillTlvs(&configReq->tlvs[index++], FAPI_UPLINK_FREQUENCY_TAG, \
2088 sizeof(uint32_t), macCfgParams.ulCarrCfg.freq, &msgLen);
2089 //fillTlvs(&configReq->tlvs[index++], FAPI_UL_K0_TAG, \
2090 sizeof(uint16_t), macCfgParams.ulCarrCfg.k0[0], &msgLen);
2091 //fillTlvs(&configReq->tlvs[index++], FAPI_UL_GRID_SIZE_TAG, \
2092 sizeof(uint16_t), macCfgParams.ulCarrCfg.gridSize[0], &msgLen);
2093 fillTlvs(&configReq->tlvs[index++], FAPI_NUM_RX_ANT_TAG, \
2094 sizeof(uint16_t), macCfgParams.ulCarrCfg.numAnt, &msgLen);
2096 //fillTlvs(&configReq->tlvs[index++], FAPI_FREQUENCY_SHIFT_7P5_KHZ_TAG, \
2097 sizeof(uint8_t), macCfgParams.freqShft, &msgLen);
2099 /* fill cell config */
2100 fillTlvs(&configReq->tlvs[index++], FAPI_PHY_CELL_ID_TAG, \
2101 sizeof(uint8_t), macCfgParams.phyCellId, &msgLen);
2102 fillTlvs(&configReq->tlvs[index++], FAPI_FRAME_DUPLEX_TYPE_TAG, \
2103 sizeof(uint8_t), macCfgParams.dupType, &msgLen);
2105 /* fill SSB configuration */
2106 fillTlvs(&configReq->tlvs[index++], FAPI_SS_PBCH_POWER_TAG, \
2107 sizeof(uint32_t), macCfgParams.ssbCfg.ssbPbchPwr, &msgLen);
2108 //fillTlvs(&configReq->tlvs[index++], FAPI_BCH_PAYLOAD_TAG, \
2109 sizeof(uint8_t), macCfgParams.ssbCfg.bchPayloadFlag, &msgLen);
2110 fillTlvs(&configReq->tlvs[index++], FAPI_SCS_COMMON_TAG, \
2111 sizeof(uint8_t), macCfgParams.ssbCfg.scsCmn, &msgLen);
2113 /* fill PRACH configuration */
2114 //fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_SEQUENCE_LENGTH_TAG, \
2115 sizeof(uint8_t), macCfgParams.prachCfg.prachSeqLen, &msgLen);
2116 fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_SUBC_SPACING_TAG, \
2117 sizeof(uint8_t), macCfgParams.prachCfg.prachSubcSpacing, &msgLen);
2118 fillTlvs(&configReq->tlvs[index++], FAPI_RESTRICTED_SET_CONFIG_TAG, \
2119 sizeof(uint8_t), macCfgParams.prachCfg.prachRstSetCfg, &msgLen);
2120 fillTlvs(&configReq->tlvs[index++], FAPI_NUM_PRACH_FD_OCCASIONS_TAG,
2121 sizeof(uint8_t), macCfgParams.prachCfg.msg1Fdm, &msgLen);
2122 fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_CONFIG_INDEX_TAG,
2123 sizeof(uint8_t), macCfgParams.prachCfg.prachCfgIdx, &msgLen);
2124 fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_ROOT_SEQUENCE_INDEX_TAG, \
2125 sizeof(uint16_t), macCfgParams.prachCfg.fdm[0].rootSeqIdx, &msgLen);
2126 //fillTlvs(&configReq->tlvs[index++], FAPI_NUM_ROOT_SEQUENCES_TAG, \
2127 sizeof(uint8_t), macCfgParams.prachCfg.fdm[0].numRootSeq, &msgLen);
2128 fillTlvs(&configReq->tlvs[index++], FAPI_K1_TAG, \
2129 sizeof(uint16_t), macCfgParams.prachCfg.fdm[0].k1, &msgLen);
2130 fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_ZERO_CORR_CONF_TAG , \
2131 sizeof(uint8_t), macCfgParams.prachCfg.fdm[0].zeroCorrZoneCfg, &msgLen);
2132 //fillTlvs(&configReq->tlvs[index++], FAPI_NUM_UNUSED_ROOT_SEQUENCES_TAG, \
2133 sizeof(uint8_t), macCfgParams.prachCfg.fdm[0].numUnusedRootSeq, &msgLen);
2134 /* if(macCfgParams.prachCfg.fdm[0].numUnusedRootSeq)
2136 for(idx = 0; idx < macCfgParams.prachCfg.fdm[0].numUnusedRootSeq; idx++)
2137 fillTlvs(&configReq->tlvs[index++], FAPI_UNUSED_ROOT_SEQUENCES_TAG, \
2138 sizeof(uint8_t), macCfgParams.prachCfg.fdm[0].unsuedRootSeq[idx], \
2143 macCfgParams.prachCfg.fdm[0].unsuedRootSeq = NULL;
2146 fillTlvs(&configReq->tlvs[index++], FAPI_SSB_PER_RACH_TAG, \
2147 sizeof(uint8_t), macCfgParams.prachCfg.ssbPerRach, &msgLen);
2148 //fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_MULTIPLE_CARRIERS_IN_A_BAND_TAG, \
2149 sizeof(uint8_t), macCfgParams.prachCfg.prachMultCarrBand, &msgLen);
2151 /* fill SSB table */
2152 fillTlvs(&configReq->tlvs[index++], FAPI_SSB_OFFSET_POINT_A_TAG, \
2153 sizeof(uint16_t), macCfgParams.ssbCfg.ssbOffsetPointA, &msgLen);
2154 //fillTlvs(&configReq->tlvs[index++], FAPI_BETA_PSS_TAG, \
2155 sizeof(uint8_t), macCfgParams.ssbCfg.betaPss, &msgLen);
2156 fillTlvs(&configReq->tlvs[index++], FAPI_SSB_PERIOD_TAG, \
2157 sizeof(uint8_t), macCfgParams.ssbCfg.ssbPeriod, &msgLen);
2158 fillTlvs(&configReq->tlvs[index++], FAPI_SSB_SUBCARRIER_OFFSET_TAG, \
2159 sizeof(uint8_t), macCfgParams.ssbCfg.ssbScOffset, &msgLen);
2161 setMibPdu(macCfgParams.ssbCfg.mibPdu, &mib, 0);
2162 fillTlvs(&configReq->tlvs[index++], FAPI_MIB_TAG , \
2163 sizeof(uint32_t), mib, &msgLen);
2165 fillTlvs(&configReq->tlvs[index++], FAPI_SSB_MASK_TAG, \
2166 sizeof(uint32_t), macCfgParams.ssbCfg.ssbMask[0], &msgLen);
2167 fillTlvs(&configReq->tlvs[index++], FAPI_BEAM_ID_TAG, \
2168 sizeof(uint8_t), macCfgParams.ssbCfg.beamId[0], &msgLen);
2169 //fillTlvs(&configReq->tlvs[index++], FAPI_SS_PBCH_MULTIPLE_CARRIERS_IN_A_BAND_TAG, \
2170 sizeof(uint8_t), macCfgParams.ssbCfg.multCarrBand, &msgLen);
2171 //fillTlvs(&configReq->tlvs[index++], FAPI_MULTIPLE_CELLS_SS_PBCH_IN_A_CARRIER_TAG, \
2172 sizeof(uint8_t), macCfgParams.ssbCfg.multCellCarr, &msgLen);
2175 /* fill TDD table */
2176 fillTlvs(&configReq->tlvs[index++], FAPI_TDD_PERIOD_TAG, \
2177 sizeof(uint8_t), macCfgParams.tddCfg.tddPeriod, &msgLen);
2178 for(slotIdx =0 ;slotIdx< MAX_TDD_PERIODICITY_SLOTS; slotIdx++)
2180 for(symbolIdx = 0; symbolIdx< MAX_SYMB_PER_SLOT; symbolIdx++)
2182 fillTlvs(&configReq->tlvs[index++], FAPI_SLOT_CONFIG_TAG, \
2183 sizeof(uint8_t), macCfgParams.tddCfg.slotCfg[slotIdx][symbolIdx], &msgLen);
2188 /* fill measurement config */
2189 //fillTlvs(&configReq->tlvs[index++], FAPI_RSSI_MEASUREMENT_TAG, \
2190 sizeof(uint8_t), macCfgParams.rssiUnit, &msgLen);
2192 /* fill DMRS Type A Pos */
2193 fillTlvs(&configReq->tlvs[index++], FAPI_DMRS_TYPE_A_POS_TAG, \
2194 sizeof(uint8_t), macCfgParams.dmrsTypeAPos, &msgLen);
2196 /* Fill message header */
2197 LWR_MAC_ALLOC(headerElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_msg_header_t)));
2200 DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in config req");
2201 LWR_MAC_ALLOC(cfgReqQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_config_req_t)));
2202 LWR_MAC_ALLOC(vendorMsgQElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
2205 FILL_FAPI_LIST_ELEM(headerElem, cfgReqQElem, FAPI_VENDOR_MSG_HEADER_IND, 1, \
2206 sizeof(fapi_msg_header_t));
2207 msgHeader = (fapi_msg_header_t *)(headerElem + 1);
2208 msgHeader->num_msg = 2; /* Config req msg and vendor specific msg */
2209 msgHeader->handle = 0;
2211 DU_LOG("\nDEBUG --> LWR_MAC: Sending Config Request to Phy");
2212 LwrMacSendToL1(headerElem);
2216 } /* lwr_mac_handleConfigReqEvt */
2218 /*******************************************************************
2220 * @brief Processes config response from phy
2224 * Function : lwr_mac_procConfigRspEvt
2227 * Processes config response from phy
2229 * @params[in] FAPI message pointer
2230 * @return ROK - success
2233 * ****************************************************************/
2235 uint8_t lwr_mac_procConfigRspEvt(void *msg)
2238 fapi_config_resp_t *configRsp;
2239 configRsp = (fapi_config_resp_t *)msg;
2241 DU_LOG("\nINFO --> LWR_MAC: Received EVENT[%d] at STATE[%d]", lwrMacCb.event, \
2244 if(configRsp != NULL)
2246 if(configRsp->error_code == MSG_OK)
2248 DU_LOG("\nDEBUG --> LWR_MAC: PHY has moved to Configured state \n");
2249 lwrMacCb.phyState = PHY_STATE_CONFIGURED;
2250 lwrMacCb.cellCb[0].state = PHY_STATE_CONFIGURED;
2252 * Store config response into an intermediate struture and send to MAC
2253 * Support LC and LWLC for sending config rsp to MAC
2255 fapiMacConfigRsp(lwrMacCb.cellCb[0].cellId);
2259 DU_LOG("\nERROR --> LWR_MAC: Invalid error code %d", configRsp->error_code);
2265 DU_LOG("\nERROR --> LWR_MAC: Config Response received from PHY is NULL");
2271 } /* lwr_mac_procConfigRspEvt */
2273 /*******************************************************************
2275 * @brief Build and send start request to phy
2279 * Function : lwr_mac_procStartReqEvt
2282 * Build and send start request to phy
2284 * @params[in] FAPI message pointer
2285 * @return ROK - success
2288 * ****************************************************************/
2289 uint8_t lwr_mac_procStartReqEvt(void *msg)
2292 #ifdef CALL_FLOW_DEBUG_LOG
2293 DU_LOG("\nCall Flow: ENTMAC -> ENTLWRMAC : START_REQ\n");
2295 fapi_msg_header_t *msgHeader;
2296 fapi_start_req_t *startReq;
2297 fapi_vendor_msg_t *vendorMsg;
2298 p_fapi_api_queue_elem_t headerElem;
2299 p_fapi_api_queue_elem_t startReqElem;
2300 p_fapi_api_queue_elem_t vendorMsgElem;
2302 /* Allocte And fill Vendor msg */
2303 LWR_MAC_ALLOC(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
2306 DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in start req");
2309 FILL_FAPI_LIST_ELEM(vendorMsgElem, NULLP, FAPI_VENDOR_MESSAGE, 1, sizeof(fapi_vendor_msg_t));
2310 vendorMsg = (fapi_vendor_msg_t *)(vendorMsgElem + 1);
2311 fillMsgHeader(&vendorMsg->header, FAPI_VENDOR_MESSAGE, sizeof(fapi_vendor_msg_t));
2312 vendorMsg->start_req_vendor.sfn = 0;
2313 vendorMsg->start_req_vendor.slot = 0;
2314 vendorMsg->start_req_vendor.mode = 4; /* for Radio mode */
2316 vendorMsg->start_req_vendor.count = 0;
2317 vendorMsg->start_req_vendor.period = 1;
2320 /* Fill FAPI config req */
2321 LWR_MAC_ALLOC(startReqElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_start_req_t)));
2324 DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for start req");
2325 LWR_MAC_ALLOC(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
2328 FILL_FAPI_LIST_ELEM(startReqElem, vendorMsgElem, FAPI_START_REQUEST, 1, \
2329 sizeof(fapi_start_req_t));
2331 startReq = (fapi_start_req_t *)(startReqElem + 1);
2332 memset(startReq, 0, sizeof(fapi_start_req_t));
2333 fillMsgHeader(&startReq->header, FAPI_START_REQUEST, sizeof(fapi_start_req_t));
2335 /* Fill message header */
2336 LWR_MAC_ALLOC(headerElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_msg_header_t)));
2339 DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in config req");
2340 LWR_MAC_ALLOC(startReqElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_start_req_t)));
2341 LWR_MAC_ALLOC(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
2344 FILL_FAPI_LIST_ELEM(headerElem, startReqElem, FAPI_VENDOR_MSG_HEADER_IND, 1, \
2345 sizeof(fapi_msg_header_t));
2346 msgHeader = (fapi_msg_header_t *)(headerElem + 1);
2347 msgHeader->num_msg = 2; /* Start req msg and vendor specific msg */
2348 msgHeader->handle = 0;
2351 DU_LOG("\nDEBUG --> LWR_MAC: Sending Start Request to Phy");
2352 LwrMacSendToL1(headerElem);
2355 } /* lwr_mac_procStartReqEvt */
2357 /*******************************************************************
2359 * @brief Sends FAPI Stop Req to PHY
2363 * Function : lwr_mac_procStopReqEvt
2366 * -Sends FAPI Stop Req to PHY
2369 * @return ROK - success
2372 ********************************************************************/
2374 uint8_t lwr_mac_procStopReqEvt(SlotTimingInfo slotInfo, p_fapi_api_queue_elem_t prevElem)
2377 #ifdef CALL_FLOW_DEBUG_LOG
2378 DU_LOG("\nCall Flow: ENTMAC -> ENTLWRMAC : STOP_REQ\n");
2381 fapi_stop_req_t *stopReq;
2382 fapi_vendor_msg_t *vendorMsg;
2383 p_fapi_api_queue_elem_t stopReqElem;
2384 p_fapi_api_queue_elem_t vendorMsgElem;
2386 /* Allocte And fill Vendor msg */
2387 LWR_MAC_ALLOC(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
2390 DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for vendor msg in stop req");
2393 FILL_FAPI_LIST_ELEM(vendorMsgElem, NULLP, FAPI_VENDOR_MESSAGE, 1, sizeof(fapi_vendor_msg_t));
2394 vendorMsg = (fapi_vendor_msg_t *)(vendorMsgElem + 1);
2395 fillMsgHeader(&vendorMsg->header, FAPI_VENDOR_MESSAGE, sizeof(fapi_vendor_msg_t));
2396 vendorMsg->stop_req_vendor.sfn = slotInfo.sfn;
2397 vendorMsg->stop_req_vendor.slot = slotInfo.slot;
2399 /* Fill FAPI stop req */
2400 LWR_MAC_ALLOC(stopReqElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_stop_req_t)));
2403 DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for stop req");
2404 LWR_MAC_FREE(vendorMsgElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_vendor_msg_t)));
2407 FILL_FAPI_LIST_ELEM(stopReqElem, vendorMsgElem, FAPI_STOP_REQUEST, 1, \
2408 sizeof(fapi_stop_req_t));
2409 stopReq = (fapi_stop_req_t *)(stopReqElem + 1);
2410 memset(stopReq, 0, sizeof(fapi_stop_req_t));
2411 fillMsgHeader(&stopReq->header, FAPI_STOP_REQUEST, sizeof(fapi_stop_req_t));
2414 DU_LOG("\nINFO --> LWR_MAC: Sending Stop Request to Phy");
2415 prevElem->p_next = stopReqElem;
2422 /*******************************************************************
2424 * @brief fills SSB PDU required for DL TTI info in MAC
2428 * Function : fillSsbPdu
2431 * -Fills the SSB PDU info
2434 * @params[in] Pointer to FAPI DL TTI Req
2435 * Pointer to RgCellCb
2436 * Pointer to msgLen of DL TTI Info
2439 ******************************************************************/
2441 uint8_t fillSsbPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, MacCellCfg *macCellCfg,
2442 MacDlSlot *currDlSlot, uint8_t ssbIdxCount, uint16_t sfn)
2444 uint32_t mibPayload = 0;
2445 if(dlTtiReqPdu != NULL)
2447 dlTtiReqPdu->pduType = SSB_PDU_TYPE; /* SSB PDU */
2448 dlTtiReqPdu->pdu.ssb_pdu.physCellId = macCellCfg->phyCellId;
2449 dlTtiReqPdu->pdu.ssb_pdu.betaPss = macCellCfg->ssbCfg.betaPss;
2450 dlTtiReqPdu->pdu.ssb_pdu.ssbBlockIndex = currDlSlot->dlInfo.brdcstAlloc.ssbInfo[ssbIdxCount].ssbIdx;
2451 dlTtiReqPdu->pdu.ssb_pdu.ssbSubCarrierOffset = macCellCfg->ssbCfg.ssbScOffset;
2452 /* ssbOfPdufstA to be filled in ssbCfg */
2453 dlTtiReqPdu->pdu.ssb_pdu.ssbOffsetPointA = macCellCfg->ssbCfg.ssbOffsetPointA;
2454 dlTtiReqPdu->pdu.ssb_pdu.bchPayloadFlag = macCellCfg->ssbCfg.bchPayloadFlag;
2455 /* Bit manipulation for SFN */
2456 setMibPdu(macCellCfg->ssbCfg.mibPdu, &mibPayload, sfn);
2457 dlTtiReqPdu->pdu.ssb_pdu.bchPayload.bchPayload = mibPayload;
2458 dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming.numPrgs = 0;
2459 dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming.prgSize = 0;
2460 dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming.digBfInterfaces = 0;
2461 dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming.pmi_bfi[0].pmIdx = 0;
2462 dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming. \
2463 pmi_bfi[0].beamIdx[0].beamidx = macCellCfg->ssbCfg.beamId[0];
2464 dlTtiReqPdu->pduSize = sizeof(fapi_dl_ssb_pdu_t); /* Size of SSB PDU */
2471 /*******************************************************************
2473 * @brief fills Dl DCI PDU required for DL TTI info in MAC
2477 * Function : fillSib1DlDciPdu
2480 * -Fills the Dl DCI PDU
2482 * @params[in] Pointer to fapi_dl_dci_t
2483 * Pointer to PdcchCfg
2486 ******************************************************************/
2488 void fillSib1DlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *sib1PdcchInfo)
2490 if(dlDciPtr != NULLP)
2496 uint16_t coreset0Size=0;
2499 uint32_t freqDomResAssign=0;
2500 uint32_t timeDomResAssign=0;
2501 uint8_t VRB2PRBMap=0;
2502 uint32_t modNCodScheme=0;
2503 uint8_t redundancyVer=0;
2504 uint32_t sysInfoInd=0;
2505 uint32_t reserved=0;
2507 /* Size(in bits) of each field in DCI format 0_1
2508 * as mentioned in spec 38.214 */
2509 uint8_t freqDomResAssignSize = 0;
2510 uint8_t timeDomResAssignSize = 4;
2511 uint8_t VRB2PRBMapSize = 1;
2512 uint8_t modNCodSchemeSize = 5;
2513 uint8_t redundancyVerSize = 2;
2514 uint8_t sysInfoIndSize = 1;
2515 uint8_t reservedSize = 15;
2517 dlDciPtr->rnti = sib1PdcchInfo->dci.rnti;
2518 dlDciPtr->scramblingId = sib1PdcchInfo->dci.scramblingId;
2519 dlDciPtr->scramblingRnti = sib1PdcchInfo->dci.scramblingRnti;
2520 dlDciPtr->cceIndex = sib1PdcchInfo->dci.cceIndex;
2521 dlDciPtr->aggregationLevel = sib1PdcchInfo->dci.aggregLevel;
2522 dlDciPtr->pc_and_bform.numPrgs = sib1PdcchInfo->dci.beamPdcchInfo.numPrgs;
2523 dlDciPtr->pc_and_bform.prgSize = sib1PdcchInfo->dci.beamPdcchInfo.prgSize;
2524 dlDciPtr->pc_and_bform.digBfInterfaces = sib1PdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
2525 dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = sib1PdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
2526 dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = sib1PdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
2527 dlDciPtr->beta_pdcch_1_0 = sib1PdcchInfo->dci.txPdcchPower.powerValue;
2528 dlDciPtr->powerControlOffsetSS = sib1PdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
2530 /* Calculating freq domain resource allocation field value and size
2531 * coreset0Size = Size of coreset 0
2532 * RBStart = Starting Virtual Rsource block
2533 * RBLen = length of contiguously allocted RBs
2534 * Spec 38.214 Sec 5.1.2.2.2
2536 coreset0Size= sib1PdcchInfo->coresetCfg.coreSetSize;
2537 rbStart = sib1PdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.startPrb;
2538 rbLen = sib1PdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb;
2540 if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
2542 if((rbLen - 1) <= floor(coreset0Size / 2))
2543 freqDomResAssign = (coreset0Size * (rbLen-1)) + rbStart;
2545 freqDomResAssign = (coreset0Size * (coreset0Size - rbLen + 1)) \
2546 + (coreset0Size - 1 - rbStart);
2548 freqDomResAssignSize = ceil(log2(coreset0Size * (coreset0Size + 1) / 2));
2551 /* Fetching DCI field values */
2552 timeDomResAssign = sib1PdcchInfo->dci.pdschCfg->pdschTimeAlloc.rowIndex -1;
2553 VRB2PRBMap = sib1PdcchInfo->dci.pdschCfg->pdschFreqAlloc.vrbPrbMapping;
2554 modNCodScheme = sib1PdcchInfo->dci.pdschCfg->codeword[0].mcsIndex;
2555 redundancyVer = sib1PdcchInfo->dci.pdschCfg->codeword[0].rvIndex;
2556 sysInfoInd = 0; /* 0 for SIB1; 1 for SI messages */
2559 /* Reversing bits in each DCI field */
2560 freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
2561 timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
2562 VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
2563 modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
2564 redundancyVer = reverseBits(redundancyVer, redundancyVerSize);
2565 sysInfoInd = reverseBits(sysInfoInd, sysInfoIndSize);
2567 /* Calulating total number of bytes in buffer */
2568 dlDciPtr->payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\
2569 + VRB2PRBMapSize + modNCodSchemeSize + redundancyVerSize\
2570 + sysInfoIndSize + reservedSize;
2572 numBytes = dlDciPtr->payloadSizeBits / 8;
2573 if(dlDciPtr->payloadSizeBits % 8)
2576 if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
2578 DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
2582 /* Initialize buffer */
2583 for(bytePos = 0; bytePos < numBytes; bytePos++)
2584 dlDciPtr->payload[bytePos] = 0;
2586 bytePos = numBytes - 1;
2589 /* Packing DCI format fields */
2590 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2591 freqDomResAssign, freqDomResAssignSize);
2592 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2593 timeDomResAssign, timeDomResAssignSize);
2594 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2595 VRB2PRBMap, VRB2PRBMapSize);
2596 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2597 modNCodScheme, modNCodSchemeSize);
2598 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2599 redundancyVer, redundancyVerSize);
2600 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2601 sysInfoInd, sysInfoIndSize);
2602 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2603 reserved, reservedSize);
2606 } /* fillSib1DlDciPdu */
2609 /*******************************************************************
2611 * @brief fills Dl DCI PDU for Paging required for DL TTI info in MAC
2615 * Function : fillPageDlDciPdu
2618 * -Fills the Dl DCI PDU for Paging
2620 * @params[in] Pointer to fapi_dl_dci_t
2621 * Pointer to dlPageAlloc
2624 ******************************************************************/
2626 void fillPageDlDciPdu(fapi_dl_dci_t *dlDciPtr, DlPageAlloc *dlPageAlloc)
2628 if(dlDciPtr != NULLP)
2634 uint16_t coreset0Size = 0;
2635 uint16_t rbStart = 0;
2637 uint8_t shortMsgInd = 0;
2638 uint8_t shortMsg = 0;
2639 uint32_t freqDomResAssign = 0;
2640 uint32_t timeDomResAssign = 0;
2641 uint8_t VRB2PRBMap = 0;
2642 uint32_t modNCodScheme = 0;
2643 uint8_t tbScaling = 0;
2644 uint32_t reserved = 0;
2646 /* Size(in bits) of each field in DCI format 1_0
2647 * as mentioned in spec 38.214 */
2648 uint8_t shortMsgIndSize = 2;
2649 uint8_t shortMsgSize = 8;
2650 uint8_t freqDomResAssignSize = 0;
2651 uint8_t timeDomResAssignSize = 4;
2652 uint8_t VRB2PRBMapSize = 1;
2653 uint8_t modNCodSchemeSize = 5;
2654 uint8_t tbScalingSize = 2;
2655 uint8_t reservedSize = 6;
2657 dlDciPtr->rnti = dlPageAlloc->pagePdcchCfg.dci.rnti;
2658 dlDciPtr->scramblingId = dlPageAlloc->pagePdcchCfg.dci.scramblingId;
2659 dlDciPtr->scramblingRnti = dlPageAlloc->pagePdcchCfg.dci.scramblingRnti;
2660 dlDciPtr->cceIndex = dlPageAlloc->pagePdcchCfg.dci.cceIndex;
2661 dlDciPtr->aggregationLevel = dlPageAlloc->pagePdcchCfg.dci.aggregLevel;
2662 dlDciPtr->pc_and_bform.numPrgs = dlPageAlloc->pagePdcchCfg.dci.beamPdcchInfo.numPrgs;
2663 dlDciPtr->pc_and_bform.prgSize = dlPageAlloc->pagePdcchCfg.dci.beamPdcchInfo.prgSize;
2664 dlDciPtr->pc_and_bform.digBfInterfaces = dlPageAlloc->pagePdcchCfg.dci.beamPdcchInfo.digBfInterfaces;
2665 dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = dlPageAlloc->pagePdcchCfg.dci.beamPdcchInfo.prg[0].pmIdx;
2666 dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = dlPageAlloc->pagePdcchCfg.dci.beamPdcchInfo.prg[0].beamIdx[0];
2667 dlDciPtr->beta_pdcch_1_0 = dlPageAlloc->pagePdcchCfg.dci.txPdcchPower.powerValue;
2668 dlDciPtr->powerControlOffsetSS = dlPageAlloc->pagePdcchCfg.dci.txPdcchPower.powerControlOffsetSS;
2670 /* Calculating freq domain resource allocation field value and size
2671 * coreset0Size = Size of coreset 0
2672 * RBStart = Starting Virtual Rsource block
2673 * RBLen = length of contiguously allocted RBs
2674 * Spec 38.214 Sec 5.1.2.2.2
2676 coreset0Size = dlPageAlloc->pagePdcchCfg.coresetCfg.coreSetSize;
2677 rbStart = dlPageAlloc->pagePdcchCfg.dci.pdschCfg->pdschFreqAlloc.freqAlloc.startPrb;
2678 rbLen = dlPageAlloc->pagePdcchCfg.dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb;
2680 if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
2682 if((rbLen - 1) <= floor(coreset0Size / 2))
2683 freqDomResAssign = (coreset0Size * (rbLen-1)) + rbStart;
2685 freqDomResAssign = (coreset0Size * (coreset0Size - rbLen + 1)) \
2686 + (coreset0Size - 1 - rbStart);
2688 freqDomResAssignSize = ceil(log2(coreset0Size * (coreset0Size + 1) / 2));
2691 /*Fetching DCI field values */
2693 /*Refer:38.212 - Table 7.3.1.2.1-1: Short Message indicator >*/
2694 if(dlPageAlloc->shortMsgInd != TRUE)
2696 /*When Short Msg is absent*/
2702 /*Short Msg is Present*/
2703 if(dlPageAlloc->dlPagePduLen == 0 || dlPageAlloc->dlPagePdu == NULLP)
2705 /*When Paging Msg is absent*/
2710 /*Both Short and Paging is present*/
2713 shortMsg = dlPageAlloc->shortMsg;
2716 timeDomResAssign = dlPageAlloc->pagePdcchCfg.dci.pdschCfg->pdschTimeAlloc.rowIndex -1;
2717 VRB2PRBMap = dlPageAlloc->pagePdcchCfg.dci.pdschCfg->pdschFreqAlloc.vrbPrbMapping;
2718 modNCodScheme = dlPageAlloc->pagePdcchCfg.dci.pdschCfg->codeword[0].mcsIndex;
2722 /* Reversing bits in each DCI field */
2723 shortMsgInd = reverseBits(shortMsgInd, shortMsgIndSize);
2724 shortMsg = reverseBits(shortMsg, shortMsgSize);
2725 timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
2726 freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
2727 timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
2728 VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
2729 modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
2730 tbScaling = reverseBits(tbScaling, tbScalingSize);
2732 /* Calulating total number of bytes in buffer */
2733 dlDciPtr->payloadSizeBits = shortMsgIndSize + shortMsgSize + freqDomResAssignSize\
2734 + timeDomResAssignSize + VRB2PRBMapSize + modNCodSchemeSize\
2735 + tbScaling + reservedSize;
2737 numBytes = dlDciPtr->payloadSizeBits / 8;
2738 if(dlDciPtr->payloadSizeBits % 8)
2743 if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
2745 DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
2749 /* Initialize buffer */
2750 for(bytePos = 0; bytePos < numBytes; bytePos++)
2752 dlDciPtr->payload[bytePos] = 0;
2755 bytePos = numBytes - 1;
2758 /* Packing DCI format fields */
2759 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2760 shortMsgInd, shortMsgIndSize);
2761 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2762 shortMsg, shortMsgSize);
2763 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2764 freqDomResAssign, freqDomResAssignSize);
2765 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2766 timeDomResAssign, timeDomResAssignSize);
2767 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2768 VRB2PRBMap, VRB2PRBMapSize);
2769 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2770 modNCodScheme, modNCodSchemeSize);
2771 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2772 tbScaling, tbScalingSize);
2773 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2774 reserved, reservedSize);
2776 } /* fillPageDlDciPdu */
2778 /*******************************************************************
2780 * @brief fills Dl DCI PDU required for DL TTI info in MAC
2784 * Function : fillRarDlDciPdu
2787 * -Fills the Dl DCI PDU
2789 * @params[in] Pointer to fapi_dl_dci_t
2790 * Pointer to PdcchCfg
2793 ******************************************************************/
2795 void fillRarDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *rarPdcchInfo)
2797 if(dlDciPtr != NULLP)
2799 uint8_t numBytes =0;
2803 uint16_t coreset0Size =0;
2804 uint16_t rbStart =0;
2806 uint32_t freqDomResAssign =0;
2807 uint8_t timeDomResAssign =0;
2808 uint8_t VRB2PRBMap =0;
2809 uint8_t modNCodScheme =0;
2810 uint8_t tbScaling =0;
2811 uint32_t reserved =0;
2813 /* Size(in bits) of each field in DCI format 1_0 */
2814 uint8_t freqDomResAssignSize = 0;
2815 uint8_t timeDomResAssignSize = 4;
2816 uint8_t VRB2PRBMapSize = 1;
2817 uint8_t modNCodSchemeSize = 5;
2818 uint8_t tbScalingSize = 2;
2819 uint8_t reservedSize = 16;
2821 dlDciPtr->rnti = rarPdcchInfo->dci.rnti;
2822 dlDciPtr->scramblingId = rarPdcchInfo->dci.scramblingId;
2823 dlDciPtr->scramblingRnti = rarPdcchInfo->dci.scramblingRnti;
2824 dlDciPtr->cceIndex = rarPdcchInfo->dci.cceIndex;
2825 dlDciPtr->aggregationLevel = rarPdcchInfo->dci.aggregLevel;
2826 dlDciPtr->pc_and_bform.numPrgs = rarPdcchInfo->dci.beamPdcchInfo.numPrgs;
2827 dlDciPtr->pc_and_bform.prgSize = rarPdcchInfo->dci.beamPdcchInfo.prgSize;
2828 dlDciPtr->pc_and_bform.digBfInterfaces = rarPdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
2829 dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
2830 dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
2831 dlDciPtr->beta_pdcch_1_0 = rarPdcchInfo->dci.txPdcchPower.powerValue;
2832 dlDciPtr->powerControlOffsetSS = rarPdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
2834 /* Calculating freq domain resource allocation field value and size
2835 * coreset0Size = Size of coreset 0
2836 * RBStart = Starting Virtual Rsource block
2837 * RBLen = length of contiguously allocted RBs
2838 * Spec 38.214 Sec 5.1.2.2.2
2841 /* TODO: Fill values of coreset0Size, rbStart and rbLen */
2842 coreset0Size= rarPdcchInfo->coresetCfg.coreSetSize;
2843 rbStart = rarPdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.startPrb;
2844 rbLen = rarPdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb;
2846 if((rbLen >=1) && (rbLen <= coreset0Size - rbStart))
2848 if((rbLen - 1) <= floor(coreset0Size / 2))
2849 freqDomResAssign = (coreset0Size * (rbLen-1)) + rbStart;
2851 freqDomResAssign = (coreset0Size * (coreset0Size - rbLen + 1)) \
2852 + (coreset0Size - 1 - rbStart);
2854 freqDomResAssignSize = ceil(log2(coreset0Size * (coreset0Size + 1) / 2));
2857 /* Fetching DCI field values */
2858 timeDomResAssign = rarPdcchInfo->dci.pdschCfg->pdschTimeAlloc.rowIndex;
2859 VRB2PRBMap = rarPdcchInfo->dci.pdschCfg->pdschFreqAlloc.vrbPrbMapping;
2860 modNCodScheme = rarPdcchInfo->dci.pdschCfg->codeword[0].mcsIndex;
2861 tbScaling = 0; /* configured to 0 scaling */
2864 /* Reversing bits in each DCI field */
2865 freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
2866 timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
2867 VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
2868 modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
2869 tbScaling = reverseBits(tbScaling, tbScalingSize);
2871 /* Calulating total number of bytes in buffer */
2872 dlDciPtr->payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\
2873 + VRB2PRBMapSize + modNCodSchemeSize + tbScalingSize + reservedSize;
2875 numBytes = dlDciPtr->payloadSizeBits / 8;
2876 if(dlDciPtr->payloadSizeBits % 8)
2879 if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
2881 DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
2885 /* Initialize buffer */
2886 for(bytePos = 0; bytePos < numBytes; bytePos++)
2887 dlDciPtr->payload[bytePos] = 0;
2889 bytePos = numBytes - 1;
2892 /* Packing DCI format fields */
2893 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2894 freqDomResAssign, freqDomResAssignSize);
2895 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2896 timeDomResAssign, timeDomResAssignSize);
2897 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2898 VRB2PRBMap, VRB2PRBMapSize);
2899 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2900 modNCodScheme, modNCodSchemeSize);
2901 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2902 tbScaling, tbScalingSize);
2903 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
2904 reserved, reservedSize);
2906 } /* fillRarDlDciPdu */
2908 /*******************************************************************
2910 * @brief fills DL DCI PDU required for DL TTI info in MAC
2914 * Function : fillDlMsgDlDciPdu
2917 * -Fills the Dl DCI PDU
2919 * @params[in] Pointer to fapi_dl_dci_t
2920 * Pointer to PdcchCfg
2923 ******************************************************************/
2924 void fillDlMsgDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *pdcchInfo,\
2925 DlMsgInfo *dlMsgInfo)
2927 if(dlDciPtr != NULLP)
2933 uint16_t coresetSize = 0;
2934 uint16_t rbStart = 0;
2936 uint8_t dciFormatId;
2937 uint32_t freqDomResAssign;
2938 uint8_t timeDomResAssign;
2940 uint8_t modNCodScheme;
2942 uint8_t redundancyVer = 0;
2943 uint8_t harqProcessNum = 0;
2944 uint8_t dlAssignmentIdx = 0;
2945 uint8_t pucchTpc = 0;
2946 uint8_t pucchResoInd = 0;
2947 uint8_t harqFeedbackInd = 0;
2949 /* Size(in bits) of each field in DCI format 1_0 */
2950 uint8_t dciFormatIdSize = 1;
2951 uint8_t freqDomResAssignSize = 0;
2952 uint8_t timeDomResAssignSize = 4;
2953 uint8_t VRB2PRBMapSize = 1;
2954 uint8_t modNCodSchemeSize = 5;
2955 uint8_t ndiSize = 1;
2956 uint8_t redundancyVerSize = 2;
2957 uint8_t harqProcessNumSize = 4;
2958 uint8_t dlAssignmentIdxSize = 2;
2959 uint8_t pucchTpcSize = 2;
2960 uint8_t pucchResoIndSize = 3;
2961 uint8_t harqFeedbackIndSize = 3;
2963 dlDciPtr->rnti = pdcchInfo->dci.rnti;
2964 dlDciPtr->scramblingId = pdcchInfo->dci.scramblingId;
2965 dlDciPtr->scramblingRnti = pdcchInfo->dci.scramblingRnti;
2966 dlDciPtr->cceIndex = pdcchInfo->dci.cceIndex;
2967 dlDciPtr->aggregationLevel = pdcchInfo->dci.aggregLevel;
2968 dlDciPtr->pc_and_bform.numPrgs = pdcchInfo->dci.beamPdcchInfo.numPrgs;
2969 dlDciPtr->pc_and_bform.prgSize = pdcchInfo->dci.beamPdcchInfo.prgSize;
2970 dlDciPtr->pc_and_bform.digBfInterfaces = pdcchInfo->dci.beamPdcchInfo.digBfInterfaces;
2971 dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = pdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx;
2972 dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = pdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0];
2973 dlDciPtr->beta_pdcch_1_0 = pdcchInfo->dci.txPdcchPower.powerValue;
2974 dlDciPtr->powerControlOffsetSS = pdcchInfo->dci.txPdcchPower.powerControlOffsetSS;
2976 /* Calculating freq domain resource allocation field value and size
2977 * coreset0Size = Size of coreset 0
2978 * RBStart = Starting Virtual Rsource block
2979 * RBLen = length of contiguously allocted RBs
2980 * Spec 38.214 Sec 5.1.2.2.2
2982 coresetSize = pdcchInfo->coresetCfg.coreSetSize;
2983 rbStart = pdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.startPrb;
2984 rbLen = pdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb;
2986 if((rbLen >=1) && (rbLen <= coresetSize - rbStart))
2988 if((rbLen - 1) <= floor(coresetSize / 2))
2989 freqDomResAssign = (coresetSize * (rbLen-1)) + rbStart;
2991 freqDomResAssign = (coresetSize * (coresetSize - rbLen + 1)) \
2992 + (coresetSize - 1 - rbStart);
2994 freqDomResAssignSize = ceil(log2(coresetSize * (coresetSize + 1) / 2));
2997 /* Fetching DCI field values */
2998 dciFormatId = dlMsgInfo->dciFormatId; /* Always set to 1 for DL */
2999 timeDomResAssign = pdcchInfo->dci.pdschCfg->pdschTimeAlloc.rowIndex -1;
3000 VRB2PRBMap = pdcchInfo->dci.pdschCfg->pdschFreqAlloc.vrbPrbMapping;
3001 modNCodScheme = pdcchInfo->dci.pdschCfg->codeword[0].mcsIndex;
3002 ndi = dlMsgInfo->ndi;
3003 redundancyVer = pdcchInfo->dci.pdschCfg->codeword[0].rvIndex;
3004 harqProcessNum = dlMsgInfo->harqProcNum;
3005 dlAssignmentIdx = dlMsgInfo->dlAssignIdx;
3006 pucchTpc = dlMsgInfo->pucchTpc;
3007 pucchResoInd = dlMsgInfo->pucchResInd;
3008 harqFeedbackInd = dlMsgInfo->harqFeedbackInd;
3010 /* Reversing bits in each DCI field */
3011 dciFormatId = reverseBits(dciFormatId, dciFormatIdSize);
3012 freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
3013 timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
3014 VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize);
3015 modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
3016 ndi = reverseBits(ndi, ndiSize);
3017 redundancyVer = reverseBits(redundancyVer, redundancyVerSize);
3018 harqProcessNum = reverseBits(harqProcessNum, harqProcessNumSize);
3019 dlAssignmentIdx = reverseBits(dlAssignmentIdx , dlAssignmentIdxSize);
3020 pucchTpc = reverseBits(pucchTpc, pucchTpcSize);
3021 pucchResoInd = reverseBits(pucchResoInd, pucchResoIndSize);
3022 harqFeedbackInd = reverseBits(harqFeedbackInd, harqFeedbackIndSize);
3025 /* Calulating total number of bytes in buffer */
3026 dlDciPtr->payloadSizeBits = (dciFormatIdSize + freqDomResAssignSize\
3027 + timeDomResAssignSize + VRB2PRBMapSize + modNCodSchemeSize\
3028 + ndiSize + redundancyVerSize + harqProcessNumSize + dlAssignmentIdxSize\
3029 + pucchTpcSize + pucchResoIndSize + harqFeedbackIndSize);
3031 numBytes = dlDciPtr->payloadSizeBits / 8;
3032 if(dlDciPtr->payloadSizeBits % 8)
3035 if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
3037 DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
3041 /* Initialize buffer */
3042 for(bytePos = 0; bytePos < numBytes; bytePos++)
3043 dlDciPtr->payload[bytePos] = 0;
3045 bytePos = numBytes - 1;
3048 /* Packing DCI format fields */
3049 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
3050 dciFormatId, dciFormatIdSize);
3051 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
3052 freqDomResAssign, freqDomResAssignSize);
3053 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
3054 timeDomResAssign, timeDomResAssignSize);
3055 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
3056 VRB2PRBMap, VRB2PRBMapSize);
3057 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
3058 modNCodScheme, modNCodSchemeSize);
3059 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
3061 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
3062 redundancyVer, redundancyVerSize);
3063 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
3064 redundancyVer, redundancyVerSize);
3065 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
3066 harqProcessNum, harqProcessNumSize);
3067 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
3068 dlAssignmentIdx, dlAssignmentIdxSize);
3069 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
3070 pucchTpc, pucchTpcSize);
3071 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
3072 pucchResoInd, pucchResoIndSize);
3073 fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\
3074 harqFeedbackInd, harqFeedbackIndSize);
3078 /*******************************************************************
3080 * @brief fills PDCCH PDU required for DL TTI info in MAC
3084 * Function : fillPdcchPdu
3087 * -Fills the Pdcch PDU info
3090 * @params[in] Pointer to FAPI DL TTI Req
3091 * Pointer to PdcchCfg
3094 ******************************************************************/
3095 uint8_t fillPdcchPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, MacDlSlot *dlSlot, int8_t dlMsgSchInfoIdx, \
3096 RntiType rntiType, uint8_t coreSetType, uint8_t ueIdx)
3098 if(dlTtiReqPdu != NULLP)
3100 PdcchCfg *pdcchInfo = NULLP;
3101 BwpCfg *bwp = NULLP;
3103 memset(&dlTtiReqPdu->pdu.pdcch_pdu, 0, sizeof(fapi_dl_pdcch_pdu_t));
3104 if(rntiType == SI_RNTI_TYPE)
3106 pdcchInfo = &dlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg;
3107 bwp = &dlSlot->dlInfo.brdcstAlloc.sib1Alloc.bwp;
3108 fillSib1DlDciPdu(dlTtiReqPdu->pdu.pdcch_pdu.dlDci, pdcchInfo);
3110 else if(rntiType == P_RNTI_TYPE)
3112 pdcchInfo = &dlSlot->pageAllocInfo->pagePdcchCfg;
3113 bwp = &dlSlot->pageAllocInfo->bwp;
3114 fillPageDlDciPdu(dlTtiReqPdu->pdu.pdcch_pdu.dlDci, dlSlot->pageAllocInfo);
3116 else if(rntiType == RA_RNTI_TYPE)
3118 pdcchInfo = &dlSlot->dlInfo.rarAlloc[ueIdx]->rarPdcchCfg;
3119 bwp = &dlSlot->dlInfo.rarAlloc[ueIdx]->bwp;
3120 fillRarDlDciPdu(dlTtiReqPdu->pdu.pdcch_pdu.dlDci, pdcchInfo);
3122 else if(rntiType == TC_RNTI_TYPE || rntiType == C_RNTI_TYPE)
3124 pdcchInfo = &dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[dlMsgSchInfoIdx].dlMsgPdcchCfg;
3125 bwp = &dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[dlMsgSchInfoIdx].bwp;
3126 fillDlMsgDlDciPdu(dlTtiReqPdu->pdu.pdcch_pdu.dlDci, pdcchInfo,\
3127 &dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[dlMsgSchInfoIdx].dlMsgInfo);
3131 DU_LOG("\nERROR --> LWR_MAC: Failed filling PDCCH Pdu");
3134 dlTtiReqPdu->pduType = PDCCH_PDU_TYPE;
3135 dlTtiReqPdu->pdu.pdcch_pdu.bwpSize = bwp->freqAlloc.numPrb;
3136 dlTtiReqPdu->pdu.pdcch_pdu.bwpStart = bwp->freqAlloc.startPrb;
3137 dlTtiReqPdu->pdu.pdcch_pdu.subCarrierSpacing = bwp->subcarrierSpacing;
3138 dlTtiReqPdu->pdu.pdcch_pdu.cyclicPrefix = bwp->cyclicPrefix;
3139 dlTtiReqPdu->pdu.pdcch_pdu.startSymbolIndex = pdcchInfo->coresetCfg.startSymbolIndex;
3140 dlTtiReqPdu->pdu.pdcch_pdu.durationSymbols = pdcchInfo->coresetCfg.durationSymbols;
3141 memcpy(dlTtiReqPdu->pdu.pdcch_pdu.freqDomainResource, pdcchInfo->coresetCfg.freqDomainResource, 6);
3142 dlTtiReqPdu->pdu.pdcch_pdu.cceRegMappingType = pdcchInfo->coresetCfg.cceRegMappingType;
3143 dlTtiReqPdu->pdu.pdcch_pdu.regBundleSize = pdcchInfo->coresetCfg.regBundleSize;
3144 dlTtiReqPdu->pdu.pdcch_pdu.interleaverSize = pdcchInfo->coresetCfg.interleaverSize;
3145 dlTtiReqPdu->pdu.pdcch_pdu.shiftIndex = pdcchInfo->coresetCfg.shiftIndex;
3146 dlTtiReqPdu->pdu.pdcch_pdu.precoderGranularity = pdcchInfo->coresetCfg.precoderGranularity;
3147 dlTtiReqPdu->pdu.pdcch_pdu.numDlDci = pdcchInfo->numDlDci;
3148 dlTtiReqPdu->pdu.pdcch_pdu.coreSetType = coreSetType;
3150 /* Calculating PDU length. Considering only one dl dci pdu for now */
3151 dlTtiReqPdu->pduSize = sizeof(fapi_dl_pdcch_pdu_t);
3157 /*******************************************************************
3159 * @brief fills PDSCH PDU required for DL TTI info in MAC
3163 * Function : fillPdschPdu
3166 * -Fills the Pdsch PDU info
3169 * @params[in] Pointer to FAPI DL TTI Req
3170 * Pointer to PdschCfg
3171 * Pointer to msgLen of DL TTI Info
3174 ******************************************************************/
3176 void fillPdschPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, PdschCfg *pdschInfo,
3177 BwpCfg bwp, uint16_t pduIndex)
3181 if(dlTtiReqPdu != NULLP)
3183 dlTtiReqPdu->pduType = PDSCH_PDU_TYPE;
3184 memset(&dlTtiReqPdu->pdu.pdsch_pdu, 0, sizeof(fapi_dl_pdsch_pdu_t));
3185 dlTtiReqPdu->pdu.pdsch_pdu.pduBitMap = pdschInfo->pduBitmap;
3186 dlTtiReqPdu->pdu.pdsch_pdu.rnti = pdschInfo->rnti;
3187 dlTtiReqPdu->pdu.pdsch_pdu.pdu_index = pduIndex;
3188 dlTtiReqPdu->pdu.pdsch_pdu.bwpSize = bwp.freqAlloc.numPrb;
3189 dlTtiReqPdu->pdu.pdsch_pdu.bwpStart = bwp.freqAlloc.startPrb;
3190 dlTtiReqPdu->pdu.pdsch_pdu.subCarrierSpacing = bwp.subcarrierSpacing;
3191 dlTtiReqPdu->pdu.pdsch_pdu.cyclicPrefix = bwp.cyclicPrefix;
3192 dlTtiReqPdu->pdu.pdsch_pdu.nrOfCodeWords = pdschInfo->numCodewords;
3193 for(idx = 0; idx < MAX_CODEWORDS ; idx++)
3195 dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].targetCodeRate = pdschInfo->codeword[idx].targetCodeRate;
3196 dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].qamModOrder = pdschInfo->codeword[idx].qamModOrder;
3197 dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].mcsIndex = pdschInfo->codeword[idx].mcsIndex;
3198 dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].mcsTable = pdschInfo->codeword[idx].mcsTable;
3199 dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].rvIndex = pdschInfo->codeword[idx].rvIndex;
3200 dlTtiReqPdu->pdu.pdsch_pdu.cwInfo[idx].tbSize = pdschInfo->codeword[idx].tbSize;
3202 dlTtiReqPdu->pdu.pdsch_pdu.dataScramblingId = pdschInfo->dataScramblingId;
3203 dlTtiReqPdu->pdu.pdsch_pdu.nrOfLayers = pdschInfo->numLayers;
3204 dlTtiReqPdu->pdu.pdsch_pdu.transmissionScheme = pdschInfo->transmissionScheme;
3205 dlTtiReqPdu->pdu.pdsch_pdu.refPoint = pdschInfo->refPoint;
3206 dlTtiReqPdu->pdu.pdsch_pdu.dlDmrsSymbPos = pdschInfo->dmrs.dlDmrsSymbPos;
3207 dlTtiReqPdu->pdu.pdsch_pdu.dmrsConfigType = pdschInfo->dmrs.dmrsConfigType;
3208 dlTtiReqPdu->pdu.pdsch_pdu.dlDmrsScramblingId = pdschInfo->dmrs.dlDmrsScramblingId;
3209 dlTtiReqPdu->pdu.pdsch_pdu.scid = pdschInfo->dmrs.scid;
3210 dlTtiReqPdu->pdu.pdsch_pdu.numDmrsCdmGrpsNoData = pdschInfo->dmrs.numDmrsCdmGrpsNoData;
3211 dlTtiReqPdu->pdu.pdsch_pdu.dmrsPorts = pdschInfo->dmrs.dmrsPorts;
3212 dlTtiReqPdu->pdu.pdsch_pdu.resourceAlloc = pdschInfo->pdschFreqAlloc.resourceAllocType;
3213 /* since we are using type-1, hence rbBitmap excluded */
3214 dlTtiReqPdu->pdu.pdsch_pdu.rbStart = pdschInfo->pdschFreqAlloc.freqAlloc.startPrb;
3215 dlTtiReqPdu->pdu.pdsch_pdu.rbSize = pdschInfo->pdschFreqAlloc.freqAlloc.numPrb;
3216 dlTtiReqPdu->pdu.pdsch_pdu.vrbToPrbMapping = pdschInfo->pdschFreqAlloc.vrbPrbMapping;
3217 dlTtiReqPdu->pdu.pdsch_pdu.startSymbIndex = pdschInfo->pdschTimeAlloc.timeAlloc.startSymb;
3218 dlTtiReqPdu->pdu.pdsch_pdu.nrOfSymbols = pdschInfo->pdschTimeAlloc.timeAlloc.numSymb;
3219 dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.numPrgs = pdschInfo->beamPdschInfo.numPrgs;
3220 dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.prgSize = pdschInfo->beamPdschInfo.prgSize;
3221 dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.digBfInterfaces = pdschInfo->beamPdschInfo.digBfInterfaces;
3222 dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.pmi_bfi[0]. \
3223 pmIdx = pdschInfo->beamPdschInfo.prg[0].pmIdx;
3224 dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.pmi_bfi[0]. \
3225 beamIdx[0].beamidx = pdschInfo->beamPdschInfo.prg[0].beamIdx[0];
3226 dlTtiReqPdu->pdu.pdsch_pdu.powerControlOffset = pdschInfo->txPdschPower.powerControlOffset;
3227 dlTtiReqPdu->pdu.pdsch_pdu.powerControlOffsetSS = pdschInfo->txPdschPower.powerControlOffsetSS;
3228 dlTtiReqPdu->pdu.pdsch_pdu.mappingType = pdschInfo->dmrs.mappingType;
3229 dlTtiReqPdu->pdu.pdsch_pdu.nrOfDmrsSymbols = pdschInfo->dmrs.nrOfDmrsSymbols;
3230 dlTtiReqPdu->pdu.pdsch_pdu.dmrsAddPos = pdschInfo->dmrs.dmrsAddPos;
3232 dlTtiReqPdu->pduSize = sizeof(fapi_dl_pdsch_pdu_t);
3236 /***********************************************************************
3238 * @brief calculates the total size to be allocated for DL TTI Req
3242 * Function : calcDlTtiReqPduCount
3245 * -calculates the total pdu count to be allocated for DL TTI Req
3247 * @params[in] MacDlSlot *dlSlot
3250 * ********************************************************************/
3251 uint8_t calcDlTtiReqPduCount(MacDlSlot *dlSlot)
3254 uint8_t idx = 0, ueIdx=0;
3256 if(dlSlot->dlInfo.isBroadcastPres)
3258 if(dlSlot->dlInfo.brdcstAlloc.ssbTrans)
3260 for(idx = 0; idx < dlSlot->dlInfo.brdcstAlloc.ssbIdxSupported; idx++)
3262 /* SSB PDU is filled */
3266 if(dlSlot->dlInfo.brdcstAlloc.sib1Trans)
3268 /* PDCCH and PDSCH PDU is filled */
3273 if(dlSlot->pageAllocInfo)
3275 /* PDCCH and PDSCH PDU is filled */
3279 for(ueIdx=0; ueIdx<MAX_NUM_UE; ueIdx++)
3281 if(dlSlot->dlInfo.rarAlloc[ueIdx] != NULLP)
3283 /* PDCCH and PDSCH PDU is filled */
3284 if(dlSlot->dlInfo.rarAlloc[ueIdx]->pduPres == BOTH)
3290 if(dlSlot->dlInfo.dlMsgAlloc[ueIdx] != NULLP)
3292 for(idx=0; idx<dlSlot->dlInfo.dlMsgAlloc[ueIdx]->numSchedInfo; idx++)
3294 /* PDCCH and PDSCH PDU is filled */
3295 if(dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[idx].pduPres == BOTH)
3297 else if(dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[idx].pduPres != NONE)
3305 /***********************************************************************
3307 * @brief calculates the total size to be allocated for DL TTI Req
3311 * Function : calcTxDataReqPduCount
3314 * -calculates the total pdu count to be allocated for DL TTI Req
3316 * @params[in] DlBrdcstAlloc *cellBroadcastInfo
3319 * ********************************************************************/
3320 uint8_t calcTxDataReqPduCount(MacDlSlot *dlSlot)
3322 uint8_t idx = 0, count = 0, ueIdx=0;
3324 if(dlSlot->dlInfo.isBroadcastPres && dlSlot->dlInfo.brdcstAlloc.sib1Trans)
3328 if(dlSlot->pageAllocInfo)
3333 for(ueIdx=0; ueIdx<MAX_NUM_UE; ueIdx++)
3335 if((dlSlot->dlInfo.rarAlloc[ueIdx] != NULLP) && \
3336 ((dlSlot->dlInfo.rarAlloc[ueIdx]->pduPres == BOTH) || (dlSlot->dlInfo.rarAlloc[ueIdx]->pduPres == PDSCH_PDU)))
3339 if(dlSlot->dlInfo.dlMsgAlloc[ueIdx] != NULLP)
3341 for(idx=0; idx<dlSlot->dlInfo.dlMsgAlloc[ueIdx]->numSchedInfo; idx++)
3343 if(dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[idx].pduPres == BOTH || \
3344 dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[idx].pduPres == PDSCH_PDU)
3352 /***********************************************************************
3354 * @brief fills the SIB1 TX-DATA request message
3358 * Function : fillSib1TxDataReq
3361 * - fills the SIB1 TX-DATA request message
3363 * @params[in] fapi_tx_pdu_desc_t *pduDesc
3364 * @params[in] macCellCfg consist of SIB1 pdu
3365 * @params[in] uint32_t *msgLen
3366 * @params[in] uint16_t pduIndex
3369 * ********************************************************************/
3370 uint8_t fillSib1TxDataReq(fapi_tx_pdu_desc_t *pduDesc, uint16_t pduIndex, MacCellCfg *macCellCfg,
3373 uint32_t payloadSize = 0;
3374 uint8_t *sib1Payload = NULLP;
3375 fapi_api_queue_elem_t *payloadElem = NULLP;
3376 #ifdef INTEL_WLS_MEM
3377 void * wlsHdlr = NULLP;
3380 pduDesc[pduIndex].pdu_index = pduIndex;
3381 pduDesc[pduIndex].num_tlvs = 1;
3384 payloadSize = pdschCfg.codeword[0].tbSize;
3385 pduDesc[pduIndex].tlvs[0].tl.tag = ((payloadSize & 0xff0000) >> 8) | FAPI_TX_DATA_PTR_TO_PAYLOAD_64;
3386 pduDesc[pduIndex].tlvs[0].tl.length = (payloadSize & 0x0000ffff);
3387 LWR_MAC_ALLOC(sib1Payload, payloadSize);
3388 if(sib1Payload == NULLP)
3392 payloadElem = (fapi_api_queue_elem_t *)sib1Payload;
3393 FILL_FAPI_LIST_ELEM(payloadElem, NULLP, FAPI_VENDOR_MSG_PHY_ZBC_BLOCK_REQ, 1, \
3394 macCellCfg->sib1Cfg.sib1PduLen);
3395 memcpy(sib1Payload + TX_PAYLOAD_HDR_LEN, macCellCfg->sib1Cfg.sib1Pdu, macCellCfg->sib1Cfg.sib1PduLen);
3397 #ifdef INTEL_WLS_MEM
3398 mtGetWlsHdl(&wlsHdlr);
3399 pduDesc[pduIndex].tlvs[0].value = WLS_VA2PA(wlsHdlr, sib1Payload);
3401 pduDesc[pduIndex].tlvs[0].value = sib1Payload;
3403 pduDesc[pduIndex].pdu_length = payloadSize;
3405 #ifdef INTEL_WLS_MEM
3406 addWlsBlockToFree(sib1Payload, payloadSize, (lwrMacCb.phySlotIndCntr-1));
3408 LWR_MAC_FREE(sib1Payload, payloadSize);
3414 /***********************************************************************
3416 * @brief fills the PAGE TX-DATA request message
3420 * Function : fillPageTxDataReq
3423 * - fills the Page TX-DATA request message
3425 * @params[in] fapi_tx_pdu_desc_t *pduDesc
3426 * @params[in] macCellCfg consist of SIB1 pdu
3427 * @params[in] uint32_t *msgLen
3428 * @params[in] uint16_t pduIndex
3431 * ********************************************************************/
3432 uint8_t fillPageTxDataReq(fapi_tx_pdu_desc_t *pduDesc, uint16_t pduIndex, DlPageAlloc *pageAllocInfo,
3435 uint32_t payloadSize = 0;
3436 uint8_t *pagePayload = NULLP;
3437 fapi_api_queue_elem_t *payloadElem = NULLP;
3438 #ifdef INTEL_WLS_MEM
3439 void * wlsHdlr = NULLP;
3442 pduDesc[pduIndex].pdu_index = pduIndex;
3443 pduDesc[pduIndex].num_tlvs = 1;
3446 payloadSize = pdschCfg.codeword[0].tbSize;
3447 pduDesc[pduIndex].tlvs[0].tl.tag = ((payloadSize & 0xff0000) >> 8) | FAPI_TX_DATA_PTR_TO_PAYLOAD_64;
3448 pduDesc[pduIndex].tlvs[0].tl.length = (payloadSize & 0x0000ffff);
3449 LWR_MAC_ALLOC(pagePayload, payloadSize);
3450 if(pagePayload == NULLP)
3454 payloadElem = (fapi_api_queue_elem_t *)pagePayload;
3455 FILL_FAPI_LIST_ELEM(payloadElem, NULLP, FAPI_VENDOR_MSG_PHY_ZBC_BLOCK_REQ, 1, \
3456 pageAllocInfo->dlPagePduLen);
3457 memcpy(pagePayload + TX_PAYLOAD_HDR_LEN, pageAllocInfo->dlPagePdu, pageAllocInfo->dlPagePduLen);
3459 #ifdef INTEL_WLS_MEM
3460 mtGetWlsHdl(&wlsHdlr);
3461 pduDesc[pduIndex].tlvs[0].value = WLS_VA2PA(wlsHdlr, pagePayload);
3463 pduDesc[pduIndex].tlvs[0].value = pagePayload;
3465 pduDesc[pduIndex].pdu_length = payloadSize;
3467 #ifdef INTEL_WLS_MEM
3468 addWlsBlockToFree(pagePayload, payloadSize, (lwrMacCb.phySlotIndCntr-1));
3470 LWR_MAC_FREE(pagePayload, payloadSize);
3476 /***********************************************************************
3478 * @brief fills the RAR TX-DATA request message
3482 * Function : fillRarTxDataReq
3485 * - fills the RAR TX-DATA request message
3487 * @params[in] fapi_tx_pdu_desc_t *pduDesc
3488 * @params[in] RarInfo *rarInfo
3489 * @params[in] uint32_t *msgLen
3490 * @params[in] uint16_t pduIndex
3493 * ********************************************************************/
3494 uint8_t fillRarTxDataReq(fapi_tx_pdu_desc_t *pduDesc, uint16_t pduIndex, RarInfo *rarInfo, PdschCfg pdschCfg)
3496 uint16_t payloadSize;
3497 uint8_t *rarPayload = NULLP;
3498 fapi_api_queue_elem_t *payloadElem = NULLP;
3499 #ifdef INTEL_WLS_MEM
3500 void * wlsHdlr = NULLP;
3503 pduDesc[pduIndex].pdu_index = pduIndex;
3504 pduDesc[pduIndex].num_tlvs = 1;
3507 payloadSize = pdschCfg.codeword[0].tbSize;
3508 pduDesc[pduIndex].tlvs[0].tl.tag = FAPI_TX_DATA_PTR_TO_PAYLOAD_64;
3509 pduDesc[pduIndex].tlvs[0].tl.length = payloadSize;
3510 LWR_MAC_ALLOC(rarPayload, payloadSize);
3511 if(rarPayload == NULLP)
3515 payloadElem = (fapi_api_queue_elem_t *)rarPayload;
3516 FILL_FAPI_LIST_ELEM(payloadElem, NULLP, FAPI_VENDOR_MSG_PHY_ZBC_BLOCK_REQ, 1, rarInfo->rarPduLen);
3517 memcpy(rarPayload + TX_PAYLOAD_HDR_LEN, rarInfo->rarPdu, rarInfo->rarPduLen);
3519 #ifdef INTEL_WLS_MEM
3520 mtGetWlsHdl(&wlsHdlr);
3521 pduDesc[pduIndex].tlvs[0].value = WLS_VA2PA(wlsHdlr, rarPayload);
3523 pduDesc[pduIndex].tlvs[0].value = rarPayload;
3525 pduDesc[pduIndex].pdu_length = payloadSize;
3527 #ifdef INTEL_WLS_MEM
3528 addWlsBlockToFree(rarPayload, payloadSize, (lwrMacCb.phySlotIndCntr-1));
3530 LWR_MAC_FREE(rarPayload, payloadSize);
3535 /***********************************************************************
3537 * @brief fills the DL dedicated Msg TX-DATA request message
3541 * Function : fillDlMsgTxDataReq
3544 * - fills the Dl Dedicated Msg TX-DATA request message
3546 * @params[in] fapi_tx_pdu_desc_t *pduDesc
3547 * @params[in] DlMsgInfo *dlMsgInfo
3548 * @params[in] uint32_t *msgLen
3549 * @params[in] uint16_t pduIndex
3552 * ********************************************************************/
3553 uint8_t fillDlMsgTxDataReq(fapi_tx_pdu_desc_t *pduDesc, uint16_t pduIndex, DlMsgInfo *dlMsgInfo, PdschCfg pdschCfg)
3555 uint16_t payloadSize;
3556 uint8_t *dlMsgPayload = NULLP;
3557 fapi_api_queue_elem_t *payloadElem = NULLP;
3558 #ifdef INTEL_WLS_MEM
3559 void * wlsHdlr = NULLP;
3562 pduDesc[pduIndex].pdu_index = pduIndex;
3563 pduDesc[pduIndex].num_tlvs = 1;
3566 payloadSize = pdschCfg.codeword[0].tbSize;
3567 pduDesc[pduIndex].tlvs[0].tl.tag = FAPI_TX_DATA_PTR_TO_PAYLOAD_64;
3568 pduDesc[pduIndex].tlvs[0].tl.length = payloadSize;
3569 LWR_MAC_ALLOC(dlMsgPayload, payloadSize);
3570 if(dlMsgPayload == NULLP)
3574 payloadElem = (fapi_api_queue_elem_t *)dlMsgPayload;
3575 FILL_FAPI_LIST_ELEM(payloadElem, NULLP, FAPI_VENDOR_MSG_PHY_ZBC_BLOCK_REQ, 1, dlMsgInfo->dlMsgPduLen);
3576 memcpy(dlMsgPayload + TX_PAYLOAD_HDR_LEN, dlMsgInfo->dlMsgPdu, dlMsgInfo->dlMsgPduLen);
3578 #ifdef INTEL_WLS_MEM
3579 mtGetWlsHdl(&wlsHdlr);
3580 pduDesc[pduIndex].tlvs[0].value = WLS_VA2PA(wlsHdlr, dlMsgPayload);
3582 pduDesc[pduIndex].tlvs[0].value = dlMsgPayload;
3584 pduDesc[pduIndex].pdu_length = payloadSize;
3586 #ifdef INTEL_WLS_MEM
3587 addWlsBlockToFree(dlMsgPayload, payloadSize, (lwrMacCb.phySlotIndCntr-1));
3589 LWR_MAC_FREE(dlMsgPayload, payloadSize);
3596 /*******************************************************************
3598 * @brief Sends DL TTI Request to PHY
3602 * Function : fillDlTtiReq
3605 * -Sends FAPI DL TTI req to PHY
3607 * @params[in] timing info
3608 * @return ROK - success
3611 * ****************************************************************/
3612 uint16_t fillDlTtiReq(SlotTimingInfo currTimingInfo)
3614 #ifdef CALL_FLOW_DEBUG_LOG
3615 DU_LOG("\nCall Flow: ENTMAC -> ENTLWRMAC : DL_TTI_REQUEST\n");
3621 uint8_t numPduEncoded = 0;
3623 uint16_t cellIdx =0;
3624 uint16_t pduIndex = 0;
3626 SlotTimingInfo dlTtiReqTimingInfo;
3627 MacDlSlot *currDlSlot = NULLP;
3628 MacCellCfg macCellCfg;
3630 fapi_dl_tti_req_t *dlTtiReq = NULLP;
3631 fapi_msg_header_t *msgHeader = NULLP;
3632 p_fapi_api_queue_elem_t dlTtiElem;
3633 p_fapi_api_queue_elem_t headerElem;
3634 p_fapi_api_queue_elem_t prevElem;
3636 if(lwrMacCb.phyState == PHY_STATE_RUNNING)
3638 GET_CELL_IDX(currTimingInfo.cellId, cellIdx);
3639 /* consider phy delay */
3640 ADD_DELTA_TO_TIME(currTimingInfo,dlTtiReqTimingInfo,PHY_DELTA_DL);
3641 dlTtiReqTimingInfo.cellId = currTimingInfo.cellId;
3643 macCellCfg = macCb.macCell[cellIdx]->macCellCfg;
3645 currDlSlot = &macCb.macCell[cellIdx]->dlSlot[dlTtiReqTimingInfo.slot];
3647 LWR_MAC_ALLOC(dlTtiElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_dl_tti_req_t)));
3650 FILL_FAPI_LIST_ELEM(dlTtiElem, NULLP, FAPI_DL_TTI_REQUEST, 1, \
3651 sizeof(fapi_dl_tti_req_t));
3653 /* Fill message header */
3654 LWR_MAC_ALLOC(headerElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_msg_header_t)));
3657 DU_LOG("\nERROR --> LWR_MAC: Memory allocation failed for header in DL TTI req");
3658 LWR_MAC_FREE(dlTtiElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_dl_tti_req_t)));
3661 FILL_FAPI_LIST_ELEM(headerElem, dlTtiElem, FAPI_VENDOR_MSG_HEADER_IND, 1, \
3662 sizeof(fapi_msg_header_t));
3663 msgHeader = (fapi_msg_header_t *)(headerElem + 1);
3664 msgHeader->num_msg = 1;
3665 msgHeader->handle = 0;
3667 /* Fill Dl TTI Request */
3668 dlTtiReq = (fapi_dl_tti_req_t *)(dlTtiElem +1);
3669 memset(dlTtiReq, 0, sizeof(fapi_dl_tti_req_t));
3670 fillMsgHeader(&dlTtiReq->header, FAPI_DL_TTI_REQUEST, sizeof(fapi_dl_tti_req_t));
3672 dlTtiReq->sfn = dlTtiReqTimingInfo.sfn;
3673 dlTtiReq->slot = dlTtiReqTimingInfo.slot;
3674 dlTtiReq->nPdus = calcDlTtiReqPduCount(currDlSlot); /* get total Pdus */
3675 nPdu = dlTtiReq->nPdus;
3676 dlTtiReq->nGroup = 0;
3677 if(dlTtiReq->nPdus > 0)
3679 if(currDlSlot->dlInfo.isBroadcastPres)
3681 if(currDlSlot->dlInfo.brdcstAlloc.ssbTrans)
3683 if(dlTtiReq->pdus != NULLP)
3685 for(idx = 0; idx < currDlSlot->dlInfo.brdcstAlloc.ssbIdxSupported; idx++)
3687 fillSsbPdu(&dlTtiReq->pdus[numPduEncoded], &macCellCfg,\
3688 currDlSlot, idx, dlTtiReq->sfn);
3692 DU_LOG("\033[1;31m");
3693 DU_LOG("\nDEBUG --> LWR_MAC: MIB sent..");
3697 if(currDlSlot->dlInfo.brdcstAlloc.sib1Trans)
3699 /* Filling SIB1 param */
3700 if(numPduEncoded != nPdu)
3702 rntiType = SI_RNTI_TYPE;
3703 fillPdcchPdu(&dlTtiReq->pdus[numPduEncoded], currDlSlot, -1, \
3704 rntiType, CORESET_TYPE0, MAX_NUM_UE);
3706 fillPdschPdu(&dlTtiReq->pdus[numPduEncoded],
3707 &currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdschCfg,
3708 currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.bwp,
3710 dlTtiReq->ue_grp_info[dlTtiReq->nGroup].pduIdx[pduIndex] = pduIndex;
3714 DU_LOG("\033[1;34m");
3715 DU_LOG("\nDEBUG --> LWR_MAC: SIB1 sent...");
3720 if(currDlSlot->pageAllocInfo != NULLP)
3722 /* Filling DL Paging Alloc param */
3723 if(numPduEncoded != nPdu)
3725 rntiType = P_RNTI_TYPE;
3726 fillPdcchPdu(&dlTtiReq->pdus[numPduEncoded], currDlSlot, -1, \
3727 rntiType, CORESET_TYPE0, MAX_NUM_UE);
3729 fillPdschPdu(&dlTtiReq->pdus[numPduEncoded],
3730 &currDlSlot->pageAllocInfo->pagePdschCfg,
3731 currDlSlot->pageAllocInfo->bwp,
3733 dlTtiReq->ue_grp_info[dlTtiReq->nGroup].pduIdx[pduIndex] = pduIndex;
3737 DU_LOG("\033[1;34m");
3738 DU_LOG("\nDEBUG --> LWR_MAC: PAGE sent...");
3742 for(ueIdx=0; ueIdx<MAX_NUM_UE; ueIdx++)
3744 if(currDlSlot->dlInfo.rarAlloc[ueIdx] != NULLP)
3746 /* Filling RAR param */
3747 rntiType = RA_RNTI_TYPE;
3748 if((currDlSlot->dlInfo.rarAlloc[ueIdx]->pduPres == BOTH) || \
3749 (currDlSlot->dlInfo.rarAlloc[ueIdx]->pduPres == PDCCH_PDU))
3751 fillPdcchPdu(&dlTtiReq->pdus[numPduEncoded], \
3752 currDlSlot, -1, rntiType, CORESET_TYPE0, ueIdx);
3755 if((currDlSlot->dlInfo.rarAlloc[ueIdx]->pduPres == BOTH) || \
3756 (currDlSlot->dlInfo.rarAlloc[ueIdx]->pduPres == PDSCH_PDU))
3758 fillPdschPdu(&dlTtiReq->pdus[numPduEncoded],
3759 &currDlSlot->dlInfo.rarAlloc[ueIdx]->rarPdschCfg,
3760 currDlSlot->dlInfo.rarAlloc[ueIdx]->bwp,
3765 DU_LOG("\033[1;32m");
3766 DU_LOG("\nDEBUG --> LWR_MAC: RAR sent...");
3771 if(currDlSlot->dlInfo.dlMsgAlloc[ueIdx] != NULLP)
3773 for(idx=0; idx<currDlSlot->dlInfo.dlMsgAlloc[ueIdx]->numSchedInfo; idx++)
3775 /* Filling Msg4 param */
3776 if((currDlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[idx].pduPres == BOTH) || \
3777 (currDlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[idx].pduPres == PDCCH_PDU))
3779 if(currDlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[idx].dlMsgInfo.isMsg4Pdu)
3781 rntiType = TC_RNTI_TYPE;
3782 fillPdcchPdu(&dlTtiReq->pdus[numPduEncoded], \
3783 currDlSlot, idx, rntiType, CORESET_TYPE0, ueIdx);
3787 /* Filling other DL msg params */
3788 rntiType = C_RNTI_TYPE;
3789 fillPdcchPdu(&dlTtiReq->pdus[numPduEncoded], \
3790 currDlSlot, idx, rntiType, CORESET_TYPE1, ueIdx);
3795 if(currDlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[idx].dlMsgInfo.dlMsgPdu != NULLP)
3797 if((currDlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[idx].pduPres == BOTH) || \
3798 (currDlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[idx].pduPres == PDSCH_PDU))
3800 fillPdschPdu(&dlTtiReq->pdus[numPduEncoded], \
3801 &currDlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[idx].dlMsgPdschCfg,\
3802 currDlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[idx].bwp, pduIndex);
3806 DU_LOG("\033[1;32m");
3807 if(currDlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[idx].dlMsgInfo.isMsg4Pdu)
3809 DU_LOG("\nDEBUG --> LWR_MAC: MSG4 sent...");
3813 DU_LOG("\nDEBUG --> LWR_MAC: DL MSG sent...");
3821 MAC_FREE(currDlSlot->dlInfo.dlMsgAlloc[ueIdx], sizeof(DlMsgAlloc));
3822 currDlSlot->dlInfo.dlMsgAlloc[ueIdx] = NULLP;
3829 dlTtiReq->ue_grp_info[dlTtiReq->nGroup].nUe = MAX_NUM_UE_PER_TTI;
3832 #ifdef ODU_SLOT_IND_DEBUG_LOG
3833 DU_LOG("\nDEBUG --> LWR_MAC: Sending DL TTI Request");
3836 /* Intel L1 expects UL_TTI.request following DL_TTI.request */
3837 fillUlTtiReq(currTimingInfo, dlTtiElem);
3838 msgHeader->num_msg++;
3840 /* Intel L1 expects UL_DCI.request following DL_TTI.request */
3841 fillUlDciReq(dlTtiReqTimingInfo, dlTtiElem->p_next);
3842 msgHeader->num_msg++;
3844 /* send Tx-DATA req message */
3845 sendTxDataReq(dlTtiReqTimingInfo, currDlSlot, dlTtiElem->p_next->p_next);
3846 if(dlTtiElem->p_next->p_next->p_next)
3848 msgHeader->num_msg++;
3849 prevElem = dlTtiElem->p_next->p_next->p_next;
3852 prevElem = dlTtiElem->p_next->p_next;
3856 #ifdef ODU_SLOT_IND_DEBUG_LOG
3857 DU_LOG("\nDEBUG --> LWR_MAC: Sending DL TTI Request");
3860 /* Intel L1 expects UL_TTI.request following DL_TTI.request */
3861 fillUlTtiReq(currTimingInfo, dlTtiElem);
3862 msgHeader->num_msg++;
3864 /* Intel L1 expects UL_DCI.request following DL_TTI.request */
3865 fillUlDciReq(dlTtiReqTimingInfo, dlTtiElem->p_next);
3866 msgHeader->num_msg++;
3868 prevElem = dlTtiElem->p_next->p_next;
3871 if(macCb.macCell[cellIdx]->state == CELL_TO_BE_STOPPED)
3873 /* Intel L1 expects UL_DCI.request following DL_TTI.request */
3874 lwr_mac_procStopReqEvt(currTimingInfo, prevElem);
3875 msgHeader->num_msg++;
3876 macCb.macCell[cellIdx]->state = CELL_STOP_IN_PROGRESS;
3878 LwrMacSendToL1(headerElem);
3879 memset(currDlSlot, 0, sizeof(MacDlSlot));
3884 DU_LOG("\nERROR --> LWR_MAC: Failed to allocate memory for DL TTI Request");
3885 memset(currDlSlot, 0, sizeof(MacDlSlot));
3891 lwr_mac_procInvalidEvt(&currTimingInfo);
3898 /*******************************************************************
3900 * @brief Sends TX data Request to PHY
3904 * Function : sendTxDataReq
3907 * -Sends FAPI TX data req to PHY
3909 * @params[in] timing info
3910 * @return ROK - success
3913 * ****************************************************************/
3914 uint16_t sendTxDataReq(SlotTimingInfo currTimingInfo, MacDlSlot *dlSlot, p_fapi_api_queue_elem_t prevElem)
3917 #ifdef CALL_FLOW_DEBUG_LOG
3918 DU_LOG("\nCall Flow: ENTMAC -> ENTLWRMAC : TX_DATA_REQ\n");
3923 uint8_t schInfoIdx = 0;
3925 uint16_t pduIndex = 0;
3926 fapi_tx_data_req_t *txDataReq =NULLP;
3927 p_fapi_api_queue_elem_t txDataElem = 0;
3929 GET_CELL_IDX(currTimingInfo.cellId, cellIdx);
3931 /* send TX_Data request message */
3932 nPdu = calcTxDataReqPduCount(dlSlot);
3935 LWR_MAC_ALLOC(txDataElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_tx_data_req_t)));
3936 if(txDataElem == NULLP)
3938 DU_LOG("\nERROR --> LWR_MAC: Failed to allocate memory for TX data Request");
3942 FILL_FAPI_LIST_ELEM(txDataElem, NULLP, FAPI_TX_DATA_REQUEST, 1, \
3943 sizeof(fapi_tx_data_req_t));
3944 txDataReq = (fapi_tx_data_req_t *)(txDataElem +1);
3945 memset(txDataReq, 0, sizeof(fapi_tx_data_req_t));
3946 fillMsgHeader(&txDataReq->header, FAPI_TX_DATA_REQUEST, sizeof(fapi_tx_data_req_t));
3948 txDataReq->sfn = currTimingInfo.sfn;
3949 txDataReq->slot = currTimingInfo.slot;
3950 if(dlSlot->dlInfo.brdcstAlloc.sib1Trans)
3952 fillSib1TxDataReq(txDataReq->pdu_desc, pduIndex, &macCb.macCell[cellIdx]->macCellCfg, \
3953 dlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdschCfg);
3955 txDataReq->num_pdus++;
3957 if(dlSlot->pageAllocInfo != NULLP)
3959 fillPageTxDataReq(txDataReq->pdu_desc, pduIndex, dlSlot->pageAllocInfo, \
3960 dlSlot->pageAllocInfo->pagePdschCfg);
3962 txDataReq->num_pdus++;
3963 MAC_FREE(dlSlot->pageAllocInfo->dlPagePdu, sizeof(dlSlot->pageAllocInfo->dlPagePduLen));
3964 MAC_FREE(dlSlot->pageAllocInfo,sizeof(DlPageAlloc));
3967 for(ueIdx=0; ueIdx<MAX_NUM_UE; ueIdx++)
3969 if(dlSlot->dlInfo.rarAlloc[ueIdx] != NULLP)
3971 if((dlSlot->dlInfo.rarAlloc[ueIdx]->pduPres == BOTH) || (dlSlot->dlInfo.rarAlloc[ueIdx]->pduPres == PDSCH_PDU))
3973 fillRarTxDataReq(txDataReq->pdu_desc, pduIndex, &dlSlot->dlInfo.rarAlloc[ueIdx]->rarInfo,\
3974 dlSlot->dlInfo.rarAlloc[ueIdx]->rarPdschCfg);
3976 txDataReq->num_pdus++;
3978 MAC_FREE(dlSlot->dlInfo.rarAlloc[ueIdx],sizeof(RarAlloc));
3981 if(dlSlot->dlInfo.dlMsgAlloc[ueIdx] != NULLP)
3983 for(schInfoIdx=0; schInfoIdx < dlSlot->dlInfo.dlMsgAlloc[ueIdx]->numSchedInfo; schInfoIdx++)
3985 if((dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[schInfoIdx].pduPres == BOTH) || \
3986 (dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[schInfoIdx].pduPres == PDSCH_PDU))
3988 fillDlMsgTxDataReq(txDataReq->pdu_desc, pduIndex, \
3989 &dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[schInfoIdx].dlMsgInfo, \
3990 dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[schInfoIdx].dlMsgPdschCfg);
3992 txDataReq->num_pdus++;
3994 MAC_FREE(dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[schInfoIdx].dlMsgInfo.dlMsgPdu, \
3995 dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[schInfoIdx].dlMsgInfo.dlMsgPduLen);
3996 dlSlot->dlInfo.dlMsgAlloc[ueIdx]->dlMsgSchedInfo[schInfoIdx].dlMsgInfo.dlMsgPdu = NULLP;
3998 MAC_FREE(dlSlot->dlInfo.dlMsgAlloc[ueIdx], sizeof(DlMsgAlloc));
4002 /* Fill message header */
4003 DU_LOG("\nDEBUG --> LWR_MAC: Sending TX DATA Request");
4004 prevElem->p_next = txDataElem;
4010 /***********************************************************************
4012 * @brief calculates the total size to be allocated for UL TTI Req
4016 * Function : getnPdus
4019 * -calculates the total pdu count to be allocated for UL TTI Req
4021 * @params[in] Pointer to fapi Ul TTI Req
4022 * Pointer to CurrUlSlot
4024 * ********************************************************************/
4026 uint8_t getnPdus(fapi_ul_tti_req_t *ulTtiReq, MacUlSlot *currUlSlot)
4028 uint8_t pduCount = 0;
4030 if(ulTtiReq && currUlSlot)
4032 if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PRACH)
4035 ulTtiReq->rachPresent++;
4037 if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PUSCH)
4042 if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PUSCH_UCI)
4047 if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_UCI)
4052 if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_SRS)
4061 /***********************************************************************
4063 * @brief Set the value of zero correlation config in PRACH PDU
4067 * Function : setNumCs
4070 * -Set the value of zero correlation config in PRACH PDU
4072 * @params[in] Pointer to zero correlation config
4073 * Pointer to MacCellCfg
4074 * ********************************************************************/
4076 void setNumCs(uint16_t *numCs, MacCellCfg *macCellCfg)
4080 if(macCellCfg != NULLP)
4082 idx = macCellCfg->prachCfg.fdm[0].zeroCorrZoneCfg;
4083 *numCs = UnrestrictedSetNcsTable[idx];
4088 /***********************************************************************
4090 * @brief Fills the PRACH PDU in UL TTI Request
4094 * Function : fillPrachPdu
4097 * -Fills the PRACH PDU in UL TTI Request
4099 * @params[in] Pointer to Prach Pdu
4100 * Pointer to CurrUlSlot
4101 * Pointer to macCellCfg
4103 * ********************************************************************/
4106 void fillPrachPdu(fapi_ul_tti_req_pdu_t *ulTtiReqPdu, MacCellCfg *macCellCfg, MacUlSlot *currUlSlot)
4108 if(ulTtiReqPdu != NULLP)
4110 ulTtiReqPdu->pduType = PRACH_PDU_TYPE;
4111 ulTtiReqPdu->pdu.prach_pdu.physCellId = macCellCfg->phyCellId;
4112 ulTtiReqPdu->pdu.prach_pdu.numPrachOcas = \
4113 currUlSlot->ulInfo.prachSchInfo.numPrachOcas;
4114 ulTtiReqPdu->pdu.prach_pdu.prachFormat = \
4115 currUlSlot->ulInfo.prachSchInfo.prachFormat;
4116 ulTtiReqPdu->pdu.prach_pdu.numRa = currUlSlot->ulInfo.prachSchInfo.numRa;
4117 ulTtiReqPdu->pdu.prach_pdu.prachStartSymbol = \
4118 currUlSlot->ulInfo.prachSchInfo.prachStartSymb;
4119 setNumCs(&ulTtiReqPdu->pdu.prach_pdu.numCs, macCellCfg);
4120 ulTtiReqPdu->pdu.prach_pdu.beamforming.numPrgs = 0;
4121 ulTtiReqPdu->pdu.prach_pdu.beamforming.prgSize = 0;
4122 ulTtiReqPdu->pdu.prach_pdu.beamforming.digBfInterface = 0;
4123 ulTtiReqPdu->pdu.prach_pdu.beamforming.rx_bfi[0].beamIdx[0].beamidx = 0;
4124 ulTtiReqPdu->pduSize = sizeof(fapi_ul_prach_pdu_t);
4128 /*******************************************************************
4130 * @brief Filling PUSCH PDU in UL TTI Request
4134 * Function : fillPuschPdu
4136 * Functionality: Filling PUSCH PDU in UL TTI Request
4139 * @return ROK - success
4142 * ****************************************************************/
4143 void fillPuschPdu(fapi_ul_tti_req_pdu_t *ulTtiReqPdu, MacCellCfg *macCellCfg, MacUlSlot *currUlSlot)
4145 if(ulTtiReqPdu != NULLP)
4147 ulTtiReqPdu->pduType = PUSCH_PDU_TYPE;
4148 memset(&ulTtiReqPdu->pdu.pusch_pdu, 0, sizeof(fapi_ul_pusch_pdu_t));
4149 ulTtiReqPdu->pdu.pusch_pdu.pduBitMap = 1;
4150 ulTtiReqPdu->pdu.pusch_pdu.rnti = currUlSlot->ulInfo.crnti;
4151 /* TODO : Fill handle in raCb when scheduling pusch and access here */
4152 ulTtiReqPdu->pdu.pusch_pdu.handle = 100;
4153 ulTtiReqPdu->pdu.pusch_pdu.bwpSize = macCellCfg->initialUlBwp.bwp.numPrb;
4154 ulTtiReqPdu->pdu.pusch_pdu.bwpStart = macCellCfg->initialUlBwp.bwp.firstPrb;
4155 ulTtiReqPdu->pdu.pusch_pdu.subCarrierSpacing = \
4156 macCellCfg->initialUlBwp.bwp.scs;
4157 ulTtiReqPdu->pdu.pusch_pdu.cyclicPrefix = \
4158 macCellCfg->initialUlBwp.bwp.cyclicPrefix;
4159 ulTtiReqPdu->pdu.pusch_pdu.targetCodeRate = 308;
4160 ulTtiReqPdu->pdu.pusch_pdu.qamModOrder = currUlSlot->ulInfo.schPuschInfo.tbInfo.qamOrder;
4161 ulTtiReqPdu->pdu.pusch_pdu.mcsIndex = currUlSlot->ulInfo.schPuschInfo.tbInfo.mcs;
4162 ulTtiReqPdu->pdu.pusch_pdu.mcsTable = currUlSlot->ulInfo.schPuschInfo.tbInfo.mcsTable;
4163 ulTtiReqPdu->pdu.pusch_pdu.transformPrecoding = 1;
4164 ulTtiReqPdu->pdu.pusch_pdu.dataScramblingId = currUlSlot->ulInfo.cellId;
4165 ulTtiReqPdu->pdu.pusch_pdu.nrOfLayers = 1;
4166 ulTtiReqPdu->pdu.pusch_pdu.ulDmrsSymbPos = 4;
4167 ulTtiReqPdu->pdu.pusch_pdu.dmrsConfigType = 0;
4168 ulTtiReqPdu->pdu.pusch_pdu.ulDmrsScramblingId = currUlSlot->ulInfo.cellId;
4169 ulTtiReqPdu->pdu.pusch_pdu.scid = 0;
4170 ulTtiReqPdu->pdu.pusch_pdu.numDmrsCdmGrpsNoData = 1;
4171 ulTtiReqPdu->pdu.pusch_pdu.dmrsPorts = 0;
4172 ulTtiReqPdu->pdu.pusch_pdu.resourceAlloc = \
4173 currUlSlot->ulInfo.schPuschInfo.resAllocType;
4174 ulTtiReqPdu->pdu.pusch_pdu.rbStart = \
4175 currUlSlot->ulInfo.schPuschInfo.fdAlloc.startPrb;
4176 ulTtiReqPdu->pdu.pusch_pdu.rbSize = \
4177 currUlSlot->ulInfo.schPuschInfo.fdAlloc.numPrb;
4178 ulTtiReqPdu->pdu.pusch_pdu.vrbToPrbMapping = 0;
4179 ulTtiReqPdu->pdu.pusch_pdu.frequencyHopping = 0;
4180 ulTtiReqPdu->pdu.pusch_pdu.txDirectCurrentLocation = 0;
4181 ulTtiReqPdu->pdu.pusch_pdu.uplinkFrequencyShift7p5khz = 0;
4182 ulTtiReqPdu->pdu.pusch_pdu.startSymbIndex = \
4183 currUlSlot->ulInfo.schPuschInfo.tdAlloc.startSymb;
4184 ulTtiReqPdu->pdu.pusch_pdu.nrOfSymbols = \
4185 currUlSlot->ulInfo.schPuschInfo.tdAlloc.numSymb;
4186 ulTtiReqPdu->pdu.pusch_pdu.mappingType = \
4187 currUlSlot->ulInfo.schPuschInfo.dmrsMappingType;
4188 ulTtiReqPdu->pdu.pusch_pdu.nrOfDmrsSymbols = \
4189 currUlSlot->ulInfo.schPuschInfo.nrOfDmrsSymbols;
4190 ulTtiReqPdu->pdu.pusch_pdu.dmrsAddPos = \
4191 currUlSlot->ulInfo.schPuschInfo.dmrsAddPos;
4192 ulTtiReqPdu->pdu.pusch_pdu.puschData.rvIndex = \
4193 currUlSlot->ulInfo.schPuschInfo.tbInfo.rv;
4194 ulTtiReqPdu->pdu.pusch_pdu.puschData.harqProcessId = \
4195 currUlSlot->ulInfo.schPuschInfo.harqProcId;
4196 ulTtiReqPdu->pdu.pusch_pdu.puschData.newDataIndicator = \
4197 currUlSlot->ulInfo.schPuschInfo.tbInfo.ndi;
4198 ulTtiReqPdu->pdu.pusch_pdu.puschData.tbSize = \
4199 currUlSlot->ulInfo.schPuschInfo.tbInfo.tbSize;
4200 /* numCb is 0 for new transmission */
4201 ulTtiReqPdu->pdu.pusch_pdu.puschData.numCb = 0;
4203 ulTtiReqPdu->pduSize = sizeof(fapi_ul_pusch_pdu_t);
4207 /*******************************************************************
4209 * @brief Fill PUCCH PDU in Ul TTI Request
4213 * Function : fillPucchPdu
4215 * Functionality: Fill PUCCH PDU in Ul TTI Request
4218 * @return ROK - success
4221 * ****************************************************************/
4222 void fillPucchPdu(fapi_ul_tti_req_pdu_t *ulTtiReqPdu, MacCellCfg *macCellCfg,\
4223 MacUlSlot *currUlSlot)
4225 if(ulTtiReqPdu != NULLP)
4227 ulTtiReqPdu->pduType = PUCCH_PDU_TYPE;
4228 memset(&ulTtiReqPdu->pdu.pucch_pdu, 0, sizeof(fapi_ul_pucch_pdu_t));
4229 ulTtiReqPdu->pdu.pucch_pdu.rnti = currUlSlot->ulInfo.schPucchInfo.rnti;
4230 /* TODO : Fill handle in raCb when scheduling pucch and access here */
4231 ulTtiReqPdu->pdu.pucch_pdu.handle = 100;
4232 ulTtiReqPdu->pdu.pucch_pdu.bwpSize = macCellCfg->initialUlBwp.bwp.numPrb;
4233 ulTtiReqPdu->pdu.pucch_pdu.bwpStart = macCellCfg->initialUlBwp.bwp.firstPrb;
4234 ulTtiReqPdu->pdu.pucch_pdu.subCarrierSpacing = macCellCfg->initialUlBwp.bwp.scs;
4235 ulTtiReqPdu->pdu.pucch_pdu.cyclicPrefix = macCellCfg->initialUlBwp.bwp.cyclicPrefix;
4236 ulTtiReqPdu->pdu.pucch_pdu.formatType = currUlSlot->ulInfo.schPucchInfo.pucchFormat; /* Supporting PUCCH Format 0 */
4237 ulTtiReqPdu->pdu.pucch_pdu.multiSlotTxIndicator = 0; /* No Multi Slot transmission */
4239 ulTtiReqPdu->pdu.pucch_pdu.prbStart = currUlSlot->ulInfo.schPucchInfo.fdAlloc.startPrb;
4240 ulTtiReqPdu->pdu.pucch_pdu.prbSize = currUlSlot->ulInfo.schPucchInfo.fdAlloc.numPrb;
4241 ulTtiReqPdu->pdu.pucch_pdu.startSymbolIndex = currUlSlot->ulInfo.schPucchInfo.tdAlloc.startSymb;
4242 ulTtiReqPdu->pdu.pucch_pdu.nrOfSymbols = currUlSlot->ulInfo.schPucchInfo.tdAlloc.numSymb;
4243 ulTtiReqPdu->pdu.pucch_pdu.freqHopFlag = currUlSlot->ulInfo.schPucchInfo.intraFreqHop;
4244 ulTtiReqPdu->pdu.pucch_pdu.secondHopPrb = currUlSlot->ulInfo.schPucchInfo.secondPrbHop;
4245 ulTtiReqPdu->pdu.pucch_pdu.groupHopFlag = 0;
4246 ulTtiReqPdu->pdu.pucch_pdu.sequenceHopFlag = 0;
4247 ulTtiReqPdu->pdu.pucch_pdu.hoppingId = 0;
4249 ulTtiReqPdu->pdu.pucch_pdu.initialCyclicShift = currUlSlot->ulInfo.schPucchInfo.initialCyclicShift;
4251 ulTtiReqPdu->pdu.pucch_pdu.dataScramblingId = 0; /* Valid for Format 2, 3, 4 */
4252 ulTtiReqPdu->pdu.pucch_pdu.timeDomainOccIdx = currUlSlot->ulInfo.schPucchInfo.timeDomOCC;
4253 ulTtiReqPdu->pdu.pucch_pdu.preDftOccIdx = currUlSlot->ulInfo.schPucchInfo.occIdx; /* Valid for Format 4 only */
4254 ulTtiReqPdu->pdu.pucch_pdu.preDftOccLen = currUlSlot->ulInfo.schPucchInfo.occLen; /* Valid for Format 4 only */
4255 ulTtiReqPdu->pdu.pucch_pdu.pi2Bpsk = currUlSlot->ulInfo.schPucchInfo.cmnFormatCfg.pi2BPSK;
4256 ulTtiReqPdu->pdu.pucch_pdu.addDmrsFlag = currUlSlot->ulInfo.schPucchInfo.cmnFormatCfg.addDmrs;/* Valid for Format 3, 4 only */
4257 ulTtiReqPdu->pdu.pucch_pdu.dmrsScramblingId = 0; /* Valid for Format 2 */
4258 ulTtiReqPdu->pdu.pucch_pdu.dmrsCyclicShift = 0; /* Valid for Format 4 */
4259 ulTtiReqPdu->pdu.pucch_pdu.srFlag = currUlSlot->ulInfo.schPucchInfo.srFlag;
4260 ulTtiReqPdu->pdu.pucch_pdu.bitLenHarq = currUlSlot->ulInfo.schPucchInfo.numHarqBits;
4261 ulTtiReqPdu->pdu.pucch_pdu.bitLenCsiPart1 = 0; /* Valid for Format 2, 3, 4 */
4262 ulTtiReqPdu->pdu.pucch_pdu.bitLenCsiPart2 = 0; /* Valid for Format 2, 3, 4 */
4263 ulTtiReqPdu->pdu.pucch_pdu.beamforming.numPrgs = 0; /* Not Supported */
4264 ulTtiReqPdu->pdu.pucch_pdu.beamforming.prgSize = 0;
4265 ulTtiReqPdu->pdu.pucch_pdu.beamforming.digBfInterface = 0;
4266 ulTtiReqPdu->pdu.pucch_pdu.beamforming.rx_bfi[0].beamIdx[0].beamidx = 0;
4268 ulTtiReqPdu->pduSize = sizeof(fapi_ul_pucch_pdu_t);
4274 /*******************************************************************
4276 * @brief Sends UL TTI Request to PHY
4280 * Function : fillUlTtiReq
4283 * -Sends FAPI Param req to PHY
4285 * @params[in] Pointer to CmLteTimingInfo
4286 * @return ROK - success
4289 ******************************************************************/
4290 uint16_t fillUlTtiReq(SlotTimingInfo currTimingInfo, p_fapi_api_queue_elem_t prevElem)
4292 #ifdef CALL_FLOW_DEBUG_LOG
4293 DU_LOG("\nCall Flow: ENTMAC -> ENTLWRMAC : UL_TTI_REQUEST\n");
4297 uint16_t cellIdx =0;
4298 uint8_t pduIdx = -1;
4299 SlotTimingInfo ulTtiReqTimingInfo;
4300 MacUlSlot *currUlSlot = NULLP;
4301 MacCellCfg macCellCfg;
4302 fapi_ul_tti_req_t *ulTtiReq = NULLP;
4303 p_fapi_api_queue_elem_t ulTtiElem;
4305 if(lwrMacCb.phyState == PHY_STATE_RUNNING)
4307 GET_CELL_IDX(currTimingInfo.cellId, cellIdx);
4308 macCellCfg = macCb.macCell[cellIdx]->macCellCfg;
4311 ADD_DELTA_TO_TIME(currTimingInfo,ulTtiReqTimingInfo,PHY_DELTA_UL);
4312 currUlSlot = &macCb.macCell[cellIdx]->ulSlot[ulTtiReqTimingInfo.slot % MAX_SLOTS];
4314 LWR_MAC_ALLOC(ulTtiElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_ul_tti_req_t)));
4317 FILL_FAPI_LIST_ELEM(ulTtiElem, NULLP, FAPI_UL_TTI_REQUEST, 1, \
4318 sizeof(fapi_ul_tti_req_t));
4319 ulTtiReq = (fapi_ul_tti_req_t *)(ulTtiElem +1);
4320 memset(ulTtiReq, 0, sizeof(fapi_ul_tti_req_t));
4321 fillMsgHeader(&ulTtiReq->header, FAPI_UL_TTI_REQUEST, sizeof(fapi_ul_tti_req_t));
4322 ulTtiReq->sfn = ulTtiReqTimingInfo.sfn;
4323 ulTtiReq->slot = ulTtiReqTimingInfo.slot;
4324 ulTtiReq->nPdus = getnPdus(ulTtiReq, currUlSlot);
4325 ulTtiReq->nGroup = 0;
4326 if(ulTtiReq->nPdus > 0)
4328 /* Fill Prach Pdu */
4329 if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PRACH)
4332 fillPrachPdu(&ulTtiReq->pdus[pduIdx], &macCellCfg, currUlSlot);
4335 /* Fill PUSCH PDU */
4336 if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_PUSCH)
4339 fillPuschPdu(&ulTtiReq->pdus[pduIdx], &macCellCfg, currUlSlot);
4341 /* Fill PUCCH PDU */
4342 if(currUlSlot->ulInfo.dataType & SCH_DATATYPE_UCI)
4345 fillPucchPdu(&ulTtiReq->pdus[pduIdx], &macCellCfg, currUlSlot);
4349 #ifdef ODU_SLOT_IND_DEBUG_LOG
4350 DU_LOG("\nDEBUG --> LWR_MAC: Sending UL TTI Request");
4352 prevElem->p_next = ulTtiElem;
4354 memset(currUlSlot, 0, sizeof(MacUlSlot));
4359 DU_LOG("\nERROR --> LWR_MAC: Failed to allocate memory for UL TTI Request");
4360 memset(currUlSlot, 0, sizeof(MacUlSlot));
4366 lwr_mac_procInvalidEvt(&currTimingInfo);
4373 /*******************************************************************
4375 * @brief fills bsr Ul DCI PDU required for UL DCI Request to PHY
4379 * Function : fillUlDciPdu
4382 * -Fills the Ul DCI PDU, spec Ref:38.212, Table 7.3.1-1
4384 * @params[in] Pointer to fapi_dl_dci_t
4385 * Pointer to DciInfo
4388 ******************************************************************/
4389 void fillUlDciPdu(fapi_dl_dci_t *ulDciPtr, DciInfo *schDciInfo)
4391 #ifdef CALL_FLOW_DEBUG_LOG
4392 DU_LOG("\nCall Flow: ENTMAC -> ENTLWRMAC : UL_DCI_REQUEST\n");
4394 if(ulDciPtr != NULLP)
4396 uint8_t numBytes =0;
4400 uint8_t coreset1Size = 0;
4401 uint16_t rbStart = 0;
4403 uint8_t dciFormatId = 0;
4404 uint32_t freqDomResAssign =0;
4405 uint8_t timeDomResAssign =0;
4406 uint8_t freqHopFlag =0;
4407 uint8_t modNCodScheme =0;
4409 uint8_t redundancyVer = 0;
4410 uint8_t harqProcessNum = 0;
4411 uint8_t puschTpc = 0;
4412 uint8_t ul_SlInd = 0;
4414 /* Size(in bits) of each field in DCI format 0_0 */
4415 uint8_t dciFormatIdSize = 1;
4416 uint8_t freqDomResAssignSize = 0;
4417 uint8_t timeDomResAssignSize = 4;
4418 uint8_t freqHopFlagSize = 1;
4419 uint8_t modNCodSchemeSize = 5;
4420 uint8_t ndiSize = 1;
4421 uint8_t redundancyVerSize = 2;
4422 uint8_t harqProcessNumSize = 4;
4423 uint8_t puschTpcSize = 2;
4424 uint8_t ul_SlIndSize = 1;
4426 ulDciPtr->rnti = schDciInfo->dciInfo.rnti;
4427 ulDciPtr->scramblingId = schDciInfo->dciInfo.scramblingId;
4428 ulDciPtr->scramblingRnti = schDciInfo->dciInfo.scramblingRnti;
4429 ulDciPtr->cceIndex = schDciInfo->dciInfo.cceIndex;
4430 ulDciPtr->aggregationLevel = schDciInfo->dciInfo.aggregLevel;
4431 ulDciPtr->pc_and_bform.numPrgs = schDciInfo->dciInfo.beamPdcchInfo.numPrgs;
4432 ulDciPtr->pc_and_bform.prgSize = schDciInfo->dciInfo.beamPdcchInfo.prgSize;
4433 ulDciPtr->pc_and_bform.digBfInterfaces = schDciInfo->dciInfo.beamPdcchInfo.digBfInterfaces;
4434 ulDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = schDciInfo->dciInfo.beamPdcchInfo.prg[0].pmIdx;
4435 ulDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = schDciInfo->dciInfo.beamPdcchInfo.prg[0].beamIdx[0];
4436 ulDciPtr->beta_pdcch_1_0 = schDciInfo->dciInfo.txPdcchPower.powerValue;
4437 ulDciPtr->powerControlOffsetSS = schDciInfo->dciInfo.txPdcchPower.powerControlOffsetSS;
4439 /* Calculating freq domain resource allocation field value and size
4440 * coreset1Size = Size of coreset 1
4441 * RBStart = Starting Virtual Rsource block
4442 * RBLen = length of contiguously allocted RBs
4443 * Spec 38.214 Sec 5.1.2.2.2
4445 if(schDciInfo->formatType == FORMAT0_0)
4447 coreset1Size = schDciInfo->coresetCfg.coreSetSize;
4448 rbLen = schDciInfo->format.format0_0.freqAlloc.numPrb;
4449 rbStart = schDciInfo->format.format0_0.freqAlloc.startPrb;
4451 if((rbLen >=1) && (rbLen <= coreset1Size - rbStart))
4453 if((rbLen - 1) <= floor(coreset1Size / 2))
4454 freqDomResAssign = (coreset1Size * (rbLen-1)) + rbStart;
4456 freqDomResAssign = (coreset1Size * (coreset1Size - rbLen + 1)) \
4457 + (coreset1Size - 1 - rbStart);
4459 freqDomResAssignSize = ceil(log2(coreset1Size * (coreset1Size + 1) / 2));
4461 /* Fetching DCI field values */
4462 dciFormatId = schDciInfo->formatType; /* DCI indentifier for UL DCI */
4463 timeDomResAssign = schDciInfo->format.format0_0.rowIndex;
4464 freqHopFlag = schDciInfo->format.format0_0.freqHopFlag;
4465 modNCodScheme = schDciInfo->format.format0_0.mcs;
4466 ndi = schDciInfo->format.format0_0.ndi;
4467 redundancyVer = schDciInfo->format.format0_0.rv;
4468 harqProcessNum = schDciInfo->format.format0_0.harqProcId;
4469 puschTpc = schDciInfo->format.format0_0.tpcCmd;
4470 ul_SlInd = schDciInfo->format.format0_0.sUlCfgd;
4472 /* Reversing bits in each DCI field */
4473 dciFormatId = reverseBits(dciFormatId, dciFormatIdSize);
4474 freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize);
4475 timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize);
4476 modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize);
4477 redundancyVer = reverseBits(redundancyVer, redundancyVerSize);
4478 harqProcessNum = reverseBits(harqProcessNum, harqProcessNumSize);
4479 puschTpc = reverseBits(puschTpc, puschTpcSize);
4480 ul_SlInd = reverseBits(ul_SlInd, ul_SlIndSize);
4482 /* Calulating total number of bytes in buffer */
4483 ulDciPtr->payloadSizeBits = (dciFormatIdSize + freqDomResAssignSize\
4484 + timeDomResAssignSize + freqHopFlagSize + modNCodSchemeSize + ndi \
4485 + redundancyVerSize + harqProcessNumSize + puschTpcSize + ul_SlIndSize);
4487 numBytes = ulDciPtr->payloadSizeBits / 8;
4488 if(ulDciPtr->payloadSizeBits % 8)
4491 if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN)
4493 DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected");
4497 /* Initialize buffer */
4498 for(bytePos = 0; bytePos < numBytes; bytePos++)
4499 ulDciPtr->payload[bytePos] = 0;
4501 bytePos = numBytes - 1;
4504 /* Packing DCI format fields */
4505 fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
4506 dciFormatId, dciFormatIdSize);
4507 fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
4508 freqDomResAssign, freqDomResAssignSize);
4509 fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
4510 timeDomResAssign, timeDomResAssignSize);
4511 fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
4512 freqHopFlag, freqHopFlagSize);
4513 fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
4514 modNCodScheme, modNCodSchemeSize);
4515 fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
4517 fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
4518 redundancyVer, redundancyVerSize);
4519 fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
4520 harqProcessNum, harqProcessNumSize);
4521 fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
4522 puschTpc, puschTpcSize);
4523 fillDlDciPayload(ulDciPtr->payload, &bytePos, &bitPos,\
4524 ul_SlInd, ul_SlIndSize);
4526 } /* fillUlDciPdu */
4528 /*******************************************************************
4530 * @brief fills PDCCH PDU required for UL DCI REQ to PHY
4534 * Function : fillUlDciPdcchPdu
4537 * -Fills the Pdcch PDU info
4539 * @params[in] Pointer to FAPI DL TTI Req
4540 * Pointer to PdcchCfg
4543 ******************************************************************/
4544 uint8_t fillUlDciPdcchPdu(fapi_dci_pdu_t *ulDciReqPdu, DlSchedInfo *dlInfo, uint8_t coreSetType)
4546 if(ulDciReqPdu != NULLP)
4548 memset(&ulDciReqPdu->pdcchPduConfig, 0, sizeof(fapi_dl_pdcch_pdu_t));
4549 fillUlDciPdu(ulDciReqPdu->pdcchPduConfig.dlDci, dlInfo->ulGrant);
4550 ulDciReqPdu->pduType = PDCCH_PDU_TYPE;
4551 ulDciReqPdu->pdcchPduConfig.bwpSize = dlInfo->ulGrant->bwpCfg.freqAlloc.numPrb;
4552 ulDciReqPdu->pdcchPduConfig.bwpStart = dlInfo->ulGrant->bwpCfg.freqAlloc.startPrb;
4553 ulDciReqPdu->pdcchPduConfig.subCarrierSpacing = dlInfo->ulGrant->bwpCfg.subcarrierSpacing;
4554 ulDciReqPdu->pdcchPduConfig.cyclicPrefix = dlInfo->ulGrant->bwpCfg.cyclicPrefix;
4555 ulDciReqPdu->pdcchPduConfig.startSymbolIndex = dlInfo->ulGrant->coresetCfg.startSymbolIndex;
4556 ulDciReqPdu->pdcchPduConfig.durationSymbols = dlInfo->ulGrant->coresetCfg.durationSymbols;
4557 memcpy(ulDciReqPdu->pdcchPduConfig.freqDomainResource, dlInfo->ulGrant->coresetCfg.freqDomainResource, 6);
4558 ulDciReqPdu->pdcchPduConfig.cceRegMappingType = dlInfo->ulGrant->coresetCfg.cceRegMappingType;
4559 ulDciReqPdu->pdcchPduConfig.regBundleSize = dlInfo->ulGrant->coresetCfg.regBundleSize;
4560 ulDciReqPdu->pdcchPduConfig.interleaverSize = dlInfo->ulGrant->coresetCfg.interleaverSize;
4561 ulDciReqPdu->pdcchPduConfig.shiftIndex = dlInfo->ulGrant->coresetCfg.shiftIndex;
4562 ulDciReqPdu->pdcchPduConfig.precoderGranularity = dlInfo->ulGrant->coresetCfg.precoderGranularity;
4563 ulDciReqPdu->pdcchPduConfig.numDlDci = 1;
4564 ulDciReqPdu->pdcchPduConfig.coreSetType = coreSetType;
4566 /* Calculating PDU length. Considering only one Ul dci pdu for now */
4567 ulDciReqPdu->pduSize = sizeof(fapi_dl_pdcch_pdu_t);
4572 /*******************************************************************
4574 * @brief Sends UL DCI Request to PHY
4578 * Function : fillUlDciReq
4581 * -Sends FAPI Ul Dci req to PHY
4583 * @params[in] Pointer to CmLteTimingInfo
4584 * @return ROK - success
4587 ******************************************************************/
4588 uint16_t fillUlDciReq(SlotTimingInfo currTimingInfo, p_fapi_api_queue_elem_t prevElem)
4592 uint8_t numPduEncoded = 0;
4593 SlotTimingInfo ulDciReqTimingInfo ={0};
4594 MacDlSlot *currDlSlot = NULLP;
4595 fapi_ul_dci_req_t *ulDciReq =NULLP;
4596 p_fapi_api_queue_elem_t ulDciElem;
4598 if(lwrMacCb.phyState == PHY_STATE_RUNNING)
4600 GET_CELL_IDX(currTimingInfo.cellId, cellIdx);
4601 memcpy(&ulDciReqTimingInfo, &currTimingInfo, sizeof(SlotTimingInfo));
4602 currDlSlot = &macCb.macCell[cellIdx]->dlSlot[ulDciReqTimingInfo.slot % MAX_SLOTS];
4604 LWR_MAC_ALLOC(ulDciElem, (sizeof(fapi_api_queue_elem_t) + sizeof(fapi_ul_dci_req_t)));
4607 FILL_FAPI_LIST_ELEM(ulDciElem, NULLP, FAPI_UL_DCI_REQUEST, 1, \
4608 sizeof(fapi_ul_dci_req_t));
4609 ulDciReq = (fapi_ul_dci_req_t *)(ulDciElem +1);
4610 memset(ulDciReq, 0, sizeof(fapi_ul_dci_req_t));
4611 fillMsgHeader(&ulDciReq->header, FAPI_UL_DCI_REQUEST, sizeof(fapi_ul_dci_req_t));
4613 ulDciReq->sfn = ulDciReqTimingInfo.sfn;
4614 ulDciReq->slot = ulDciReqTimingInfo.slot;
4615 if(currDlSlot->dlInfo.ulGrant != NULLP)
4617 ulDciReq->numPdus = 1; // No. of PDCCH PDUs
4618 if(ulDciReq->numPdus > 0)
4620 /* Fill PDCCH configuration Pdu */
4621 fillUlDciPdcchPdu(&ulDciReq->pdus[numPduEncoded], &currDlSlot->dlInfo, CORESET_TYPE1);
4623 /* free UL GRANT at SCH */
4624 MAC_FREE(currDlSlot->dlInfo.ulGrant, sizeof(DciInfo));
4626 #ifdef ODU_SLOT_IND_DEBUG_LOG
4627 DU_LOG("\nDEBUG --> LWR_MAC: Sending UL DCI Request");
4630 prevElem->p_next = ulDciElem;
4635 lwr_mac_procInvalidEvt(&currTimingInfo);
4641 lwrMacFsmHdlr fapiEvtHdlr[MAX_STATE][MAX_EVENT] =
4644 /* PHY_STATE_IDLE */
4645 #ifdef INTEL_TIMER_MODE
4646 lwr_mac_procIqSamplesReqEvt,
4648 lwr_mac_procParamReqEvt,
4649 lwr_mac_procParamRspEvt,
4650 lwr_mac_procConfigReqEvt,
4651 lwr_mac_procConfigRspEvt,
4652 lwr_mac_procInvalidEvt,
4653 lwr_mac_procInvalidEvt,
4656 /* PHY_STATE_CONFIGURED */
4657 #ifdef INTEL_TIMER_MODE
4658 lwr_mac_procInvalidEvt,
4660 lwr_mac_procParamReqEvt,
4661 lwr_mac_procParamRspEvt,
4662 lwr_mac_procConfigReqEvt,
4663 lwr_mac_procConfigRspEvt,
4664 lwr_mac_procStartReqEvt,
4665 lwr_mac_procInvalidEvt,
4668 /* PHY_STATE_RUNNING */
4669 #ifdef INTEL_TIMER_MODE
4670 lwr_mac_procInvalidEvt,
4672 lwr_mac_procInvalidEvt,
4673 lwr_mac_procInvalidEvt,
4674 lwr_mac_procConfigReqEvt,
4675 lwr_mac_procConfigRspEvt,
4676 lwr_mac_procInvalidEvt,
4677 lwr_mac_procInvalidEvt,
4681 /*******************************************************************
4683 * @brief Sends message to LWR_MAC Fsm Event Handler
4687 * Function : sendToLowerMac
4690 * -Sends message to LowerMac
4692 * @params[in] Message Type
4698 ******************************************************************/
4699 void sendToLowerMac(uint16_t msgType, uint32_t msgLen, void *msg)
4701 lwrMacCb.event = msgType;
4702 fapiEvtHdlr[lwrMacCb.phyState][lwrMacCb.event](msg);
4704 /**********************************************************************
4706 **********************************************************************/