src/5gnrmac/lwr_mac.h

   1 /*******************************************************************************
   2 ################################################################################
   3 #   Copyright (c) [2017-2019] [Radisys]                                        #
   4 #                                                                              #
   5 #   Licensed under the Apache License, Version 2.0 (the "License");            #
   6 #   you may not use this file except in compliance with the License.           #
   7 #   You may obtain a copy of the License at                                    #
   8 #                                                                              #
   9 #       http://www.apache.org/licenses/LICENSE-2.0                             #
  10 #                                                                              #
  11 #   Unless required by applicable law or agreed to in writing, software        #
  12 #   distributed under the License is distributed on an "AS IS" BASIS,          #
  13 #   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.   #
  14 #   See the License for the specific language governing permissions and        #
  15 #   limitations under the License.                                             #
  16 ################################################################################
  17 *******************************************************************************/
  18
  19 /* Contains definitions for MAC CL modules */
  20 #ifndef __LWR_MAC_H__
  21 #define __LWR_MAC_H__
  22
  23 #ifdef INTEL_WLS_MEM
  24 #define LWR_MAC_ALLOC(_datPtr, _size)   WLS_MEM_ALLOC(_datPtr, _size);
  25 #else
  26 #define LWR_MAC_ALLOC(_datPtr, _size)   MAC_ALLOC(_datPtr, _size);
  27 #endif
  28
  29 #ifdef INTEL_WLS_MEM
  30 #define LWR_MAC_FREE(_datPtr, _size) WLS_MEM_FREE(_datPtr, _size);
  31 #else
  32 #define LWR_MAC_FREE(_datPtr, _size) MAC_FREE(_datPtr, _size);
  33 #endif
  34
  35 typedef enum
  36 {
  37    PHY_STATE_IDLE,
  38    PHY_STATE_CONFIGURED,
  39    PHY_STATE_RUNNING,
  40    MAX_STATE
  41 }PhyState;
  42
  43 /* Events in Lower Mac */
  44 typedef enum{
  45    PARAM_REQUEST,
  46    PARAM_RESPONSE,
  47    CONFIG_REQUEST,
  48    CONFIG_RESPONSE,
  49    START_REQUEST,
  50    STOP_REQUEST,
  51    MAX_EVENT
  52 }EventState;
  53
  54 typedef struct cellCb
  55 {
  56    uint16_t     cellId;
  57    uint16_t     phyCellId;
  58    PhyState     state;
  59 }LwrMacCellCb;
  60
  61 typedef struct lwrMacGlobalCb
  62 {
  63    Region          region;
  64    Pool            pool;
  65    bool            clCfgDone;   /* CL configuration done */
  66    LwrMacCellCb    cellCb[MAX_NUM_CELL];   /* List of Cells configured */
  67    uint8_t         numCell;  /* Number of Cells configured */
  68    PhyState        phyState;    /* State of PHY */
  69    EventState      event;       /* State of Event */
  70 }LwrMacCb;
  71
  72 typedef enum
  73 {
  74    FAPI_RELEASE_15
  75 }ReleaseCapab;
  76
  77 typedef enum
  78 {
  79    NOT_SUPPORTED,
  80    SUPPORTED
  81 }ParamSupport;
  82
  83 typedef enum
  84 {
  85    NORMAL_CYCLIC_PREFIX_MASK,
  86    EXTENDED_CYCLIC_PREFIX_MASK
  87 }CyclicPrefix;
  88
  89 typedef enum
  90 {
  91    SPACING_15_KHZ,
  92    SPACING_30_KHZ,
  93    SPACING_60_KHZ,
  94    SPACING_120_KHZ
  95 }SubCarrierSpacing;
  96
  97 typedef enum
  98 {
  99    BW_5MHZ,
 100    BW_10MHZ,
 101    BW_15MHZ,
 102    BW_20MHZ,
 103    BW_40MHZ,
 104    BW_50MHZ,
 105    BW_60MHZ,
 106    BW_70MHZ,
 107    BW_80MHZ,
 108    BW_90MHZ,
 109    BW_100MHZ,
 110    BW_200MHZ,
 111    BW_400MHZ
 112 }SupportedBandwidth;
 113
 114 typedef enum
 115 {
 116    CCE_MAPPING_INTERLEAVED_MASK,
 117    CCE_MAPPING_NONINTERLVD_MASK
 118 }CCEMappingType;
 119
 120 typedef enum
 121 {
 122    FORMAT_0,
 123    FORMAT_1,
 124    FORMAT_2,
 125    FORMAT_3,
 126    FORMAT_4
 127 }Formats;
 128
 129 typedef enum
 130 {
 131    MAPPING_TYPE_A,
 132    MAPPING_TYPE_B,
 133 }MappingType;
 134
 135 typedef enum
 136 {
 137    ALLOCATION_TYPE_0,
 138    ALLOCATION_TYPE_1,
 139 }AllocationType;
 140
 141 typedef enum
 142 {
 143    VRB_TO_PRB_MAP_NON_INTLV,
 144    VRB_TO_PRB_MAP_INTLVD
 145 }VrbToPrbMap;
 146
 147 typedef enum
 148 {
 149    DMRS_CONFIG_TYPE_1,
 150    DMRS_CONFIG_TYPE_2
 151 }DmrsConfigType;
 152
 153 typedef enum
 154 {
 155    DMRS_MAX_LENGTH_1,
 156    DMRS_MAX_LENGTH_2
 157 }DmrMaxLen;
 158
 159 typedef enum
 160 {
 161    DMRS_ADDITIONAL_POS_0,
 162    DMRS_ADDITIONAL_POS_1,
 163    DMRS_ADDITIONAL_POS_2,
 164    DMRS_ADDITIONAL_POS_3
 165 }DmrsPos;
 166
 167 typedef enum
 168 {
 169    MOD_QPSK,
 170    MOD_16QAM,
 171    MOD_64QAM,
 172    MOD_256QAM
 173 }ModulationOrder;
 174
 175 typedef enum
 176 {
 177    AGG_FACTOR_1,
 178    AGG_FACTOR_2,
 179    AGG_FACTOR_4,
 180    AGG_FACTOR_8
 181 }AggregationFactor;
 182
 183 typedef enum
 184 {
 185    SF_FORMAT_A1,
 186    SF_FORMAT_A2,
 187    SF_FORMAT_A3,
 188    SF_FORMAT_B1,
 189    SF_FORMAT_B2,
 190    SF_FORMAT_B3,
 191    SF_FORMAT_B4,
 192    SF_FORMAT_C0,
 193    SF_FORMAT_C2
 194 }ShortFormat;
 195
 196 typedef enum
 197 {
 198    PRACH_FD_OCC_IN_A_SLOT_1   = 1,
 199    PRACH_FD_OCC_IN_A_SLOT_2   = 2,
 200    PRACH_FD_OCC_IN_A_SLOT_4   = 4,
 201    PRACH_FD_OCC_IN_A_SLOT_8   = 8
 202 }FdOccPerSlot;
 203
 204 typedef enum
 205 {
 206    RSSI_REPORT_DBM,
 207    RSSI_REPORT_DBFS
 208 }RssiMeasurement;
 209
 210 typedef struct clCellParam
 211 {
 212    ReleaseCapab          releaseCapability;                    /* Release Capability */
 213    PhyState              ParamPhystate;
 214    ParamSupport          skipBlankDlConfig;
 215    ParamSupport          skipBlankUlConfig;
 216    ParamSupport          numTlvsToReport;
 217    CyclicPrefix          cyclicPrefix;
 218    SubCarrierSpacing     supportedSubcarrierSpacingDl;
 219    SupportedBandwidth    supportedBandwidthDl;
 220    SubCarrierSpacing     supportedSubcarrierSpacingsUl;
 221    SupportedBandwidth    supportedBandwidthUl;
 222    CCEMappingType        cceMappingType;
 223    ParamSupport          coresetOutsideFirst3OfdmSymsOfSlot;
 224    ParamSupport          precoderGranularityCoreset;
 225    ParamSupport          pdcchMuMimo;
 226    ParamSupport          pdcchPrecoderCycling;
 227    uint8_t               maxPdcchsPerSlot;
 228    Formats               pucchFormats;
 229    uint8_t               maxPucchsPerSlot;
 230    MappingType           pdschMappingType;
 231    AllocationType        pdschAllocationTypes;
 232    VrbToPrbMap           pdschVrbToPrbMapping;
 233    ParamSupport          pdschCbg;
 234    DmrsConfigType        pdschDmrsConfigTypes;
 235    DmrMaxLen             pdschDmrsMaxLength;
 236    DmrsPos               pdschDmrsAdditionalPos;
 237    uint8_t               maxPdschsTBsPerSlot;
 238    uint8_t               maxNumberMimoLayersPdsch;
 239    ModulationOrder       supportedMaxModulationOrderDl;
 240    uint8_t               maxMuMimoUsersDl;
 241    ParamSupport          pdschDataInDmrsSymbols;
 242    ParamSupport          premptionSupport;
 243    ParamSupport          pdschNonSlotSupport;
 244    ParamSupport          uciMuxUlschInPusch;
 245    ParamSupport          uciOnlyPusch;
 246    ParamSupport          puschFrequencyHopping;
 247    DmrsConfigType        puschDmrsConfigTypes;
 248    DmrMaxLen             puschDmrsMaxLength;
 249    DmrsPos               puschDmrsAdditionalPos;
 250    ParamSupport          puschCbg;
 251    MappingType           puschMappingType;
 252    AllocationType        puschAllocationTypes;
 253    VrbToPrbMap           puschVrbToPrbMapping;
 254    uint8_t               puschMaxPtrsPorts;
 255    uint8_t               maxPduschsTBsPerSlot;
 256    uint8_t               maxNumberMimoLayersNonCbPusch;
 257    ModulationOrder       supportedModulationOrderUl;
 258    uint8_t               maxMuMimoUsersUl;
 259    ParamSupport          dftsOfdmSupport;
 260    AggregationFactor     puschAggregationFactor;
 261    Formats                prachLongFormats;
 262    ShortFormat           prachShortFormats;
 263    ParamSupport          prachRestrictedSets;
 264    FdOccPerSlot          maxPrachFdOccasionsInASlot;
 265    RssiMeasurement       rssiMeasurementSupport;
 266 }ClCellParam;
 267
 268 LwrMacCb lwrMacCb;
 269 LwrMacCellCb * lwrMacGetCellCb ARGS((uint16_t cellId));
 270 uint32_t reverseBits(uint32_t num, uint8_t numBits);
 271 void fillDlDciPayload(uint8_t *buf, uint8_t *bytePos, uint8_t *bitPos,\
 272       uint32_t val, uint8_t valSize);
 273 void lwrMacLayerInit();
 274
 275 #endif
 276
 277 /**********************************************************************
 278   End of file
 279  **********************************************************************/