src/5gnrmac/lwr_mac.h

   1 /*******************************************************************************
   2 ################################################################################
   3 #   Copyright (c) [2017-2019] [Radisys]                                        #
   4 #                                                                              #
   5 #   Licensed under the Apache License, Version 2.0 (the "License");            #
   6 #   you may not use this file except in compliance with the License.           #
   7 #   You may obtain a copy of the License at                                    #
   8 #                                                                              #
   9 #       http://www.apache.org/licenses/LICENSE-2.0                             #
  10 #                                                                              #
  11 #   Unless required by applicable law or agreed to in writing, software        #
  12 #   distributed under the License is distributed on an "AS IS" BASIS,          #
  13 #   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.   #
  14 #   See the License for the specific language governing permissions and        #
  15 #   limitations under the License.                                             #
  16 ################################################################################
  17 *******************************************************************************/
  18
  19 /* Contains definitions for MAC CL modules */
  20 #ifndef __LWR_MAC_H__
  21 #define __LWR_MAC_H__
  22
  23 #define MAX_NUM_CELL_SUPP 1
  24
  25 #include "envdep.h"
  26 #include "gen.h"
  27 #include "ssi.h"
  28 #include "cm_hash.h"
  29
  30 #include "gen.x"
  31 #include "ssi.x"
  32 #include "cm_hash.x"
  33 #include "cm_lib.x"
  34 #include "du_app_mac_inf.h"
  35
  36 typedef enum
  37 {
  38    PHY_STATE_IDLE,
  39    PHY_STATE_CONFIGURED,
  40    PHY_STATE_RUNNING,
  41    MAX_STATE
  42 }PhyState;
  43
  44 /* Events in Lower Mac */
  45 typedef enum{
  46   PARAM_REQ,
  47   PARAM_RSP,
  48   CONFIG_REQ,
  49   CONFIG_RSP,
  50   START_REQ,
  51   STOP_REQ,
  52   MAX_EVENT
  53 }EventState;
  54
  55 typedef struct clCb
  56 {
  57    Region          region;
  58    Pool            pool;
  59    Bool            clCfgDone;   /* CL configuration done */
  60    CmHashListCp    cellCbLst;   /* List of Cells configured */
  61    U8              numOfCells;  /* Number of Cells configured */
  62    PhyState        phyState;    /* State of PHY */
  63    EventState      event;       /* State of Event */
  64 }ClCb;
  65
  66 typedef struct cellCb
  67 {
  68    U16         cellId;
  69    MacCellCfg   cellCfg;
  70    PhyState    phyState;
  71 }ClCellCb;
  72
  73 typedef enum
  74 {
  75    RELEASE_15
  76 }ReleaseCapab;
  77
  78 typedef enum
  79 {
  80    NOT_SUPPORTED,
  81    SUPPORTED
  82 }ParamSupport;
  83
  84 typedef enum
  85 {
  86    NORMAL_CYCLIC_PREFIX_MASK,
  87    EXTENDED_CYCLIC_PREFIX_MASK
  88 }CyclicPrefix;
  89
  90 typedef enum
  91 {
  92    SPACING_15_KHZ,
  93    SPACING_30_KHZ,
  94    SPACING_60_KHZ,
  95    SPACING_120_KHZ
  96 }SubCarrierSpacing;
  97
  98 typedef enum
  99 {
 100    BW_5MHZ,
 101    BW_10MHZ,
 102    BW_15MHZ,
 103    BW_20MHZ,
 104    BW_40MHZ,
 105    BW_50MHZ,
 106    BW_60MHZ,
 107    BW_70MHZ,
 108    BW_80MHZ,
 109    BW_90MHZ,
 110    BW_100MHZ,
 111    BW_200MHZ,
 112    BW_400MHZ
 113 }SupportedBandwidth;
 114
 115 typedef enum
 116 {
 117    CCE_MAPPING_INTERLEAVED_MASK,
 118    CCE_MAPPING_NONINTERLVD_MASK
 119 }CCEMappingType;
 120
 121 typedef enum
 122 {
 123    FORMAT_0,
 124    FORMAT_1,
 125    FORMAT_2,
 126    FORMAT_3,
 127    FORMAT_4
 128 }Formats;
 129
 130 typedef enum
 131 {
 132    MAPPING_TYPE_A,
 133    MAPPING_TYPE_B,
 134 }MappingType;
 135
 136 typedef enum
 137 {
 138    ALLOCATION_TYPE_0,
 139    ALLOCATION_TYPE_1,
 140 }AllocationType;
 141
 142 typedef enum
 143 {
 144    VRB_TO_PRB_MAP_NON_INTLV,
 145    VRB_TO_PRB_MAP_INTLVD
 146 }VrbToPrbMap;
 147
 148 typedef enum
 149 {
 150    DMRS_CONFIG_TYPE_1,
 151    DMRS_CONFIG_TYPE_2
 152 }DmrsConfigType;
 153
 154 typedef enum
 155 {
 156    DMRS_MAX_LENGTH_1,
 157    DMRS_MAX_LENGTH_2
 158 }DmrMaxLen;
 159
 160 typedef enum
 161 {
 162    DMRS_ADDITIONAL_POS_0,
 163    DMRS_ADDITIONAL_POS_1,
 164    DMRS_ADDITIONAL_POS_2,
 165    DMRS_ADDITIONAL_POS_3
 166 }DmrsPos;
 167
 168 typedef enum
 169 {
 170    MOD_QPSK,
 171    MOD_16QAM,
 172    MOD_64QAM,
 173    MOD_256QAM
 174 }ModulationOrder;
 175
 176 typedef enum
 177 {
 178    AGG_FACTOR_1,
 179    AGG_FACTOR_2,
 180    AGG_FACTOR_4,
 181    AGG_FACTOR_8
 182 }AggregationFactor;
 183
 184 typedef enum
 185 {
 186    SF_FORMAT_A1,
 187    SF_FORMAT_A2,
 188    SF_FORMAT_A3,
 189    SF_FORMAT_B1,
 190    SF_FORMAT_B2,
 191    SF_FORMAT_B3,
 192    SF_FORMAT_B4,
 193    SF_FORMAT_C0,
 194    SF_FORMAT_C2
 195 }ShortFormat;
 196
 197 typedef enum
 198 {
 199    PRACH_FD_OCC_IN_A_SLOT_1   = 1,
 200    PRACH_FD_OCC_IN_A_SLOT_2   = 2,
 201    PRACH_FD_OCC_IN_A_SLOT_4   = 4,
 202    PRACH_FD_OCC_IN_A_SLOT_8   = 8
 203 }FdOccPerSlot;
 204
 205 typedef enum
 206 {
 207    RSSI_REPORT_DBM,
 208    RSSI_REPORT_DBFS
 209 }RssiMeasurement;
 210
 211 typedef struct clCellParam
 212 {
 213    ReleaseCapab          releaseCapability;                    /* Release Capability */
 214    PhyState              ParamPhystate;
 215    ParamSupport          skipBlankDlConfig;
 216    ParamSupport          skipBlankUlConfig;
 217    ParamSupport          numTlvsToReport;
 218    CyclicPrefix          cyclicPrefix;
 219    SubCarrierSpacing     supportedSubcarrierSpacingDl;
 220    SupportedBandwidth    supportedBandwidthDl;
 221    SubCarrierSpacing     supportedSubcarrierSpacingsUl;
 222    SupportedBandwidth    supportedBandwidthUl;
 223    CCEMappingType        cceMappingType;
 224    ParamSupport          coresetOutsideFirst3OfdmSymsOfSlot;
 225    ParamSupport          precoderGranularityCoreset;
 226    ParamSupport          pdcchMuMimo;
 227    ParamSupport          pdcchPrecoderCycling;
 228    U8                    maxPdcchsPerSlot;
 229    Formats               pucchFormats;
 230    U8                    maxPucchsPerSlot;
 231    MappingType           pdschMappingType;
 232    AllocationType        pdschAllocationTypes;
 233    VrbToPrbMap           pdschVrbToPrbMapping;
 234    ParamSupport          pdschCbg;
 235    DmrsConfigType        pdschDmrsConfigTypes;
 236    DmrMaxLen             pdschDmrsMaxLength;
 237    DmrsPos               pdschDmrsAdditionalPos;
 238    U8                    maxPdschsTBsPerSlot;
 239    U8                    maxNumberMimoLayersPdsch;
 240    ModulationOrder       supportedMaxModulationOrderDl;
 241    U8                    maxMuMimoUsersDl;
 242    ParamSupport          pdschDataInDmrsSymbols;
 243    ParamSupport          premptionSupport;
 244    ParamSupport          pdschNonSlotSupport;
 245    ParamSupport          uciMuxUlschInPusch;
 246    ParamSupport          uciOnlyPusch;
 247    ParamSupport          puschFrequencyHopping;
 248    DmrsConfigType        puschDmrsConfigTypes;
 249    DmrMaxLen             puschDmrsMaxLength;
 250    DmrsPos               puschDmrsAdditionalPos;
 251    ParamSupport          puschCbg;
 252    MappingType           puschMappingType;
 253    AllocationType        puschAllocationTypes;
 254    VrbToPrbMap           puschVrbToPrbMapping;
 255    U8                    puschMaxPtrsPorts;
 256    U8                    maxPduschsTBsPerSlot;
 257    U8                    maxNumberMimoLayersNonCbPusch;
 258    ModulationOrder       supportedModulationOrderUl;
 259    U8                    maxMuMimoUsersUl;
 260    ParamSupport          dftsOfdmSupport;
 261    AggregationFactor     puschAggregationFactor;
 262    Formats                prachLongFormats;
 263    ShortFormat           prachShortFormats;
 264    ParamSupport          prachRestrictedSets;
 265    FdOccPerSlot          maxPrachFdOccasionsInASlot;
 266    RssiMeasurement       rssiMeasurementSupport;
 267 }ClCellParam;
 268
 269
 270 EXTERN ClCb clGlobalCp;
 271 EXTERN ClCellCb * rgClUtlGetCellCb ARGS((U16 cellId));
 272
 273 #endif
 274
 275 /**********************************************************************
 276          End of file
 277 **********************************************************************/