src/5gnrmac/lwr_mac.h

   1 /*******************************************************************************
   2 ################################################################################
   3 #   Copyright (c) [2017-2019] [Radisys]                                        #
   4 #                                                                              #
   5 #   Licensed under the Apache License, Version 2.0 (the "License");            #
   6 #   you may not use this file except in compliance with the License.           #
   7 #   You may obtain a copy of the License at                                    #
   8 #                                                                              #
   9 #       http://www.apache.org/licenses/LICENSE-2.0                             #
  10 #                                                                              #
  11 #   Unless required by applicable law or agreed to in writing, software        #
  12 #   distributed under the License is distributed on an "AS IS" BASIS,          #
  13 #   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.   #
  14 #   See the License for the specific language governing permissions and        #
  15 #   limitations under the License.                                             #
  16 ################################################################################
  17 *******************************************************************************/
  18
  19 /* Contains definitions for MAC CL modules */
  20 #ifndef __LWR_MAC_H__
  21 #define __LWR_MAC_H__
  22
  23 #define MAX_NUM_CELL_SUPP 1
  24
  25 #include "du_app_mac_inf.h"
  26
  27 #ifdef INTEL_WLS
  28 #define LWR_MAC_ALLOC(_datPtr, _size)   WLS_MEM_ALLOC(_datPtr, _size);
  29 #else
  30 #define LWR_MAC_ALLOC(_datPtr, _size)   MAC_ALLOC(_datPtr, _size);
  31 #endif
  32
  33 typedef enum
  34 {
  35    PHY_STATE_IDLE,
  36    PHY_STATE_CONFIGURED,
  37    PHY_STATE_RUNNING,
  38    MAX_STATE
  39 }PhyState;
  40
  41 /* Events in Lower Mac */
  42 typedef enum{
  43   PARAM_REQUEST,
  44   PARAM_RESPONSE,
  45   CONFIG_REQUEST,
  46   CONFIG_RESPONSE,
  47   START_REQUEST,
  48   STOP_REQUEST,
  49   MAX_EVENT
  50 }EventState;
  51
  52 typedef struct clCb
  53 {
  54    Region          region;
  55    Pool            pool;
  56    Bool            clCfgDone;   /* CL configuration done */
  57    CmHashListCp    cellCbLst;   /* List of Cells configured */
  58    U8              numOfCells;  /* Number of Cells configured */
  59    PhyState        phyState;    /* State of PHY */
  60    EventState      event;       /* State of Event */
  61 }ClCb;
  62
  63 typedef struct cellCb
  64 {
  65    U16         cellId;
  66    MacCellCfg   cellCfg;
  67    PhyState    phyState;
  68 }ClCellCb;
  69
  70 typedef enum
  71 {
  72    FAPI_RELEASE_15
  73 }ReleaseCapab;
  74
  75 typedef enum
  76 {
  77    NOT_SUPPORTED,
  78    SUPPORTED
  79 }ParamSupport;
  80
  81 typedef enum
  82 {
  83    NORMAL_CYCLIC_PREFIX_MASK,
  84    EXTENDED_CYCLIC_PREFIX_MASK
  85 }CyclicPrefix;
  86
  87 typedef enum
  88 {
  89    SPACING_15_KHZ,
  90    SPACING_30_KHZ,
  91    SPACING_60_KHZ,
  92    SPACING_120_KHZ
  93 }SubCarrierSpacing;
  94
  95 typedef enum
  96 {
  97    BW_5MHZ,
  98    BW_10MHZ,
  99    BW_15MHZ,
 100    BW_20MHZ,
 101    BW_40MHZ,
 102    BW_50MHZ,
 103    BW_60MHZ,
 104    BW_70MHZ,
 105    BW_80MHZ,
 106    BW_90MHZ,
 107    BW_100MHZ,
 108    BW_200MHZ,
 109    BW_400MHZ
 110 }SupportedBandwidth;
 111
 112 typedef enum
 113 {
 114    CCE_MAPPING_INTERLEAVED_MASK,
 115    CCE_MAPPING_NONINTERLVD_MASK
 116 }CCEMappingType;
 117
 118 typedef enum
 119 {
 120    FORMAT_0,
 121    FORMAT_1,
 122    FORMAT_2,
 123    FORMAT_3,
 124    FORMAT_4
 125 }Formats;
 126
 127 typedef enum
 128 {
 129    MAPPING_TYPE_A,
 130    MAPPING_TYPE_B,
 131 }MappingType;
 132
 133 typedef enum
 134 {
 135    ALLOCATION_TYPE_0,
 136    ALLOCATION_TYPE_1,
 137 }AllocationType;
 138
 139 typedef enum
 140 {
 141    VRB_TO_PRB_MAP_NON_INTLV,
 142    VRB_TO_PRB_MAP_INTLVD
 143 }VrbToPrbMap;
 144
 145 typedef enum
 146 {
 147    DMRS_CONFIG_TYPE_1,
 148    DMRS_CONFIG_TYPE_2
 149 }DmrsConfigType;
 150
 151 typedef enum
 152 {
 153    DMRS_MAX_LENGTH_1,
 154    DMRS_MAX_LENGTH_2
 155 }DmrMaxLen;
 156
 157 typedef enum
 158 {
 159    DMRS_ADDITIONAL_POS_0,
 160    DMRS_ADDITIONAL_POS_1,
 161    DMRS_ADDITIONAL_POS_2,
 162    DMRS_ADDITIONAL_POS_3
 163 }DmrsPos;
 164
 165 typedef enum
 166 {
 167    MOD_QPSK,
 168    MOD_16QAM,
 169    MOD_64QAM,
 170    MOD_256QAM
 171 }ModulationOrder;
 172
 173 typedef enum
 174 {
 175    AGG_FACTOR_1,
 176    AGG_FACTOR_2,
 177    AGG_FACTOR_4,
 178    AGG_FACTOR_8
 179 }AggregationFactor;
 180
 181 typedef enum
 182 {
 183    SF_FORMAT_A1,
 184    SF_FORMAT_A2,
 185    SF_FORMAT_A3,
 186    SF_FORMAT_B1,
 187    SF_FORMAT_B2,
 188    SF_FORMAT_B3,
 189    SF_FORMAT_B4,
 190    SF_FORMAT_C0,
 191    SF_FORMAT_C2
 192 }ShortFormat;
 193
 194 typedef enum
 195 {
 196    PRACH_FD_OCC_IN_A_SLOT_1   = 1,
 197    PRACH_FD_OCC_IN_A_SLOT_2   = 2,
 198    PRACH_FD_OCC_IN_A_SLOT_4   = 4,
 199    PRACH_FD_OCC_IN_A_SLOT_8   = 8
 200 }FdOccPerSlot;
 201
 202 typedef enum
 203 {
 204    RSSI_REPORT_DBM,
 205    RSSI_REPORT_DBFS
 206 }RssiMeasurement;
 207
 208 typedef struct clCellParam
 209 {
 210    ReleaseCapab          releaseCapability;                    /* Release Capability */
 211    PhyState              ParamPhystate;
 212    ParamSupport          skipBlankDlConfig;
 213    ParamSupport          skipBlankUlConfig;
 214    ParamSupport          numTlvsToReport;
 215    CyclicPrefix          cyclicPrefix;
 216    SubCarrierSpacing     supportedSubcarrierSpacingDl;
 217    SupportedBandwidth    supportedBandwidthDl;
 218    SubCarrierSpacing     supportedSubcarrierSpacingsUl;
 219    SupportedBandwidth    supportedBandwidthUl;
 220    CCEMappingType        cceMappingType;
 221    ParamSupport          coresetOutsideFirst3OfdmSymsOfSlot;
 222    ParamSupport          precoderGranularityCoreset;
 223    ParamSupport          pdcchMuMimo;
 224    ParamSupport          pdcchPrecoderCycling;
 225    U8                    maxPdcchsPerSlot;
 226    Formats               pucchFormats;
 227    U8                    maxPucchsPerSlot;
 228    MappingType           pdschMappingType;
 229    AllocationType        pdschAllocationTypes;
 230    VrbToPrbMap           pdschVrbToPrbMapping;
 231    ParamSupport          pdschCbg;
 232    DmrsConfigType        pdschDmrsConfigTypes;
 233    DmrMaxLen             pdschDmrsMaxLength;
 234    DmrsPos               pdschDmrsAdditionalPos;
 235    U8                    maxPdschsTBsPerSlot;
 236    U8                    maxNumberMimoLayersPdsch;
 237    ModulationOrder       supportedMaxModulationOrderDl;
 238    U8                    maxMuMimoUsersDl;
 239    ParamSupport          pdschDataInDmrsSymbols;
 240    ParamSupport          premptionSupport;
 241    ParamSupport          pdschNonSlotSupport;
 242    ParamSupport          uciMuxUlschInPusch;
 243    ParamSupport          uciOnlyPusch;
 244    ParamSupport          puschFrequencyHopping;
 245    DmrsConfigType        puschDmrsConfigTypes;
 246    DmrMaxLen             puschDmrsMaxLength;
 247    DmrsPos               puschDmrsAdditionalPos;
 248    ParamSupport          puschCbg;
 249    MappingType           puschMappingType;
 250    AllocationType        puschAllocationTypes;
 251    VrbToPrbMap           puschVrbToPrbMapping;
 252    U8                    puschMaxPtrsPorts;
 253    U8                    maxPduschsTBsPerSlot;
 254    U8                    maxNumberMimoLayersNonCbPusch;
 255    ModulationOrder       supportedModulationOrderUl;
 256    U8                    maxMuMimoUsersUl;
 257    ParamSupport          dftsOfdmSupport;
 258    AggregationFactor     puschAggregationFactor;
 259    Formats                prachLongFormats;
 260    ShortFormat           prachShortFormats;
 261    ParamSupport          prachRestrictedSets;
 262    FdOccPerSlot          maxPrachFdOccasionsInASlot;
 263    RssiMeasurement       rssiMeasurementSupport;
 264 }ClCellParam;
 265
 266 EXTERN ClCb clGlobalCp;
 267 EXTERN ClCellCb * rgClUtlGetCellCb ARGS((U16 cellId));
 268 EXTERN uint32_t reverseBits(uint32_t num, uint8_t numBits);
 269 EXTERN void fillDlDciPayload(uint8_t *buf, uint8_t *bytePos, uint8_t *bitPos,\
 270    uint32_t val, uint8_t valSize);
 271 EXTERN void lwrMacInit();
 272
 273 #endif
 274
 275 /**********************************************************************
 276          End of file
 277 **********************************************************************/