src/5gnrmac/lwr_mac.h

   1 /*******************************************************************************
   2 ################################################################################
   3 #   Copyright (c) [2017-2019] [Radisys]                                        #
   4 #                                                                              #
   5 #   Licensed under the Apache License, Version 2.0 (the "License");            #
   6 #   you may not use this file except in compliance with the License.           #
   7 #   You may obtain a copy of the License at                                    #
   8 #                                                                              #
   9 #       http://www.apache.org/licenses/LICENSE-2.0                             #
  10 #                                                                              #
  11 #   Unless required by applicable law or agreed to in writing, software        #
  12 #   distributed under the License is distributed on an "AS IS" BASIS,          #
  13 #   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.   #
  14 #   See the License for the specific language governing permissions and        #
  15 #   limitations under the License.                                             #
  16 ################################################################################
  17 *******************************************************************************/
  18
  19 /* Contains definitions for MAC CL modules */
  20 #ifndef __LWR_MAC_H__
  21 #define __LWR_MAC_H__
  22
  23 #ifdef INTEL_WLS
  24 #define LWR_MAC_ALLOC(_datPtr, _size)   WLS_MEM_ALLOC(_datPtr, _size);
  25 #else
  26 #define LWR_MAC_ALLOC(_datPtr, _size)   MAC_ALLOC(_datPtr, _size);
  27 #endif
  28
  29 typedef enum
  30 {
  31    PHY_STATE_IDLE,
  32    PHY_STATE_CONFIGURED,
  33    PHY_STATE_RUNNING,
  34    MAX_STATE
  35 }PhyState;
  36
  37 /* Events in Lower Mac */
  38 typedef enum{
  39    PARAM_REQUEST,
  40    PARAM_RESPONSE,
  41    CONFIG_REQUEST,
  42    CONFIG_RESPONSE,
  43    START_REQUEST,
  44    STOP_REQUEST,
  45    MAX_EVENT
  46 }EventState;
  47
  48 typedef struct cellCb
  49 {
  50    uint16_t     cellId;
  51    uint16_t     phyCellId;
  52    PhyState     state;
  53 }LwrMacCellCb;
  54
  55 typedef struct lwrMacGlobalCb
  56 {
  57    Region          region;
  58    Pool            pool;
  59    bool            clCfgDone;   /* CL configuration done */
  60    LwrMacCellCb    cellCb[MAX_NUM_CELL];   /* List of Cells configured */
  61    uint8_t         numCell;  /* Number of Cells configured */
  62    PhyState        phyState;    /* State of PHY */
  63    EventState      event;       /* State of Event */
  64 }LwrMacCb;
  65
  66 typedef enum
  67 {
  68    FAPI_RELEASE_15
  69 }ReleaseCapab;
  70
  71 typedef enum
  72 {
  73    NOT_SUPPORTED,
  74    SUPPORTED
  75 }ParamSupport;
  76
  77 typedef enum
  78 {
  79    NORMAL_CYCLIC_PREFIX_MASK,
  80    EXTENDED_CYCLIC_PREFIX_MASK
  81 }CyclicPrefix;
  82
  83 typedef enum
  84 {
  85    SPACING_15_KHZ,
  86    SPACING_30_KHZ,
  87    SPACING_60_KHZ,
  88    SPACING_120_KHZ
  89 }SubCarrierSpacing;
  90
  91 typedef enum
  92 {
  93    BW_5MHZ,
  94    BW_10MHZ,
  95    BW_15MHZ,
  96    BW_20MHZ,
  97    BW_40MHZ,
  98    BW_50MHZ,
  99    BW_60MHZ,
 100    BW_70MHZ,
 101    BW_80MHZ,
 102    BW_90MHZ,
 103    BW_100MHZ,
 104    BW_200MHZ,
 105    BW_400MHZ
 106 }SupportedBandwidth;
 107
 108 typedef enum
 109 {
 110    CCE_MAPPING_INTERLEAVED_MASK,
 111    CCE_MAPPING_NONINTERLVD_MASK
 112 }CCEMappingType;
 113
 114 typedef enum
 115 {
 116    FORMAT_0,
 117    FORMAT_1,
 118    FORMAT_2,
 119    FORMAT_3,
 120    FORMAT_4
 121 }Formats;
 122
 123 typedef enum
 124 {
 125    MAPPING_TYPE_A,
 126    MAPPING_TYPE_B,
 127 }MappingType;
 128
 129 typedef enum
 130 {
 131    ALLOCATION_TYPE_0,
 132    ALLOCATION_TYPE_1,
 133 }AllocationType;
 134
 135 typedef enum
 136 {
 137    VRB_TO_PRB_MAP_NON_INTLV,
 138    VRB_TO_PRB_MAP_INTLVD
 139 }VrbToPrbMap;
 140
 141 typedef enum
 142 {
 143    DMRS_CONFIG_TYPE_1,
 144    DMRS_CONFIG_TYPE_2
 145 }DmrsConfigType;
 146
 147 typedef enum
 148 {
 149    DMRS_MAX_LENGTH_1,
 150    DMRS_MAX_LENGTH_2
 151 }DmrMaxLen;
 152
 153 typedef enum
 154 {
 155    DMRS_ADDITIONAL_POS_0,
 156    DMRS_ADDITIONAL_POS_1,
 157    DMRS_ADDITIONAL_POS_2,
 158    DMRS_ADDITIONAL_POS_3
 159 }DmrsPos;
 160
 161 typedef enum
 162 {
 163    MOD_QPSK,
 164    MOD_16QAM,
 165    MOD_64QAM,
 166    MOD_256QAM
 167 }ModulationOrder;
 168
 169 typedef enum
 170 {
 171    AGG_FACTOR_1,
 172    AGG_FACTOR_2,
 173    AGG_FACTOR_4,
 174    AGG_FACTOR_8
 175 }AggregationFactor;
 176
 177 typedef enum
 178 {
 179    SF_FORMAT_A1,
 180    SF_FORMAT_A2,
 181    SF_FORMAT_A3,
 182    SF_FORMAT_B1,
 183    SF_FORMAT_B2,
 184    SF_FORMAT_B3,
 185    SF_FORMAT_B4,
 186    SF_FORMAT_C0,
 187    SF_FORMAT_C2
 188 }ShortFormat;
 189
 190 typedef enum
 191 {
 192    PRACH_FD_OCC_IN_A_SLOT_1   = 1,
 193    PRACH_FD_OCC_IN_A_SLOT_2   = 2,
 194    PRACH_FD_OCC_IN_A_SLOT_4   = 4,
 195    PRACH_FD_OCC_IN_A_SLOT_8   = 8
 196 }FdOccPerSlot;
 197
 198 typedef enum
 199 {
 200    RSSI_REPORT_DBM,
 201    RSSI_REPORT_DBFS
 202 }RssiMeasurement;
 203
 204 typedef struct clCellParam
 205 {
 206    ReleaseCapab          releaseCapability;                    /* Release Capability */
 207    PhyState              ParamPhystate;
 208    ParamSupport          skipBlankDlConfig;
 209    ParamSupport          skipBlankUlConfig;
 210    ParamSupport          numTlvsToReport;
 211    CyclicPrefix          cyclicPrefix;
 212    SubCarrierSpacing     supportedSubcarrierSpacingDl;
 213    SupportedBandwidth    supportedBandwidthDl;
 214    SubCarrierSpacing     supportedSubcarrierSpacingsUl;
 215    SupportedBandwidth    supportedBandwidthUl;
 216    CCEMappingType        cceMappingType;
 217    ParamSupport          coresetOutsideFirst3OfdmSymsOfSlot;
 218    ParamSupport          precoderGranularityCoreset;
 219    ParamSupport          pdcchMuMimo;
 220    ParamSupport          pdcchPrecoderCycling;
 221    uint8_t               maxPdcchsPerSlot;
 222    Formats               pucchFormats;
 223    uint8_t               maxPucchsPerSlot;
 224    MappingType           pdschMappingType;
 225    AllocationType        pdschAllocationTypes;
 226    VrbToPrbMap           pdschVrbToPrbMapping;
 227    ParamSupport          pdschCbg;
 228    DmrsConfigType        pdschDmrsConfigTypes;
 229    DmrMaxLen             pdschDmrsMaxLength;
 230    DmrsPos               pdschDmrsAdditionalPos;
 231    uint8_t               maxPdschsTBsPerSlot;
 232    uint8_t               maxNumberMimoLayersPdsch;
 233    ModulationOrder       supportedMaxModulationOrderDl;
 234    uint8_t               maxMuMimoUsersDl;
 235    ParamSupport          pdschDataInDmrsSymbols;
 236    ParamSupport          premptionSupport;
 237    ParamSupport          pdschNonSlotSupport;
 238    ParamSupport          uciMuxUlschInPusch;
 239    ParamSupport          uciOnlyPusch;
 240    ParamSupport          puschFrequencyHopping;
 241    DmrsConfigType        puschDmrsConfigTypes;
 242    DmrMaxLen             puschDmrsMaxLength;
 243    DmrsPos               puschDmrsAdditionalPos;
 244    ParamSupport          puschCbg;
 245    MappingType           puschMappingType;
 246    AllocationType        puschAllocationTypes;
 247    VrbToPrbMap           puschVrbToPrbMapping;
 248    uint8_t               puschMaxPtrsPorts;
 249    uint8_t               maxPduschsTBsPerSlot;
 250    uint8_t               maxNumberMimoLayersNonCbPusch;
 251    ModulationOrder       supportedModulationOrderUl;
 252    uint8_t               maxMuMimoUsersUl;
 253    ParamSupport          dftsOfdmSupport;
 254    AggregationFactor     puschAggregationFactor;
 255    Formats                prachLongFormats;
 256    ShortFormat           prachShortFormats;
 257    ParamSupport          prachRestrictedSets;
 258    FdOccPerSlot          maxPrachFdOccasionsInASlot;
 259    RssiMeasurement       rssiMeasurementSupport;
 260 }ClCellParam;
 261
 262 LwrMacCb lwrMacCb;
 263 LwrMacCellCb * lwrMacGetCellCb ARGS((uint16_t cellId));
 264 uint32_t reverseBits(uint32_t num, uint8_t numBits);
 265 void fillDlDciPayload(uint8_t *buf, uint8_t *bytePos, uint8_t *bitPos,\
 266       uint32_t val, uint8_t valSize);
 267 void lwrMacInit();
 268
 269 #endif
 270
 271 /**********************************************************************
 272   End of file
 273  **********************************************************************/