src/5gnrmac/lwr_mac.h

   1 /*******************************************************************************
   2 ################################################################################
   3 #   Copyright (c) [2017-2019] [Radisys]                                        #
   4 #                                                                              #
   5 #   Licensed under the Apache License, Version 2.0 (the "License");            #
   6 #   you may not use this file except in compliance with the License.           #
   7 #   You may obtain a copy of the License at                                    #
   8 #                                                                              #
   9 #       http://www.apache.org/licenses/LICENSE-2.0                             #
  10 #                                                                              #
  11 #   Unless required by applicable law or agreed to in writing, software        #
  12 #   distributed under the License is distributed on an "AS IS" BASIS,          #
  13 #   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.   #
  14 #   See the License for the specific language governing permissions and        #
  15 #   limitations under the License.                                             #
  16 ################################################################################
  17 *******************************************************************************/
  18
  19 /* Contains definitions for MAC CL modules */
  20 #ifndef __LWR_MAC_H__
  21 #define __LWR_MAC_H__
  22
  23 #ifdef INTEL_WLS_MEM
  24 #define LWR_MAC_ALLOC(_datPtr, _size)   WLS_MEM_ALLOC(_datPtr, _size);
  25 #else
  26 #define LWR_MAC_ALLOC(_datPtr, _size)   MAC_ALLOC(_datPtr, _size);
  27 #endif
  28
  29 #ifdef INTEL_WLS_MEM
  30 #define LWR_MAC_FREE(_datPtr, _size) WLS_MEM_FREE(_datPtr, _size);
  31 #else
  32 #define LWR_MAC_FREE(_datPtr, _size) MAC_FREE(_datPtr, _size);
  33 #endif
  34
  35 typedef enum
  36 {
  37    PHY_STATE_IDLE,
  38    PHY_STATE_CONFIGURED,
  39    PHY_STATE_RUNNING,
  40    MAX_STATE
  41 }PhyState;
  42
  43 /* Events in Lower Mac */
  44 typedef enum{
  45 #ifdef INTEL_TIMER_MODE
  46    UL_IQ_SAMPLE,
  47 #endif
  48    PARAM_REQUEST,
  49    PARAM_RESPONSE,
  50    CONFIG_REQUEST,
  51    CONFIG_RESPONSE,
  52    START_REQUEST,
  53    STOP_REQUEST,
  54    MAX_EVENT
  55 }EventState;
  56
  57 typedef struct cellCb
  58 {
  59    uint16_t     cellId;
  60    uint16_t     phyCellId;
  61    PhyState     state;
  62 }LwrMacCellCb;
  63
  64 typedef struct lwrMacGlobalCb
  65 {
  66    Region          region;
  67    Pool            pool;
  68    bool            clCfgDone;   /* CL configuration done */
  69    LwrMacCellCb    cellCb[MAX_NUM_CELL];   /* List of Cells configured */
  70    uint8_t         numCell;  /* Number of Cells configured */
  71    PhyState        phyState;    /* State of PHY */
  72    EventState      event;       /* State of Event */
  73 }LwrMacCb;
  74
  75 typedef enum
  76 {
  77    FAPI_RELEASE_15
  78 }ReleaseCapab;
  79
  80 typedef enum
  81 {
  82    NOT_SUPPORTED,
  83    SUPPORTED
  84 }ParamSupport;
  85
  86 typedef enum
  87 {
  88    NORMAL_CYCLIC_PREFIX_MASK,
  89    EXTENDED_CYCLIC_PREFIX_MASK
  90 }CyclicPrefix;
  91
  92 typedef enum
  93 {
  94    SPACING_15_KHZ,
  95    SPACING_30_KHZ,
  96    SPACING_60_KHZ,
  97    SPACING_120_KHZ
  98 }SubCarrierSpacing;
  99
 100 typedef enum
 101 {
 102    BW_5MHZ,
 103    BW_10MHZ,
 104    BW_15MHZ,
 105    BW_20MHZ,
 106    BW_40MHZ,
 107    BW_50MHZ,
 108    BW_60MHZ,
 109    BW_70MHZ,
 110    BW_80MHZ,
 111    BW_90MHZ,
 112    BW_100MHZ,
 113    BW_200MHZ,
 114    BW_400MHZ
 115 }SupportedBandwidth;
 116
 117 typedef enum
 118 {
 119    CCE_MAPPING_INTERLEAVED_MASK,
 120    CCE_MAPPING_NONINTERLVD_MASK
 121 }CCEMappingType;
 122
 123 typedef enum
 124 {
 125    FORMAT_0,
 126    FORMAT_1,
 127    FORMAT_2,
 128    FORMAT_3,
 129    FORMAT_4
 130 }Formats;
 131
 132 typedef enum
 133 {
 134    MAPPING_TYPE_A,
 135    MAPPING_TYPE_B,
 136 }MappingType;
 137
 138 typedef enum
 139 {
 140    ALLOCATION_TYPE_0,
 141    ALLOCATION_TYPE_1,
 142 }AllocationType;
 143
 144 typedef enum
 145 {
 146    VRB_TO_PRB_MAP_NON_INTLV,
 147    VRB_TO_PRB_MAP_INTLVD
 148 }VrbToPrbMap;
 149
 150 typedef enum
 151 {
 152    DMRS_CONFIG_TYPE_1,
 153    DMRS_CONFIG_TYPE_2
 154 }DmrsConfigType;
 155
 156 typedef enum
 157 {
 158    DMRS_MAX_LENGTH_1,
 159    DMRS_MAX_LENGTH_2
 160 }DmrMaxLen;
 161
 162 typedef enum
 163 {
 164    DMRS_ADDITIONAL_POS_0,
 165    DMRS_ADDITIONAL_POS_1,
 166    DMRS_ADDITIONAL_POS_2,
 167    DMRS_ADDITIONAL_POS_3
 168 }DmrsPos;
 169
 170 typedef enum
 171 {
 172    MOD_QPSK,
 173    MOD_16QAM,
 174    MOD_64QAM,
 175    MOD_256QAM
 176 }ModulationOrder;
 177
 178 typedef enum
 179 {
 180    AGG_FACTOR_1,
 181    AGG_FACTOR_2,
 182    AGG_FACTOR_4,
 183    AGG_FACTOR_8
 184 }AggregationFactor;
 185
 186 typedef enum
 187 {
 188    SF_FORMAT_A1,
 189    SF_FORMAT_A2,
 190    SF_FORMAT_A3,
 191    SF_FORMAT_B1,
 192    SF_FORMAT_B2,
 193    SF_FORMAT_B3,
 194    SF_FORMAT_B4,
 195    SF_FORMAT_C0,
 196    SF_FORMAT_C2
 197 }ShortFormat;
 198
 199 typedef enum
 200 {
 201    PRACH_FD_OCC_IN_A_SLOT_1   = 1,
 202    PRACH_FD_OCC_IN_A_SLOT_2   = 2,
 203    PRACH_FD_OCC_IN_A_SLOT_4   = 4,
 204    PRACH_FD_OCC_IN_A_SLOT_8   = 8
 205 }FdOccPerSlot;
 206
 207 typedef enum
 208 {
 209    RSSI_REPORT_DBM,
 210    RSSI_REPORT_DBFS
 211 }RssiMeasurement;
 212
 213 typedef struct clCellParam
 214 {
 215    ReleaseCapab          releaseCapability;                    /* Release Capability */
 216    PhyState              ParamPhystate;
 217    ParamSupport          skipBlankDlConfig;
 218    ParamSupport          skipBlankUlConfig;
 219    ParamSupport          numTlvsToReport;
 220    CyclicPrefix          cyclicPrefix;
 221    SubCarrierSpacing     supportedSubcarrierSpacingDl;
 222    SupportedBandwidth    supportedBandwidthDl;
 223    SubCarrierSpacing     supportedSubcarrierSpacingsUl;
 224    SupportedBandwidth    supportedBandwidthUl;
 225    CCEMappingType        cceMappingType;
 226    ParamSupport          coresetOutsideFirst3OfdmSymsOfSlot;
 227    ParamSupport          precoderGranularityCoreset;
 228    ParamSupport          pdcchMuMimo;
 229    ParamSupport          pdcchPrecoderCycling;
 230    uint8_t               maxPdcchsPerSlot;
 231    Formats               pucchFormats;
 232    uint8_t               maxPucchsPerSlot;
 233    MappingType           pdschMappingType;
 234    AllocationType        pdschAllocationTypes;
 235    VrbToPrbMap           pdschVrbToPrbMapping;
 236    ParamSupport          pdschCbg;
 237    DmrsConfigType        pdschDmrsConfigTypes;
 238    DmrMaxLen             pdschDmrsMaxLength;
 239    DmrsPos               pdschDmrsAdditionalPos;
 240    uint8_t               maxPdschsTBsPerSlot;
 241    uint8_t               maxNumberMimoLayersPdsch;
 242    ModulationOrder       supportedMaxModulationOrderDl;
 243    uint8_t               maxMuMimoUsersDl;
 244    ParamSupport          pdschDataInDmrsSymbols;
 245    ParamSupport          premptionSupport;
 246    ParamSupport          pdschNonSlotSupport;
 247    ParamSupport          uciMuxUlschInPusch;
 248    ParamSupport          uciOnlyPusch;
 249    ParamSupport          puschFrequencyHopping;
 250    DmrsConfigType        puschDmrsConfigTypes;
 251    DmrMaxLen             puschDmrsMaxLength;
 252    DmrsPos               puschDmrsAdditionalPos;
 253    ParamSupport          puschCbg;
 254    MappingType           puschMappingType;
 255    AllocationType        puschAllocationTypes;
 256    VrbToPrbMap           puschVrbToPrbMapping;
 257    uint8_t               puschMaxPtrsPorts;
 258    uint8_t               maxPduschsTBsPerSlot;
 259    uint8_t               maxNumberMimoLayersNonCbPusch;
 260    ModulationOrder       supportedModulationOrderUl;
 261    uint8_t               maxMuMimoUsersUl;
 262    ParamSupport          dftsOfdmSupport;
 263    AggregationFactor     puschAggregationFactor;
 264    Formats                prachLongFormats;
 265    ShortFormat           prachShortFormats;
 266    ParamSupport          prachRestrictedSets;
 267    FdOccPerSlot          maxPrachFdOccasionsInASlot;
 268    RssiMeasurement       rssiMeasurementSupport;
 269 }ClCellParam;
 270
 271 LwrMacCb lwrMacCb;
 272 LwrMacCellCb * lwrMacGetCellCb ARGS((uint16_t cellId));
 273 uint32_t reverseBits(uint32_t num, uint8_t numBits);
 274 void fillDlDciPayload(uint8_t *buf, uint8_t *bytePos, uint8_t *bitPos,\
 275       uint32_t val, uint8_t valSize);
 276 void lwrMacLayerInit();
 277
 278 #endif
 279
 280 /**********************************************************************
 281   End of file
 282  **********************************************************************/