1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_MU0_NUM_SLOTS 10
21 #define SCH_MU1_NUM_SLOTS 20
22 #define SCH_MU2_NUM_SLOTS 30
23 #define SCH_MU3_NUM_SLOTS 40
24 #define SCH_MU4_NUM_SLOTS 50
25 #define SCH_MAX_SFN 1024
26 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
27 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
28 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
29 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
30 #define SCH_SSB_NUM_SYMB 4
31 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
36 #define PDSCH_START_RB 10
37 /* Considering pdsch region from 3 to 13, DMRS exclued.
38 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
39 #define NUM_PDSCH_SYMBOL 11
40 #define PUSCH_START_RB 15
41 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
42 #define SI_RNTI 0xFFFF
44 #define DMRS_MAP_TYPE_A 1
45 #define NUM_DMRS_SYMBOLS 1
46 #define DMRS_ADDITIONAL_POS 0
47 #define SCH_DEFAULT_K1 1
48 #define SSB_IDX_SUPPORTED 1
53 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
54 #define UL_GRANT_SIZE 224
56 #define PRB_BITMAP_IDX_LEN 64
57 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
59 #define SCH_MAX_NUM_UL_HQ_PROC 16
60 #define SCH_MAX_NUM_DL_HQ_PROC 16
61 #define SCH_MAX_NUM_MSG3_TX 2
62 #define SCH_MAX_NUM_DL_HQ_TX 3
63 #define SCH_MAX_NUM_UL_HQ_TX 3
64 #define SCH_MAX_NUM_MSG4_TX 2
68 #define ROOT_SEQ_LEN_1 139
69 #define ROOT_SEQ_LEN_2 839
72 /* As per 38.331 the largest offset which can be used in of size 10240.
73 * But using this much size of array can cause memory related issue so thats why
74 * taking this size which are a multiple of the larger size */
75 #define MAX_DRX_SIZE 512
78 #define NUM_SCH_TYPE 2 /*Supported number of Scheduler Algorithm types*/
80 #define SCH_TQ_SIZE 10
82 /*3GPP 38.331,'frequencyDomainResources' :Number of PRBs per Resource Block Group*/
83 #define NUM_PRBS_PER_RBG 6
85 /*3GPP 38.214 Table 5.2.2.1-2*/
86 #define MAX_NUM_CQI_IDX 16
88 /*3GPP 38.211 Table 7.3.2.1-1*/
89 #define MAX_NUM_AGG_LVL 5
91 #define PUCCH_RES_IND 0
93 typedef struct schDlHqProcCb SchDlHqProcCb;
94 typedef struct schUlHqEnt SchUlHqEnt;
95 typedef struct schRaReq SchRaReq;
96 typedef struct schDlHqEnt SchDlHqEnt;
97 typedef struct schCellCb SchCellCb;
98 typedef struct schUeCb SchUeCb;
117 SCH_UE_STATE_INACTIVE,
119 SCH_UE_HANDIN_IN_PROGRESS
124 SCH_RA_STATE_MSG2_HANDLE,
125 SCH_RA_STATE_MSG3_PENDING,
126 SCH_RA_STATE_MSG4_PENDING,
127 SCH_RA_STATE_MSG4_DONE
132 SCH_LC_STATE_INACTIVE,
166 /*Following structures to keep record and estimations of PRB allocated for each
167 * LC taking into consideration the RRM policies*/
168 typedef struct lcInfo
170 uint8_t lcId; /*LCID for which BO are getting recorded*/
171 uint32_t reqBO; /*Size of the BO requested/to be allocated for this LC*/
172 uint32_t allocBO; /*TBS/BO Size which is actually allocated*/
173 uint8_t allocPRB; /*PRB count which is allocated based on RRM policy/FreePRB*/
176 typedef struct schUlHqTbCb
184 SchMcsTable mcsTable;
190 uint8_t cntrRetxAllocFail;
194 typedef struct schDlHqTbCb
207 uint8_t isAckNackDtx;
208 uint8_t cntrRetxAllocFail;
209 //InfUeTbInfo tbCompInfo;
214 typedef struct schDrxHarqCb
216 uint32_t rttExpIndex;
218 uint32_t retxStrtIndex;
219 CmLList *retxStrtNode;
220 uint32_t retxExpIndex;
221 CmLList *retxExpNode;
225 typedef struct schUlHqProcCb
227 uint8_t procId; /*!< HARQ Process ID */
229 uint8_t maxHqTxPerHqP;
235 void *schSpcUlHqProcCb; /*!< Scheduler specific HARQ Proc CB */
236 CmLList ulHqProcLink;
237 uint8_t puschResType; /*!< Resource allocation type */
238 uint16_t puschStartPrb;
239 uint16_t puschNumPrb;
240 uint8_t dmrsMappingType;
241 uint8_t nrOfDmrsSymbols;
243 SlotTimingInfo puschTime;
245 SchDrxHarqCb ulDrxHarqCb;
251 uint8_t procId; /*!< HARQ Process ID */
253 uint8_t maxHqTxPerHqP;
256 SchDlHqTbCb tbInfo[2];
258 void *schSpcDlHqProcCb; /*!< Scheduler specific HARQ Proc CB */
259 CmLList dlHqProcLink;
260 SlotTimingInfo pucchTime;
262 SchDrxHarqCb dlDrxHarqCb;
267 SchCellCb *cell; /*!< Contains the pointer to cell*/
268 SchUeCb *ue; /*!< Contains the pointer to ue*/
269 CmLListCp free; /*!< List of free HARQ processes */
270 CmLListCp inUse; /*!< List of in-use HARQ processes */
271 uint8_t maxHqTx; /*!< Maximum number of harq re-transmissions */
272 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
273 SchUlHqProcCb procs[SCH_MAX_NUM_UL_HQ_PROC]; /*!< Uplink harq process info */
277 SchCellCb *cell; /*!< Contains the pointer to cell */
278 SchUeCb *ue; /*!< Contains the pointer to UE */
279 CmLListCp free; /*!< List of free HARQ processes */
280 CmLListCp inUse; /*!< List of in-use HARQ processes */
281 uint8_t maxHqTx; /*!< Maximum number of harq transmissions */
282 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
283 SchDlHqProcCb procs[SCH_MAX_NUM_DL_HQ_PROC];/*!< Downlink harq processes */
288 * Structure holding LTE MAC's General Configuration information.
290 typedef struct schGenCb
292 uint8_t startCellId; /*!< Starting Cell Id */
294 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
295 of RLC control BO and SRB BO on
296 PCell. val 0 means don't force*/
297 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
301 typedef struct freePrbBlock
310 * PRB allocations for a symbol within a slot
312 typedef struct schPrbAlloc
314 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
315 uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
316 uint16_t numPrbAlloc;
320 typedef struct schPdcchAllocInfo
330 * scheduler allocationsfor DL per cell.
332 typedef struct schDlSlotInfo
334 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
335 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
336 uint8_t ssbIdxSupported; /*!< Max SSB index */
337 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
338 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
339 uint8_t pdcchUe; /*!< UE for which PDCCH Common is scheduled in this slot */
340 RarAlloc *rarAlloc[MAX_NUM_UE]; /*!< RAR allocation per UE*/
342 DlMsgSchInfo *dlMsgAlloc[MAX_NUM_UE]; /*!< Dl msg allocation per UE*/
345 typedef struct schRaCb
350 uint16_t dlMsgPduLen;
351 SchUlHqProcCb msg3HqProc;
352 SchUlHqProcCb *retxMsg3HqProc;
360 * scheduler allocationsfor UL per cell.
362 typedef struct schUlSlotInfo
364 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
365 uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */
366 bool puschPres; /*!< PUSCH presence field */
367 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
368 bool pucchPres; /*!< PUCCH presence field */
369 SchPucchInfo schPucchInfo; /*!< PUCCH info */
370 uint8_t pucchUe; /*!< Store UE id for which PUCCH is scheduled */
371 uint8_t puschUe; /*!< Store UE id for which PUSCH is scheduled */
376 * BSR info per slot per UE.
378 typedef struct bsrInfo
380 uint8_t priority; /* CG priority */
381 uint32_t dataVol; /* Data volume requested in bytes */
384 typedef struct schLcCtxt
386 uint8_t lcId; // logical Channel ID
387 uint8_t lcp; // logical Channel Prioritization
390 uint16_t pduSessionId; /*Pdu Session Id*/
391 Snssai *snssai; /*S-NSSAI assoc with LCID*/
392 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
393 uint16_t rsvdDedicatedPRB;
396 typedef struct schDlCb
398 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
401 typedef struct schUlLcCtxt
408 uint8_t pbr; // prioritisedBitRate
409 uint8_t bsd; // bucketSizeDuration
410 uint16_t pduSessionId; /*Pdu Session Id*/
411 Snssai *snssai; /*S-NSSAI assoc with LCID*/
412 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
413 uint16_t rsvdDedicatedPRB;
416 typedef struct schUlCb
418 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
421 typedef struct schUeCfgCb
426 bool macCellGrpCfgPres;
427 SchMacCellGrpCfg macCellGrpCfg;
428 bool phyCellGrpCfgPres;
429 SchPhyCellGrpCfg phyCellGrpCfg;
431 SchSpCellRecfg spCellCfg;
433 SchModulationInfo dlModInfo;
434 SchModulationInfo ulModInfo;
435 SchDataTransmission dataTransmissionAction;
438 typedef struct schHqDlMap
443 typedef struct schHqUlMap
449 typedef struct schDrxUeCb
451 bool drxDlUeActiveStatus; /* Final Dl Ue status which is marked as true if drxDlUeActiveMask or drxDlUeActiveMaskForHarq is present */
452 bool drxUlUeActiveStatus; /* Final Ul Ue status which is marked as true if drxUlUeActiveMask or drxUlUeActiveMaskForHarq is present */
453 uint32_t drxDlUeActiveMask; /* variable is used to store the status about downlink active status of Ue for On-duration, inactive timer*/
454 uint32_t drxUlUeActiveMask; /* variable is used to store the status about uplink active status for on-duration inactive timer*/
455 uint32_t drxDlUeActiveMaskForHarq; /* variable is used to store the status about downlink active status for harq*/
456 uint32_t drxUlUeActiveMaskForHarq; /* variable is used to store the status about uplink active status for harq */
457 uint32_t onDurationLen; /* length of on duration which is received from ue cfg/recfg in form of ms and subms, informs about after how many slots on duration gets expire */
458 uint32_t inActvTimerLen; /* length of inActvTimer value received from ue cfg/recfg in form of ms, informs about after how many slots in active gets expire */
459 uint8_t harqRttDlTimerLen; /* length of harqRttDlTimer received from ue cfg/recfg in form of symbols, inform about after how many slots on the harq drx-HARQ-RTT-TimerDL expire */
460 uint8_t harqRttUlTimerLen; /* length of harqRttUlTimer received from ue cfg/recfg in form of symbols,informs about after how many slots on harq drx-HARQ-RTT-TimerUL expire*/
461 uint32_t retransDlTimerLen; /* length of retransDlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer dl timer expire*/
462 uint32_t retransUlTimerLen; /* length of retransUlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer ul timer expire*/
463 uint32_t longCycleLen; /* length of long Cycle value received from ue cfg/recfg in form of ms*/
464 bool longCycleToBeUsed; /* long cycle should be used once the short cycle gets expires */
465 uint32_t drxStartOffset; /* length of drxStartOffset value received from ue cfg/recfg in form of ms, which helps in getting on duration start point*/
466 bool shortCyclePresent; /* set this value if shortCycle is Present */
467 uint32_t shortCycleLen; /* length of short Cycle value received from ue cfg/recfg in form of ms*/
468 uint32_t shortCycleTmrLen; /* value shortCycleTmr is the multiple of shortCycle which is received from ue cfg/recfg in form of integer*/
469 uint32_t drxSlotOffset; /* drxSlotOffset value received from ue cfg/recfg which is used to delay before starting the drx-onDuration*/
470 uint32_t onDurationStartIndex; /* Index at which UE is stored in onDuration starts list */
471 uint32_t onDurationExpiryIndex; /* Index at which UE is stored in onDuration expires in the list */
472 uint32_t inActvExpiryIndex; /* Index at which UE is stored in inActvTimer expires in the list */
473 uint32_t shortCycleExpiryIndex; /* Index at which UE is stored in shortCycle expires in the list */
474 int32_t shortCycleDistance; /* Distance after how many slot short cycle tmr gets expire */
475 int32_t onDurationStartDistance;/* Distance after how many slot on Duration Start tmr gets expire */
476 int32_t onDurationExpiryDistance;/* Distance after how many slot on Duration tmr gets expire */
477 int32_t inActiveTmrExpiryDistance;/* Distance after how many slot inActive tmr gets expire */
478 CmLList *onDurationStartNodeInfo; /* Node present in on duration start list*/
479 CmLList *onDurationExpiryNodeInfo;/* Node present in on duration exp list*/
480 CmLList *inActvTimerExpiryNodeInfo; /* Node present in in active exp list*/
481 CmLList *shortCycleTmrExpiryNodeInfo; /* Node present in short cycle exp list*/
485 typedef struct schPdcchInfo
487 SchControlRsrcSet *cRSetRef; /*Coreset Cfg reference from SchUeCfgCb*/
488 SchSearchSpace *ssRef; /*SearchSpace Cfg reference from SchUeCfgCb*/
489 uint16_t totalPrbs; /*Total PRBs configured for this CORESET*/
490 uint8_t nrOfPRBPerCce; /*CCE Size*/
491 uint8_t totalCceCount; /*Count of CCE in this CORESET*/
492 uint8_t cqiIndxAggLvlMap[MAX_NUM_CQI_IDX];/*Agg Level to be used for each CQI Index*/
493 uint32_t *y; /*Coefficient variable to calculate CCE Index as per 3gpp Spec 38.213 Sec 10.1*/
500 typedef struct schUeCb
507 SchCfraResource cfraResource;
510 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
515 SchDlHqProcCb *msg4HqProc;
516 SchDlHqProcCb *retxMsg4HqProc;
517 SchHqDlMap **hqDlmap;
518 SchHqUlMap **hqUlmap;
525 SchK0K1TimingInfoTbl k0K1InfoTbl;
527 SchK2TimingInfoTbl k2InfoTbl;
528 SchPdcchInfo pdcchInfo[MAX_NUM_CRSET];
535 typedef struct schRaReq
538 RachIndInfo *rachInd;
540 SchUeCb *ueCb; /* Filled only if isCFRA = true */
541 SlotTimingInfo winStartTime;
542 SlotTimingInfo winEndTime;
545 typedef struct schPageInfo
547 uint16_t pf; /*Value of Paging Frame received from DUAPP*/
548 uint8_t i_s; /*Value of Paging Occ Index received from DUAPP*/
549 SlotTimingInfo pageTxTime; /*Start Paging window*/
550 uint8_t mcs; /*MCS index*/
551 uint16_t msgLen; /*Pdu length */
552 uint8_t *pagePdu; /*RRC Page PDU bit string*/
555 typedef struct schPagingOcc
558 uint8_t pagingOccSlot;
561 typedef struct schPageCb
563 CmLListCp pageIndInfoRecord[MAX_SFN]; /*List of Page Records received which are stored per sfn*/
564 SchPagingOcc pagMonOcc[MAX_PO_PER_PF]; /*Paging Occasion Slot/FrameOffset are stored*/
568 typedef struct schDrxCb
570 CmLListCp onDurationStartList; /*!< Tracks the start of onDuration Timer. */
571 CmLListCp onDurationExpiryList; /*!< Tracks the Expiry of onDuration Timer. */
572 CmLListCp inActvTmrExpiryList; /*!< Tracks the Expiry of drx-InactivityTimer. */
573 CmLListCp shortCycleExpiryList; /*!< Tracks the Expiry of DRX Short Cycle. */
574 CmLListCp dlHarqRttExpiryList; /*!< Tracks the Expiry of DL HARQ RTT timer. */
575 CmLListCp dlRetransExpiryList; /*!< Tracks the Expiry of DL Re-Transmission timer. */
576 CmLListCp ulHarqRttExpiryList; /*!< Tracks the Expiry of UL HARQ RTT timer. */
577 CmLListCp ulRetransExpiryList; /*!< Tracks the Expiry of UL Re-Transmission timer. */
578 CmLListCp dlRetransTmrStartList; /*!< It has list of DL harq procs for */
579 CmLListCp ulRetransTmrStartList; /*!< It has list of UL harq procs for */
583 typedef struct schAllApis
585 uint8_t (* SchCellCfgReq)(SchCellCb *cellCb);
586 void (* SchCellDeleteReq)(SchCellCb *cellCb);
587 uint8_t (* SchAddUeConfigReq)(SchUeCb *ueCb);
588 void (* SchModUeConfigReq)(SchUeCb *ueCb);
589 void (* SchUeDeleteReq)(SchUeCb *ueCb);
590 void (* SchDlHarqInd)();
591 void (* SchPagingInd)();
592 void (* SchRachRsrcReq)();
593 void (* SchRachRsrcRel)();
594 void (* SchCrcInd)(SchCellCb *cellCb, uint16_t ueId);
595 void (* SchRachInd)(SchCellCb *cellCb, uint16_t ueId);
596 void (* SchDlRlcBoInfo)(SchCellCb *cellCb, uint16_t ueId);
597 void (* SchSrUciInd)(SchCellCb *cellCb, uint16_t ueId);
598 void (* SchBsr)(SchCellCb *cellCb, uint16_t ueId);
599 void (* SchHandleLcList)(void *ptr, CmLList *node, ActionTypeLL action);
600 void (* SchAddToDlHqRetxList)(SchDlHqProcCb *hqP);
601 void (* SchAddToUlHqRetxList)(SchUlHqProcCb *hqP);
602 void (* SchRemoveFrmDlHqRetxList)(SchUeCb *ueCb, CmLList *node);
603 void (* SchRemoveFrmUlHqRetxList)(SchUeCb *ueCb, CmLList *node);
604 uint8_t (* SchAddUeToSchedule)(SchCellCb *cellCb, uint16_t ueId);
605 void (* SchRemoveUeFrmScheduleLst)(SchCellCb *cell, CmLList *node);
606 uint8_t (* SchInitDlHqProcCb)(SchDlHqProcCb *hqP);
607 uint8_t (* SchInitUlHqProcCb)(SchUlHqProcCb *hqP);
608 void (* SchFreeDlHqProcCb)(SchDlHqProcCb *hqP);
609 void (* SchFreeUlHqProcCb)(SchUlHqProcCb *hqP);
610 void (* SchDeleteDlHqProcCb)(SchDlHqProcCb *hqP);
611 void (* SchDeleteUlHqProcCb)(SchUlHqProcCb *hqP);
612 void (* SchScheduleSlot)(SchCellCb *cell, SlotTimingInfo *slotInd, Inst schInst);
613 uint32_t (* SchScheduleDlLc)(SlotTimingInfo pdcchTime, SlotTimingInfo pdschTime, uint8_t pdschNumSymbols, \
614 uint16_t *startPrb, bool isRetx, SchDlHqProcCb **hqP);
615 uint8_t (* SchScheduleUlLc)(SlotTimingInfo dciTime, SlotTimingInfo puschTime, uint8_t startStmb, \
616 uint8_t symbLen, bool isRetx, SchUlHqProcCb **hqP);
619 typedef struct schHqCfgParam
621 uint8_t maxDlDataHqTx;
623 uint8_t maxUlDataHqTx;
628 /* parameters derived in scheduler */
631 PdcchCfg sib1PdcchCfg;
632 PdschCfg sib1PdschCfg;
635 typedef struct dlTotalPrbUsage
637 uint16_t numPrbUsedForTx;
638 uint16_t totalPrbAvailForTx;
643 TotalPrbUsage *dlTotalPrbUsage;
644 TotalPrbUsage *ulTotalPrbUsage;
649 CmLListCp dlTotPrbUseList;
650 CmLListCp ulTotPrbUseList;
653 typedef struct schStatsGrp
656 uint64_t subscriptionId;
658 uint16_t periodicity; /* In milliseconds */
660 SchKpiSupported kpiStats;
663 typedef struct schStatistics
665 CmLListCp statsGrpList;
666 SchKpiActive activeKpiList;
671 * Cell Control block per cell.
673 typedef struct schCellCb
675 uint16_t cellId; /*!< Cell ID */
676 Inst instIdx; /*!< Index of the scheduler instance */
677 Inst macInst; /*!< Index of the MAC instance */
678 uint16_t numSlots; /*!< Number of slots in current frame */
679 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
680 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
681 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
682 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
684 bool firstSsbTransmitted;
685 bool firstSib1Transmitted;
686 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!< start symbol per SSB beam */
687 uint64_t dedPreambleBitMap; /*!< Bit map to find used/free preambles index */
688 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
689 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
690 uint16_t numActvUe; /*!< Number of active UEs */
691 uint32_t actvUeBitMap; /*!< Bit map to find active UEs */
692 uint32_t boIndBitMap; /*!< Bit map to indicate UEs that have recevied BO */
693 SchUeCb ueCb[MAX_NUM_UE]; /*!< Pointer to UE contexts of this cell */
694 SchPageCb pageCb; /*!< Page Record at Schedular*/
696 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
697 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
698 SchSymbolConfig slotCfg[MAX_TDD_PERIODICITY_SLOTS][MAX_SYMB_PER_SLOT];
701 SchDrxCb drxCb[MAX_DRX_SIZE]; /*!< Drx cb*/
703 SchType schAlgoType; /*!< The scheduler type which the cell is configured with.*/
704 SchAllApis *api; /*!< Reference of sch APIs for this cell based on the SchType*/
705 void *schSpcCell; /*Ref of Scheduler specific structure*/
707 SchK0K1TimingInfoTbl k0K1InfoTbl;
708 SchK2TimingInfoTbl msg3K2InfoTbl;
709 SchK2TimingInfoTbl k2InfoTbl;
710 SchSib1Cfg sib1SchCfg; /* SIB1 config */
711 uint8_t maxMsg3Tx; /* MAximum num of msg3 tx*/
714 typedef struct schTimer
716 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
717 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
718 uint8_t tmrRes; /*!< Timer resolution */
723 * Control block for sch
727 TskInit schInit; /*!< Task Init info */
728 SchGenCb genCfg; /*!< General Config info */
729 SchTimer schTimersInfo; /*!< Sch timer queues and resolution */
730 SchAllApis allApis[NUM_SCH_TYPE]; /*!<List of All Scheduler Type dependent Function pointers*/
731 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
732 CmLListCp sliceCfg; /* Linklist to Store Slice configuration */
733 SchStatistics statistics; /* Statistics configuration and calculated values */
736 /* Declaration for scheduler control blocks */
737 SchCb schCb[SCH_MAX_INST];
739 /* function declarations */
740 short int schActvTmr(Ent ent,Inst inst);
741 void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
743 /* Configuration related function declarations */
744 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
745 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
746 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
747 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
748 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
749 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
750 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
751 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
752 uint8_t addUeToBeScheduled(SchCellCb *cell, uint8_t ueId);
754 /* Incoming message handler function declarations */
755 uint8_t SchProcCellCfgReq(Pst *pst, SchCellCfg *schCellCfg);
756 uint8_t SchProcSlotInd(Pst *pst, SlotTimingInfo *slotInd);
757 uint8_t SchProcRachInd(Pst *pst, RachIndInfo *rachInd);
758 uint8_t SchProcCrcInd(Pst *pst, CrcIndInfo *crcInd);
759 uint8_t SchProcUlCqiInd(Pst *pst, SchUlCqiInd *ulCqiInd);
760 uint8_t SchProcDlCqiInd(Pst *pst, SchDlCqiInd *dlCqiInd);
761 uint8_t SchProcPhrInd(Pst *pst, SchPwrHeadroomInd *schPhrInd);
762 uint8_t SchProcDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo);
763 uint8_t SchAddUeConfigReq(Pst *pst, SchUeCfgReq *ueCfgToSch);
764 uint8_t SchProcBsr(Pst *pst, UlBufferStatusRptInd *bsrInd);
765 uint8_t SchProcSrUciInd(Pst *pst, SrUciIndInfo *uciInd);
766 uint8_t SchModUeConfigReq(Pst *pst, SchUeRecfgReq *ueRecfgToSch);
767 uint8_t SchProcUeDeleteReq(Pst *pst, SchUeDelete *ueDelete);
768 uint8_t SchProcCellDeleteReq(Pst *pst, SchCellDeleteReq *schCellDelete);
769 uint8_t SchProcSliceCfgReq(Pst *pst, SchSliceCfgReq *schSliceCfgReq);
770 uint8_t SchProcSliceRecfgReq(Pst *pst, SchSliceRecfgReq *schSliceRecfgReq);
771 uint8_t SchProcRachRsrcReq(Pst *pst, SchRachRsrcReq *schRachRsrcReq);
772 uint8_t SchProcRachRsrcRel(Pst *pst, SchRachRsrcRel *schRachRsrcRel);
773 uint8_t SchProcPagingInd(Pst *pst, SchPageInd *pageInd);
774 uint8_t SchProcDlHarqInd(Pst *pst, DlHarqInd *dlHarqInd);
776 /* DL scheduling related function declarations */
777 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
778 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
779 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
780 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
781 bool schProcessRaReq(Inst schInst, SchCellCb *cellCb, SlotTimingInfo currTime, uint8_t ueId);
782 uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId,bool isRetxMsg4, SchDlHqProcCb **hqP);
783 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAlloc *rarAlloc, uint8_t k0Index);
784 bool schFillBoGrantDlSchedInfo(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchDlHqProcCb **hqP);
785 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti, uint32_t tbSize, DlMsgSchInfo *dlMsgAlloc,\
786 uint16_t startPRB, uint8_t pdschStartSymbol, uint8_t pdschNumSymbols,bool isRetx, SchDlHqProcCb* hqP, SchPdcchAllocInfo pdcchAllocInfo);
787 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueId, DlMsgSchInfo *msg4Alloc,\
788 uint8_t pdschStartSymbol, uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP);
789 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
790 uint16_t *startPrb, uint16_t numPrb);
791 void fillDlMsgInfo(DlMsgSchInfo *dlMsgInfo, uint16_t crnti, bool isRetx, SchDlHqProcCb* hqP); /*AS per 38.473 V15.3.0, Section 9.3.1.32 crnti value range is b/w 0..65535*/
792 bool findValidK0K1Value(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool dedMsg, uint8_t *pdschStartSymbol, uint8_t *pdschSymblLen,\
793 SlotTimingInfo *pdcchTime, SlotTimingInfo *pdschTime, SlotTimingInfo *pucchTime, bool isRetx, SchDlHqProcCb *hqP, SchPdcchAllocInfo *pdcchAllocInfo);
794 RaRspWindowStatus isInRaRspWindow(SchRaReq *raReq, SlotTimingInfo frameToCheck, uint16_t numSlotsPerSystemFrame);
796 /* UL scheduling related function declarations */
797 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
798 bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo);
799 uint8_t schCalcPrachNumRb(SchCellCb *cell);
800 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo);
801 uint8_t schAllocPucchResource(SchCellCb *cell, SlotTimingInfo pucchTime, SchUeCb *ueCb, SchDlHqProcCb *hqP, SchPdcchAllocInfo *pdcchAllocInfo);
802 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo *puschInfo, DciInfo *dciInfo, bool isRetx, SchUlHqProcCb *hqP);
803 uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo puschTime, uint32_t tbSize,
804 uint8_t startSymb, uint8_t symbLen, uint16_t startPrb, bool isRetx, SchUlHqProcCb *hqP);
805 uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
806 uint16_t *startPrb, uint16_t numPrb);
807 bool schProcessSrOrBsrReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchUlHqProcCb **hqP);
809 /*Generic Functions*/
810 void updateGrantSizeForBoRpt(CmLListCp *lcLL, DlMsgSchInfo *dlMsgAlloc, BsrInfo *bsrInfo, uint32_t *accumalatedBOSize);
811 uint16_t searchLargestFreeBlock(SchCellCb *cell, SlotTimingInfo slotTime,uint16_t *startPrb, Direction dir);
812 LcInfo* handleLcLList(CmLListCp *lcLL, uint8_t lcId, ActionTypeLL action);
813 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
814 uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd);
815 void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status);
816 uint8_t fillUeCoresetAndSsInfo(SchUeCb *ue);
817 bool schDlCandidateSelection(SchUeCb *ue, SlotTimingInfo slotTime, SchPdcchAllocInfo *pdcchAllocInfo);
820 void schProcPagingCfg(SchCellCb *cell);
821 void schCfgPdcchMonOccOfPO(SchCellCb *cell);
822 void schIncrSlot(SlotTimingInfo *timingInfo, uint8_t incr, uint16_t numSlotsPerRF);
823 uint8_t schFillPagePdschCfg(SchCellCb *cell, PageDlSch *pageDlSch, SlotTimingInfo slotTime, \
824 uint16_t tbSize, uint8_t mcs, uint16_t startPrb);
825 /*DL HARQ Functions*/
826 void schDlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
827 void schMsg4FeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk);
828 void schDlHqFeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk1, uint8_t fdbk2);
829 uint8_t schDlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchDlHqProcCb **hqP);
830 void schDlReleaseHqProcess(SchDlHqProcCb *hqP);
831 void schDlHqEntDelete(SchUeCb *ueCb);
833 /*UL HARQ Functions*/
834 void schUlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
835 uint8_t schMsg3RetxSchedulingForUe(SchRaCb *raCb);
836 void schUlHqProcessNack(SchUlHqProcCb *hqP);
837 void schUlHqProcessAck(SchUlHqProcCb *hqP);
838 uint8_t schUlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchUlHqProcCb **hqP);
839 void schUlReleaseHqProcess(SchUlHqProcCb *hqP, Bool togNdi);
840 void schUlHqEntDelete(SchUeCb *ueCb);
842 /* UE Manager HARQ Fun*/
843 void schUpdateHarqFdbk(SchUeCb *ueCb, uint8_t numHarq, uint8_t *harqPayload,SlotTimingInfo *slotInd);
845 /* Round Robbin Scheduler funtions*/
846 uint8_t schFillUlDciForMsg3Retx(SchRaCb *raCb, SchPuschInfo *puschInfo, DciInfo *dciInfo);
847 bool schGetMsg3K2(SchCellCb *cell, SchUlHqProcCb* msg3HqProc, uint16_t dlTime, SlotTimingInfo *msg3Time, bool isRetx);
848 void schMsg4Complete(SchUeCb *ueCb);
850 /* Statistics Function */
851 uint8_t SchProcStatsReq(Pst *pst, SchStatsReq *statsReq);
852 uint8_t SchSendStatsIndToMac(Inst inst, SchStatsInd *statsInd);
853 uint8_t schCalcAndSendGrpStats(SchStatsGrp *grpInfo);
854 uint8_t SchProcStatsDeleteReq(Pst *pst, SchStatsDeleteReq *statsDeleteReq);
855 uint8_t SchProcStatsModificationReq(Pst *pst, SchStatsModificationReq *statsModificationReq);
856 void deleteStatsGrpInfo(Inst inst, SchStatsGrp *statsGrpInfo);
857 /**********************************************************************
859 **********************************************************************/