1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_MU0_NUM_SLOTS 10
21 #define SCH_MU1_NUM_SLOTS 20
22 #define SCH_MU2_NUM_SLOTS 30
23 #define SCH_MU3_NUM_SLOTS 40
24 #define SCH_MU4_NUM_SLOTS 50
25 #define SCH_MAX_SFN 1024
26 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
27 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
28 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
29 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
30 #define SCH_SSB_NUM_SYMB 4
31 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
36 #define PDSCH_START_RB 10
37 /* Considering pdsch region from 3 to 13, DMRS exclued.
38 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
39 #define NUM_PDSCH_SYMBOL 11
40 #define PUSCH_START_RB 15
41 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
42 #define SI_RNTI 0xFFFF
44 #define DMRS_MAP_TYPE_A 1
45 #define NUM_DMRS_SYMBOLS 1
46 #define DMRS_ADDITIONAL_POS 0
47 #define SCH_DEFAULT_K1 1
48 #define SSB_IDX_SUPPORTED 1
53 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
54 #define UL_GRANT_SIZE 224
56 #define PRB_BITMAP_IDX_LEN 64
57 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
59 #define SCH_MAX_NUM_UL_HQ_PROC 16
60 #define SCH_MAX_NUM_DL_HQ_PROC 16
61 #define SCH_MAX_NUM_MSG3_TX 2
62 #define SCH_MAX_NUM_DL_HQ_TX 3
63 #define SCH_MAX_NUM_UL_HQ_TX 3
64 #define SCH_MAX_NUM_MSG4_TX 2
68 #define ROOT_SEQ_LEN_1 139
69 #define ROOT_SEQ_LEN_2 839
72 /* As per 38.331 the largest offset which can be used in of size 10240.
73 * But using this much size of array can cause memory related issue so thats why
74 * taking this size which are a multiple of the larger size */
75 #define MAX_DRX_SIZE 512
78 #define NUM_SCH_TYPE 2 /*Supported number of Scheduler Algorithm types*/
80 #define SCH_TQ_SIZE 10
82 /*3GPP 38.331,'frequencyDomainResources' :Number of PRBs per Resource Block Group*/
83 #define NUM_PRBS_PER_RBG 6
85 typedef struct schDlHqProcCb SchDlHqProcCb;
86 typedef struct schUlHqEnt SchUlHqEnt;
87 typedef struct schRaReq SchRaReq;
88 typedef struct schDlHqEnt SchDlHqEnt;
89 typedef struct schCellCb SchCellCb;
90 typedef struct schUeCb SchUeCb;
109 SCH_UE_STATE_INACTIVE,
111 SCH_UE_HANDIN_IN_PROGRESS
116 SCH_RA_STATE_MSG2_HANDLE,
117 SCH_RA_STATE_MSG3_PENDING,
118 SCH_RA_STATE_MSG4_PENDING,
119 SCH_RA_STATE_MSG4_DONE
124 SCH_LC_STATE_INACTIVE,
158 /*Following structures to keep record and estimations of PRB allocated for each
159 * LC taking into consideration the RRM policies*/
160 typedef struct lcInfo
162 uint8_t lcId; /*LCID for which BO are getting recorded*/
163 uint32_t reqBO; /*Size of the BO requested/to be allocated for this LC*/
164 uint32_t allocBO; /*TBS/BO Size which is actually allocated*/
165 uint8_t allocPRB; /*PRB count which is allocated based on RRM policy/FreePRB*/
168 typedef struct schUlHqTbCb
176 SchMcsTable mcsTable;
182 uint8_t cntrRetxAllocFail;
186 typedef struct schDlHqTbCb
199 uint8_t isAckNackDtx;
200 uint8_t cntrRetxAllocFail;
201 //InfUeTbInfo tbCompInfo;
206 typedef struct schDrxHarqCb
208 uint32_t rttExpIndex;
210 uint32_t retxStrtIndex;
211 CmLList *retxStrtNode;
212 uint32_t retxExpIndex;
213 CmLList *retxExpNode;
217 typedef struct schUlHqProcCb
219 uint8_t procId; /*!< HARQ Process ID */
221 uint8_t maxHqTxPerHqP;
227 void *schSpcUlHqProcCb; /*!< Scheduler specific HARQ Proc CB */
228 CmLList ulHqProcLink;
229 uint8_t puschResType; /*!< Resource allocation type */
230 uint16_t puschStartPrb;
231 uint16_t puschNumPrb;
232 uint8_t dmrsMappingType;
233 uint8_t nrOfDmrsSymbols;
235 SlotTimingInfo puschTime;
237 SchDrxHarqCb ulDrxHarqCb;
243 uint8_t procId; /*!< HARQ Process ID */
245 uint8_t maxHqTxPerHqP;
248 SchDlHqTbCb tbInfo[2];
250 void *schSpcDlHqProcCb; /*!< Scheduler specific HARQ Proc CB */
251 CmLList dlHqProcLink;
252 SlotTimingInfo pucchTime;
254 SchDrxHarqCb dlDrxHarqCb;
259 SchCellCb *cell; /*!< Contains the pointer to cell*/
260 SchUeCb *ue; /*!< Contains the pointer to ue*/
261 CmLListCp free; /*!< List of free HARQ processes */
262 CmLListCp inUse; /*!< List of in-use HARQ processes */
263 uint8_t maxHqTx; /*!< Maximum number of harq re-transmissions */
264 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
265 SchUlHqProcCb procs[SCH_MAX_NUM_UL_HQ_PROC]; /*!< Uplink harq process info */
269 SchCellCb *cell; /*!< Contains the pointer to cell */
270 SchUeCb *ue; /*!< Contains the pointer to UE */
271 CmLListCp free; /*!< List of free HARQ processes */
272 CmLListCp inUse; /*!< List of in-use HARQ processes */
273 uint8_t maxHqTx; /*!< Maximum number of harq transmissions */
274 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
275 SchDlHqProcCb procs[SCH_MAX_NUM_DL_HQ_PROC];/*!< Downlink harq processes */
280 * Structure holding LTE MAC's General Configuration information.
282 typedef struct schGenCb
284 uint8_t startCellId; /*!< Starting Cell Id */
286 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
287 of RLC control BO and SRB BO on
288 PCell. val 0 means don't force*/
289 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
293 typedef struct freePrbBlock
302 * PRB allocations for a symbol within a slot
304 typedef struct schPrbAlloc
306 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
307 uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
308 uint16_t numPrbAlloc;
313 * scheduler allocationsfor DL per cell.
315 typedef struct schDlSlotInfo
317 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
318 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
319 uint8_t ssbIdxSupported; /*!< Max SSB index */
320 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
321 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
322 uint8_t pdcchUe; /*!< UE for which PDCCH is scheduled in this slot */
323 uint8_t pdschUe; /*!< UE for which PDSCH is scheduled in this slot */
324 RarAlloc *rarAlloc[MAX_NUM_UE]; /*!< RAR allocation per UE*/
326 DlMsgSchInfo *dlMsgAlloc[MAX_NUM_UE]; /*!< Dl msg allocation per UE*/
329 typedef struct schRaCb
334 uint16_t dlMsgPduLen;
335 SchUlHqProcCb msg3HqProc;
336 SchUlHqProcCb *retxMsg3HqProc;
344 * scheduler allocationsfor UL per cell.
346 typedef struct schUlSlotInfo
348 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
349 uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */
350 bool puschPres; /*!< PUSCH presence field */
351 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
352 bool pucchPres; /*!< PUCCH presence field */
353 SchPucchInfo schPucchInfo; /*!< PUCCH info */
354 uint8_t pucchUe; /*!< Store UE id for which PUCCH is scheduled */
355 uint8_t puschUe; /*!< Store UE id for which PUSCH is scheduled */
360 * BSR info per slot per UE.
362 typedef struct bsrInfo
364 uint8_t priority; /* CG priority */
365 uint32_t dataVol; /* Data volume requested in bytes */
368 typedef struct schLcCtxt
370 uint8_t lcId; // logical Channel ID
371 uint8_t lcp; // logical Channel Prioritization
374 uint16_t pduSessionId; /*Pdu Session Id*/
375 Snssai *snssai; /*S-NSSAI assoc with LCID*/
376 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
377 uint16_t rsvdDedicatedPRB;
380 typedef struct schDlCb
382 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
385 typedef struct schUlLcCtxt
392 uint8_t pbr; // prioritisedBitRate
393 uint8_t bsd; // bucketSizeDuration
394 uint16_t pduSessionId; /*Pdu Session Id*/
395 Snssai *snssai; /*S-NSSAI assoc with LCID*/
396 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
397 uint16_t rsvdDedicatedPRB;
400 typedef struct schUlCb
402 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
405 typedef struct schUeCfgCb
410 bool macCellGrpCfgPres;
411 SchMacCellGrpCfg macCellGrpCfg;
412 bool phyCellGrpCfgPres;
413 SchPhyCellGrpCfg phyCellGrpCfg;
415 SchSpCellRecfg spCellCfg;
417 SchModulationInfo dlModInfo;
418 SchModulationInfo ulModInfo;
419 SchDataTransmission dataTransmissionAction;
422 typedef struct schHqDlMap
427 typedef struct schHqUlMap
433 typedef struct schDrxUeCb
435 bool drxDlUeActiveStatus; /* Final Dl Ue status which is marked as true if drxDlUeActiveMask or drxDlUeActiveMaskForHarq is present */
436 bool drxUlUeActiveStatus; /* Final Ul Ue status which is marked as true if drxUlUeActiveMask or drxUlUeActiveMaskForHarq is present */
437 uint32_t drxDlUeActiveMask; /* variable is used to store the status about downlink active status of Ue for On-duration, inactive timer*/
438 uint32_t drxUlUeActiveMask; /* variable is used to store the status about uplink active status for on-duration inactive timer*/
439 uint32_t drxDlUeActiveMaskForHarq; /* variable is used to store the status about downlink active status for harq*/
440 uint32_t drxUlUeActiveMaskForHarq; /* variable is used to store the status about uplink active status for harq */
441 uint32_t onDurationLen; /* length of on duration which is received from ue cfg/recfg in form of ms and subms, informs about after how many slots on duration gets expire */
442 uint32_t inActvTimerLen; /* length of inActvTimer value received from ue cfg/recfg in form of ms, informs about after how many slots in active gets expire */
443 uint8_t harqRttDlTimerLen; /* length of harqRttDlTimer received from ue cfg/recfg in form of symbols, inform about after how many slots on the harq drx-HARQ-RTT-TimerDL expire */
444 uint8_t harqRttUlTimerLen; /* length of harqRttUlTimer received from ue cfg/recfg in form of symbols,informs about after how many slots on harq drx-HARQ-RTT-TimerUL expire*/
445 uint32_t retransDlTimerLen; /* length of retransDlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer dl timer expire*/
446 uint32_t retransUlTimerLen; /* length of retransUlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer ul timer expire*/
447 uint32_t longCycleLen; /* length of long Cycle value received from ue cfg/recfg in form of ms*/
448 bool longCycleToBeUsed; /* long cycle should be used once the short cycle gets expires */
449 uint32_t drxStartOffset; /* length of drxStartOffset value received from ue cfg/recfg in form of ms, which helps in getting on duration start point*/
450 bool shortCyclePresent; /* set this value if shortCycle is Present */
451 uint32_t shortCycleLen; /* length of short Cycle value received from ue cfg/recfg in form of ms*/
452 uint32_t shortCycleTmrLen; /* value shortCycleTmr is the multiple of shortCycle which is received from ue cfg/recfg in form of integer*/
453 uint32_t drxSlotOffset; /* drxSlotOffset value received from ue cfg/recfg which is used to delay before starting the drx-onDuration*/
454 uint32_t onDurationStartIndex; /* Index at which UE is stored in onDuration starts list */
455 uint32_t onDurationExpiryIndex; /* Index at which UE is stored in onDuration expires in the list */
456 uint32_t inActvExpiryIndex; /* Index at which UE is stored in inActvTimer expires in the list */
457 uint32_t shortCycleExpiryIndex; /* Index at which UE is stored in shortCycle expires in the list */
458 int32_t shortCycleDistance; /* Distance after how many slot short cycle tmr gets expire */
459 int32_t onDurationStartDistance;/* Distance after how many slot on Duration Start tmr gets expire */
460 int32_t onDurationExpiryDistance;/* Distance after how many slot on Duration tmr gets expire */
461 int32_t inActiveTmrExpiryDistance;/* Distance after how many slot inActive tmr gets expire */
462 CmLList *onDurationStartNodeInfo; /* Node present in on duration start list*/
463 CmLList *onDurationExpiryNodeInfo;/* Node present in on duration exp list*/
464 CmLList *inActvTimerExpiryNodeInfo; /* Node present in in active exp list*/
465 CmLList *shortCycleTmrExpiryNodeInfo; /* Node present in short cycle exp list*/
472 typedef struct schUeCb
479 SchCfraResource cfraResource;
482 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
487 SchDlHqProcCb *msg4HqProc;
488 SchDlHqProcCb *retxMsg4HqProc;
489 SchHqDlMap **hqDlmap;
490 SchHqUlMap **hqUlmap;
497 SchK0K1TimingInfoTbl k0K1InfoTbl;
499 SchK2TimingInfoTbl k2InfoTbl;
506 typedef struct schRaReq
509 RachIndInfo *rachInd;
511 SchUeCb *ueCb; /* Filled only if isCFRA = true */
512 SlotTimingInfo winStartTime;
513 SlotTimingInfo winEndTime;
516 typedef struct schPageInfo
518 uint16_t pf; /*Value of Paging Frame received from DUAPP*/
519 uint8_t i_s; /*Value of Paging Occ Index received from DUAPP*/
520 SlotTimingInfo pageTxTime; /*Start Paging window*/
521 uint8_t mcs; /*MCS index*/
522 uint16_t msgLen; /*Pdu length */
523 uint8_t *pagePdu; /*RRC Page PDU bit string*/
526 typedef struct schPagingOcc
529 uint8_t pagingOccSlot;
532 typedef struct schPageCb
534 CmLListCp pageIndInfoRecord[MAX_SFN]; /*List of Page Records received which are stored per sfn*/
535 SchPagingOcc pagMonOcc[MAX_PO_PER_PF]; /*Paging Occasion Slot/FrameOffset are stored*/
539 typedef struct schDrxCb
541 CmLListCp onDurationStartList; /*!< Tracks the start of onDuration Timer. */
542 CmLListCp onDurationExpiryList; /*!< Tracks the Expiry of onDuration Timer. */
543 CmLListCp inActvTmrExpiryList; /*!< Tracks the Expiry of drx-InactivityTimer. */
544 CmLListCp shortCycleExpiryList; /*!< Tracks the Expiry of DRX Short Cycle. */
545 CmLListCp dlHarqRttExpiryList; /*!< Tracks the Expiry of DL HARQ RTT timer. */
546 CmLListCp dlRetransExpiryList; /*!< Tracks the Expiry of DL Re-Transmission timer. */
547 CmLListCp ulHarqRttExpiryList; /*!< Tracks the Expiry of UL HARQ RTT timer. */
548 CmLListCp ulRetransExpiryList; /*!< Tracks the Expiry of UL Re-Transmission timer. */
549 CmLListCp dlRetransTmrStartList; /*!< It has list of DL harq procs for */
550 CmLListCp ulRetransTmrStartList; /*!< It has list of UL harq procs for */
554 typedef struct schAllApis
556 uint8_t (* SchCellCfgReq)(SchCellCb *cellCb);
557 void (* SchCellDeleteReq)(SchCellCb *cellCb);
558 uint8_t (* SchAddUeConfigReq)(SchUeCb *ueCb);
559 void (* SchModUeConfigReq)(SchUeCb *ueCb);
560 void (* SchUeDeleteReq)(SchUeCb *ueCb);
561 void (* SchDlHarqInd)();
562 void (* SchPagingInd)();
563 void (* SchRachRsrcReq)();
564 void (* SchRachRsrcRel)();
565 void (* SchCrcInd)(SchCellCb *cellCb, uint16_t ueId);
566 void (* SchRachInd)(SchCellCb *cellCb, uint16_t ueId);
567 void (* SchDlRlcBoInfo)(SchCellCb *cellCb, uint16_t ueId);
568 void (* SchSrUciInd)(SchCellCb *cellCb, uint16_t ueId);
569 void (* SchBsr)(SchCellCb *cellCb, uint16_t ueId);
570 void (* SchHandleLcList)(void *ptr, CmLList *node, ActionTypeLL action);
571 void (* SchAddToDlHqRetxList)(SchDlHqProcCb *hqP);
572 void (* SchAddToUlHqRetxList)(SchUlHqProcCb *hqP);
573 void (* SchRemoveFrmDlHqRetxList)(SchUeCb *ueCb, CmLList *node);
574 void (* SchRemoveFrmUlHqRetxList)(SchUeCb *ueCb, CmLList *node);
575 uint8_t (* SchAddUeToSchedule)(SchCellCb *cellCb, uint16_t ueId);
576 void (* SchRemoveUeFrmScheduleLst)(SchCellCb *cell, CmLList *node);
577 uint8_t (* SchInitDlHqProcCb)(SchDlHqProcCb *hqP);
578 uint8_t (* SchInitUlHqProcCb)(SchUlHqProcCb *hqP);
579 void (* SchFreeDlHqProcCb)(SchDlHqProcCb *hqP);
580 void (* SchFreeUlHqProcCb)(SchUlHqProcCb *hqP);
581 void (* SchDeleteDlHqProcCb)(SchDlHqProcCb *hqP);
582 void (* SchDeleteUlHqProcCb)(SchUlHqProcCb *hqP);
583 void (* SchScheduleSlot)(SchCellCb *cell, SlotTimingInfo *slotInd, Inst schInst);
584 uint32_t (* SchScheduleDlLc)(SlotTimingInfo pdcchTime, SlotTimingInfo pdschTime, uint8_t pdschNumSymbols, \
585 uint16_t *startPrb, bool isRetx, SchDlHqProcCb **hqP);
586 uint8_t (* SchScheduleUlLc)(SlotTimingInfo dciTime, SlotTimingInfo puschTime, uint8_t startStmb, \
587 uint8_t symbLen, bool isRetx, SchUlHqProcCb **hqP);
590 typedef struct schHqCfgParam
592 uint8_t maxDlDataHqTx;
594 uint8_t maxUlDataHqTx;
599 /* parameters derived in scheduler */
602 PdcchCfg sib1PdcchCfg;
603 PdschCfg sib1PdschCfg;
606 typedef struct dlTotalPrbUsage
608 uint16_t numPrbUsedForTx;
609 uint16_t totalPrbAvailForTx;
614 TotalPrbUsage *dlTotalPrbUsage;
615 TotalPrbUsage *ulTotalPrbUsage;
620 CmLListCp dlTotPrbUseList;
621 CmLListCp ulTotPrbUseList;
624 typedef struct schStatsGrp
627 uint64_t subscriptionId;
629 uint16_t periodicity; /* In milliseconds */
631 SchKpiSupported kpiStats;
634 typedef struct schStatistics
636 CmLListCp statsGrpList;
637 SchKpiActive activeKpiList;
642 * Cell Control block per cell.
644 typedef struct schCellCb
646 uint16_t cellId; /*!< Cell ID */
647 Inst instIdx; /*!< Index of the scheduler instance */
648 Inst macInst; /*!< Index of the MAC instance */
649 uint16_t numSlots; /*!< Number of slots in current frame */
650 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
651 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
652 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
653 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
655 bool firstSsbTransmitted;
656 bool firstSib1Transmitted;
657 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!< start symbol per SSB beam */
658 uint64_t dedPreambleBitMap; /*!< Bit map to find used/free preambles index */
659 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
660 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
661 uint16_t numActvUe; /*!< Number of active UEs */
662 uint32_t actvUeBitMap; /*!< Bit map to find active UEs */
663 uint32_t boIndBitMap; /*!< Bit map to indicate UEs that have recevied BO */
664 SchUeCb ueCb[MAX_NUM_UE]; /*!< Pointer to UE contexts of this cell */
665 SchPageCb pageCb; /*!< Page Record at Schedular*/
667 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
668 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
669 SchSymbolConfig slotCfg[MAX_TDD_PERIODICITY_SLOTS][MAX_SYMB_PER_SLOT];
672 SchDrxCb drxCb[MAX_DRX_SIZE]; /*!< Drx cb*/
674 SchType schAlgoType; /*!< The scheduler type which the cell is configured with.*/
675 SchAllApis *api; /*!< Reference of sch APIs for this cell based on the SchType*/
676 void *schSpcCell; /*Ref of Scheduler specific structure*/
678 SchK0K1TimingInfoTbl k0K1InfoTbl;
679 SchK2TimingInfoTbl msg3K2InfoTbl;
680 SchK2TimingInfoTbl k2InfoTbl;
681 SchSib1Cfg sib1SchCfg; /* SIB1 config */
682 uint8_t maxMsg3Tx; /* MAximum num of msg3 tx*/
685 typedef struct schTimer
687 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
688 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
689 uint8_t tmrRes; /*!< Timer resolution */
694 * Control block for sch
698 TskInit schInit; /*!< Task Init info */
699 SchGenCb genCfg; /*!< General Config info */
700 SchTimer schTimersInfo; /*!< Sch timer queues and resolution */
701 SchAllApis allApis[NUM_SCH_TYPE]; /*!<List of All Scheduler Type dependent Function pointers*/
702 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
703 CmLListCp sliceCfg; /* Linklist to Store Slice configuration */
704 SchStatistics statistics; /* Statistics configuration and calculated values */
707 /* Declaration for scheduler control blocks */
708 SchCb schCb[SCH_MAX_INST];
710 /* function declarations */
711 short int schActvTmr(Ent ent,Inst inst);
712 void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
714 /* Configuration related function declarations */
715 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
716 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
717 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
718 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
719 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
720 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
721 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
722 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
723 uint8_t addUeToBeScheduled(SchCellCb *cell, uint8_t ueId);
725 /* Incoming message handler function declarations */
726 uint8_t SchProcCellCfgReq(Pst *pst, SchCellCfg *schCellCfg);
727 uint8_t SchProcSlotInd(Pst *pst, SlotTimingInfo *slotInd);
728 uint8_t SchProcRachInd(Pst *pst, RachIndInfo *rachInd);
729 uint8_t SchProcCrcInd(Pst *pst, CrcIndInfo *crcInd);
730 uint8_t SchProcUlCqiInd(Pst *pst, SchUlCqiInd *ulCqiInd);
731 uint8_t SchProcDlCqiInd(Pst *pst, SchDlCqiInd *dlCqiInd);
732 uint8_t SchProcPhrInd(Pst *pst, SchPwrHeadroomInd *schPhrInd);
733 uint8_t SchProcDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo);
734 uint8_t SchAddUeConfigReq(Pst *pst, SchUeCfgReq *ueCfgToSch);
735 uint8_t SchProcBsr(Pst *pst, UlBufferStatusRptInd *bsrInd);
736 uint8_t SchProcSrUciInd(Pst *pst, SrUciIndInfo *uciInd);
737 uint8_t SchModUeConfigReq(Pst *pst, SchUeRecfgReq *ueRecfgToSch);
738 uint8_t SchProcUeDeleteReq(Pst *pst, SchUeDelete *ueDelete);
739 uint8_t SchProcCellDeleteReq(Pst *pst, SchCellDeleteReq *schCellDelete);
740 uint8_t SchProcSliceCfgReq(Pst *pst, SchSliceCfgReq *schSliceCfgReq);
741 uint8_t SchProcSliceRecfgReq(Pst *pst, SchSliceRecfgReq *schSliceRecfgReq);
742 uint8_t SchProcRachRsrcReq(Pst *pst, SchRachRsrcReq *schRachRsrcReq);
743 uint8_t SchProcRachRsrcRel(Pst *pst, SchRachRsrcRel *schRachRsrcRel);
744 uint8_t SchProcPagingInd(Pst *pst, SchPageInd *pageInd);
745 uint8_t SchProcDlHarqInd(Pst *pst, DlHarqInd *dlHarqInd);
747 /* DL scheduling related function declarations */
748 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
749 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
750 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
751 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
752 bool schProcessRaReq(Inst schInst, SchCellCb *cellCb, SlotTimingInfo currTime, uint8_t ueId);
753 uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId,bool isRetxMsg4, SchDlHqProcCb **hqP);
754 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAlloc *rarAlloc, uint8_t k0Index);
755 bool schFillBoGrantDlSchedInfo(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchDlHqProcCb **hqP);
756 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
757 uint32_t tbSize, DlMsgSchInfo *dlMsgAlloc, uint16_t startPRB, uint8_t pdschStartSymbol, uint8_t pdschNumSymbols,bool isRetx, SchDlHqProcCb* hqP);
758 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueId, DlMsgSchInfo *msg4Alloc,\
759 uint8_t pdschStartSymbol, uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP);
760 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
761 uint16_t *startPrb, uint16_t numPrb);
762 void fillDlMsgInfo(DlMsgSchInfo *dlMsgInfo, uint16_t crnti, bool isRetx, SchDlHqProcCb* hqP); /*AS per 38.473 V15.3.0, Section 9.3.1.32 crnti value range is b/w 0..65535*/
763 bool findValidK0K1Value(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool dedMsg, uint8_t *pdschStartSymbol,\
764 uint8_t *pdschSymblLen, SlotTimingInfo *pdcchTime, SlotTimingInfo *pdschTime, SlotTimingInfo *pucchTime, bool isRetx, SchDlHqProcCb *hqP);
765 RaRspWindowStatus isInRaRspWindow(SchRaReq *raReq, SlotTimingInfo frameToCheck, uint16_t numSlotsPerSystemFrame);
767 /* UL scheduling related function declarations */
768 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
769 bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo);
770 uint8_t schCalcPrachNumRb(SchCellCb *cell);
771 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo);
772 uint16_t schAllocPucchResource(SchCellCb *cell, SlotTimingInfo pucchTime, uint16_t crnti,SchUeCb *ueCb, bool isRetx, SchDlHqProcCb *hqP);
773 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo *puschInfo, DciInfo *dciInfo, bool isRetx, SchUlHqProcCb *hqP);
774 uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo puschTime, uint32_t tbSize,
775 uint8_t startSymb, uint8_t symbLen, uint16_t startPrb, bool isRetx, SchUlHqProcCb *hqP);
776 uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
777 uint16_t *startPrb, uint16_t numPrb);
778 bool schProcessSrOrBsrReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchUlHqProcCb **hqP);
780 /*Generic Functions*/
781 void updateGrantSizeForBoRpt(CmLListCp *lcLL, DlMsgSchInfo *dlMsgAlloc, BsrInfo *bsrInfo, uint32_t *accumalatedBOSize);
782 uint16_t searchLargestFreeBlock(SchCellCb *cell, SlotTimingInfo slotTime,uint16_t *startPrb, Direction dir);
783 LcInfo* handleLcLList(CmLListCp *lcLL, uint8_t lcId, ActionTypeLL action);
784 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
785 uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd);
786 void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status);
789 void schProcPagingCfg(SchCellCb *cell);
790 void schCfgPdcchMonOccOfPO(SchCellCb *cell);
791 void schIncrSlot(SlotTimingInfo *timingInfo, uint8_t incr, uint16_t numSlotsPerRF);
792 uint8_t schFillPagePdschCfg(SchCellCb *cell, PageDlSch *pageDlSch, SlotTimingInfo slotTime, \
793 uint16_t tbSize, uint8_t mcs, uint16_t startPrb);
794 /*DL HARQ Functions*/
795 void schDlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
796 void schMsg4FeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk);
797 void schDlHqFeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk1, uint8_t fdbk2);
798 uint8_t schDlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchDlHqProcCb **hqP);
799 void schDlReleaseHqProcess(SchDlHqProcCb *hqP);
800 void schDlHqEntDelete(SchUeCb *ueCb);
802 /*UL HARQ Functions*/
803 void schUlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
804 uint8_t schMsg3RetxSchedulingForUe(SchRaCb *raCb);
805 void schUlHqProcessNack(SchUlHqProcCb *hqP);
806 void schUlHqProcessAck(SchUlHqProcCb *hqP);
807 uint8_t schUlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchUlHqProcCb **hqP);
808 void schUlReleaseHqProcess(SchUlHqProcCb *hqP, Bool togNdi);
809 void schUlHqEntDelete(SchUeCb *ueCb);
811 /* UE Manager HARQ Fun*/
812 void schUpdateHarqFdbk(SchUeCb *ueCb, uint8_t numHarq, uint8_t *harqPayload,SlotTimingInfo *slotInd);
814 /* Round Robbin Scheduler funtions*/
815 uint8_t schFillUlDciForMsg3Retx(SchRaCb *raCb, SchPuschInfo *puschInfo, DciInfo *dciInfo);
816 bool schGetMsg3K2(SchCellCb *cell, SchUlHqProcCb* msg3HqProc, uint16_t dlTime, SlotTimingInfo *msg3Time, bool isRetx);
817 void schMsg4Complete(SchUeCb *ueCb);
819 /* Statistics Function */
820 uint8_t SchProcStatsReq(Pst *pst, SchStatsReq *statsReq);
821 uint8_t SchSendStatsIndToMac(Inst inst, SchStatsInd *statsInd);
822 uint8_t schCalcAndSendGrpStats(SchStatsGrp *grpInfo);
823 uint8_t SchProcStatsDeleteReq(Pst *pst, SchStatsDeleteReq *statsDeleteReq);
824 uint8_t SchProcStatsModificationReq(Pst *pst, SchStatsModificationReq *statsModificationReq);
825 void deleteStatsGrpInfo(Inst inst, SchStatsGrp *statsGrpInfo);
826 /**********************************************************************
828 **********************************************************************/