1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
20 #define SCH_MU0_NUM_SLOTS 10
21 #define SCH_MU1_NUM_SLOTS 20
22 #define SCH_MU2_NUM_SLOTS 30
23 #define SCH_MU3_NUM_SLOTS 40
24 #define SCH_MU4_NUM_SLOTS 50
25 #define SCH_MAX_SFN 1024
26 #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */
27 #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */
28 #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
29 #define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */
30 #define SCH_SSB_NUM_SYMB 4
31 #define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */
36 #define PDSCH_START_RB 10
37 /* Considering pdsch region from 3 to 13, DMRS exclued.
38 * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */
39 #define NUM_PDSCH_SYMBOL 11
40 #define PUSCH_START_RB 15
41 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
42 #define SI_RNTI 0xFFFF
44 #define DMRS_MAP_TYPE_A 1
45 #define NUM_DMRS_SYMBOLS 1
46 #define DMRS_ADDITIONAL_POS 0
47 #define SCH_DEFAULT_K1 1
48 #define SSB_IDX_SUPPORTED 1
53 #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */
54 #define UL_GRANT_SIZE 224
56 #define PRB_BITMAP_IDX_LEN 64
57 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN)
59 #define SCH_MAX_NUM_UL_HQ_PROC 16
60 #define SCH_MAX_NUM_DL_HQ_PROC 16
61 #define SCH_MAX_NUM_MSG3_TX 2
62 #define SCH_MAX_NUM_DL_HQ_TX 3
63 #define SCH_MAX_NUM_UL_HQ_TX 3
64 #define SCH_MAX_NUM_MSG4_TX 2
68 #define ROOT_SEQ_LEN_1 139
69 #define ROOT_SEQ_LEN_2 839
72 /* As per 38.331 the largest offset which can be used in of size 10240.
73 * But using this much size of array can cause memory related issue so thats why
74 * taking this size which are a multiple of the larger size */
75 #define MAX_DRX_SIZE 512
78 #define NUM_SCH_TYPE 2 /*Supported number of Scheduler Algorithm types*/
80 #define SCH_TQ_SIZE 10
82 typedef struct schDlHqProcCb SchDlHqProcCb;
83 typedef struct schUlHqEnt SchUlHqEnt;
84 typedef struct schRaReq SchRaReq;
85 typedef struct schDlHqEnt SchDlHqEnt;
86 typedef struct schCellCb SchCellCb;
87 typedef struct schUeCb SchUeCb;
106 SCH_UE_STATE_INACTIVE,
108 SCH_UE_HANDIN_IN_PROGRESS
113 SCH_RA_STATE_MSG2_HANDLE,
114 SCH_RA_STATE_MSG3_PENDING,
115 SCH_RA_STATE_MSG4_PENDING,
116 SCH_RA_STATE_MSG4_DONE
121 SCH_LC_STATE_INACTIVE,
155 /*Following structures to keep record and estimations of PRB allocated for each
156 * LC taking into consideration the RRM policies*/
157 typedef struct lcInfo
159 uint8_t lcId; /*LCID for which BO are getting recorded*/
160 uint32_t reqBO; /*Size of the BO requested/to be allocated for this LC*/
161 uint32_t allocBO; /*TBS/BO Size which is actually allocated*/
162 uint8_t allocPRB; /*PRB count which is allocated based on RRM policy/FreePRB*/
165 typedef struct schUlHqTbCb
173 SchMcsTable mcsTable;
179 uint8_t cntrRetxAllocFail;
183 typedef struct schDlHqTbCb
196 uint8_t isAckNackDtx;
197 uint8_t cntrRetxAllocFail;
198 //InfUeTbInfo tbCompInfo;
203 typedef struct schDrxHarqCb
205 uint32_t rttExpIndex;
207 uint32_t retxStrtIndex;
208 CmLList *retxStrtNode;
209 uint32_t retxExpIndex;
210 CmLList *retxExpNode;
214 typedef struct schUlHqProcCb
216 uint8_t procId; /*!< HARQ Process ID */
218 uint8_t maxHqTxPerHqP;
224 void *schSpcUlHqProcCb; /*!< Scheduler specific HARQ Proc CB */
225 CmLList ulHqProcLink;
226 uint8_t puschResType; /*!< Resource allocation type */
227 uint16_t puschStartPrb;
228 uint16_t puschNumPrb;
229 uint8_t dmrsMappingType;
230 uint8_t nrOfDmrsSymbols;
232 SlotTimingInfo puschTime;
234 SchDrxHarqCb ulDrxHarqCb;
240 uint8_t procId; /*!< HARQ Process ID */
242 uint8_t maxHqTxPerHqP;
245 SchDlHqTbCb tbInfo[2];
247 void *schSpcDlHqProcCb; /*!< Scheduler specific HARQ Proc CB */
248 CmLList dlHqProcLink;
249 SlotTimingInfo pucchTime;
251 SchDrxHarqCb dlDrxHarqCb;
256 SchCellCb *cell; /*!< Contains the pointer to cell*/
257 SchUeCb *ue; /*!< Contains the pointer to ue*/
258 CmLListCp free; /*!< List of free HARQ processes */
259 CmLListCp inUse; /*!< List of in-use HARQ processes */
260 uint8_t maxHqTx; /*!< Maximum number of harq re-transmissions */
261 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
262 SchUlHqProcCb procs[SCH_MAX_NUM_UL_HQ_PROC]; /*!< Uplink harq process info */
266 SchCellCb *cell; /*!< Contains the pointer to cell */
267 SchUeCb *ue; /*!< Contains the pointer to UE */
268 CmLListCp free; /*!< List of free HARQ processes */
269 CmLListCp inUse; /*!< List of in-use HARQ processes */
270 uint8_t maxHqTx; /*!< Maximum number of harq transmissions */
271 uint8_t numHqPrcs; /*!< Number of HARQ Processes */
272 SchDlHqProcCb procs[SCH_MAX_NUM_DL_HQ_PROC];/*!< Downlink harq processes */
277 * Structure holding LTE MAC's General Configuration information.
279 typedef struct schGenCb
281 uint8_t startCellId; /*!< Starting Cell Id */
283 bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
284 of RLC control BO and SRB BO on
285 PCell. val 0 means don't force*/
286 bool isSCellActDeactAlgoEnable; /*!< TRUE will enable activation/deactivation algo at Schd */
290 typedef struct freePrbBlock
299 * PRB allocations for a symbol within a slot
301 typedef struct schPrbAlloc
303 CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */
304 uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */
305 uint16_t numPrbAlloc;
310 * scheduler allocationsfor DL per cell.
312 typedef struct schDlSlotInfo
314 SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */
315 bool ssbPres; /*!< Flag to determine if SSB is present in this slot */
316 uint8_t ssbIdxSupported; /*!< Max SSB index */
317 SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */
318 bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */
319 uint8_t pdcchUe; /*!< UE for which PDCCH is scheduled in this slot */
320 uint8_t pdschUe; /*!< UE for which PDSCH is scheduled in this slot */
321 RarAlloc *rarAlloc[MAX_NUM_UE]; /*!< RAR allocation per UE*/
323 DlMsgSchInfo *dlMsgAlloc[MAX_NUM_UE]; /*!< Dl msg allocation per UE*/
326 typedef struct schRaCb
331 uint16_t dlMsgPduLen;
332 SchUlHqProcCb msg3HqProc;
333 SchUlHqProcCb *retxMsg3HqProc;
341 * scheduler allocationsfor UL per cell.
343 typedef struct schUlSlotInfo
345 SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */
346 uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */
347 bool puschPres; /*!< PUSCH presence field */
348 SchPuschInfo *schPuschInfo; /*!< PUSCH info */
349 bool pucchPres; /*!< PUCCH presence field */
350 SchPucchInfo schPucchInfo; /*!< PUCCH info */
351 uint8_t pucchUe; /*!< Store UE id for which PUCCH is scheduled */
352 uint8_t puschUe; /*!< Store UE id for which PUSCH is scheduled */
357 * BSR info per slot per UE.
359 typedef struct bsrInfo
361 uint8_t priority; /* CG priority */
362 uint32_t dataVol; /* Data volume requested in bytes */
365 typedef struct schLcCtxt
367 uint8_t lcId; // logical Channel ID
368 uint8_t lcp; // logical Channel Prioritization
371 uint16_t pduSessionId; /*Pdu Session Id*/
372 Snssai *snssai; /*S-NSSAI assoc with LCID*/
373 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
374 uint16_t rsvdDedicatedPRB;
377 typedef struct schDlCb
379 SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
382 typedef struct schUlLcCtxt
389 uint8_t pbr; // prioritisedBitRate
390 uint8_t bsd; // bucketSizeDuration
391 uint16_t pduSessionId; /*Pdu Session Id*/
392 Snssai *snssai; /*S-NSSAI assoc with LCID*/
393 bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/
394 uint16_t rsvdDedicatedPRB;
397 typedef struct schUlCb
399 SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
402 typedef struct schUeCfgCb
407 bool macCellGrpCfgPres;
408 SchMacCellGrpCfg macCellGrpCfg;
409 bool phyCellGrpCfgPres;
410 SchPhyCellGrpCfg phyCellGrpCfg;
412 SchSpCellRecfg spCellCfg;
414 SchModulationInfo dlModInfo;
415 SchModulationInfo ulModInfo;
416 SchDataTransmission dataTransmissionAction;
419 typedef struct schHqDlMap
424 typedef struct schHqUlMap
430 typedef struct schDrxUeCb
432 bool drxDlUeActiveStatus; /* Final Dl Ue status which is marked as true if drxDlUeActiveMask or drxDlUeActiveMaskForHarq is present */
433 bool drxUlUeActiveStatus; /* Final Ul Ue status which is marked as true if drxUlUeActiveMask or drxUlUeActiveMaskForHarq is present */
434 uint32_t drxDlUeActiveMask; /* variable is used to store the status about downlink active status of Ue for On-duration, inactive timer*/
435 uint32_t drxUlUeActiveMask; /* variable is used to store the status about uplink active status for on-duration inactive timer*/
436 uint32_t drxDlUeActiveMaskForHarq; /* variable is used to store the status about downlink active status for harq*/
437 uint32_t drxUlUeActiveMaskForHarq; /* variable is used to store the status about uplink active status for harq */
438 uint32_t onDurationLen; /* length of on duration which is received from ue cfg/recfg in form of ms and subms, informs about after how many slots on duration gets expire */
439 uint32_t inActvTimerLen; /* length of inActvTimer value received from ue cfg/recfg in form of ms, informs about after how many slots in active gets expire */
440 uint8_t harqRttDlTimerLen; /* length of harqRttDlTimer received from ue cfg/recfg in form of symbols, inform about after how many slots on the harq drx-HARQ-RTT-TimerDL expire */
441 uint8_t harqRttUlTimerLen; /* length of harqRttUlTimer received from ue cfg/recfg in form of symbols,informs about after how many slots on harq drx-HARQ-RTT-TimerUL expire*/
442 uint32_t retransDlTimerLen; /* length of retransDlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer dl timer expire*/
443 uint32_t retransUlTimerLen; /* length of retransUlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer ul timer expire*/
444 uint32_t longCycleLen; /* length of long Cycle value received from ue cfg/recfg in form of ms*/
445 bool longCycleToBeUsed; /* long cycle should be used once the short cycle gets expires */
446 uint32_t drxStartOffset; /* length of drxStartOffset value received from ue cfg/recfg in form of ms, which helps in getting on duration start point*/
447 bool shortCyclePresent; /* set this value if shortCycle is Present */
448 uint32_t shortCycleLen; /* length of short Cycle value received from ue cfg/recfg in form of ms*/
449 uint32_t shortCycleTmrLen; /* value shortCycleTmr is the multiple of shortCycle which is received from ue cfg/recfg in form of integer*/
450 uint32_t drxSlotOffset; /* drxSlotOffset value received from ue cfg/recfg which is used to delay before starting the drx-onDuration*/
451 uint32_t onDurationStartIndex; /* Index at which UE is stored in onDuration starts list */
452 uint32_t onDurationExpiryIndex; /* Index at which UE is stored in onDuration expires in the list */
453 uint32_t inActvExpiryIndex; /* Index at which UE is stored in inActvTimer expires in the list */
454 uint32_t shortCycleExpiryIndex; /* Index at which UE is stored in shortCycle expires in the list */
455 int32_t shortCycleDistance; /* Distance after how many slot short cycle tmr gets expire */
456 int32_t onDurationStartDistance;/* Distance after how many slot on Duration Start tmr gets expire */
457 int32_t onDurationExpiryDistance;/* Distance after how many slot on Duration tmr gets expire */
458 int32_t inActiveTmrExpiryDistance;/* Distance after how many slot inActive tmr gets expire */
459 CmLList *onDurationStartNodeInfo; /* Node present in on duration start list*/
460 CmLList *onDurationExpiryNodeInfo;/* Node present in on duration exp list*/
461 CmLList *inActvTimerExpiryNodeInfo; /* Node present in in active exp list*/
462 CmLList *shortCycleTmrExpiryNodeInfo; /* Node present in short cycle exp list*/
469 typedef struct schUeCb
476 SchCfraResource cfraResource;
479 BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
484 SchDlHqProcCb *msg4HqProc;
485 SchDlHqProcCb *retxMsg4HqProc;
486 SchHqDlMap **hqDlmap;
487 SchHqUlMap **hqUlmap;
494 SchK0K1TimingInfoTbl k0K1InfoTbl;
496 SchK2TimingInfoTbl k2InfoTbl;
503 typedef struct schRaReq
506 RachIndInfo *rachInd;
508 SchUeCb *ueCb; /* Filled only if isCFRA = true */
509 SlotTimingInfo winStartTime;
510 SlotTimingInfo winEndTime;
513 typedef struct schPageInfo
515 uint16_t pf; /*Value of Paging Frame received from DUAPP*/
516 uint8_t i_s; /*Value of Paging Occ Index received from DUAPP*/
517 SlotTimingInfo pageTxTime; /*Start Paging window*/
518 uint8_t mcs; /*MCS index*/
519 uint16_t msgLen; /*Pdu length */
520 uint8_t *pagePdu; /*RRC Page PDU bit string*/
523 typedef struct schPagingOcc
526 uint8_t pagingOccSlot;
529 typedef struct schPageCb
531 CmLListCp pageIndInfoRecord[MAX_SFN]; /*List of Page Records received which are stored per sfn*/
532 SchPagingOcc pagMonOcc[MAX_PO_PER_PF]; /*Paging Occasion Slot/FrameOffset are stored*/
536 typedef struct schDrxCb
538 CmLListCp onDurationStartList; /*!< Tracks the start of onDuration Timer. */
539 CmLListCp onDurationExpiryList; /*!< Tracks the Expiry of onDuration Timer. */
540 CmLListCp inActvTmrExpiryList; /*!< Tracks the Expiry of drx-InactivityTimer. */
541 CmLListCp shortCycleExpiryList; /*!< Tracks the Expiry of DRX Short Cycle. */
542 CmLListCp dlHarqRttExpiryList; /*!< Tracks the Expiry of DL HARQ RTT timer. */
543 CmLListCp dlRetransExpiryList; /*!< Tracks the Expiry of DL Re-Transmission timer. */
544 CmLListCp ulHarqRttExpiryList; /*!< Tracks the Expiry of UL HARQ RTT timer. */
545 CmLListCp ulRetransExpiryList; /*!< Tracks the Expiry of UL Re-Transmission timer. */
546 CmLListCp dlRetransTmrStartList; /*!< It has list of DL harq procs for */
547 CmLListCp ulRetransTmrStartList; /*!< It has list of UL harq procs for */
551 typedef struct schAllApis
553 uint8_t (* SchCellCfgReq)(SchCellCb *cellCb);
554 void (* SchCellDeleteReq)(SchCellCb *cellCb);
555 uint8_t (* SchAddUeConfigReq)(SchUeCb *ueCb);
556 void (* SchModUeConfigReq)(SchUeCb *ueCb);
557 void (* SchUeDeleteReq)(SchUeCb *ueCb);
558 void (* SchDlHarqInd)();
559 void (* SchPagingInd)();
560 void (* SchRachRsrcReq)();
561 void (* SchRachRsrcRel)();
562 void (* SchCrcInd)(SchCellCb *cellCb, uint16_t ueId);
563 void (* SchRachInd)(SchCellCb *cellCb, uint16_t ueId);
564 void (* SchDlRlcBoInfo)(SchCellCb *cellCb, uint16_t ueId);
565 void (* SchSrUciInd)(SchCellCb *cellCb, uint16_t ueId);
566 void (* SchBsr)(SchCellCb *cellCb, uint16_t ueId);
567 void (* SchHandleLcList)(void *ptr, CmLList *node, ActionTypeLL action);
568 void (* SchAddToDlHqRetxList)(SchDlHqProcCb *hqP);
569 void (* SchAddToUlHqRetxList)(SchUlHqProcCb *hqP);
570 void (* SchRemoveFrmDlHqRetxList)(SchUeCb *ueCb, CmLList *node);
571 void (* SchRemoveFrmUlHqRetxList)(SchUeCb *ueCb, CmLList *node);
572 uint8_t (* SchAddUeToSchedule)(SchCellCb *cellCb, uint16_t ueId);
573 void (* SchRemoveUeFrmScheduleLst)(SchCellCb *cell, CmLList *node);
574 uint8_t (* SchInitDlHqProcCb)(SchDlHqProcCb *hqP);
575 uint8_t (* SchInitUlHqProcCb)(SchUlHqProcCb *hqP);
576 void (* SchFreeDlHqProcCb)(SchDlHqProcCb *hqP);
577 void (* SchFreeUlHqProcCb)(SchUlHqProcCb *hqP);
578 void (* SchDeleteDlHqProcCb)(SchDlHqProcCb *hqP);
579 void (* SchDeleteUlHqProcCb)(SchUlHqProcCb *hqP);
580 void (* SchScheduleSlot)(SchCellCb *cell, SlotTimingInfo *slotInd, Inst schInst);
581 uint32_t (* SchScheduleDlLc)(SlotTimingInfo pdcchTime, SlotTimingInfo pdschTime, uint8_t pdschNumSymbols, \
582 uint16_t *startPrb, bool isRetx, SchDlHqProcCb **hqP);
583 uint8_t (* SchScheduleUlLc)(SlotTimingInfo dciTime, SlotTimingInfo puschTime, uint8_t startStmb, \
584 uint8_t symbLen, bool isRetx, SchUlHqProcCb **hqP);
587 typedef struct schHqCfgParam
589 uint8_t maxDlDataHqTx;
591 uint8_t maxUlDataHqTx;
596 /* parameters derived in scheduler */
599 PdcchCfg sib1PdcchCfg;
600 PdschCfg sib1PdschCfg;
603 typedef struct dlTotalPrbUsage
606 uint16_t numPrbUsedForTx;
607 uint16_t totalPrbAvailForTx;
608 uint16_t periodicity;
612 typedef struct schStatistics
614 TotalPrbUsage *dlTotalPrbUsage;
615 TotalPrbUsage *ulTotalPrbUsage;
620 * Cell Control block per cell.
622 typedef struct schCellCb
624 uint16_t cellId; /*!< Cell ID */
625 Inst instIdx; /*!< Index of the scheduler instance */
626 Inst macInst; /*!< Index of the MAC instance */
627 uint16_t numSlots; /*!< Number of slots in current frame */
628 SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/
629 SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
630 SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
631 SchCellCfg cellCfg; /*!< Cell ocnfiguration */
633 bool firstSsbTransmitted;
634 bool firstSib1Transmitted;
635 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!< start symbol per SSB beam */
636 uint64_t dedPreambleBitMap; /*!< Bit map to find used/free preambles index */
637 SchRaReq *raReq[MAX_NUM_UE]; /*!< Pending RA request */
638 SchRaCb raCb[MAX_NUM_UE]; /*!< RA Cb */
639 uint16_t numActvUe; /*!< Number of active UEs */
640 uint32_t actvUeBitMap; /*!< Bit map to find active UEs */
641 uint32_t boIndBitMap; /*!< Bit map to indicate UEs that have recevied BO */
642 SchUeCb ueCb[MAX_NUM_UE]; /*!< Pointer to UE contexts of this cell */
643 SchPageCb pageCb; /*!< Page Record at Schedular*/
645 uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
646 uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
647 SchSymbolConfig slotCfg[MAX_TDD_PERIODICITY_SLOTS][MAX_SYMB_PER_SLOT];
650 SchDrxCb drxCb[MAX_DRX_SIZE]; /*!< Drx cb*/
652 SchType schAlgoType; /*!< The scheduler type which the cell is configured with.*/
653 SchAllApis *api; /*!< Reference of sch APIs for this cell based on the SchType*/
654 void *schSpcCell; /*Ref of Scheduler specific structure*/
656 SchK0K1TimingInfoTbl k0K1InfoTbl;
657 SchK2TimingInfoTbl msg3K2InfoTbl;
658 SchK2TimingInfoTbl k2InfoTbl;
659 SchSib1Cfg sib1SchCfg; /* SIB1 config */
660 uint8_t maxMsg3Tx; /* MAximum num of msg3 tx*/
663 typedef struct schTimer
665 CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */
666 CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */
667 uint8_t tmrRes; /*!< Timer resolution */
672 * Control block for sch
676 TskInit schInit; /*!< Task Init info */
677 SchGenCb genCfg; /*!< General Config info */
678 SchTimer schTimersInfo; /*!< Sch timer queues and resolution */
679 SchAllApis allApis[NUM_SCH_TYPE]; /*!<List of All Scheduler Type dependent Function pointers*/
680 SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */
681 CmLListCp sliceCfg; /* Linklist to Store Slice configuration */
682 SchStatistics statistics; /* Statistics configuration and calculated values */
685 /* Declaration for scheduler control blocks */
686 SchCb schCb[SCH_MAX_INST];
688 /* function declarations */
689 short int schActvTmr(Ent ent,Inst inst);
690 void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
692 /* Configuration related function declarations */
693 void schInitUlSlot(SchUlSlotInfo *schUlSlotInfo);
694 void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo);
695 void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, \
696 SchPdschCfgCmn pdschCmnCfg,SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl);
697 void BuildK2InfoTable(SchCellCb *cell, SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[], \
698 uint16_t puschSymTblSize, SchK2TimingInfoTbl *msg3K2InfoTbl, SchK2TimingInfoTbl *k2InfoTbl);
699 uint8_t SchSendCfgCfm(Pst *pst, RgMngmt *cfm);
700 SchUeCb* schGetUeCb(SchCellCb *cellCb, uint16_t crnti);
701 uint8_t addUeToBeScheduled(SchCellCb *cell, uint8_t ueId);
703 /* Incoming message handler function declarations */
704 uint8_t SchProcCellCfgReq(Pst *pst, SchCellCfg *schCellCfg);
705 uint8_t SchProcSlotInd(Pst *pst, SlotTimingInfo *slotInd);
706 uint8_t SchProcRachInd(Pst *pst, RachIndInfo *rachInd);
707 uint8_t SchProcCrcInd(Pst *pst, CrcIndInfo *crcInd);
708 uint8_t SchProcUlCqiInd(Pst *pst, SchUlCqiInd *ulCqiInd);
709 uint8_t SchProcDlCqiInd(Pst *pst, SchDlCqiInd *dlCqiInd);
710 uint8_t SchProcPhrInd(Pst *pst, SchPwrHeadroomInd *schPhrInd);
711 uint8_t SchProcDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo);
712 uint8_t SchAddUeConfigReq(Pst *pst, SchUeCfgReq *ueCfgToSch);
713 uint8_t SchProcBsr(Pst *pst, UlBufferStatusRptInd *bsrInd);
714 uint8_t SchProcSrUciInd(Pst *pst, SrUciIndInfo *uciInd);
715 uint8_t SchModUeConfigReq(Pst *pst, SchUeRecfgReq *ueRecfgToSch);
716 uint8_t SchProcUeDeleteReq(Pst *pst, SchUeDelete *ueDelete);
717 uint8_t SchProcCellDeleteReq(Pst *pst, SchCellDeleteReq *schCellDelete);
718 uint8_t SchProcSliceCfgReq(Pst *pst, SchSliceCfgReq *schSliceCfgReq);
719 uint8_t SchProcSliceRecfgReq(Pst *pst, SchSliceRecfgReq *schSliceRecfgReq);
720 uint8_t SchProcRachRsrcReq(Pst *pst, SchRachRsrcReq *schRachRsrcReq);
721 uint8_t SchProcRachRsrcRel(Pst *pst, SchRachRsrcRel *schRachRsrcRel);
722 uint8_t SchProcPagingInd(Pst *pst, SchPageInd *pageInd);
723 uint8_t SchProcDlHarqInd(Pst *pst, DlHarqInd *dlHarqInd);
725 /* DL scheduling related function declarations */
726 PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime);
727 PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime);
728 uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
729 uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc);
730 bool schProcessRaReq(Inst schInst, SchCellCb *cellCb, SlotTimingInfo currTime, uint8_t ueId);
731 uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId,bool isRetxMsg4, SchDlHqProcCb **hqP);
732 uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAlloc *rarAlloc, uint8_t k0Index);
733 bool schFillBoGrantDlSchedInfo(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchDlHqProcCb **hqP);
734 uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti,
735 uint32_t tbSize, DlMsgSchInfo *dlMsgAlloc, uint16_t startPRB, uint8_t pdschStartSymbol, uint8_t pdschNumSymbols,bool isRetx, SchDlHqProcCb* hqP);
736 uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueId, DlMsgSchInfo *msg4Alloc,\
737 uint8_t pdschStartSymbol, uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP);
738 uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
739 uint16_t *startPrb, uint16_t numPrb);
740 void fillDlMsgInfo(DlMsgSchInfo *dlMsgInfo, uint16_t crnti, bool isRetx, SchDlHqProcCb* hqP); /*AS per 38.473 V15.3.0, Section 9.3.1.32 crnti value range is b/w 0..65535*/
741 bool findValidK0K1Value(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool dedMsg, uint8_t *pdschStartSymbol,\
742 uint8_t *pdschSymblLen, SlotTimingInfo *pdcchTime, SlotTimingInfo *pdschTime, SlotTimingInfo *pucchTime, bool isRetx, SchDlHqProcCb *hqP);
743 RaRspWindowStatus isInRaRspWindow(SchRaReq *raReq, SlotTimingInfo frameToCheck, uint16_t numSlotsPerSystemFrame);
745 /* UL scheduling related function declarations */
746 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst);
747 bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo);
748 uint8_t schCalcPrachNumRb(SchCellCb *cell);
749 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotTimingInfo prachOccasionTimingInfo);
750 uint16_t schAllocPucchResource(SchCellCb *cell, SlotTimingInfo pucchTime, uint16_t crnti,SchUeCb *ueCb, bool isRetx, SchDlHqProcCb *hqP);
751 uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo *puschInfo, DciInfo *dciInfo, bool isRetx, SchUlHqProcCb *hqP);
752 uint8_t schFillPuschAlloc(SchUeCb *ueCb, SlotTimingInfo puschTime, uint32_t tbSize,
753 uint8_t startSymb, uint8_t symbLen, uint16_t startPrb, bool isRetx, SchUlHqProcCb *hqP);
754 uint8_t allocatePrbUl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \
755 uint16_t *startPrb, uint16_t numPrb);
756 bool schProcessSrOrBsrReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchUlHqProcCb **hqP);
758 /*Generic Functions*/
759 void updateGrantSizeForBoRpt(CmLListCp *lcLL, DlMsgSchInfo *dlMsgAlloc, BsrInfo *bsrInfo, uint32_t *accumalatedBOSize);
760 uint16_t searchLargestFreeBlock(SchCellCb *cell, SlotTimingInfo slotTime,uint16_t *startPrb, Direction dir);
761 LcInfo* handleLcLList(CmLListCp *lcLL, uint8_t lcId, ActionTypeLL action);
762 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
763 uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd);
764 void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status);
767 void schProcPagingCfg(SchCellCb *cell);
768 void schCfgPdcchMonOccOfPO(SchCellCb *cell);
769 void schIncrSlot(SlotTimingInfo *timingInfo, uint8_t incr, uint16_t numSlotsPerRF);
770 uint8_t schFillPagePdschCfg(SchCellCb *cell, PageDlSch *pageDlSch, SlotTimingInfo slotTime, \
771 uint16_t tbSize, uint8_t mcs, uint16_t startPrb);
772 /*DL HARQ Functions*/
773 void schDlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
774 void schMsg4FeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk);
775 void schDlHqFeedbackUpdate(SchDlHqProcCb *hqP, uint8_t fdbk1, uint8_t fdbk2);
776 uint8_t schDlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchDlHqProcCb **hqP);
777 void schDlReleaseHqProcess(SchDlHqProcCb *hqP);
778 void schDlHqEntDelete(SchUeCb *ueCb);
780 /*UL HARQ Functions*/
781 void schUlHqEntInit(SchCellCb *cellCb, SchUeCb *ueCb);
782 uint8_t schMsg3RetxSchedulingForUe(SchRaCb *raCb);
783 void schUlHqProcessNack(SchUlHqProcCb *hqP);
784 void schUlHqProcessAck(SchUlHqProcCb *hqP);
785 uint8_t schUlGetAvlHqProcess(SchCellCb *cellCb, SchUeCb *ueCb, SchUlHqProcCb **hqP);
786 void schUlReleaseHqProcess(SchUlHqProcCb *hqP, Bool togNdi);
787 void schUlHqEntDelete(SchUeCb *ueCb);
789 /* UE Manager HARQ Fun*/
790 void schUpdateHarqFdbk(SchUeCb *ueCb, uint8_t numHarq, uint8_t *harqPayload,SlotTimingInfo *slotInd);
792 /* Round Robbin Scheduler funtions*/
793 uint8_t schFillUlDciForMsg3Retx(SchRaCb *raCb, SchPuschInfo *puschInfo, DciInfo *dciInfo);
794 bool schGetMsg3K2(SchCellCb *cell, SchUlHqProcCb* msg3HqProc, uint16_t dlTime, SlotTimingInfo *msg3Time, bool isRetx);
795 void schMsg4Complete(SchUeCb *ueCb);
797 /* Statistics Function */
798 uint8_t SchProcStatsReq(Pst *pst, SchStatsReq *statsReq);
799 uint8_t SchSendStatsIndToMac(Inst inst, SchMeasurementType measType, double value);
801 /**********************************************************************
803 **********************************************************************/