1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for Entry point fucntions
29 **********************************************************************/
31 /** @file rg_sch_utl.c
32 @brief This file implements the schedulers main access to MAC layer code.
36 /* header include files -- defines (.h) */
37 #include "common_def.h"
42 #include "rg_sch_err.h"
43 #include "rg_sch_inf.h"
45 #include "rg_sch_cmn.h"
48 /* header/extern include files (.x) */
49 #include "tfu.x" /* TFU types */
50 #include "lrg.x" /* layer management typedefs for MAC */
51 #include "rgr.x" /* layer management typedefs for MAC */
53 #include "rg_sch_inf.x" /* typedefs for Scheduler */
54 #include "rg_sch.x" /* typedefs for Scheduler */
55 #include "rg_sch_cmn.x" /* typedefs for Scheduler */
57 #include "rg_sch_emtc_ext.x"
62 uint32_t rgNumPrachRecvd =0; /* Num of Rach Req received including dedicated preambles */
63 uint32_t rgNumRarSched =0; /* Num of RARs sent */
64 uint32_t rgNumBI =0; /* Num of BackOff Ind sent */
65 uint32_t rgNumMsg3CrcPassed =0; /* Num of CRC success for Msg3 */
66 uint32_t rgNumMsg3CrcFailed =0; /* Num of CRC fail for Msg 3 */
67 uint32_t rgNumMsg3FailMaxRetx =0; /* Num of Msg3 fail after Max Retx attempts */
68 uint32_t rgNumMsg4Ack =0; /* Num of Acks for Msg4 Tx */
69 uint32_t rgNumMsg4Nack =0;
70 /* Num of Nacks for Msg4 Tx */
71 uint32_t rgNumMsg4FailMaxRetx =0; /* Num of Msg4 Tx failed after Max Retx attempts */
72 uint32_t rgNumSrRecvd =0; /* Num of Sched Req received */
73 uint32_t rgNumSrGrant =0; /* Num of Sched Req Grants sent */
74 uint32_t rgNumMsg3CrntiCE =0; /* Num of Msg 3 CRNTI CE received */
75 uint32_t rgNumDedPream =0; /* Num of Dedicated Preambles recvd */
76 uint32_t rgNumMsg3CCCHSdu =0; /* Num of Msg 3 CCCH Sdus recvd */
77 uint32_t rgNumCCCHSduCrntiNotFound =0; /*UE Ctx not found for CCCH SDU Msg 3 */
78 uint32_t rgNumCrntiCeCrntiNotFound =0; /*UE Ctx not found for CRNTI CE Msg 3 */
79 uint32_t rgNumMsg4WithCCCHSdu =0; /* Num of Msg4 with CCCH Sdu */
80 uint32_t rgNumMsg4WoCCCHSdu =0; /* Num of Msg4 without CCCH Sdu */
81 uint32_t rgNumMsg4Dtx =0; /* Num of DTX received for Msg 4 */
82 uint32_t rgNumMsg3AckSent =0; /* Num of PHICH Ack sent for Msg 3 */
83 uint32_t rgNumMsg3NackSent =0; /* Num of PHICH Nack sent for Msg 3 */
84 uint32_t rgNumMsg4PdcchWithCrnti =0; /* Num of PDCCH for CRNTI based contention resolution */
85 uint32_t rgNumRarFailDuetoRntiExhaustion =0; /* Num of RACH Failures due to RNTI pool exhaution */
86 uint32_t rgNumTAModified =0; /* Num of times TA received is different from prev value */
87 uint32_t rgNumTASent =0; /* Num of TA Command sent */
88 uint32_t rgNumMsg4ToBeTx =0; /* Num of times MSG4 that should be sent */
89 uint32_t rgNumMsg4Txed =0; /* Num of MSG4 actually sent *//* ysNumMsg4ToBeTx -ysNumMsg4Txed == Failed MSG4 TX */
90 uint32_t rgNumMsg3DtxRcvd =0; /* CRC Fail with SINR < 0 */
92 uint32_t rgNumDedPreamUECtxtFound =0; /* Num of Dedicated Preambles recvd */
94 static uint8_t rgSchDciAmbigSizeTbl[61] = {0,0,0,0,0,0,0,0,0,0,0,
95 0,1,0,1,0,1,0,0,0,1,
96 0,0,0,1,0,1,0,0,0,0,
97 0,1,0,0,0,0,0,0,0,1,
98 0,0,0,1,0,0,0,0,0,0,
103 uint32_t rgSchCmnBetaCqiOffstTbl[16];
104 uint32_t rgSchCmnBetaRiOffstTbl[16];
105 RgSchdApis rgSchCmnApis;
106 S16 RgUiRgmSendPrbRprtInd ARGS((
109 RgmPrbRprtInd *prbRprtInd
112 S16 RgUiRgmSendTmModeChangeInd ARGS((
115 RgmTransModeInd *txModeChngInd
118 S16 rgSCHEmtcUtlGetSfAlloc ARGS((
121 S16 rgSCHEmtcUtlPutSfAlloc ARGS((
124 Void rgSCHEmtcUtlUpdUeDciSize ARGS((
128 Void rgSCHEmtcGetDciFrmt61ASize ARGS((
131 Void rgSCHEmtcGetDciFrmt60ASize ARGS((
134 S16 rgSCHEmtcUtlFillPdschDciInfo ARGS((
135 TfuPdschDciInfo *pdsch,
138 Void rgSCHEmtcUtlRlsRnti ARGS((
140 RgSchRntiLnk *rntiLnk,
143 S16 rgSCHEmtcPdcchAlloc ARGS((
147 Void rgSCHEmtcPdcchFree ARGS((
152 /* Functions specific to TM1/TM2/TM6/TM7 for PRB calculation*/
153 Void rgSchUtlDlCalc1CwPrb ARGS(( RgSchCellCb *cell,
156 uint32_t *prbReqrd));
158 /* Functions specific to TM3/TM4 for PRB calculation*/
159 Void rgSchUtlDlCalc2CwPrb ARGS(( RgSchCellCb *cell,
162 uint32_t *prbReqrd));
165 RgSchCellCb* rgSchUtlGetCellCb ARGS(( Inst inst,
170 typedef Void (*RgSchUtlDlCalcPrbFunc) ARGS((RgSchCellCb *cell, RgSchUeCb *ue,
171 uint32_t bo, uint32_t *prbRequrd));
173 /* Functions specific to each transmission mode for PRB calculation*/
174 RgSchUtlDlCalcPrbFunc dlCalcPrbFunc[7] = {rgSchUtlDlCalc1CwPrb,
175 rgSchUtlDlCalc1CwPrb, rgSchUtlDlCalc2CwPrb, rgSchUtlDlCalc2CwPrb,
176 NULLP, rgSchUtlDlCalc1CwPrb, rgSchUtlDlCalc1CwPrb};
179 /* Functions specific to each transmission mode for PRB calculation*/
180 RgSchUtlDlCalcPrbFunc dlCalcPrbFunc[9] = {rgSchUtlDlCalc1CwPrb,
181 rgSchUtlDlCalc1CwPrb, rgSchUtlDlCalc2CwPrb, rgSchUtlDlCalc2CwPrb,
182 NULLP, rgSchUtlDlCalc1CwPrb, rgSchUtlDlCalc1CwPrb, NULLP, NULLP};
187 /* The below table will be used to map the UL SF number in a TDD Cfg 0
188 frame to the ul Sf array maintained in cellCb */
189 static uint8_t rgSchTddCfg0UlSfTbl[] = {2, 3, 4, 7, 8, 9};
192 static S16 rgSCHUtlUlAllocDbInit ARGS((
197 static Void rgSCHUtlUlAllocDbDeinit ARGS((
201 static S16 rgSCHUtlUlHoleDbInit ARGS((
208 static Void rgSCHUtlUlHoleDbDeinit ARGS((
213 static S16 rgSCHChkBoUpdate ARGS((
215 RgInfCmnBoRpt *boUpdt
219 static uint8_t rgSCHUtlFetchPcqiBitSz ARGS((
226 /* sorted in ascending order of tbSz */
227 const struct rgSchUtlBcchPcchTbSz
229 uint8_t rbIndex; /* RB index {2,3} */
230 uint16_t tbSz; /* one of the Transport block size in bits of
232 /* Corrected allocation for common channels */
233 uint8_t mcs; /* imcs */
234 } rgSchUtlBcchPcchTbSzTbl[44] = {
235 { 2, 32, 0 }, { 2, 56, 1 }, { 2, 72, 2 }, { 3, 88, 1 },
236 { 2, 104, 3 }, { 2, 120, 4 }, { 2, 144, 5 }, { 2, 176, 6 },
237 { 3, 208, 4 }, { 2, 224, 7 }, { 2, 256, 8 }, { 2, 296, 9 },
238 { 2, 328, 10 }, { 2, 376, 11 }, { 3, 392, 8 }, { 2, 440, 12 },
239 { 3, 456, 9 }, { 2, 488, 13 }, { 3, 504, 10 }, { 2, 552, 14 },
240 { 3, 584, 11 }, { 2, 600, 15 }, { 2, 632, 16 }, { 3, 680, 12 },
241 { 2, 696, 17 }, { 3, 744, 13 }, { 2, 776, 18 }, { 2, 840, 19 },
242 { 2, 904, 20 }, { 3, 968, 16 }, { 2, 1000, 21 }, { 2, 1064, 22 },
243 { 2, 1128, 23 }, { 3, 1160, 18 }, { 2, 1192, 24 }, { 2, 1256, 25 },
244 { 3, 1288, 19 }, { 3, 1384, 20 }, { 2, 1480, 26 }, { 3, 1608, 22 },
245 { 3, 1736, 23 }, { 3, 1800, 24 }, { 3, 1864, 25 }, { 3, 2216, 26 }
252 /* forward references */
254 static Void rgSCHUtlUpdPrachOcc ARGS((
256 RgrTddPrachInfo *cellCfg));
259 #define RGSCH_NUM_PCFICH_REG 4
260 #define RGSCH_NUM_REG_PER_CCE 9
261 #define RGSCH_NUM_REG_PER_PHICH_GRP 3
264 #define RGSCH_INITPHICH(_phich, _hqFeedBack, _nDmrs, _rbStart, _iPhich) {\
265 (_phich)->hqFeedBack = _hqFeedBack; \
266 (_phich)->rbStart = _rbStart; \
267 (_phich)->nDmrs = _nDmrs; \
268 (_phich)->iPhich = _iPhich; \
269 (_phich)->lnk.next = NULLP; \
270 (_phich)->lnk.prev = NULLP; \
271 (_phich)->lnk.node = (PTR)(_phich); \
274 #define RGSCH_INITPHICH(_phich, _hqFeedBack, _nDmrs, _rbStart, _isForMsg3) {\
275 (_phich)->hqFeedBack = _hqFeedBack; \
276 (_phich)->rbStart = _rbStart; \
277 (_phich)->nDmrs = _nDmrs; \
278 (_phich)->isForMsg3 = _isForMsg3; \
279 (_phich)->lnk.next = NULLP; \
280 (_phich)->lnk.prev = NULLP; \
281 (_phich)->lnk.node = (PTR)(_phich); \
285 #define RGSCH_PHICH_ALLOC(_inst,_dataPtr, _size, _ret) {\
286 _ret = rgSCHUtlAllocSBuf(_inst, (Data **)&_dataPtr, _size); \
289 /* ccpu00117052 - MOD - Passing double pointer
290 for proper NULLP assignment*/
291 #define RGSCH_PHICH_FREE(_inst, _dataPtr, _size) {\
292 rgSCHUtlFreeSBuf(_inst, (Data **)(&(_dataPtr)), _size); \
296 #define RGSCH_GETBIT(a, b) ((((uint8_t*)a)[(b)>>3] >> ((7-((b)&7)))) & 1)
302 * Desc: This function finds of the Power of x raised to n
304 * Ret: value of x raised to n
311 F64 rgSCHUtlPower(F64 x,F64 n)
319 return ( x * rgSCHUtlPower( x, n-1 ) );
323 return ( (1/x) * rgSCHUtlPower( x, n+1 ) );
325 } /* end of rgSCHUtlPower*/
331 * Desc: This function parses bits x to y of an array and
332 * returns the integer value out of it.
334 * Ret: integer value of z bits
341 uint32_t rgSCHUtlParse(uint8_t *buff,uint8_t startPos,uint8_t endPos,uint8_t buffSize)
343 uint8_t pointToChar,pointToEnd, loop;
344 uint8_t size = endPos - startPos;
346 pointToEnd = (startPos)%8;
347 for ( loop=0; loop<size; loop++)
349 pointToChar = (((startPos)+loop)/8);
350 if (RGSCH_GETBIT(buff+pointToChar,pointToEnd%8)==1)
352 result=result+(rgSCHUtlPower(2,(size-loop-1)));
356 return ((uint32_t)result);
357 } /* end of rgSCHUtlParse*/
361 * Fun: rgSCHUtlFindDist
363 * Desc: This function calculates the iterations need to cover
364 * before the valid Index can be used for next possible Reception
366 * Ret: integer value of z bits
373 uint8_t rgSCHUtlFindDist(uint16_t crntTime,uint16_t tempIdx)
376 /* ccpu00137113- Distance is not estimated properly if the periodicity is
377 * equal to RG_SCH_PCQI_SRS_SR_TRINS_SIZE.
379 while(crntTime<=tempIdx)
381 crntTime += RG_SCH_PCQI_SRS_SR_TRINS_SIZE;
385 } /* end of rgSCHUtlFindDist*/
390 * @brief This function checks availability of a PDCCH
394 * Function: rgSCHUtlPdcchAvail
395 * Purpose: This function checks if a particular PDCCH is in use.
396 * map field of PDCCH is used to track the CCEs arleady
397 * allocated. Each bit of map represents one CCE and the
398 * LSBit of first byte represents CCE 0.
400 * 1. Locate the set of bits that represent the PDCCH for
401 * the provided location.
402 * 2. If the value of the bits is non-zero one or many CCEs
403 * for the PDCCH are in use and hence the PDCCH is not available.
404 * 3. If pdcch is available, assign it to [out]pdcch.
405 * 4. Set all of the bits to one. There is no check performed
406 * to see if the PDCCH is available.
408 * Invoked by: scheduler
410 * @param[in] RgSchCellCb* cell
411 * @param[in] RgSchPdcchInfo* pdcchInfo
412 * @param[in] uint8_t loc
413 * @param[in] uint8_t aggrLvl
414 * @param[out] RgSchPdcch** pdcch
416 * -# TRUE if available
420 Bool rgSCHUtlPdcchAvail
423 RgSchPdcchInfo *pdcchInfo,
424 CmLteAggrLvl aggrLvl,
432 Inst inst = cell->instIdx;
434 uint16_t offsetStepMask;
438 byte = &pdcchInfo->map[0];
439 initMask = (0xffff >> (16 - aggrLvl));
441 /* if N(symbol, xPDCCH) =2, then xPDCCH will be candidates in
442 * search space of index {0,1,2,3} and {8,9,..14}
444 if ((cell->cell5gtfCb.cfi == 2) && (aggrLvl == CM_LTE_AGGR_LVL2))
446 offsetStepMask = 0xc;
450 offsetStepMask = 0xc0;
453 /* Loop till the number of bytes available in the CCE map */
454 while (offset < ((pdcchInfo->nCce+ 7) >> 3))
456 byte = &pdcchInfo->map[offset];
457 /* Checking for available CCE */
458 if ((*byte & currMask) == 0)
462 /* if the number of CCEs required are not available, move to next offset */
463 if (currMask & offsetStepMask)
470 /* Move to the next available CCE index in the current byte(cce map) */
471 currMask = currMask << aggrLvl;
475 if ((offset >= ((pdcchInfo->nCce + 7) >> 3)) ||
476 ((aggrLvl == CM_LTE_AGGR_LVL16) && (offset > 0)))
481 byte = &pdcchInfo->map[offset];
483 if (cell->pdcchLst.first != NULLP)
485 *pdcch = (RgSchPdcch *)(cell->pdcchLst.first->node);
486 cmLListDelFrm(&cell->pdcchLst, cell->pdcchLst.first);
490 ret = rgSCHUtlAllocSBuf(inst, (Data **)pdcch, sizeof(RgSchPdcch));
500 /* ALL CCEs will be used in case of level 16 */
501 if (aggrLvl == CM_LTE_AGGR_LVL16)
503 *(byte+1) |= currMask;
505 (*pdcch)->aggrLvl = aggrLvl;
506 cmLListAdd2Tail(&pdcchInfo->pdcchs, &((*pdcch)->lnk));
507 (*pdcch)->lnk.node = (PTR)*pdcch;
508 (*pdcch)->nCce = aggrLvl;
509 (*pdcch)->ue = NULLP;
517 * @brief This function releases a PDCCH
521 * Function: rgSCHUtlPdcchPut
522 * Purpose: This function releases a PDCCH.
524 * 1. Locate the set of bits that represent the PDCCH for
525 * the provided location.
526 * 2. Set all of the bits to zero.
527 * 3. Release the memory of PDCCH to the cell free Q
529 * Invoked by: scheduler
531 * @param[in] RgSchPdcchInfo* pdcchInfo
532 * @param[in] uint8_t loc
533 * @param[in] uint8_t aggrLvl
537 Void rgSCHUtlPdcchPut(RgSchCellCb *cell,RgSchPdcchInfo *pdcchInfo,RgSchPdcch *pdcch)
543 switch(pdcch->aggrLvl)
545 case CM_LTE_AGGR_LVL2:
546 offset = (pdcch->nCce >> 1) & 3;
547 mask = 0x3 << (offset * 2); /*ccpu00128826 - Offset Correction */
549 case CM_LTE_AGGR_LVL4:
550 offset = (pdcch->nCce >> 2) & 1;
551 mask = 0xf << (offset * 4);/*ccpu00128826 - Offset Correction */
553 case CM_LTE_AGGR_LVL8:
556 case CM_LTE_AGGR_LVL16:
562 /* Placing common computation of byte from all the cases above here
564 byte = &pdcchInfo->map[pdcch->nCce >> 3];
566 cmLListDelFrm(&pdcchInfo->pdcchs, &pdcch->lnk);
567 cmLListAdd2Tail(&cell->pdcchLst, &pdcch->lnk);
568 pdcch->lnk.node = (PTR)pdcch;
577 * @brief This function initializes PDCCH information for frame
581 * Function: rgSCHUtlPdcchInit
582 * Purpose: This function initializes PDCCH information for
583 * a slot. It removes the list of PDCCHs allocated
584 * in the prior use of this slot structure.
586 * Invoked by: rgSCHUtlSubFrmPut
588 * @param[in] RgSchCellCb* cell
589 * @param[in] RgSubFrm* subFrm
593 Void rgSCHUtlPdcchInit(RgSchCellCb *cell,RgSchDlSf *subFrm,uint16_t nCce)
595 RgSchPdcchInfo *pdcchInfo;
597 Inst inst = cell->instIdx;
601 pdcchInfo = &subFrm->pdcchInfo;
602 while(pdcchInfo->pdcchs.first != NULLP)
604 pdcch = (RgSchPdcch *)pdcchInfo->pdcchs.first->node;
605 cmLListDelFrm(&pdcchInfo->pdcchs, pdcchInfo->pdcchs.first);
606 cmLListAdd2Tail(&cell->pdcchLst, &pdcch->lnk);
609 cmLListInit(&pdcchInfo->pdcchs);
612 subFrm->relPdcch = NULLP;
615 cceMapSz = ((pdcchInfo->nCce + 7) >> 3);
617 /* The bitMap array size is the number of ceiling(CCEs/8) */
618 /* If nCce received is not the same as the one stored in
619 * pdcchInfo, free the pdcchInfo map */
621 if(pdcchInfo->nCce != nCce)
625 rgSCHUtlFreeSBuf(inst, (Data **)(&(pdcchInfo->map)), cceMapSz);
627 pdcchInfo->nCce = nCce;
628 cceMapSz = ((pdcchInfo->nCce + 7) >> 3);
629 rgSCHUtlAllocSBuf(inst, (Data **)&pdcchInfo->map,
631 if (pdcchInfo->map == NULLP)
633 /* Generate log error here */
638 memset(subFrm->pdcchInfo.map, 0, cceMapSz);
639 /* If nCce is not exactly same as the bitMap size(no of bits allocated
640 * to represent the Cce's, then mark the extra bits as unavailable
641 extra bits = (((pdcchInfo->nCce + 7) >> 3)*8) - pdcchInfo->nCce
642 The last byte of bit map = subFrm->pdcchInfo.map[((pdcchInfo->nCce + 7) >> 3) - 1]
643 NOTE : extra bits are most significant of the last byte eg. */
644 extraBits = (cceMapSz)*8 - pdcchInfo->nCce;
645 subFrm->pdcchInfo.map[cceMapSz - 1] |=
646 ((1 << extraBits) - 1) << (8 - extraBits);
650 /* LTE_ADV_FLAG_REMOVED_START */
652 * @brief This function frees Pool
655 * Function: rgSchSFRTotalPoolFree
657 * Invoked by: rgSchSFRTotalPoolInit
659 * @param[in] RgSchCellCb* cell
660 * @param[in] RgSubFrm* subFrm
664 Void rgSchSFRTotalPoolFree(RgSchSFRTotalPoolInfo *sfrTotalPoolInfo,RgSchCellCb *cell)
669 /*Deinitialise if these cc pools and ce pools are already existent*/
670 l = &sfrTotalPoolInfo->ccPool;
674 /*REMOVING Cell Centred POOLS IF ANY*/
675 n = cmLListDelFrm(l, n);
677 /* Deallocate buffer */
678 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(n->node)), sizeof(RgSchSFRPoolInfo));
680 /* Deallocate buffer */
681 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(n)), sizeof(CmLList));
685 /*REMOVING Cell Edged POOLS IF ANY*/
686 l = &sfrTotalPoolInfo->cePool;
690 n = cmLListDelFrm(l, n);
692 /* Deallocate buffer */
693 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(n->node)), sizeof(RgSchSFRPoolInfo));
695 /* Deallocate buffer */
696 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(n)), sizeof(CmLList));
703 * @brief This function resets temporary variables in Pool
706 * Function: rgSchSFRResetPoolVariables
708 * Invoked by: rgSCHSFRUtlTotalPoolInit
710 * @param[in] RgSchCellCb* cell
711 * @param[in] RgSubFrm* subFrm
715 S16 rgSchSFRTotalPoolInit(RgSchCellCb *cell,RgSchDlSf *sf)
717 /* Initialise the variables */
718 RgSchSFRPoolInfo *sfrCCPool;
719 RgSchSFRPoolInfo *sfrCEPool;
722 CmLList *temp = NULLP;
725 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo, cell);
726 sf->sfrTotalPoolInfo.CCPool1BwAvlbl = 0;
727 sf->sfrTotalPoolInfo.CCPool2BwAvlbl = 0;
728 sf->sfrTotalPoolInfo.CEPoolBwAvlbl = 0;
729 sf->sfrTotalPoolInfo.CC1 = FALSE;
730 sf->sfrTotalPoolInfo.CC2 = FALSE;
731 /*Initialise the CE Pools*/
732 cmLListInit (&(sf->sfrTotalPoolInfo.cePool));
734 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp, sizeof(CmLList));
737 DU_LOG("\nERROR --> SCH : CE Pool memory allocation FAILED for cell");
738 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo, cell);
742 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp->node, sizeof(RgSchSFRPoolInfo));
745 DU_LOG("\nERROR --> SCH : CE Pool memory allocation FAILED for cell ");
746 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
750 l = &sf->sfrTotalPoolInfo.cePool;
751 cmLListAdd2Tail(l, temp);
753 /*Initialise Bandwidth and startRB and endRB for each pool*/
756 /* Initialise the CE Pools */
757 sfrCEPool = (RgSchSFRPoolInfo*)n->node;
759 sfrCEPool->poolstartRB = cell->lteAdvCb.sfrCfg.cellEdgeRbRange.startRb;
760 sfrCEPool->poolendRB = cell->lteAdvCb.sfrCfg.cellEdgeRbRange.endRb;
761 sfrCEPool->bw = sfrCEPool->poolendRB - sfrCEPool->poolstartRB + 1;
762 sf->sfrTotalPoolInfo.CEPoolBwAvlbl = sfrCEPool->bw;
764 sfrCEPool->bwAlloced = 0;
765 sfrCEPool->type2Start = sfrCEPool->poolstartRB;
766 sfrCEPool->type2End = RGSCH_CEIL(sfrCEPool->poolstartRB, cell->rbgSize);
767 sfrCEPool->type0End = ((sfrCEPool->poolendRB + 1) / cell->rbgSize) - 1;
768 sfrCEPool->pwrHiCCRange.startRb = 0;
769 sfrCEPool->pwrHiCCRange.endRb = 0;
771 /*Initialise CC Pool*/
772 cmLListInit (&(sf->sfrTotalPoolInfo.ccPool));
774 /*Add memory and Update CCPool*/
775 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp, sizeof(CmLList));
778 DU_LOG("\nERROR --> SCH : CC Pool memory allocation FAILED for cell ");
779 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
783 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp->node, sizeof(RgSchSFRPoolInfo));
786 DU_LOG("\nERROR --> SCH : CC Pool memory allocation FAILED for cell ");
787 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
791 l = &sf->sfrTotalPoolInfo.ccPool;
792 cmLListAdd2Tail(l, temp);
794 /*Initialise Bandwidth and startRB and endRB for each pool*/
795 if(sfrCEPool->poolstartRB)
798 sfrCCPool = (RgSchSFRPoolInfo*)n->node;
800 sfrCCPool->poolstartRB = 0;
801 sfrCCPool->poolendRB = sfrCEPool->poolstartRB - 1;
802 sfrCCPool->bw = sfrCCPool->poolendRB - sfrCCPool->poolstartRB + 1;
803 sf->sfrTotalPoolInfo.CCPool1BwAvlbl = sfrCCPool->bw;
804 sfrCCPool->bwAlloced = 0;
805 sfrCCPool->type2Start = 0;
806 sfrCCPool->type2End = 0;
807 sfrCCPool->type0End = ((sfrCCPool->poolendRB + 1) / cell->rbgSize) - 1;
808 sf->sfrTotalPoolInfo.CC1 = TRUE;
809 sfrCCPool->pwrHiCCRange.startRb = 0;
810 sfrCCPool->pwrHiCCRange.endRb = 0;
815 sfrCCPool = (RgSchSFRPoolInfo*)n->node;
817 sfrCCPool->poolstartRB = sfrCEPool->poolendRB + 1;
818 sfrCCPool->poolendRB = sf->bw - 1;
819 sfrCCPool->bw = sfrCCPool->poolendRB - sfrCCPool->poolstartRB + 1;
820 sf->sfrTotalPoolInfo.CCPool2BwAvlbl = sfrCCPool->bw;
821 sfrCCPool->CCPool2Exists = TRUE;
822 sfrCCPool->bwAlloced = 0;
823 sfrCCPool->type2Start = sfrCCPool->poolstartRB;
824 sfrCCPool->type2End = RGSCH_CEIL(sfrCCPool->poolstartRB, cell->rbgSize);
825 sfrCCPool->type0End = ((sfrCCPool->poolendRB + 1) / cell->rbgSize) - 1;
826 sf->sfrTotalPoolInfo.CC2 = TRUE;
827 sfrCEPool->adjCCPool = sfrCCPool; /* SFR_FIX */
828 sfrCCPool->pwrHiCCRange.startRb = 0;
829 sfrCCPool->pwrHiCCRange.endRb = 0;
832 if((sfrCEPool->poolendRB != sf->bw - 1) && (!sfrCCPool->poolstartRB))
834 /*Add memory and Update CCPool*/
835 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp, sizeof(CmLList));
838 DU_LOG("\nERROR --> SCH : CC Pool memory allocation FAILED for cell ");
839 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
843 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&temp->node, sizeof(RgSchSFRPoolInfo));
846 DU_LOG("\nERROR --> SCH : CC Pool memory allocation FAILED for cell ");
847 rgSchSFRTotalPoolFree(&sf->sfrTotalPoolInfo,cell);
851 cmLListAdd2Tail(l, temp);
854 sfrCCPool = (RgSchSFRPoolInfo*)n->node;
856 sfrCCPool->poolstartRB = sfrCEPool->poolendRB + 1;
857 sfrCCPool->poolendRB = sf->bw - 1;
858 sfrCCPool->bw = sfrCCPool->poolendRB - sfrCCPool->poolstartRB + 1;
859 sf->sfrTotalPoolInfo.CCPool2BwAvlbl = sfrCCPool->bw;
860 sfrCCPool->CCPool2Exists = TRUE;
861 sfrCCPool->bwAlloced = 0;
862 sfrCCPool->type2Start = sfrCCPool->poolstartRB;
863 sfrCCPool->type2End = RGSCH_CEIL(sfrCCPool->poolstartRB, cell->rbgSize);
864 sfrCCPool->type0End = ((sfrCCPool->poolendRB + 1) / cell->rbgSize) - 1;
865 sf->sfrTotalPoolInfo.CC2 = TRUE;
866 sfrCEPool->adjCCPool = sfrCCPool; /* SFR_FIX */
867 sfrCCPool->pwrHiCCRange.startRb = 0;
868 sfrCCPool->pwrHiCCRange.endRb = 0;
871 sf->sfrTotalPoolInfo.CCRetx = FALSE;
872 sf->sfrTotalPoolInfo.CERetx = FALSE;
874 sf->sfrTotalPoolInfo.ccBwFull = FALSE;
875 sf->sfrTotalPoolInfo.ceBwFull = FALSE;
876 sf->sfrTotalPoolInfo.isUeCellEdge = FALSE;
880 * @brief This function resets temporary variables in RNTP Prepration
883 * Function: rgSchDSFRRntpInfoInit
885 * Invoked by: rgSCHSFRUtlTotalPoolInit
887 * @param[in] TknStrOSXL* rntpPtr
888 * @param[in] RgSubFrm* subFrm
892 S16 rgSchDSFRRntpInfoInit(TknStrOSXL *rntpPtr,RgSchCellCb *cell,uint16_t bw)
894 Inst inst = cell->instIdx;
897 rntpPtr->pres = PRSNT_NODEF;
899 len = (bw % 8 == 0) ? (bw/8) : (bw/8 + 1);
903 /* Allocate memory for "scheduled UE" Info */
904 if((rgSCHUtlAllocSBuf(inst, (Data**)&(rntpPtr->val),
905 (len * sizeof(uint8_t)))) != ROK)
907 DU_LOG("\nERROR --> SCH : Memory allocation FAILED for RNTP Alloc");
915 * @brief This function release RNTP pattern from slot and Cell
918 * Function: rgSchDSFRRntpInfoFree
920 * Invoked by: rgSCHSFRUtlTotalPoolInit
922 * @param[in] TknStrOSXL* rntpPtr
923 * @param[in] RgSubFrm* subFrm
927 S16 rgSchDSFRRntpInfoFree(TknStrOSXL *rntpPtr,RgSchCellCb *cell,uint16_t bw)
929 Inst inst = cell->instIdx;
932 len = (bw % 8 == 0) ? (bw/8) : (bw/8 + 1);
934 if(rntpPtr->pres == PRSNT_NODEF)
936 rgSCHUtlFreeSBuf(inst, (Data **)(&(rntpPtr->val)),(len * sizeof(uint8_t)));
937 rntpPtr->pres = NOTPRSNT;
945 * @brief This function resets temporary variables in Pool
948 * Function: rgSchSFRResetPoolVariables
949 * Purpose: Initialise the dynamic variables in each pool.
950 * Reset bwAlloced, bwAssigned, type2End, type0End, type2Start
951 * Invoked by: rgSCHSFRUtlTotalPoolReset
953 * @param[in] RgSchCellCb* cell
954 * @param[in] RgSchSFRPoolInfo *pool
958 static Void rgSchSFRResetPoolVariables(RgSchCellCb *cell,RgSchSFRPoolInfo *pool)
963 /*type0end will be the last RBG in pool with all available RBs*/
964 pool->type0End = (((pool->poolendRB + 1)/cell->rbgSize) - 1);
966 /*type2end will be the first RBG in pool with all available RBs*/
967 pool->type2End = RGSCH_CEIL(pool->poolstartRB, cell->rbgSize);
968 pool->type2Start = pool->poolstartRB;
969 pool->bw = pool->poolendRB - pool->poolstartRB + 1;
974 * @brief This function resets SFR Pool information for frame
978 * Function: rgSCHSFRUtlTotalPooReset
979 * Purpose: Update the dynamic variables in each pool as they will be modified in each slot.
980 * Dont modify the static variables like startRB, endRB, BW
981 * Invoked by: rgSCHUtlSubFrmPut
983 * @param[in] RgSchCellCb* cell
984 * @param[in] RgSchDlSf* subFrm
988 static Void rgSCHSFRUtlTotalPoolReset(RgSchCellCb *cell,RgSchDlSf *subFrm)
990 RgSchSFRTotalPoolInfo *totalPoolInfo = &subFrm->sfrTotalPoolInfo;
991 CmLListCp *ccPool = &totalPoolInfo->ccPool;
992 CmLListCp *cePool = &totalPoolInfo->cePool;
993 CmLList *node = NULLP;
994 RgSchSFRPoolInfo *tempPool = NULLP;
996 totalPoolInfo->ccBwFull = FALSE;
997 totalPoolInfo->ceBwFull = FALSE;
998 totalPoolInfo->isUeCellEdge = FALSE;
999 totalPoolInfo->CCPool1BwAvlbl = 0;
1000 totalPoolInfo->CCPool2BwAvlbl = 0;
1001 totalPoolInfo->CEPoolBwAvlbl = 0;
1002 totalPoolInfo->CCRetx = FALSE;
1003 totalPoolInfo->CERetx = FALSE;
1005 node = ccPool->first;
1008 tempPool = (RgSchSFRPoolInfo *)(node->node);
1010 rgSchSFRResetPoolVariables(cell, tempPool);
1011 if(tempPool->poolstartRB == 0)
1012 totalPoolInfo->CCPool1BwAvlbl = tempPool->bw;
1014 totalPoolInfo->CCPool2BwAvlbl = tempPool->bw;
1017 node = cePool->first;
1020 tempPool = (RgSchSFRPoolInfo *)(node->node);
1022 rgSchSFRResetPoolVariables(cell, tempPool);
1023 totalPoolInfo->CEPoolBwAvlbl = tempPool->bw;
1028 /* LTE_ADV_FLAG_REMOVED_END */
1030 * @brief This function appends PHICH information for frame
1034 * Function: rgSCHUtlAddPhich
1035 * Purpose: This function appends PHICH information for
1040 * @param[in] RgSchCellCb* cell
1041 * @param[in] RgSubFrm* subFrm
1042 * @param[in] uint8_t hqFeedBack
1043 * @param[in] uint8_t nDmrs
1044 * @param[in] uint8_t rbStart
1050 S16 rgSCHUtlAddPhich
1053 CmLteTimingInfo frm,
1060 S16 rgSCHUtlAddPhich
1063 CmLteTimingInfo frm,
1074 Inst inst = cell->instIdx;
1076 dlSf = rgSCHUtlSubFrmGet(cell, frm);
1077 RGSCH_PHICH_ALLOC(inst, phich,sizeof(RgSchPhich), ret);
1081 DU_LOG("\nERROR --> SCH : rgSCHUtlAddPhich(): "
1082 "Allocation of RgSchPhich failed");
1086 RGSCH_INITPHICH(phich, hqFeedBack, nDmrs, rbStart, iPhich);
1088 RGSCH_INITPHICH(phich, hqFeedBack, nDmrs, rbStart, isForMsg3); /*SR_RACH_STATS */
1090 cmLListAdd2Tail(&dlSf->phichInfo.phichs, &phich->lnk);
1092 } /* rgSCHUtlAddPhich */
1095 * @brief This function resets PHICH information for frame
1099 * Function: rgSCHUtlPhichReset
1100 * Purpose: This function initializes PHICH information for
1101 * a slot. It removes the list of PHICHs allocated
1102 * in the prior use of this slot structure.
1104 * Invoked by: rgSCHUtlSubFrmPut
1106 * @param[in] RgSchCellCb* cell
1107 * @param[in] RgSubFrm* subFrm
1111 static Void rgSCHUtlPhichReset(RgSchCellCb *cell,RgSchDlSf *subFrm)
1113 RgSchPhichInfo *phichInfo;
1118 phichInfo = &subFrm->phichInfo;
1119 while(phichInfo->phichs.first != NULLP)
1121 phich = (RgSchPhich *)phichInfo->phichs.first->node;
1122 cmLListDelFrm(&phichInfo->phichs, phichInfo->phichs.first);
1123 RGSCH_PHICH_FREE(cell->instIdx, phich, sizeof(RgSchPhich));
1125 cmLListInit(&phichInfo->phichs);
1127 } /* rgSCHUtlPhichReset */
1131 * @brief This function returns slot data structure for a cell
1135 * Function: rgSCHUtlSubFrmGet
1136 * Purpose: This function resets the slot data structure
1137 * when the slot is released
1139 * Invoked by: scheduler
1141 * @param[in] RgSubFrm subFrm
1145 RgSchDlSf* rgSCHUtlSubFrmGet(RgSchCellCb *cell,CmLteTimingInfo frm)
1151 dlIdx = rgSCHUtlGetDlSfIdx(cell, &frm);
1152 //RGSCH_ARRAY_BOUND_CHECK(cell->instIdx, cell->subFrms, dlIdx);
1153 sf = cell->subFrms[dlIdx];
1155 /* Changing the idexing
1156 so that proper slot is selected */
1157 dlIdx = (((frm.sfn & 1) * RGSCH_NUM_SUB_FRAMES) + (frm.slot % RGSCH_NUM_SUB_FRAMES));
1158 RGSCH_ARRAY_BOUND_CHECK(cell->instIdx, cell->subFrms, dlIdx);
1159 sf = cell->subFrms[dlIdx];
1169 * @brief This function returns slot data structure for a cell
1173 * Function: rgSCHUtlSubFrmPut
1174 * Purpose: This function resets the slot data structure
1175 * when the slot is released
1177 * Invoked by: scheduler
1179 * @param[in] RgSubFrm subFrm
1183 Void rgSCHUtlSubFrmPut(RgSchCellCb *cell,RgSchDlSf *sf)
1189 /* Release all the held PDCCH information */
1190 rgSCHUtlPdcchInit(cell, sf, sf->nCce);
1192 /* Release all the held PDCCH information */
1193 rgSCHUtlPdcchInit(cell, sf, cell->nCce);
1195 rgSCHUtlPhichReset(cell, sf);
1197 /* Reset the bw allocated. */
1200 /* Setting allocated bandwidth to SPS bandwidth for non-SPS RB allocator */
1201 sf->bwAlloced = ((cell->spsCellCfg.maxSpsDlBw +
1202 cell->rbgSize - 1)/cell->rbgSize) * cell->rbgSize;
1203 if (sf->bwAlloced > sf->bw)
1205 sf->bwAlloced = sf->bw;
1207 sf->spsAllocdBw = 0;
1208 sf->type2Start = sf->bwAlloced;
1209 memset( &sf->dlSfAllocInfo, 0, sizeof(RgSchDlSfAllocInfo));
1212 /* Fix for ccpu00123918*/
1214 /* LTE_ADV_FLAG_REMOVED_START */
1215 /* dsfr_pal_fixes ** 21-March-2013 ** SKS */
1216 if (cell->lteAdvCb.dsfrCfg.status == RGR_ENABLE)
1218 memset(sf->rntpInfo.val, 0, sf->rntpInfo.len);
1220 /* LTE_ADV_FLAG_REMOVED_END */
1223 /*[ccpu00138609]-ADD-Reset the CCCH UE counter */
1226 /* Non DLFS scheduling using Type0 RA requires the following
1227 * parameter's tracking */
1228 /* Type 2 localized allocations start from 0th RBG and onwards */
1229 /* Type 0 allocations start from last RBG and backwards*/
1233 sf->type2End = RGSCH_CEIL(sf->bwAlloced,cell->rbgSize);
1235 sf->type0End = cell->noOfRbgs - 1;
1236 /* If last RBG is of incomplete size then special handling */
1237 (sf->bw % cell->rbgSize == 0)? (sf->lstRbgDfct = 0) :
1238 (sf->lstRbgDfct = cell->rbgSize - (sf->bw % cell->rbgSize));
1239 /* This resets the allocation for BCCH and PDCCH */
1241 /* TODO we need to move this reset for emtc functions */
1242 if(!(cell->emtcEnable))
1251 sf->bcch.pdcch = NULLP;
1252 sf->pcch.pdcch = NULLP;
1254 noRaRsps = RGSCH_MAX_TDD_RA_RSP_ALLOC;
1256 noRaRsps = RGSCH_MAX_RA_RSP_ALLOC;
1258 for (i = 0; i < noRaRsps; i++)
1260 sf->raRsp[i].pdcch = NULLP;
1261 cmLListInit(&(sf->raRsp[i].raRspLst));
1263 /* LTE_ADV_FLAG_REMOVED_START */
1264 if (cell->lteAdvCb.sfrCfg.status == RGR_ENABLE)
1266 rgSCHSFRUtlTotalPoolReset(cell, sf);
1268 /* LTE_ADV_FLAG_REMOVED_END */
1270 cmLListInit(&sf->n1PucchResLst);
1274 sf->isCceFailure = FALSE;
1275 sf->dlUlBothCmplt = 0;
1281 * @brief This function computes log N (32 bit Unsigned) to the base 2
1285 * Function: rgSCHUtlLog32bitNbase2
1286 * Purpose: This function computes log N (32 bit Unsigned) to the base 2.
1287 * For n= 0,1 ret = 0.
1289 * Invoked by: Scheduler
1291 * @param[in] uint32_t n
1295 uint8_t rgSCHUtlLog32bitNbase2(uint32_t n)
1297 uint32_t b[] = {0x2, 0xc, 0xf0, 0xff00, 0xffff0000};
1298 uint32_t s[] = {1, 2, 4, 8, 16};
1302 for (i=4; i >= 0; i--)
1316 * @brief This function is a wrapper to call scheduler specific API.
1320 * Function: rgSCHUtlDlRelPdcchFbk
1321 * Purpose: Calls scheduler's handler for SPS release PDCCH feedback
1326 * @param[in] RgSchCellCb *cell
1327 * @param[in] RgSchUeCb *ue
1328 * @param[in] uint8_t isAck
1332 Void rgSCHUtlDlRelPdcchFbk(RgSchCellCb *cell,RgSchUeCb *ue,uint8_t isAck)
1334 cell->sc.apis->rgSCHDlRelPdcchFbk(cell, ue, isAck);
1341 * @brief This function is a wrapper to call scheduler specific API.
1345 * Function: rgSCHUtlDlProcAck
1346 * Purpose: Calls scheduler's handler to process Ack
1351 * @param[in] RgSchCellCb *cell
1352 * @param[in] RgSchDlHqProcCb *hqP
1356 Void rgSCHUtlDlProcAck(RgSchCellCb *cell,RgSchDlHqProcCb *hqP)
1358 cell->sc.apis->rgSCHDlProcAck(cell, hqP);
1363 * @brief CRNTI CE Handler
1367 * Function : rgSCHUtlHdlCrntiCE
1369 * - Call scheduler common API
1372 * @param[in] RgSchCellCb *cell
1373 * @param[in] RgSchUeCb *ue
1374 * @param[out] RgSchErrInfo *err
1377 Void rgSCHUtlHdlCrntiCE(RgSchCellCb *cell,RgSchUeCb *ue)
1380 cell->sc.apis->rgSCHHdlCrntiCE(cell, ue);
1382 } /* rgSCHUtlHdlCrntiCE */
1383 #endif /* LTEMAC_SPS */
1385 /***********************************************************
1387 * Func : rgSCHUtlCalcTotalRegs
1389 * Desc : Calculate total REGs, given a bandwidth, CFI
1390 * and number of antennas.
1392 * Ret : Total REGs (uint16_t)
1394 * Notes: Could optimise if bw values are limited
1395 * (taken from RRC spec) by indexing values from
1397 * Input values are not validated. CFI is assumed
1402 **********************************************************/
1403 static uint16_t rgSCHUtlCalcTotalRegs(uint8_t bw,uint8_t cfi,uint8_t numAntna,Bool isEcp)
1407 /*ccpu00116757- removed check for (ERRCLASS & ERRCLS_DEBUG)*/
1413 /* Refer 36.211 section 6.10.1.2
1414 * For symbols 2 and 4, the REGs per RB will be based on cyclic prefix
1415 * and number of antenna ports.
1416 * For symbol 1, there are 2 REGs per RB always. Similarly symbol 3
1420 /*CR changes [ccpu00124416] - MOD*/
1423 regs = bw * RGSCH_NUM_REGS_4TH_SYM_EXT_CP;
1427 regs = bw * RGSCH_NUM_REGS_4TH_SYM_NOR_CP;
1430 regs += bw * RGSCH_NUM_REGS_3RD_SYM;
1432 /*CR changes [ccpu00124416] - MOD using number of antenna ports*/
1433 regs += (numAntna == RGSCH_NUM_ANT_PORT_FOUR) ? \
1434 (bw * RGSCH_NUM_REGS_2ND_SYM_FOUR_ANT_PORT) : \
1435 (bw * RGSCH_NUM_REGS_2ND_SYM_1OR2_ANT_PORT);
1436 default: /* case 1 */
1437 regs += bw * RGSCH_NUM_REGS_1ST_SYM;
1442 /***********************************************************
1444 * Func : rgSCHUtlCalcPhichRegs
1446 * Desc : Calculates number of PHICH REGs
1448 * Ret : Number of PHICH REGs (uint8_t)
1450 * Notes: ng6 is Ng multiplied by 6
1454 **********************************************************/
1455 static uint16_t rgSCHUtlCalcPhichRegs(uint8_t bw,uint8_t ng6)
1457 /* ccpu00115330: Corrected the calculation for number of PHICH groups*/
1458 return (RGSCH_CEIL((bw * ng6) ,(8 * 6)) * RGSCH_NUM_REG_PER_PHICH_GRP);
1463 * @brief Calculates total CCEs (N_cce)
1467 * Function: rgSCHUtlCalcNCce
1468 * Purpose: This function calculates and returns total CCEs for a
1469 * cell, given the following: bandwidth, Ng configuration
1470 * (multiplied by six), cfi (actual number of control
1471 * symbols), m factor for PHICH and number of antennas.
1473 * Invoked by: Scheduler
1475 * @param[in] uint8_t bw
1476 * @param[in] uint8_t ng6
1477 * @param[in] uint8_t cfi
1478 * @param[in] uint8_t mPhich
1479 * @param[in] uint8_t numAntna
1480 * @param[in] Bool isEcp
1481 * @return N_cce (uint8_t)
1484 uint8_t rgSCHUtlCalcNCce(uint8_t bw,RgrPhichNg ng,uint8_t cfi,uint8_t mPhich,uint8_t numAntna,Bool isEcp)
1491 /*ccpu00116757- removed check for (ERRCLASS & ERRCLS_DEBUG)*/
1495 case RGR_NG_ONESIXTH:
1510 totalRegs = rgSCHUtlCalcTotalRegs(bw, cfi, numAntna, isEcp);
1511 phichRegs = rgSCHUtlCalcPhichRegs(bw, ng6);
1512 cceRegs = totalRegs - mPhich*phichRegs - RGSCH_NUM_PCFICH_REG;
1514 return ((uint8_t)(cceRegs/RGSCH_NUM_REG_PER_CCE));
1519 * @brief Calculates total CCEs (N_cce)
1523 * Function: rgSCHUtlCalcNCce
1524 * Purpose: This function calculates and returns total CCEs for a
1525 * cell, given the following: bandwidth, Ng configuration
1526 * (multiplied by six), cfi (actual number of control
1527 * symbols) and number of antennas.
1529 * Invoked by: Scheduler
1531 * @param[in] uint8_t bw
1532 * @param[in] uint8_t ng6
1533 * @param[in] uint8_t cfi
1534 * @param[in] uint8_t numAntna
1535 * @return N_cce (uint8_t)
1538 uint8_t rgSCHUtlCalcNCce(uint8_t bw,RgrPhichNg ng,uint8_t cfi,uint8_t numAntna,Bool isEcp)
1545 /*ccpu00116757- removed check for (ERRCLASS & ERRCLS_DEBUG)*/
1549 case RGR_NG_ONESIXTH:
1564 totalRegs = rgSCHUtlCalcTotalRegs(bw, cfi, numAntna, isEcp);
1565 phichRegs = rgSCHUtlCalcPhichRegs(bw, ng6);
1566 cceRegs = totalRegs - phichRegs - RGSCH_NUM_PCFICH_REG;
1568 return ((uint8_t)(cceRegs/RGSCH_NUM_REG_PER_CCE));
1573 * @brief Returns PHICH info associated with an uplink
1574 * HARQ process allocation
1578 * Function: rgSCHUtlGetPhichInfo
1579 * Purpose: This function returns PHICH info associated with
1580 * an uplink HARQ process allocation. PHICH info
1581 * comprises RB start and N_dmrs.
1583 * @param[in] RgSchUlHqProcCb *hqProc
1584 * @param[out] uint8_t *rbStartRef
1585 * @param[out] uint8_t *nDmrsRef
1589 S16 rgSCHUtlGetPhichInfo(RgSchUlHqProcCb *hqProc,uint8_t *rbStartRef,uint8_t *nDmrsRef,uint8_t *iPhich)
1591 S16 rgSCHUtlGetPhichInfo(RgSchUlHqProcCb *hqProc,uint8_t *rbStartRef,uint8_t *nDmrsRef)
1597 if ((hqProc != NULLP) && (hqProc->alloc != NULLP))
1599 *rbStartRef = hqProc->alloc->grnt.rbStart;
1600 *nDmrsRef = hqProc->alloc->grnt.nDmrs;
1602 *iPhich = hqProc->iPhich;
1610 * @brief Returns uplink grant information required to permit
1611 * PHY to receive data
1615 * Function: rgSCHUtlAllocRcptInfo
1616 * Purpose: Given an uplink allocation, this function returns
1617 * uplink grant information which is needed by PHY to
1618 * decode data sent from UE. This information includes:
1623 * @param[in] RgSchUlAlloc *alloc
1624 * @param[out] uint8_t *rbStartRef
1625 * @param[out] uint8_t *numRbRef
1626 * @param[out] uint8_t *rvRef
1627 * @param[out] uint16_t *size
1628 * @param[out] TfuModScheme *modType
1629 * @param[out] Bool *isRtx
1630 * @param[out] uint8_t *nDmrs
1631 * @param[out] Bool *ndi
1632 * @param[out] uint8_t *hqPId
1635 S16 rgSCHUtlAllocRcptInfo
1637 RgSchUlAlloc *alloc,
1640 uint8_t *rbStartRef,
1644 TfuModScheme *modType,
1651 /* Modulation order for 16qam UEs would be
1652 * min(4,modulation order in grant). Please refer to 36.213-8.6.1*/
1653 CmLteUeCategory ueCtgy;
1655 #if (ERRCLASS & ERRCLS_DEBUG)
1656 if ((alloc == NULLP) || (alloc->hqProc == NULLP))
1662 if ( !alloc->forMsg3 )
1664 if ( ((alloc->ue) == NULLP) || (RG_SCH_CMN_GET_UE(alloc->ue, alloc->ue->cell) == NULLP))
1666 DU_LOG("\nERROR --> SCH : Failed: ue->sch is null RNTI:%d,isRetx=%d",
1667 alloc->rnti, alloc->grnt.isRtx);
1670 ueCtgy = (RG_SCH_CMN_GET_UE_CTGY(alloc->ue));
1673 *iMcsRef = alloc->grnt.iMcs;
1674 *rbStartRef = alloc->grnt.rbStart;
1675 *numRbRef = alloc->grnt.numRb;
1676 *rvRef = rgRvTable[alloc->hqProc->rvIdx];
1677 *rnti = alloc->rnti;
1678 *size = alloc->grnt.datSz;
1679 *modType = (alloc->forMsg3)? alloc->grnt.modOdr:
1680 ((ueCtgy == CM_LTE_UE_CAT_5)?
1682 (RGSCH_MIN(RGSCH_QM_QPSK,alloc->grnt.modOdr)));
1683 *isRtx = alloc->grnt.isRtx;
1684 *nDmrs = alloc->grnt.nDmrs;
1685 *ndi = alloc->hqProc->ndi;
1686 *hqPId = alloc->hqProc->procId;
1692 * @brief Returns uplink grant information required to permit
1693 * PHY to receive data
1697 * Function: rgSCHUtlAllocRcptInfo
1698 * Purpose: Given an uplink allocation, this function returns
1699 * uplink grant information which is needed by PHY to
1700 * decode data sent from UE. This information includes:
1705 * @param[in] RgSchUlAlloc *alloc
1706 * @param[out] uint8_t *rbStartRef
1707 * @param[out] uint8_t *numRbRef
1708 * @param[out] uint8_t *rvRef
1709 * @param[out] uint16_t *size
1710 * @param[out] TfuModScheme *modType
1713 S16 rgSCHUtlAllocRcptInfo(RgSchCellCb *cell,RgSchUlAlloc *alloc,CmLteTimingInfo *timeInfo,TfuUeUlSchRecpInfo *recpReq)
1715 #if (ERRCLASS & ERRCLS_DEBUG)
1716 if ((alloc == NULLP) || (alloc->hqProc == NULLP))
1721 recpReq->size = alloc->grnt.datSz;
1722 recpReq->rbStart = alloc->grnt.rbStart;
1723 recpReq->numRb = alloc->grnt.numRb;
1724 /* Modulation order min(4,mod in grant) for 16 qam UEs.
1725 * Please refer to 36.213-8.6.1*/
1726 #ifdef FOUR_TX_ANTENNA
1727 recpReq->modType = (TfuModScheme)((alloc->forMsg3)?alloc->grnt.modOdr:
1728 (/*(alloc->ue->ueCatEnum == CM_LTE_UE_CAT_5)?
1729 alloc->grnt.modOdr: *//* Chandra:TmpFx-TM500 Cat5 with Only16QAM */
1730 (RGSCH_MIN(RGSCH_QM_QPSK,alloc->grnt.modOdr))));
1732 recpReq->modType = (TfuModScheme)((alloc->forMsg3)?alloc->grnt.modOdr:
1733 ((alloc->ue->ueCatEnum == CM_LTE_UE_CAT_5)?
1735 (RGSCH_MIN(RGSCH_QM_QPSK,alloc->grnt.modOdr))));
1737 recpReq->nDmrs = alloc->grnt.nDmrs;
1738 recpReq->hoppingEnbld = FALSE;
1739 recpReq->hoppingBits = 0;
1740 recpReq->isRtx = alloc->grnt.isRtx;
1741 recpReq->ndi = alloc->hqProc->ndi;
1742 recpReq->rv = rgRvTable[alloc->hqProc->rvIdx];
1744 recpReq->harqProcId = alloc->hqProc->procId;
1746 recpReq->harqProcId = rgSCHCmnGetUlHqProcIdx(timeInfo, cell);
1748 /* Transmission mode is SISO till Uplink MIMO is implemented. */
1749 recpReq->txMode = 0;
1750 /* This value needs to filled in in the case of frequency hopping. */
1751 recpReq->crntTxNb = 0;
1753 recpReq->mcs = alloc->grnt.iMcs;
1755 recpReq->rbgStart = alloc->grnt.vrbgStart;
1756 recpReq->numRbg = alloc->grnt.numVrbg;
1757 recpReq->xPUSCHRange = alloc->grnt.xPUSCHRange;
1758 //TODO_SID Need to check
1759 recpReq->nAntPortLayer = 0;
1760 recpReq->SCID = alloc->grnt.SCID;
1761 recpReq->PMI = alloc->grnt.PMI;
1762 recpReq->uciWoTBFlag = alloc->grnt.uciOnxPUSCH;
1765 recpReq->beamIndex = alloc->ue->ue5gtfCb.BeamId;
1770 if (!alloc->forMsg3)
1772 if (alloc->grnt.isRtx)
1774 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulRetxOccns++;
1778 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulTxOccns++;
1779 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulSumiTbs += \
1780 rgSCHCmnUlGetITbsFrmIMcs(alloc->grnt.iMcs);
1781 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulNumiTbs ++;
1782 cell->tenbStats->sch.ulSumiTbs += \
1783 rgSCHCmnUlGetITbsFrmIMcs(alloc->grnt.iMcs);
1784 cell->tenbStats->sch.ulNumiTbs ++;
1786 alloc->ue->tenbStats->stats.nonPersistent.sch[RG_SCH_CELLINDEX(alloc->ue->cell)].ulPrbUsg += alloc->grnt.numRb;
1787 cell->tenbStats->sch.ulPrbUsage[0] += alloc->grnt.numRb;
1790 /* ccpu00117050 - DEL - nSrs setting at rgSCHUtlAllocRcptInfo */
1797 * @brief This function initialises the PRACH slot occasions
1801 * Function: rgSCHUtlUpdPrachOcc
1802 * Purpose: This function updates the PRACH slots based on
1803 * RGR configuration.
1805 * Invoked by: Scheduler
1807 * @param[in] RgSchCellCb *cell
1808 * @param[in] RgrTddPrachInfo *cellCfg
1812 static Void rgSCHUtlUpdPrachOcc(RgSchCellCb *cell,RgrTddPrachInfo *cellCfg)
1820 /* In the 1st half frame */
1821 if(cellCfg->halfFrm == 0)
1826 /* In the 2nd half frame */
1832 for(idx = startIdx; idx < endIdx; idx++)
1834 if(rgSchTddUlDlSubfrmTbl[cell->ulDlCfgIdx][idx]
1835 == RG_SCH_TDD_UL_slot)
1837 if(cellCfg->ulStartSfIdx == count)
1839 size = cell->rachCfg.raOccasion.size;
1840 cell->rachCfg.raOccasion.slotNum[size] = idx;
1841 cell->rachCfg.raOccasion.size++;
1851 * @brief This function initialises the PRACH occasions
1855 * Function: rgSCHUtlPrachCfgInit
1856 * Purpose: This function initialises the PRACH occasions based on
1857 * RGR configuration.
1859 * Invoked by: Scheduler
1861 * @param[in] RgSchCellCb *cell
1862 * @param[in] RgrCellCfg *cellCfg
1866 Void rgSCHUtlPrachCfgInit(RgSchCellCb *cell,RgrCellCfg *cellCfg)
1872 if(cellCfg->prachRscInfo.numRsc <= 0)
1874 DU_LOG("\nERROR --> SCH : Invalid"
1875 "PRACH resources Configuration ");
1879 /* Update SFN occasions */
1880 cell->rachCfg.raOccasion.sfnEnum =
1881 cellCfg->prachRscInfo.prachInfo[0].sfn;
1883 cell->rachCfg.raOccasion.size = 0;
1885 /* Update slot occasions */
1886 for(idx = 0; idx < cellCfg->prachRscInfo.numRsc; idx++)
1888 if(cellCfg->prachRscInfo.prachInfo[idx].freqIdx == 0)
1890 if(cellCfg->prachRscInfo.prachInfo[idx].halfFrm == 0)
1898 if(cellCfg->prachRscInfo.prachInfo[idx].ulStartSfIdx ==
1901 subfrmIdx = cell->rachCfg.raOccasion.size;
1902 cell->rachCfg.raOccasion.slotNum[subfrmIdx] = splFrm;
1903 cell->rachCfg.raOccasion.size++;
1907 rgSCHUtlUpdPrachOcc(cell,
1908 &cellCfg->prachRscInfo.prachInfo[idx]);
1916 * @brief This function performs RGR cell initialization
1920 * Function: rgSCHUtlRgrCellCfg
1921 * Purpose: This function initialises the cell with RGR configuration
1922 * and slot related initialization.
1924 * Invoked by: Scheduler
1926 * @param[in] RgSchCellCb *cell
1927 * @param[in] RgrCellCfg *cellCfg
1928 * @param[in] RgSchErrInfo *errInfo
1932 S16 rgSCHUtlRgrCellCfg(RgSchCellCb *cell,RgrCellCfg *cellCfg,RgSchErrInfo *errInfo)
1938 CmLteTimingInfo frm;
1939 uint8_t ulDlCfgIdx = cellCfg->ulDlCfgIdx;
1943 uint16_t bw; /*!< Number of RBs in the cell */
1945 memset(&frm,0,sizeof(CmLteTimingInfo));
1947 /* ccpu00132657-MOD- Determining DLSF array size independent of DELTAS */
1948 maxDlslots = rgSchTddNumDlSubfrmTbl[ulDlCfgIdx][RGSCH_NUM_SUB_FRAMES-1];
1949 maxslots = 2 * maxDlslots;
1950 cell->numDlSubfrms = maxslots;
1951 /* ACC-TDD <ccpu00130639> */
1952 cell->tddHqSfnCycle = -1;
1953 cell->ulDlCfgIdx = ulDlCfgIdx;
1955 /* PRACH Occasions Initialization */
1956 rgSCHUtlPrachCfgInit(cell, cellCfg);
1958 /* ccpu00132658- Moved out of below for loop since the updating rbgSize and
1959 * bw are independent of sfNum*/
1960 /* determine the RBG size and no of RBGs for the configured
1962 if (cell->bwCfg.dlTotalBw > 63)
1966 else if (cell->bwCfg.dlTotalBw > 26)
1970 else if (cell->bwCfg.dlTotalBw > 10)
1978 cell->noOfRbgs = RGSCH_CEIL(cell->bwCfg.dlTotalBw, cell->rbgSize);
1980 bw = cell->bwCfg.dlTotalBw;
1982 rgSCHUtlAllocSBuf(cell->instIdx,
1983 (Data **)&cell->subFrms, sizeof(RgSchDlSf *) * maxslots);
1984 if (cell->subFrms == NULLP)
1989 /* Create memory for each frame. */
1990 for(i = 0; i < maxslots; i++)
1992 while(rgSchTddUlDlSubfrmTbl[ulDlCfgIdx][sfNum] ==
1995 sfNum = (sfNum+1) % RGSCH_NUM_SUB_FRAMES;
1998 rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&sf, sizeof(RgSchDlSf));
2003 memset(sf, 0, sizeof(*sf));
2006 if (ROK != rgSCHLaaInitDlSfCb(cell, sf))
2014 /* Mark SPS bandwidth to be occupied */
2015 sf->bwAlloced = ((cellCfg->spsCfg.maxSpsDlBw +
2016 cell->rbgSize - 1)/cell->rbgSize) * cell->rbgSize;
2017 sf->spsAllocdBw = 0;
2018 sf->type2End = sf->bwAlloced/cell->rbgSize;
2021 /* Fix for ccpu00123918*/
2023 #endif /* LTEMAC_SPS */
2024 /* Initialize the ackNakRepQ here */
2025 #ifdef RG_MAC_MEASGAP
2026 cmLListInit (&(sf->ackNakRepQ));
2028 cell->subFrms[i] = sf;
2029 sfNum = (sfNum+1) % RGSCH_NUM_SUB_FRAMES;
2035 /* ccpu00117052 - MOD - Passing double pointer
2036 for proper NULLP assignment*/
2037 rgSCHUtlFreeSBuf(cell->instIdx,
2038 (Data **)(&(cell->subFrms[i-1])), sizeof(RgSchDlSf));
2040 rgSCHLaaDeInitDlSfCb(cell, sf);
2043 /* ccpu00117052 - MOD - Passing double pointer
2044 for proper NULLP assignment*/
2045 rgSCHUtlFreeSBuf(cell->instIdx,
2046 (Data **)(&(cell->subFrms)), sizeof(RgSchDlSf *) * maxslots);
2051 if (cell->sc.apis == NULLP)
2053 cell->sc.apis = &rgSchCmnApis;
2055 ret = cell->sc.apis->rgSCHRgrCellCfg(cell, cellCfg, errInfo);
2059 /* ccpu00132286- Removed deletion of sf nodes as the deletion will be
2060 * happening during CellDelete. Added return handling to provide negative
2065 /* Release the slots and thereby perform the initialization */
2066 for (i = 0; i < maxslots; i++)
2068 if((i > 0) && (i%maxDlslots == 0))
2073 frm.slot = cell->subFrms[i]->sfNum;
2074 rgSCHUtlDlRlsSubFrm(cell, frm);
2083 * @brief This function performs scheduler related cell creation
2087 * Function: rgSCHUtlRgrCellCfg
2088 * Purpose: This function creates the slots needed for the
2089 * cell. It then peforms init of the scheduler by calling
2090 * scheduler specific cell init function.
2092 * Invoked by: Scheduler
2094 * @param[in] RgSchCellCb *cell
2095 * @param[in] RgrCellCfg *cellCfg
2096 * @param[in] RgSchErrInfo *errInfo
2100 S16 rgSCHUtlRgrCellCfg(RgSchCellCb *cell,RgrCellCfg *cellCfg,RgSchErrInfo *errInfo)
2104 CmLteTimingInfo frm;
2106 Inst inst = cell->instIdx;
2107 /* LTE_ADV_FLAG_REMOVED_START */
2109 len = (uint16_t)((cell->bwCfg.dlTotalBw % 8 == 0) ? (cell->bwCfg.dlTotalBw/8) : (cell->bwCfg.dlTotalBw/8 + 1)); /*KW fix for LTE_ADV */
2110 /* LTE_ADV_FLAG_REMOVED_END */
2112 memset(&frm,0,sizeof(CmLteTimingInfo));
2114 /* determine the RBG size and no of RBGs for the configured
2116 if (cell->bwCfg.dlTotalBw > 63)
2120 else if (cell->bwCfg.dlTotalBw > 26)
2124 else if (cell->bwCfg.dlTotalBw > 10)
2132 cell->noOfRbgs = RGSCH_CEIL(cell->bwCfg.dlTotalBw, cell->rbgSize);
2133 /* Create memory for each frame. */
2134 /* Changing loop limit from
2135 RGSCH_NUM_SUB_FRAMES to RGSCH_NUM_DL_slotS */
2136 for(i = 0; i < RGSCH_NUM_DL_slotS; i++)
2138 rgSCHUtlAllocSBuf(inst, (Data **)&sf, sizeof(RgSchDlSf));
2143 memset(sf, 0, sizeof(*sf));
2146 if (ROK != rgSCHLaaInitDlSfCb(cell, sf))
2151 /* Doing MOD operation before assigning value of i */
2152 sf->sfNum = i % RGSCH_NUM_SUB_FRAMES;
2153 sf->bw = cell->bwCfg.dlTotalBw;
2154 /* Initialize the ackNakRepQ here */
2155 #ifdef RG_MAC_MEASGAP
2156 cmLListInit (&(sf->ackNakRepQ));
2158 cell->subFrms[i] = sf;
2159 /* LTE_ADV_FLAG_REMOVED_START */
2160 if (cell->lteAdvCb.dsfrCfg.status == RGR_ENABLE)
2162 /*initialize the RNTP Buffer*/
2163 if(rgSchDSFRRntpInfoInit(&sf->rntpInfo, cell, sf->bw))
2169 if (cell->lteAdvCb.sfrCfg.status == RGR_ENABLE)
2171 /*initialise the pools of CC and CE*/
2172 if(rgSchSFRTotalPoolInit(cell, sf))
2177 /* LTE_ADV_FLAG_REMOVED_END */
2180 /* LTE_ADV_FLAG_REMOVED_START */
2181 /* Allocate memory for "scheduled UE" Info */
2182 if (cell->lteAdvCb.dsfrCfg.status == RGR_ENABLE)
2184 if((rgSCHUtlAllocSBuf(inst, (Data**)&(cell->rntpAggrInfo.val),
2185 (len * sizeof(uint8_t)))) != ROK)
2187 DU_LOG("\nERROR --> SCH : Memory allocation FAILED for RNTP Alloc");
2190 cell->rntpAggrInfo.pres = PRSNT_NODEF;
2191 cell->rntpAggrInfo.len = len;
2193 /* LTE_ADV_FLAG_REMOVED_END */
2195 /* Changing loop limit from
2196 RGSCH_NUM_SUB_FRAMES to RGSCH_NUM_DL_slotS */
2197 if (i != RGSCH_NUM_DL_slotS)
2201 /* ccpu00117052 - MOD - Passing double pointer
2202 for proper NULLP assignment*/
2203 rgSCHUtlFreeSBuf(inst, (Data **)(&(cell->subFrms[i-1])),
2206 rgSCHLaaDeInitDlSfCb(cell, sf);
2212 if (cell->sc.apis == NULLP)
2214 cell->sc.apis = &rgSchCmnApis;
2217 /* Release the slots and thereby perform the initialization */
2218 for (i = 0; i < RGSCH_NUM_DL_slotS; i++)
2220 if (i >= RGSCH_NUM_SUB_FRAMES)
2222 /* [ccpu00123828]-MOD-The below statement sfn += 1incorrectly modified
2223 * the value of sfn for i>=10 thru 19. Correct way is to assign
2227 frm.slot = i % RGSCH_NUM_SUB_FRAMES;
2228 rgSCHUtlDlRlsSubFrm(cell, frm);
2231 ret = cell->sc.apis->rgSCHRgrCellCfg(cell, cellCfg, errInfo);
2234 errInfo->errCause = RGSCHERR_SCH_CFG;
2238 if(cell->emtcEnable)
2240 /* TODO: Repetition framework in RGR and APP */
2241 if (rgSCHUtlEmtcResMngmtInit(
2243 RGSCH_IOT_PDSCH_POOLSZ, RGSCH_IOT_PDSCH_DELTA, cellCfg->bwCfg.dlTotalBw,
2244 RGSCH_IOT_PUSCH_POOLSZ, RGSCH_IOT_PUSCH_DELTA, RGSCH_IOT_PUSCH_MAXFREQSZ,
2245 RGSCH_IOT_PUCCH_POOLSZ, RGSCH_IOT_PUCCH_DELTA, RGSCH_IOT_PUCCH_MAXFREQSZ) != ROK)
2247 errInfo->errCause = RGSCHERR_SCH_CFG;
2259 * @brief This function performs the cell reconfiguration at RGR interface
2263 * Function: rgSCHUtlRgrCellRecfg
2264 * Purpose: This function updates the reconfigurable parameters
2265 * on the cell control block for the scheduler.
2267 * Invoked by: Scheduler
2269 * @param[in] RgSchCellCb *cell
2270 * @param[in] RgrCellCfg *cellCfg
2271 * @param[in] RgSchErrInfo *errInfo
2275 S16 rgSCHUtlRgrCellRecfg(RgSchCellCb *cell,RgrCellRecfg *recfg,RgSchErrInfo *err)
2277 return (cell->sc.apis->rgSCHRgrCellRecfg(cell, recfg, err));
2283 * @brief This function returns the Y value of UE for a sub frame
2287 * Function: rgSCHUtlFreeCell
2288 * Purpose: This function updates the value of Y stored in the
2289 * UE control block. It uses the previously computed
2290 * value for computing for this slot.
2292 * Invoked by: Scheduler
2294 * @param[in] RgSchCellCb *cell
2298 S16 rgSCHUtlFreeCell(RgSchCellCb *cell)
2303 RgSchPdcchInfo *pdcchInfo;
2304 RgSchPhichInfo *phichInfo;
2306 Inst inst = cell->instIdx;
2309 RgSchRaReqInfo *raReqInfo;
2314 maxslots = cell->numDlSubfrms;
2316 maxslots = RGSCH_NUM_DL_slotS;
2320 /* Invoke the index for scheduler, cell deletion */
2321 cell->sc.apis->rgSCHFreeCell(cell);
2323 /* Release the slots allocated */
2324 for (i = 0; i < maxslots; i++)
2327 rgSCHLaaDeInitDlSfCb(cell, cell->subFrms[i]);
2329 pdcchInfo = &cell->subFrms[i]->pdcchInfo;
2330 /* ccpu00117052 - MOD - Passing double pointer
2331 for proper NULLP assignment*/
2332 rgSCHUtlFreeSBuf(inst, (Data **)(&(pdcchInfo->map)),
2333 (pdcchInfo->nCce + 7) >> 3);
2334 while (pdcchInfo->pdcchs.first != NULLP)
2336 pdcch = (RgSchPdcch *)pdcchInfo->pdcchs.first->node;
2337 cmLListDelFrm(&pdcchInfo->pdcchs, pdcchInfo->pdcchs.first);
2338 /* ccpu00117052 - MOD - Passing double pointer
2339 for proper NULLP assignment*/
2340 rgSCHUtlFreeSBuf(inst, (Data **)&pdcch, sizeof(RgSchPdcch));
2343 phichInfo = &cell->subFrms[i]->phichInfo;
2344 while(phichInfo->phichs.first != NULLP)
2346 phich = (RgSchPhich *)phichInfo->phichs.first->node;
2347 cmLListDelFrm(&phichInfo->phichs, phichInfo->phichs.first);
2348 RGSCH_PHICH_FREE(inst, phich, sizeof(RgSchPhich));
2351 /* LTE_ADV_FLAG_REMOVED_START */
2352 /*releasing SFR pool entries*/
2353 rgSchSFRTotalPoolFree(&cell->subFrms[i]->sfrTotalPoolInfo, cell);
2355 /*releasing dsfr rntp pattern info*/
2356 rgSchDSFRRntpInfoFree(&cell->subFrms[i]->rntpInfo, cell,
2357 cell->bwCfg.dlTotalBw);
2358 /* LTE_ADV_FLAG_REMOVED_END */
2360 /* ccpu00117052 - MOD - Passing double pointer
2361 for proper NULLP assignment*/
2362 rgSCHUtlFreeSBuf(inst, (Data **)(&(cell->subFrms[i])), sizeof(RgSchDlSf));
2365 /* Release the slot pointers */
2366 /* ccpu00117052 - MOD - Passing double pointer
2367 for proper NULLP assignment*/
2368 rgSCHUtlFreeSBuf(inst,
2369 (Data **) (&(cell->subFrms)), sizeof(RgSchDlSf *) * maxslots);
2371 for(idx=0; idx < cell->raInfo.lstSize; idx++)
2373 lst = &cell->raInfo.raReqLst[idx];
2374 while (lst->first != NULLP)
2376 raReqInfo = (RgSchRaReqInfo *)lst->first->node;
2377 cmLListDelFrm(lst, &raReqInfo->raReqLstEnt);
2378 /* ccpu00117052 - MOD - Passing double pointer
2379 for proper NULLP assignment*/
2380 rgSCHUtlFreeSBuf(inst,(Data **)&raReqInfo, sizeof(RgSchRaReqInfo));
2383 /* ccpu00117052 - MOD - Passing double pointer
2384 for proper NULLP assignment*/
2385 rgSCHUtlFreeSBuf(inst,
2386 (Data **)(&(cell->raInfo.raReqLst)),
2387 sizeof(CmLListCp) * (cell->raInfo.lstSize));
2390 /* Release allocated pdcchs */
2391 lst = &cell->pdcchLst;
2392 while (lst->first != NULLP)
2394 pdcch = (RgSchPdcch *)lst->first->node;
2395 cmLListDelFrm(lst, &pdcch->lnk);
2397 if(cell->emtcEnable)
2399 rgSCHEmtcPdcchFree(cell, pdcch);
2400 rgSCHUtlEmtcResMngmtDeinit(cell);
2403 /* ccpu00117052 - MOD - Passing double pointer
2404 for proper NULLP assignment*/
2405 rgSCHUtlFreeSBuf(inst,(Data **)&pdcch, sizeof(RgSchPdcch));
2408 rgSCHLaaFreeLists(cell);
2411 /* LTE_ADV_FLAG_REMOVED_START */
2412 /* releasing RNTP Aggregation Info from CellCb*/
2413 rgSchDSFRRntpInfoFree(&cell->rntpAggrInfo, cell, cell->bwCfg.dlTotalBw);
2414 /* LTE_ADV_FLAG_REMOVED_END */
2421 * @brief This function adds the UE to scheduler
2425 * Function: rgSCHUtlRgrUeCfg
2426 * Purpose: This function performs addition of UE to scheduler
2427 * 1. First, it updates the Y table in the UE
2428 * 2. Then, it calls the scheduler's handler for UE addition
2430 * Invoked by: Scheduler
2432 * @param[in] RgSchCellCb *cell
2433 * @param[in] RgSchUeCb *ue
2434 * @param[in] RgrUeCfg *cfg
2435 * @param[in] RgSchErrInfo *err
2439 S16 rgSCHUtlRgrUeCfg(RgSchCellCb *cell,RgSchUeCb *ue,RgrUeCfg *cfg,RgSchErrInfo *err)
2442 /* Assign TM 1 as UE's default TM */
2443 ue->mimoInfo.txMode = RGR_UE_TM_1;
2444 ue->txModeTransCmplt = TRUE;
2445 cmInitTimers(&ue->txModeTransTmr, 1);
2446 if (cfg->txMode.pres == PRSNT_NODEF)
2448 /* DL MU-MIMO not supported */
2449 if (cfg->txMode.txModeEnum == RGR_UE_TM_5)
2451 err->errCause = RGSCHERR_SCH_CFG;
2454 ue->mimoInfo.txMode = cfg->txMode.txModeEnum;
2456 ue->ul.ulTxAntSel = cfg->ulTxAntSel;
2457 ue->mimoInfo.cdbkSbstRstrctn = cfg->ueCodeBookRstCfg;
2459 ue->ueCatEnum = cfg->ueCatEnum;
2460 if ((cfg->puschDedCfg.bACKIdx > 15) ||
2461 (cfg->puschDedCfg.bCQIIdx > 15) ||
2462 (cfg->puschDedCfg.bRIIdx > 15))
2464 err->errCause = RGSCHERR_SCH_CFG;
2467 ue->ul.betaHqOffst = cfg->puschDedCfg.bACKIdx;
2468 ue->ul.betaCqiOffst = cfg->puschDedCfg.bCQIIdx;
2469 ue->ul.betaRiOffst = cfg->puschDedCfg.bRIIdx;
2471 ue->csgMmbrSta = cfg->csgMmbrSta;
2473 memset(&ue->pfsStats, 0, sizeof(RgSchPfsStats));
2475 /* Call the handler of the scheduler based on cell configuration */
2476 return (cell->sc.apis->rgSCHRgrUeCfg(cell, ue, cfg, err));
2478 /* Start : LTEMAC_2.1_DEV_CFG */
2481 * @brief This function adds a service to scheduler
2485 * Function: rgSCHUtlRgrLcCfg
2486 * Purpose: This function performs addition of service to scheduler
2487 * The addition is performed for each direction based
2488 * the direction field of the configuration
2490 * Invoked by: Scheduler
2492 * @param[in] RgSchCellCb *cell
2493 * @param[in] RgSchUeCb *ue
2494 * @param[in] RgSchDlLcCb *dlLc
2495 * @param[in] RgrLchCfg *cfg
2496 * @param[in] RgSchErrInfo *err
2500 S16 rgSCHUtlRgrLcCfg(RgSchCellCb *cell,RgSchUeCb *ue,RgSchDlLcCb *dlLc,RgrLchCfg *cfg,RgSchErrInfo *errInfo)
2502 return (cell->sc.apis->rgSCHRgrLchCfg(cell, ue, dlLc, cfg, errInfo));
2507 * @brief This function modifies a service to scheduler
2511 * Function: rgSCHUtlRgrLcRecfg
2512 * Purpose: This function performs modification of a service in
2513 * scheduler. The modification is performed for each direction
2514 * based the direction field of the configuration
2516 * Invoked by: Scheduler
2518 * @param[in] RgSchCellCb *cell
2519 * @param[in] RgSchUeCb *ue
2520 * @param[in] RgSchDlLcCb *dlLc
2521 * @param[in] RgrLchRecfg *recfg
2522 * @param[in] RgSchErrInfo *err
2526 S16 rgSCHUtlRgrLcRecfg(RgSchCellCb *cell,RgSchUeCb *ue,RgSchDlLcCb *dlLc,RgrLchRecfg *recfg,RgSchErrInfo *err)
2528 return (cell->sc.apis->rgSCHRgrLchRecfg(cell, ue, dlLc, recfg, err));
2532 * @brief This function deletes a Lc in scheduler
2536 * Function: rgSCHUtlRgrLcDel
2537 * Purpose: This function performs deletion of Lc in scheduler
2539 * Invoked by: Scheduler
2541 * @param[in] RgSchCellCb *cell
2542 * @param[in] RgSchUeCb *ue
2543 * @param[in] CmLteLcId lcId
2544 * @param[in] uint8_t lcgId
2548 S16 rgSCHUtlRgrLcDel(RgSchCellCb *cell,RgSchUeCb *ue,CmLteLcId lcId,uint8_t lcgId)
2550 cell->sc.apis->rgSCHRgrLchDel(cell, ue, lcId, lcgId);
2553 } /* rgSCHUtlRgrLcDel */
2556 * @brief This function adds a service to scheduler
2560 * Function: rgSCHUtlRgrLcgCfg
2561 * Purpose: This function performs addition of service to scheduler
2562 * The addition is performed for each direction based
2563 * the direction field of the configuration
2565 * Invoked by: Scheduler
2567 * @param[in] RgSchCellCb *cell
2568 * @param[in] RgSchUeCb *ue
2569 * @param[in] RgrLchCfg *cfg
2570 * @param[in] RgSchErrInfo *err
2574 S16 rgSCHUtlRgrLcgCfg(RgSchCellCb *cell,RgSchUeCb *ue,RgrLcgCfg *cfg,RgSchErrInfo *errInfo)
2576 return (cell->sc.apis->rgSCHRgrLcgCfg(cell, ue, &(ue->ul.lcgArr[cfg->ulInfo.lcgId]), cfg, errInfo));
2581 * @brief This function modifies a service to scheduler
2585 * Function: rgSCHUtlRgrLcgRecfg
2586 * Purpose: This function performs modification of a service in
2587 * scheduler. The modification is performed for each direction
2588 * based the direction field of the configuration
2590 * Invoked by: Scheduler
2592 * @param[in] RgSchCellCb *cell
2593 * @param[in] RgSchUeCb *ue
2594 * @param[in] RgrLcgRecfg *recfg
2595 * @param[in] RgSchErrInfo *err
2599 S16 rgSCHUtlRgrLcgRecfg(RgSchCellCb *cell,RgSchUeCb *ue,RgrLcgRecfg *recfg,RgSchErrInfo *err)
2601 return (cell->sc.apis->rgSCHRgrLcgRecfg(cell, ue, &(ue->ul.lcgArr[recfg->ulRecfg.lcgId]), recfg, err));
2602 } /* rgSCHUtlRgrLcRecfg */
2605 * @brief This function modifies a service to scheduler
2609 * Function: rgSCHUtlRgrLcgDel
2610 * Purpose: This function performs modification of a service in
2611 * scheduler. The modification is performed for each direction
2612 * based the direction field of the configuration
2614 * Invoked by: Scheduler
2616 * @param[in] RgSchCellCb *cell
2617 * @param[in] RgSchUeCb *ue
2618 * @param[in] RgrDel *lcDelInfo
2622 Void rgSCHUtlRgrLcgDel(RgSchCellCb *cell,RgSchUeCb *ue,uint8_t lcgId)
2624 cell->sc.apis->rgSCHFreeLcg(cell, ue, &ue->ul.lcgArr[lcgId]);
2626 /* Stack Crash problem for TRACE5 changes. added the return below . */
2629 } /* rgSCHUtlRgrLcgDel */
2632 /* End: LTEMAC_2.1_DEV_CFG */
2635 * @brief This function is a wrapper to call scheduler specific API.
2639 * Function: rgSCHUtlDoaInd
2640 * Purpose: Updates the DOA for the UE
2644 * @param[in] RgSchCellCb *cell
2645 * @param[in] RgSchUeCb *ue
2646 * @param[in] TfuDoaRpt *doaRpt
2650 Void rgSCHUtlDoaInd(RgSchCellCb *cell,RgSchUeCb *ue,TfuDoaRpt *doaRpt)
2652 ue->mimoInfo.doa.pres = PRSNT_NODEF;
2653 ue->mimoInfo.doa.val = doaRpt->doa;
2658 * @brief This function is a wrapper to call scheduler specific API.
2662 * Function: rgSCHUtlDlCqiInd
2663 * Purpose: Updates the DL CQI for the UE
2667 * @param[in] RgSchCellCb *cell
2668 * @param[in] RgSchUeCb *ue
2669 * @param[in] TfuDlCqiRpt *dlCqiRpt
2670 * @param[in] CmLteTimingInfo timingInfo
2674 Void rgSCHUtlDlCqiInd(RgSchCellCb *cell,RgSchUeCb *ue,TfuDlCqiRpt *dlCqiRpt,CmLteTimingInfo timingInfo)
2676 RgSchCellCb *sCellCb = NULLP;
2677 if (dlCqiRpt->isPucchInfo)
2679 sCellCb = ue->cellInfo[dlCqiRpt->dlCqiInfo.pucchCqi.cellIdx]->cell;
2680 sCellCb->sc.apis->rgSCHDlCqiInd(sCellCb, ue, dlCqiRpt->isPucchInfo, \
2681 (Void *)&dlCqiRpt->dlCqiInfo.pucchCqi, timingInfo);
2686 for (idx = 0; idx < dlCqiRpt->dlCqiInfo.pusch.numOfCells; idx++)
2688 sCellCb = ue->cellInfo[dlCqiRpt->dlCqiInfo.pusch.puschCqi[idx].cellIdx]->cell;
2689 sCellCb->sc.apis->rgSCHDlCqiInd(sCellCb, ue, dlCqiRpt->isPucchInfo, \
2690 (Void *)&dlCqiRpt->dlCqiInfo.pusch.puschCqi[idx], timingInfo);
2699 * @brief This function is a wrapper to call scheduler specific API.
2703 * Function: rgSCHUtlSrsInd
2704 * Purpose: Updates the UL SRS for the UE
2708 * @param[in] RgSchCellCb *cell
2709 * @param[in] RgSchUeCb *ue
2710 * @param[in] TfuSrsRpt* srsRpt
2711 * @param[in] CmLteTimingInfo timingInfo
2715 Void rgSCHUtlSrsInd(RgSchCellCb *cell,RgSchUeCb *ue,TfuSrsRpt *srsRpt,CmLteTimingInfo timingInfo)
2717 cell->sc.apis->rgSCHSrsInd(cell, ue, srsRpt, timingInfo);
2723 * @brief This function is a wrapper to call scheduler specific API.
2727 * Function: rgSCHUtlDlTARpt
2728 * Purpose: Reports PHY TA for a UE.
2732 * @param[in] RgSchCellCb *cell
2733 * @param[in] RgSchUeCb *ue
2737 Void rgSCHUtlDlTARpt(RgSchCellCb *cell,RgSchUeCb *ue)
2739 cell->sc.apis->rgSCHDlTARpt(cell, ue);
2745 * @brief This function is a wrapper to call scheduler specific API.
2749 * Function: rgSCHUtlDlRlsSubFrm
2750 * Purpose: Releases scheduler Information from DL SubFrm.
2754 * @param[in] RgSchCellCb *cell
2755 * @param[out] CmLteTimingInfo subFrm
2759 Void rgSCHUtlDlRlsSubFrm(RgSchCellCb *cell,CmLteTimingInfo subFrm)
2761 cell->sc.apis->rgSCHDlRlsSubFrm(cell, subFrm);
2767 * @brief This API is invoked to update the AperCQI trigger
2772 * Function : rgSCHUtlUpdACqiTrigWt
2773 * - If HqFdbk is ACK then add up weight corresponding
2774 * to ACK to the AcqiTrigWt.
2775 * - If HqFdbk is NACK then add up weight corresponding
2776 * to NACK to the AcqiTrigWt.
2777 * - If AcqiTrigWt crosses threshold then trigger
2778 * grant req for APERCQI to SCH.
2780 * @param[in] RgSchUeCb *ue
2781 * @param[in] uint8_t isAck
2785 Void rgSCHUtlUpdACqiTrigWt(RgSchUeCb *ue,RgSchUeCellInfo *cellInfo,uint8_t isAck )
2788 uint8_t triggerSet = 0;
2792 if (isAck == TFU_HQFDB_ACK)
2794 cellInfo->acqiCb.aCqiTrigWt += RG_APER_CQI_ACK_WGT;
2798 cellInfo->acqiCb.aCqiTrigWt += RG_APER_CQI_NACK_WGT;
2801 if (cellInfo->acqiCb.aCqiTrigWt > RG_APER_CQI_THRESHOLD_WGT)
2803 RgSchCellCb *cell = ue->cell;
2804 RgSchErrInfo unUsed;
2806 if(ue->dl.reqForCqi)
2808 /* Already one ACQI trigger procedure is going on
2809 * which is not yet satisfied. Delaying this request till
2810 * the previous is getting satisfied*/
2814 ue->dl.reqForCqi = TRUE;
2816 rgSchCmnSetCqiReqField(cellInfo,ue,&ue->dl.reqForCqi);
2817 //Reset aCqiTrigWt for all the serving cells for which we have triggered ACQI
2818 rgSCHTomUtlGetTrigSet(cell, ue, ue->dl.reqForCqi, &triggerSet);
2819 for (sIdx = 0; sIdx < CM_LTE_MAX_CELLS; sIdx++)
2821 /* The Aperiodic requested for SCell index sIdx */
2822 if ((triggerSet >> (7 - sIdx)) & 0x01)
2824 /* The Aperiodic request for SCell index sIdx */
2825 ue->cellInfo[sIdx]->acqiCb.aCqiTrigWt = 0;
2830 /* Force SCH to send UL grant by indicating fake SR.
2831 * If this UE already in UL SCH Qs this SR Ind will
2833 rgSCHUtlSrRcvd(cell, ue, cell->crntTime, &unUsed);
2841 * @brief This API is invoked to indicate scheduler of a CRC indication.
2845 * Function : rgSCHUtlHdlUlTransInd
2846 * This API is invoked to indicate scheduler of a CRC indication.
2848 * @param[in] RgSchCellCb *cell
2849 * @param[in] RgSchUeCb *ue
2850 * @param[in] CmLteTimingInfo timingInfo
2854 Void rgSCHUtlHdlUlTransInd(RgSchCellCb *cell,RgSchUeCb *ue,CmLteTimingInfo timingInfo)
2856 cell->sc.apis->rgSCHHdlUlTransInd(cell, ue, timingInfo);
2861 * @brief This API is invoked to indicate scheduler of a CRC failure.
2865 * Function : rgSCHUtlHdlCrcInd
2866 * This API is invoked to indicate CRC to scheduler.
2868 * @param[in] RgSchCellCb *cell
2869 * @param[in] RgSchUeCb *ue
2870 * @param[in] CmLteTimingInfo timingInfo
2874 Void rgSCHUtlHdlCrcInd(RgSchCellCb *cell,RgSchUeCb *ue,CmLteTimingInfo timingInfo)
2876 cell->sc.apis->rgSCHUlCrcInd(cell, ue, timingInfo);
2878 } /* end of rgSCHUtlHdlCrcFailInd */
2881 * @brief This API is invoked to indicate scheduler of a CRC failure.
2885 * Function : rgSCHUtlHdlCrcFailInd
2886 * This API is invoked to indicate CRC failure to scheduler.
2888 * @param[in] RgSchCellCb *cell
2889 * @param[in] RgSchUeCb *ue
2890 * @param[in] CmLteTimingInfo timingInfo
2894 Void rgSCHUtlHdlCrcFailInd(RgSchCellCb *cell,RgSchUeCb *ue,CmLteTimingInfo timingInfo)
2896 cell->sc.apis->rgSCHUlCrcFailInd(cell, ue, timingInfo);
2898 } /* end of rgSCHUtlHdlCrcFailInd */
2899 #endif /* LTEMAC_SPS */
2903 * @brief This function is a wrapper to call scheduler specific API.
2907 * Function: rgSCHUtlDlProcAddToRetx
2908 * Purpose: This function adds a HARQ process to retransmission
2909 * queue. This may be performed when a HARQ ack is
2912 * Invoked by: HARQ feedback processing
2914 * @param[in] RgSchCellCb* cell
2915 * @param[in] RgSchDlHqProc* hqP
2919 Void rgSCHUtlDlProcAddToRetx(RgSchCellCb *cell,RgSchDlHqProcCb *hqP)
2921 cell->sc.apis->rgSCHDlProcAddToRetx(cell, hqP);
2927 * @brief This function adds a HARQ process TB to transmission
2931 * Function: rgSCHUtlDlHqPTbAddToTx
2932 * Purpose: This function a HarqProcess TB to the slot
2935 * Invoked by: Scheduler
2937 * @param[in] RgSubFrm* subFrm
2938 * @param[in] RgDlHqProc* hqP
2939 * @param[in] uint8_t tbIdx
2943 Void rgSCHUtlDlHqPTbAddToTx(RgSchDlSf *subFrm,RgSchDlHqProcCb *hqP,uint8_t tbIdx)
2945 RgSchUeCb *ue = NULLP;
2946 RgSchCellCb *cell = hqP->hqE->cell;
2948 /* Addition of UE to dlSf->ueLst shall be done only to UE's PCell */
2949 /* ue->cell will always hold PCell information */
2950 if (NULLP == hqP->hqPSfLnk.node)
2955 if(NULLP == ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk.node)
2957 ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk.node = (PTR)ue;
2958 cmLListAdd2Tail(&cell->subFrms[subFrm->dlIdx]->ueLst,
2959 &ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk);
2961 ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].isPuschHarqRecpPres = FALSE;
2965 /* Add Hq proc in particular dlIdx List for this UE
2966 This list will be used while processing feedback*/
2967 hqP->hqPSfLnk.node = (PTR)hqP;
2968 cmLListAdd2Tail(&ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].hqPLst,&hqP->hqPSfLnk);
2971 uint32_t gSCellSchedCount,gPrimarySchedCount;
2972 if(RG_SCH_IS_CELL_SEC(hqP->hqE->ue,hqP->hqE->cell))
2976 gPrimarySchedCount++;
2980 else if (hqP->hqE->msg4Proc == hqP)
2982 /* Msg4 will be scheduled on PCELL only hence add directly to subFrm msg4HqpList */
2983 hqP->hqPSfLnk.node = (PTR)hqP;
2984 cmLListAdd2Tail(&subFrm->msg4HqPLst, &hqP->hqPSfLnk);
2991 if((ue) && (HQ_TB_WAITING == hqP->tbInfo[tbIdx].state))
2994 ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].totalTbCnt++;
2996 /*totalTbCnt will hold the total number of TBs across all harq Proc from all
2999 hqP->subFrm = subFrm;
3008 * @brief This function removes a HARQ process TB from transmission
3012 * Function: rgSCHUtlDlHqPTbRmvFrmTx
3013 * Purpose: This function removes a HarqProcess TB to the slot
3016 * Invoked by: Scheduler
3018 * @param[in] RgSubFrm* subFrm
3019 * @param[in] RgDlHqProc* hqP
3020 * @param[in] uint8_t tbIdx
3021 * @param[in] Bool isRepeting
3025 Void rgSCHUtlDlHqPTbRmvFrmTx(RgSchDlSf *subFrm,RgSchDlHqProcCb *hqP,uint8_t tbIdx,Bool isRepeting)
3027 RgSchCellCb *cell = NULLP;
3028 /* Check with TDD */
3030 (hqP->hqE->ue->ackNakRepCb.cfgRepCnt !=
3031 hqP->tbInfo[tbIdx].fbkRepCntr))
3033 cmLListDelFrm(&subFrm->ackNakRepQ,
3034 &hqP->tbInfo[tbIdx].anRepLnk[hqP->tbInfo[tbIdx].fbkRepCntr]);
3038 if (NULLP != hqP->hqPSfLnk.node)
3041 if (hqP->hqE->msg4Proc == hqP)
3043 /* Msg4 will be scheduled on PCELL only hence delete directly from subFrm msg4HqpList */
3044 cmLListDelFrm(&subFrm->msg4HqPLst, &hqP->hqPSfLnk);
3048 cell = hqP->hqE->cell;
3049 /* Addition of UE to dlSf->ueLst shall be done only to UE's PCell */
3050 /* ue->cell will always hold PCell information */
3051 cmLListDelFrm(&hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].hqPLst,&hqP->hqPSfLnk);
3052 if (0 == hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].hqPLst.count)
3055 cmLListDelFrm(&cell->subFrms[subFrm->dlIdx]->ueLst,
3056 &hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk);
3057 hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].dlSfUeLnk.node = (PTR)NULLP;
3058 hqP->hqE->ue->dl.dlSfHqInfo[cell->cellId][subFrm->dlIdx].totalTbCnt = 0;
3061 hqP->hqPSfLnk.node = NULLP;
3063 hqP->subFrm = NULLP;
3070 * @brief Handler for accessing the existing SCellCb identified by the key
3071 * SCellId under the CellCb.
3075 * Function : rgSchUtlGetCellCb
3078 * @param[in] *cellCb
3080 * @return RgSchUeCb*
3082 RgSchCellCb* rgSchUtlGetCellCb(Inst inst,uint16_t cellId)
3084 RgSchCellCb *cellCb = NULLP;
3086 strtCellId = rgSchCb[inst].genCfg.startCellId;
3087 cellCb = rgSchCb[inst].cells[cellId - strtCellId];
3091 } /* rgSchUtlGetCellCb */
3094 * @brief Handler for deriving the servCellidx
3098 * Function : rgSchUtlGetServCellIdx
3101 * @param[in] *cellId
3102 * @param[in] RgSchUeCb *ue
3103 * @return uint8_t servCellIdx
3105 uint8_t rgSchUtlGetServCellIdx(Inst inst, uint16_t cellId, RgSchUeCb *ue)
3107 uint8_t servCellIdx;
3108 uint16_t strtCellId;
3110 strtCellId = rgSchCb[inst].genCfg.startCellId;
3111 servCellIdx = ue->cellIdToCellIdxMap[cellId - strtCellId];
3112 return (servCellIdx);
3114 } /* rgSchUtlGetCellCb */
3117 * @brief Handler for validating the Cell Id received secondary Cell Addition
3121 * Function : rgSchUtlGetCellId
3124 * @param[in] *cellCb
3126 * @return RgSchUeCb*
3128 S16 rgSchUtlVldtCellId(Inst inst,uint16_t cellId)
3132 strtCellId = rgSchCb[inst].genCfg.startCellId;
3133 if((cellId >= strtCellId) && ((cellId - strtCellId) < CM_LTE_MAX_CELLS))
3138 } /* rgSchUtlVldtCellId */
3142 * @brief UE reconfiguration for scheduler
3146 * Function : rgSCHUtlRgrUeRecfg
3148 * This functions updates UE specific scheduler
3149 * information upon UE reconfiguration
3151 * @param[in] RgSchCellCb *cell
3152 * @param[in] RgSchUeCb *ue
3153 * @param[int] RgrUeRecfg *ueRecfg
3154 * @param[out] RgSchErrInfo *err
3159 S16 rgSCHUtlRgrUeRecfg(RgSchCellCb *cell,RgSchUeCb *ue,RgrUeRecfg *ueRecfg,RgSchErrInfo *err)
3161 /* Changes for UE Category Reconfiguration feature addition */
3162 RgSchCmnUe *ueSch = RG_SCH_CMN_GET_UE(ue, cell);
3164 /* Changes for UE Category Reconfiguration feature addition */
3165 if (ueRecfg->ueRecfgTypes & RGR_UE_UECAT_RECFG)
3167 ueSch->cmn.ueCat = ueRecfg->ueCatEnum-1;
3169 ue->ueCatEnum = ueRecfg->ueCatEnum;
3173 /* DL MU-MIMO not supported */
3174 if (ueRecfg->ueRecfgTypes & RGR_UE_TXMODE_RECFG)
3177 if (ueRecfg->txMode.pres == PRSNT_NODEF)
3179 if (ueRecfg->txMode.txModeEnum == RGR_UE_TM_5)
3181 err->errCause = RGSCHERR_SCH_CFG;
3185 if(ue->mimoInfo.txMode != ueRecfg->txMode.txModeEnum)
3187 /* Decremnt the previos A value for this cell */
3188 ue->f1bCsAVal -= rgSCHUtlGetMaxTbSupp(ue->mimoInfo.txMode);
3189 /* Update A value with the new TM Mode */
3190 ue->f1bCsAVal += rgSCHUtlGetMaxTbSupp(ueRecfg->txMode.txModeEnum);
3193 DU_LOG("\nINFO --> SCH : UeReCfg A valie is %d\n",ue->f1bCsAVal);
3196 ue->mimoInfo.txMode = ueRecfg->txMode.txModeEnum;
3200 /* [ccpu00123958]-ADD- Check for PUSCH related Reconfig from the bit mask */
3201 if(ueRecfg->ueRecfgTypes & RGR_UE_PUSCH_RECFG)
3203 /* Fix: ccpu00124012 */
3204 /* TODO:: Need to check if this is
3205 mandatory to be re-configured on UE category re-configuration */
3206 /* ue->ul.betaHqOffst = ueRecfg->puschDedCfg.bACKIdx;
3207 ue->ul.betaCqiOffst = ueRecfg->puschDedCfg.bCQIIdx;
3208 ue->ul.betaRiOffst = ueRecfg->puschDedCfg.bRIIdx;*/
3211 if (ueRecfg->ueRecfgTypes & RGR_UE_ULTXANTSEL_RECFG)
3213 ue->ul.ulTxAntSel = ueRecfg->ulTxAntSel;
3215 if (ueRecfg->ueRecfgTypes & RGR_UE_CDBKSBST_RECFG)
3217 ue->mimoInfo.cdbkSbstRstrctn = ueRecfg->ueCodeBookRstRecfg;
3220 /* Commenting here to assign garbage value when it is not set in APP. */
3221 //ue->accessStratumRls = ueRecfg->accessStratumRls;
3222 return (cell->sc.apis->rgSCHRgrUeRecfg(cell, ue, ueRecfg, err));
3223 } /* rgSCHUtlRgrUeRecfg */
3226 * @brief This function deletes a service from scheduler
3230 * Function: rgSCHUtlFreeDlLc
3231 * Purpose: This function is made available through a FP for
3232 * making scheduler aware of a service being deleted from UE
3234 * Invoked by: BO and Scheduler
3236 * @param[in] RgSchCellCb* cell
3237 * @param[in] RgSchUeCb* ue
3238 * @param[in] RgSchDlLcCb* svc
3241 Void rgSCHUtlFreeDlLc(RgSchCellCb *cell,RgSchUeCb *ue,RgSchDlLcCb *svc)
3243 cell->sc.apis->rgSCHFreeDlLc(cell, ue, svc);
3245 /* Stack Crash problem for TRACE5 changes. added the return below . */
3251 * @brief UE deletion for scheduler
3255 * Function : rgSCHUtlFreeUe
3257 * This functions deletes all scheduler information
3258 * pertaining to a UE
3260 * @param[in] RgSchCellCb *cell
3261 * @param[in] RgSchUeCb *ue
3264 Void rgSCHUtlFreeUe(RgSchCellCb *cell,RgSchUeCb *ue)
3267 rgSCHUtlDelUeANFdbkInfo(ue,RGSCH_PCELL_INDEX);
3269 cell->sc.apis->rgSCHFreeUe(cell, ue);
3271 /* Stack Crash problem for TRACE5 changes. added the return below . */
3274 } /* rgSCHUtlFreeUe */
3277 * @brief This function updates the scheduler with service for a UE
3281 * Function: rgSCHUtlDlDedBoUpd
3282 * Purpose: This function should be called whenever there is a
3283 * change BO for a service.
3285 * Invoked by: BO and Scheduler
3287 * @param[in] RgSchCellCb* cell
3288 * @param[in] RgSchUeCb* ue
3289 * @param[in] RgSchDlLcCb* lc
3292 Void rgSCHUtlDlDedBoUpd(RgSchCellCb *cell,RgSchUeCb *ue,RgSchDlLcCb *lc)
3294 cell->sc.apis->rgSCHDlDedBoUpd(cell, ue, lc);
3298 * @brief Record MSG3 allocation into the UE
3302 * Function : rgSCHUtlRecMsg3Alloc
3304 * This function is invoked to update record msg3 allocation information
3305 * in the UE when UE is detected for RaCb
3307 * @param[in] RgSchCellCb *cell
3308 * @param[in] RgSchUeCb *ue
3309 * @param[in] RgSchRaCb *raCb
3312 Void rgSCHUtlRecMsg3Alloc(RgSchCellCb *cell,RgSchUeCb *ue,RgSchRaCb *raCb)
3314 cell->sc.apis->rgSCHUlRecMsg3Alloc(cell, ue, raCb);
3317 } /* rgSCHRecMsg3Alloc */
3321 * @brief Update harq process for allocation
3325 * Function : rgSCHUtlUpdUlHqProc
3327 * This function is invoked when harq process
3328 * control block is now in a new memory location
3329 * thus requiring a pointer/reference update.
3331 * @param[in] RgSchCellCb *cell
3332 * @param[in] RgSchUlHqProcCb *curProc
3333 * @param[in] RgSchUlHqProcCb *oldProc
3338 S16 rgSCHUtlUpdUlHqProc(RgSchCellCb *cell,RgSchUlHqProcCb *curProc,RgSchUlHqProcCb *oldProc)
3340 return (cell->sc.apis->rgSCHUpdUlHqProc(cell, curProc, oldProc));
3341 } /* rgSCHUtlUpdUlHqProc */
3344 * @brief UL grant for contention resolution
3348 * Function : rgSCHUtlContResUlGrant
3350 * Add UE to another queue specifically for CRNTI based contention
3353 * @param[in] RgSchCellCb *cell
3354 * @param[in] RgSchUeCb *ue
3355 * @param[out] RgSchErrInfo *err
3360 S16 rgSCHUtlContResUlGrant(RgSchCellCb *cell,RgSchUeCb *ue,RgSchErrInfo *err)
3363 ue->isMsg4PdcchWithCrnti = TRUE;
3364 return (cell->sc.apis->rgSCHContResUlGrant(cell, ue, err));
3365 } /* rgSCHUtlContResUlGrant */
3368 * @brief SR reception handling
3372 * Function : rgSCHUtlSrRcvd
3374 * - Handles SR reception for UE
3376 * @param[in] RgSchCellCb *cell
3377 * @param[in] RgSchUeCb *ue
3378 * @param[out] RgSchErrInfo *err
3383 S16 rgSCHUtlSrRcvd(RgSchCellCb *cell,RgSchUeCb *ue,CmLteTimingInfo frm,RgSchErrInfo *err)
3385 return (cell->sc.apis->rgSCHSrRcvd(cell, ue, frm, err));
3386 } /* rgSCHUtlSrRcvd */
3389 * @brief Short BSR update
3393 * Function : rgSCHUtlUpdBsrShort
3395 * This functions does requisite updates to handle short BSR reporting
3397 * @param[in] RgSchCellCb *cell
3398 * @param[in] RgSchUeCb *ue
3399 * @param[in] uint8_t lcgId
3400 * @param[in] uint8_t bsr
3401 * @param[out] RgSchErrInfo *err
3406 Void rgSCHUtlUpdBsrShort(RgSchCellCb *cell,RgSchUeCb *ue,uint8_t lcgId,uint8_t bsr,RgSchErrInfo *err)
3408 cell->sc.apis->rgSCHUpdBsrShort(cell, ue, &ue->ul.lcgArr[lcgId], bsr, err);
3410 } /* rgSCHUtlUpdBsrShort */
3414 * @brief Truncated BSR update
3418 * Function : rgSCHUtlUpdBsrTrunc
3420 * This functions does required updates to handle truncated BSR report
3423 * @param[in] RgSchCellCb *cell
3424 * @param[in] RgSchUeCb *ue
3425 * @param[in] uint8_t lcgId
3426 * @param[in] uint8_t bsr
3427 * @param[out] RgSchErrInfo *err
3432 Void rgSCHUtlUpdBsrTrunc(RgSchCellCb *cell,RgSchUeCb *ue,uint8_t lcgId,uint8_t bsr,RgSchErrInfo *err)
3434 cell->sc.apis->rgSCHUpdBsrTrunc(cell, ue, &ue->ul.lcgArr[lcgId], bsr, err);
3436 } /* rgSCHUtlUpdBsrTrunc */
3440 * @brief Long BSR update
3444 * Function : rgSCHUtlUpdBsrLong
3446 * - Update BSRs for all configured LCGs
3447 * - Update priority of LCGs if needed
3448 * - Update UE's position within/across uplink scheduling queues
3451 * @param[in] RgSchCellCb *cell
3452 * @param[in] RgSchUeCb *ue
3453 * @param[in] uint8_t bsr0
3454 * @param[in] uint8_t bsr1
3455 * @param[in] uint8_t bsr2
3456 * @param[in] uint8_t bsr3
3457 * @param[out] RgSchErrInfo *err
3462 Void rgSCHUtlUpdBsrLong(RgSchCellCb *cell,RgSchUeCb *ue,uint8_t bsr0,uint8_t bsr1,uint8_t bsr2,uint8_t bsr3,RgSchErrInfo *err)
3469 cell->sc.apis->rgSCHUpdBsrLong(cell, ue, bsArr, err);
3471 } /* rgSCHUtlUpdBsrLong */
3474 * @brief EXT PHR update
3478 * Function : rgSCHUtlUpdExtPhr
3480 * Updates extended power headroom info for a UE
3482 * @param[in] RgSchCellCb *cell
3483 * @param[in] RgSchUeCb *ue
3484 * @param[in] uint8_t phr
3485 * @param[out] RgSchErrInfo *err
3490 S16 rgSCHUtlUpdExtPhr(RgSchCellCb *cell,RgSchUeCb *ue,RgInfExtPhrCEInfo *extPhr,RgSchErrInfo *err)
3492 return (cell->sc.apis->rgSCHUpdExtPhr(cell, ue, extPhr, err));
3493 } /* rgSCHUtlUpdExtPhr */
3502 * Function : rgSCHUtlUpdPhr
3504 * Updates power headroom info for a UE
3506 * @param[in] RgSchCellCb *cell
3507 * @param[in] RgSchUeCb *ue
3508 * @param[in] uint8_t phr
3509 * @param[out] RgSchErrInfo *err
3514 S16 rgSCHUtlUpdPhr(RgSchCellCb *cell,RgSchUeCb *ue,uint8_t phr,RgSchErrInfo *err)
3516 return (cell->sc.apis->rgSCHUpdPhr(cell, ue, phr, err));
3517 } /* rgSCHUtlUpdPhr */
3521 * @brief Indication of UL CQI
3525 * Function : rgSCHUtlUlCqiInd
3527 * - Updates uplink CQI information for the UE. Computes and
3528 * stores the lowest CQI of CQIs reported in all subbands
3530 * @param[in] RgSchCellCb *cell
3531 * @param[in] RgSchUeCb *ue
3532 * @param[in] TfuUlCqiRpt *ulCqiInfo
3535 Void rgSCHUtlUlCqiInd(RgSchCellCb *cell,RgSchUeCb *ue,TfuUlCqiRpt *ulCqiInfo)
3537 cell->sc.apis->rgSCHUlCqiInd(cell, ue, ulCqiInfo);
3539 } /* rgSCHUtlUlCqiInd */
3542 * @brief Indication of PUCCH power adjustment
3546 * Function : rgSCHUtlPucchDeltaPwrInd
3548 * - Updates uplink CQI information for the UE. Computes and
3549 * stores the lowest CQI of CQIs reported in all subbands
3551 * @param[in] RgSchCellCb *cell
3552 * @param[in] RgSchUeCb *ue
3553 * @param[in] uint8_t delta
3556 Void rgSCHUtlPucchDeltaPwrInd(RgSchCellCb *cell,RgSchUeCb *ue,S8 delta)
3558 cell->sc.apis->rgSCHPucchDeltaPwrInd(cell, ue, delta);
3560 } /* rgSCHUtlPucchDeltaPwrInd */
3562 /* Start: LTEMAC_2.1_DEV_CFG */
3564 * @brief Ue Reset Request
3568 * Function : rgSCHUtlUeReset
3571 * @param[in] RgSchCellCb *cell
3572 * @param[in] RgSchUeCb *ue
3575 Void rgSCHUtlUeReset(RgSchCellCb *cell,RgSchUeCb *ue)
3578 cell->sc.apis->rgSCHUeReset(cell, ue);
3580 } /* rgSCHUtlUeReset */
3581 /* End: LTEMAC_2.1_DEV_CFG */
3584 * @brief Returns HARQ proc for which data expected now
3588 * Function: rgSCHUtlUlHqProcForUe
3589 * Purpose: This function returns the harq process for
3590 * which data is expected in the current slot.
3591 * It does not validate if the HARQ process
3592 * has an allocation.
3596 * @param[in] RgSchCellCb *cell
3597 * @param[in] CmLteTimingInfo frm
3598 * @param[in] RgSchUeCb *ue
3599 * @param[out] RgSchUlHqProcCb **procRef
3602 Void rgSCHUtlUlHqProcForUe(RgSchCellCb *cell,CmLteTimingInfo frm,RgSchUeCb *ue,RgSchUlHqProcCb **procRef)
3604 cell->sc.apis->rgSCHUlHqProcForUe(cell, frm, ue, procRef);
3606 /* Stack Crash problems for TRACE5 changes. added the return below */
3612 * @brief Returns first uplink allocation to send reception
3617 * Function: rgSCHUtlFirstRcptnReq(cell)
3618 * Purpose: This function returns the first uplink allocation
3619 * (or NULLP if there is none) in the slot
3620 * in which is expected to prepare and send reception
3625 * @param[in] RgSchCellCb *cell
3626 * @return RgSchUlAlloc*
3628 RgSchUlAlloc *rgSCHUtlFirstRcptnReq(RgSchCellCb *cell)
3630 return (cell->sc.apis->rgSCHFirstRcptnReq(cell));
3634 * @brief Returns first uplink allocation to send reception
3639 * Function: rgSCHUtlNextRcptnReq(cell)
3640 * Purpose: This function returns the next uplink allocation
3641 * (or NULLP if there is none) in the slot
3642 * in which is expected to prepare and send reception
3647 * @param[in] RgSchCellCb *cell
3648 * @return RgSchUlAlloc*
3650 RgSchUlAlloc *rgSCHUtlNextRcptnReq(RgSchCellCb *cell,RgSchUlAlloc *alloc)
3652 return (cell->sc.apis->rgSCHNextRcptnReq(cell, alloc));
3656 * @brief Returns first uplink allocation to send HARQ feedback
3661 * Function: rgSCHUtlFirstHqFdbkAlloc
3662 * Purpose: This function returns the first uplink allocation
3663 * (or NULLP if there is none) in the slot
3664 * in which it is expected to prepare and send HARQ
3669 * @param[in] RgSchCellCb *cell
3670 * @param[in] uint8_t idx
3671 * @return RgSchUlAlloc*
3673 RgSchUlAlloc *rgSCHUtlFirstHqFdbkAlloc(RgSchCellCb *cell,uint8_t idx)
3675 return (cell->sc.apis->rgSCHFirstHqFdbkAlloc(cell, idx));
3680 * @brief Returns next allocation to send HARQ feedback for
3684 * Function: rgSCHUtlNextHqFdbkAlloc(cell)
3685 * Purpose: This function returns the next uplink allocation
3686 * (or NULLP if there is none) in the slot
3687 * for which HARQ feedback needs to be sent.
3691 * @param[in] RgSchCellCb *cell
3692 * @return RgSchUlAlloc*
3694 RgSchUlAlloc *rgSCHUtlNextHqFdbkAlloc(RgSchCellCb *cell,RgSchUlAlloc *alloc,uint8_t idx)
3696 return (cell->sc.apis->rgSCHNextHqFdbkAlloc(cell, alloc, idx));
3699 /***********************************************************
3701 * Func : rgSCHUtlResetSfAlloc
3703 * Desc : Utility Function to Reset slot allocation information.
3712 **********************************************************/
3713 S16 rgSCHUtlResetSfAlloc(RgInfSfAlloc *sfAlloc,Bool resetCmnLcInfo,Bool restAlloc)
3715 if(TRUE == restAlloc)
3717 if(sfAlloc->ueInfo.numUes)
3719 memset(sfAlloc->ueInfo.allocInfo,0x00,
3720 (sizeof(RgInfUeAlloc)*sfAlloc->ueInfo.numUes));
3722 sfAlloc->ueInfo.numUes = 0;
3723 sfAlloc->rarInfo.numRaRntis = 0;
3724 sfAlloc->flowCntrlInfo.numUes = 0;
3726 if(TRUE == resetCmnLcInfo)
3728 sfAlloc->cmnLcInfo.bitMask = 0;
3733 /***********************************************************
3735 * Func : rgSCHUtlGetRlsHqAlloc
3737 * Desc : Utility Function to Allocate slot allocation information.
3746 **********************************************************/
3747 S16 rgSCHUtlGetRlsHqAlloc(RgSchCellCb *cell)
3750 Inst inst = cell->instIdx;
3751 for(idx=0; idx < RGSCH_NUM_SUB_FRAMES; idx++)
3753 cell->rlsHqArr[idx].cellId = cell->cellId;
3755 /* Allocating with additional location, to accommodate
3756 TA scheduling along with maximum no of UEs per SF */
3758 /* Allocate memory for "scheduled UE" Info */
3759 if((rgSCHUtlAllocSBuf(inst,
3760 (Data**)&(cell->rlsHqArr[idx].ueHqInfo),
3761 (sizeof(RgInfUeHqInfo)*RGSCH_MAX_UE_PER_DL_SF))) != ROK)
3763 DU_LOG("\nERROR --> SCH : Memory allocation FAILED for "
3773 /***********************************************************
3775 * Func : rgSCHUtlPutRlsHqAlloc
3777 * Desc : Utility Function to deallocate slot allocation information.
3786 **********************************************************/
3787 S16 rgSCHUtlPutRlsHqAlloc(RgSchCellCb *cell)
3790 Inst inst = cell->instIdx;
3792 for(idx=0; idx < RGSCH_NUM_SUB_FRAMES; idx++)
3794 /* Deallocate memory for "scheduled UE" Info */
3795 if (cell->rlsHqArr[idx].ueHqInfo != NULLP)
3797 /* Freeing with additional location, to accommodate TA
3798 scheduling along with maximum no of UEs per SF */
3799 /* ccpu00117052 - MOD - Passing double pointer
3800 for proper NULLP assignment*/
3801 rgSCHUtlFreeSBuf(inst,
3802 (Data **)(&(cell->rlsHqArr[idx].ueHqInfo)),
3803 (sizeof(RgInfUeHqInfo)*RGSCH_MAX_UE_PER_DL_SF));
3812 /***********************************************************
3814 * Func : rgSCHUtlGetSfAlloc
3816 * Desc : Utility Function to Allocate slot allocation information.
3825 **********************************************************/
3826 S16 rgSCHUtlGetSfAlloc(RgSchCellCb *cell)
3830 Inst inst = cell->instIdx;
3831 RgSchCmnUlCell *cellUl = RG_SCH_CMN_GET_UL_CELL(cell);
3834 for(idx=0; idx < RGSCH_SF_ALLOC_SIZE; idx++)
3836 for(idx=0; idx < RGSCH_NUM_SUB_FRAMES; idx++)
3839 cell->sfAllocArr[idx].cellId = cell->cellId;
3841 /* Allocating with additional location, to accommodate
3842 TA scheduling along with maximum no of UEs per SF */
3844 /* Allocate memory for "scheduled UE" Info */
3845 if((rgSCHUtlAllocSBuf(inst,
3846 (Data**)&(cell->sfAllocArr[idx].ueInfo.allocInfo),
3847 (sizeof(RgInfUeAlloc)*RGSCH_MAX_UE_PER_DL_SF))) != ROK)
3849 DU_LOG("\nERROR --> SCH : Memory allocation FAILED for "
3854 /* Allocate memory for "scheduled RAR" Info */
3855 if((rgSCHUtlAllocSBuf(inst,
3856 (Data**)&(cell->sfAllocArr[idx].rarInfo.raRntiInfo),
3857 (sizeof(RgInfRaRntiInfo)*RGSCH_MAX_RARNTI_PER_DL_SF))) != ROK)
3859 DU_LOG("\nERROR --> SCH : Memory allocation FAILED for "
3863 for(indx = 0; indx < RGSCH_MAX_RARNTI_PER_DL_SF; indx++)
3865 if((rgSCHUtlAllocSBuf(inst,
3866 (Data**)&(cell->sfAllocArr[idx].rarInfo.raRntiInfo[indx].crntiInfo),
3867 (sizeof(RgInfCrntiInfo)* (cellUl->maxMsg3PerUlSf)))) != ROK)
3869 DU_LOG("\nERROR --> SCH : Memory allocation FAILED for "
3878 rgSCHEmtcUtlGetSfAlloc(cell);
3885 /***********************************************************
3887 * Func : rgSCHUtlPutSfAlloc
3889 * Desc : Utility Function to deallocate slot allocation information.
3898 **********************************************************/
3899 S16 rgSCHUtlPutSfAlloc(RgSchCellCb *cell)
3903 Inst inst = cell->instIdx;
3904 RgSchCmnUlCell *cellUl = RG_SCH_CMN_GET_UL_CELL(cell);
3907 for(idx=0; idx < RGSCH_SF_ALLOC_SIZE; idx++)
3909 for(idx=0; idx < RGSCH_NUM_SUB_FRAMES; idx++)
3912 if (cell->sfAllocArr[idx].rarInfo.raRntiInfo != NULLP)
3914 for(indx = 0; indx < RGSCH_MAX_RARNTI_PER_DL_SF; indx++)
3916 if (cell->sfAllocArr[idx].rarInfo.raRntiInfo[indx].crntiInfo != NULLP)
3917 /* ccpu00117052 - MOD - Passing double pointer
3918 for proper NULLP assignment*/
3919 rgSCHUtlFreeSBuf(inst,
3920 (Data**)(&(cell->sfAllocArr[idx].rarInfo.raRntiInfo[indx].\
3922 (sizeof(RgInfCrntiInfo)* (cellUl->maxMsg3PerUlSf)));
3924 /* Deallocate memory for "scheduled RAR" Info */
3925 /* ccpu00117052 - MOD - Passing double pointer
3926 for proper NULLP assignment*/
3927 rgSCHUtlFreeSBuf(inst,
3928 (Data**)(&(cell->sfAllocArr[idx].rarInfo.raRntiInfo)),
3929 (sizeof(RgInfRaRntiInfo)*RGSCH_MAX_RARNTI_PER_DL_SF));
3931 /* Deallocate memory for "scheduled UE" Info */
3932 if (cell->sfAllocArr[idx].ueInfo.allocInfo != NULLP)
3934 /* Freeing with additional location, to accommodate TA
3935 scheduling along with maximum no of UEs per SF */
3936 /* ccpu00117052 - MOD - Passing double pointer
3937 for proper NULLP assignment*/
3938 rgSCHUtlFreeSBuf(inst,
3939 (Data**)(&(cell->sfAllocArr[idx].ueInfo.allocInfo)),
3940 (sizeof(RgInfUeAlloc)*RGSCH_MAX_UE_PER_DL_SF));
3945 rgSCHEmtcUtlPutSfAlloc(cell);
3951 /***********************************************************
3953 * Func : rgSCHUtlAllocSBuf
3955 * Desc : Utility Function to Allocate static buffer.
3956 * Memory allocated is assumed contiguous.
3962 * Notes: Caller doesnt need to raise the alarm in case of memory
3963 * allocation gets failed.
3967 **********************************************************/
3968 S16 rgSCHUtlAllocSBuf
3970 Inst inst, /* Instance of the invoking scheduler */
3971 Data **pData, /* Pointer of the data to be returned */
3972 Size size /* size */
3975 /* Moving alarm diagnostics to available scope */
3977 /* Initialize the param to NULLP */
3980 /* May not be necessary for data performance path */
3988 /* allocate buffer */
3989 #ifdef MS_MBUF_CORRUPTION /* Should be enabled when debugging mbuf corruption */
3990 MS_BUF_ADD_ALLOC_CALLER();
3992 if (SGetSBuf(rgSchCb[inst].rgSchInit.region, rgSchCb[inst].rgSchInit.pool,
3993 pData, size) != ROK)
3995 RgUstaDgn dgn; /* Alarm diagnostics structure */
3996 dgn.type = LRG_USTA_DGNVAL_MEM;
3997 dgn.u.mem.region = rgSchCb[inst].rgSchInit.region;
3998 dgn.u.mem.pool = rgSchCb[inst].rgSchInit.pool;
3999 /* Send an alarm to Layer Manager */
4000 rgSCHLmmStaInd(inst, LCM_CATEGORY_RESOURCE, LCM_EVENT_SMEM_ALLOC_FAIL,
4001 LCM_CAUSE_MEM_ALLOC_FAIL, &dgn);
4002 DU_LOG("\nERROR --> SCH : Unable to Allocate the Buffer");
4007 /* zero out the allocated memory */
4008 memset(*pData, 0x00, size);
4012 } /* end of rgSCHUtlAllocSBuf */
4017 * Fun: rgSCHUtlFreeSBuf
4019 * Desc: The argument to rgSCHUtlFreeSBuf() is a pointer to a block
4020 * previously allocated by rgSCHUtlAllocSBuf() and size. It
4021 * deallocates the memory.
4028 Void rgSCHUtlFreeSBuf
4030 Inst inst, /* Instance of the invoking scheduler */
4031 Data **data, /* pointer to data */
4032 Size size /* size */
4038 if ((data == NULLP) || (*data == NULLP) || (size == 0))
4044 #ifdef MS_MBUF_CORRUPTION /* Should be enabled when debugging mbuf corruption */
4045 MS_BUF_ADD_CALLER();
4047 /* Deallocate buffer */
4048 ret = SPutSBuf(rgSchCb[inst].rgSchInit.region,
4049 rgSchCb[inst].rgSchInit.pool, (*data), size);
4053 DU_LOG("\nERROR --> SCH : rgSCHUtlFreeSBuf failed");
4057 /* ccpu00117052 - ADD - Assigning the pointer to NULLP */
4061 } /* end of rgSCHUtlFreeSBuf */
4067 * Fun: rgSCHUtlFreeWarningSiSeg
4069 * Desc: This is used to deallocate Warning SI Seg.
4077 Void rgSCHUtlFreeWarningSiSeg(Region reg,Pool pool,CmLListCp *siPduLst)
4082 while (siPduLst->first != NULLP)
4084 node = siPduLst->first;
4085 pdu = (Buffer *)node->node;
4086 cmLListDelFrm(siPduLst, node);
4087 RGSCH_FREE_MSG(pdu);
4088 SPutSBuf(reg, pool, (Data *)node,sizeof(CmLList));
4093 } /* end of rgSCHUtlFreeWarningSiSeg */
4098 * Fun: rgSCHUtlFreeWarningSiPdu
4100 * Desc: This is used to deallocate Warning SI PDU.
4108 Void rgSCHUtlFreeWarningSiPdu(RgSchCellCb *cell)
4112 RgSchWarningSiInfo *warningSi;
4113 RgSchWarningSiPdu *warningSiPdu;
4115 warningSi = (RgSchWarningSiInfo *) cell->siCb.\
4116 siArray[cell->siCb.siCtx.siId-1].si;
4117 /* ccpu00136659: CMAS ETWS design changes */
4118 CM_LLIST_FIRST_NODE(&warningSi->warningSiMsg.segLstCp, node);
4124 warningSiPdu = (RgSchWarningSiPdu *)node->node;
4125 pdu = warningSiPdu->pdu;
4126 /* ccpu00136659: CMAS ETWS design changes */
4127 cmLListDelFrm(&warningSi->warningSiMsg.segLstCp, node);
4128 RGSCH_FREE_MSG(pdu);
4129 if(warningSi->warningSiMsg.segLstCp.count == 0)
4131 /* ccpu00136659: CMAS ETWS design changes */
4132 cell->siCb.siArray[cell->siCb.siCtx.siId-1].si = NULLP;
4133 rgSCHUtlRgrWarningSiCfgCfm(cell->instIdx,
4134 rgSchCb[cell->instIdx].rgrSap->sapCfg.spId,
4135 cell->siCb.warningSi[warningSi->idx].siId,
4136 warningSi->warningSiMsg.transId, RGR_CFG_CFM_TX_COMPLETE);
4141 } /* end of rgSCHUtlFreeWarningSiPdu */
4146 * Fun: rgSCHUtlGetWarningSiPdu
4148 * Desc: This is used to get Warning SI PDU for Scheduling.
4156 Buffer *rgSCHUtlGetWarningSiPdu(RgSchCellCb *cell)
4158 RgSchWarningSiInfo *warningSi;
4159 RgSchWarningSiPdu *warningSiPdu;
4163 warningSi = (RgSchWarningSiInfo *) cell->siCb.
4164 siArray[cell->siCb.siCtx.siId-1].si;
4165 /* ccpu00136659: CMAS ETWS design changes */
4166 CM_LLIST_FIRST_NODE(&warningSi->warningSiMsg.segLstCp, node);
4169 warningSiPdu = (RgSchWarningSiPdu *)node->node;
4170 pdu = warningSiPdu->pdu;
4177 } /* rgSCHUtlGetWarningSiPdu */
4182 * Fun: rgSCHUtlGetMcsAndNPrb
4184 * Desc: This is used to get mcs and nPrb value.
4192 S16 rgSCHUtlGetMcsAndNPrb(RgSchCellCb *cell,uint8_t *nPrb,uint8_t *mcs,MsgLen *msgLen)
4194 RgSchWarningSiInfo *warningSi;
4195 RgSchWarningSiPdu *warningSiPdu;
4198 if(cell->siCb.siCtx.warningSiFlag == FALSE)
4200 *mcs = cell->siCb.crntSiInfo.siInfo[cell->siCb.siCtx.siId-1].mcs;
4201 *nPrb = cell->siCb.crntSiInfo.siInfo[cell->siCb.siCtx.siId-1].nPrb;
4202 *msgLen = cell->siCb.crntSiInfo.siInfo[cell->siCb.siCtx.siId-1].msgLen;
4206 warningSi = (RgSchWarningSiInfo *) cell->siCb.
4207 siArray[cell->siCb.siCtx.siId-1].si;
4208 /* ccpu00136659: CMAS ETWS design changes */
4209 CM_LLIST_FIRST_NODE(&warningSi->warningSiMsg.segLstCp, node);
4215 warningSiPdu = (RgSchWarningSiPdu *)node->node;
4216 *mcs = warningSiPdu->mcs;
4217 *nPrb = warningSiPdu->nPrb;
4218 *msgLen = warningSiPdu->msgLen;
4223 } /* rgSCHUtlGetMcsAndNPrb */
4227 * Fun: rgSCHUtlCalMacAndPrb
4229 * Desc: This is used to Calculate mcs and nPrb value for SIB1 and SIs.
4237 S16 rgSCHUtlCalMcsAndNPrb(RgSchCellCb *cell,uint8_t cfgType,MsgLen msgLen,uint8_t siId)
4242 /*Get the nPrb and mcs parametr values */
4243 if (rgSCHUtlGetAllwdCchTbSz(msgLen*8, &nPrb, &mcs) != (msgLen*8))
4245 DU_LOG("\nERROR --> SCH : msgLen does "
4246 "not match any valid TB Size");
4251 if(cfgType == RGR_SI_CFG_TYPE_SIB1 || cfgType == RGR_SI_CFG_TYPE_SIB1_PWS)
4254 if(cell->siCb.crntSiInfo.sib1Info.sib1 == NULLP)
4256 cell->siCb.crntSiInfo.sib1Info.mcs = mcs;
4257 cell->siCb.crntSiInfo.sib1Info.nPrb = nPrb;
4258 cell->siCb.crntSiInfo.sib1Info.msgLen = msgLen;
4262 cell->siCb.newSiInfo.sib1Info.mcs = mcs;
4263 cell->siCb.newSiInfo.sib1Info.nPrb= nPrb;
4264 cell->siCb.newSiInfo.sib1Info.msgLen = msgLen;
4269 if(cfgType == RGR_SI_CFG_TYPE_SI)
4271 if(cell->siCb.crntSiInfo.siInfo[siId-1].si == NULLP &&
4272 !(cell->siCb.siBitMask & RGSCH_SI_SICFG_UPD))
4274 cell->siCb.crntSiInfo.siInfo[siId-1].mcs = mcs;
4275 cell->siCb.crntSiInfo.siInfo[siId-1].nPrb = nPrb;
4276 cell->siCb.crntSiInfo.siInfo[siId-1].msgLen = msgLen;
4280 cell->siCb.newSiInfo.siInfo[siId-1].mcs = mcs;
4281 cell->siCb.newSiInfo.siInfo[siId-1].nPrb= nPrb;
4282 cell->siCb.newSiInfo.siInfo[siId-1].msgLen = msgLen;
4286 if(cfgType == RGR_SI_CFG_TYPE_SIB8_CDMA)
4288 cell->siCb.crntSiInfo.siInfo[siId-1].mcs = mcs;
4289 cell->siCb.crntSiInfo.siInfo[siId-1].nPrb = nPrb;
4290 cell->siCb.crntSiInfo.siInfo[siId-1].msgLen = msgLen;
4297 /***********************************************************
4299 * Func : rgSCHUtlFillDgnParams
4301 * Desc : Utility Function to Fill Diagonostic params.
4309 **********************************************************/
4310 Void rgSCHUtlFillDgnParams(Inst inst,RgUstaDgn *dgn,uint8_t dgnType)
4315 case LRG_USTA_DGNVAL_MEM:
4316 dgn->type = (uint8_t) LRG_USTA_DGNVAL_MEM;
4317 dgn->u.mem.region = rgSchCb[inst].rgSchInit.region;
4318 dgn->u.mem.pool = rgSchCb[inst].rgSchInit.pool;
4326 } /* end of rgSCHUtlFillDgnParams */
4328 /***********************************************************
4330 * Func : rgSCHUtlGetPstToLyr
4332 * Desc : Utility Function to get the pst structure to post a message to MAC
4338 * Notes: This function should be called while sending a msg from
4339 * scheduler instance to MAC
4343 **********************************************************/
4344 Void rgSCHUtlGetPstToLyr(Pst *pst,RgSchCb *schCb,Inst macInst)
4347 /* Only the needed params are filled */
4348 pst->region = schCb->rgSchInit.region;
4349 pst->pool = schCb->rgSchInit.pool;
4350 pst->srcInst = schCb->rgSchInit.inst+SCH_INST_START;
4351 pst->srcProcId = schCb->rgSchInit.procId;
4352 pst->dstProcId = schCb->rgSchInit.procId;
4354 pst->dstInst = macInst;
4355 pst->dstEnt = ENTMAC;
4356 pst->srcEnt = ENTMAC;
4358 pst->prior = PRIOR0;
4360 pst->route = RTESPEC;
4363 } /* end of rgSCHUtlGetPstToLyr */
4365 /** @brief This function fills in the common lc information to be sent to MAC
4369 * Function: rgSCHUtlFillRgInfCmnLcInfo
4370 * @param RgSchDlSf *sf,
4371 * @param RgInfSfAlloc *sfAlloc,
4372 * @param CmLteLcId lcId,
4373 * @param Bool sendInd
4379 S16 rgSCHUtlFillRgInfCmnLcInfo(RgSchDlSf *sf,RgInfSfAlloc *sfAlloc,CmLteLcId lcId,Bool sendInd)
4382 if((sf->bch.tbSize)&&
4383 !(sfAlloc->cmnLcInfo.bitMask & RGINF_BCH_INFO))
4386 sfAlloc->cmnLcInfo.bchInfo.lcId = lcId;
4388 sfAlloc->cmnLcInfo.bitMask |= RGINF_BCH_INFO;
4390 else if((sf->bcch.pdcch != NULLP)&&
4391 !(sfAlloc->cmnLcInfo.bitMask & RGINF_BCCH_INFO))
4393 sfAlloc->cmnLcInfo.bcchInfo.rnti = RGSCH_SI_RNTI;
4394 rgSCHUtlFillPdschDciInfo(&(sfAlloc->cmnLcInfo.bcchInfo.dciInfo),
4395 &(sf->bcch.pdcch->dci));
4397 sfAlloc->cmnLcInfo.bcchInfo.lcId = lcId;
4398 sfAlloc->cmnLcInfo.bcchInfo.sndStatInd = sendInd;
4400 sfAlloc->cmnLcInfo.bitMask |= RGINF_BCCH_INFO;
4402 else if((sf->pcch.pdcch != NULLP) &&
4403 !(sfAlloc->cmnLcInfo.bitMask & RGINF_PCCH_INFO))
4405 sfAlloc->cmnLcInfo.pcchInfo.rnti = RGSCH_P_RNTI;
4406 rgSCHUtlFillPdschDciInfo(&(sfAlloc->cmnLcInfo.pcchInfo.dciInfo),
4407 &(sf->pcch.pdcch->dci));
4408 sfAlloc->cmnLcInfo.pcchInfo.lcId = lcId;
4409 sfAlloc->cmnLcInfo.bitMask |= RGINF_PCCH_INFO;
4414 /** @brief This function fills in the RAR information to be sent to MAC
4418 * Function: rgSCHUtlFillRgInfRarInfo
4420 * @param RgSchCellCb *cell
4421 * @param RgSchDlSf *sf
4422 * @param RgInfSfAlloc *sfAlloc
4427 S16 rgSCHUtlFillRgInfRarInfo(RgSchDlSf *sf,RgInfSfAlloc *sfAlloc,RgSchCellCb *cell)
4434 RgInfRaRntiInfo *raRntiAlloc;
4436 RgSchCmnDlCell *cellDl = RG_SCH_CMN_GET_DL_CELL(cell);
4439 noRaRsps = RGSCH_MAX_TDD_RA_RSP_ALLOC;
4441 noRaRsps = RGSCH_MAX_RA_RSP_ALLOC;
4444 for(idx =0; idx < noRaRsps; idx++)
4446 if (sf->raRsp[idx].pdcch == NULLP)
4448 /* No further raResp Allocations. */
4451 /* Added Dl TB count for RACH Response transmission*/
4453 cell->dlUlTbCnt.tbTransDlTotalCnt++;
4455 raRntiAlloc = &(sfAlloc->rarInfo.raRntiInfo[idx]);
4456 raRntiAlloc->raRnti = sf->raRsp[idx].raRnti;
4457 raRntiAlloc->schdTbSz = sf->raRsp[idx].tbSz;
4458 raRntiAlloc->numCrnti = 0;
4459 rgSCHUtlFillPdschDciInfo(&(raRntiAlloc->dciInfo),
4460 &(sf->raRsp[idx].pdcch->dci));
4461 /* RACHO : fill backoff indicator information */
4462 raRntiAlloc->backOffInd = sf->raRsp[idx].backOffInd;
4464 /* Fill for contention free UEs*/
4465 lnkLst = &(sf->raRsp[idx].contFreeUeLst);
4466 CM_LLIST_FIRST_NODE(lnkLst, tmp);
4469 ue = (RgSchUeCb *)tmp->node;
4471 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].tmpCrnti = ue->ueId;
4472 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].isContFree = TRUE;
4473 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].rapId = ue->ul.rarGrnt.rapId;
4474 #ifndef MAC_5GTF_UPDATE
4475 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.hop =
4477 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.cqiBit =
4478 ue->ul.rarGrnt.cqiReqBit;
4480 /* SHASHAHNK ADD RIV CALC */
4481 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.rbStart =
4482 ue->ul.rarGrnt.rbStart;
4483 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.numRb =
4484 ue->ul.rarGrnt.numRb;
4485 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.tpc =
4487 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.iMcsCrnt =
4488 ue->ul.rarGrnt.iMcsCrnt;
4489 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].ta = ue->ul.rarGrnt.ta;
4490 raRntiAlloc->numCrnti++;
4491 cmLListDelFrm(lnkLst, &ue->ul.rarGrnt.raRspLnk);
4492 ue->ul.rarGrnt.raRspLnk.node = (PTR)NULLP;
4494 /* Fill for contention based UEs*/
4495 lnkLst = &(sf->raRsp[idx].raRspLst);
4497 CM_LLIST_FIRST_NODE(lnkLst, tmp);
4499 while((NULLP != tmp) && ((RgSchRaCb *)tmp->node != NULLP))
4501 raCb = (RgSchRaCb *)tmp->node;
4503 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].tmpCrnti = raCb->tmpCrnti;
4504 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].isContFree = FALSE;
4505 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].rapId = raCb->rapId;
4506 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].ta.pres = TRUE;
4507 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].ta.val = raCb->ta.val;
4508 #ifndef MAC_5GTF_UPDATE
4509 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.hop =
4511 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.cqiBit = FALSE;
4513 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.rbStart =
4514 raCb->msg3Grnt.rbStart;
4515 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.numRb =
4516 raCb->msg3Grnt.numRb;
4517 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.tpc =
4519 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.iMcsCrnt =
4520 raCb->msg3Grnt.iMcsCrnt;
4521 raRntiAlloc->crntiInfo[raRntiAlloc->numCrnti].grnt.delayBit =
4522 raCb->msg3Grnt.delayBit;
4523 /* For initial attaching UEs Aperiodic CQI need not be triggered */
4524 raRntiAlloc->numCrnti++;
4525 /* Search the next node */
4526 CM_LLIST_NEXT_NODE(lnkLst, tmp);
4529 sfAlloc->rarInfo.numRaRntis = idx;
4530 /* ccpu00132314-ADD-Update the tx power allocation info
4531 TODO-Need to add a check for max tx power per symbol */
4532 sfAlloc->rarInfo.txPwrOffset = cellDl->rarTxPwrOffset;
4535 } /* end of rgSCHUtlFillRgInfRarInfo */
4537 /** @brief This function fills in the pdsch data related allocation Info
4538 * from the pdcch DCI info.
4543 * Function: rgSCHUtlFillPdschDciInfo
4546 * - Depending upon the DCI Format, fill the appropriate fields.
4548 * @param [out] TfuPdschDciInfo *pdschDci
4549 * @param [in] TfuDciInfo *pdcchDci
4554 S16 rgSCHUtlFillPdschDciInfo(TfuPdschDciInfo *pdsch,TfuDciInfo *pdcchDci)
4560 pdsch->format = pdcchDci->dciFormat;
4561 switch(pdcchDci->dciFormat)
4563 case TFU_DCI_FORMAT_1:
4564 pdsch->u.format1AllocInfo = pdcchDci->u.format1Info.allocInfo;
4566 case TFU_DCI_FORMAT_1A:
4567 if (pdcchDci->u.format1aInfo.isPdcchOrder == FALSE)
4569 pdsch->u.format1aAllocInfo = pdcchDci->u.format1aInfo.t.pdschInfo.allocInfo;
4572 case TFU_DCI_FORMAT_1B:
4573 pdsch->u.format1bAllocInfo = pdcchDci->u.format1bInfo.allocInfo;
4575 case TFU_DCI_FORMAT_1C:
4576 pdsch->u.format1cAllocInfo = pdcchDci->u.format1cInfo;
4578 case TFU_DCI_FORMAT_1D:
4579 pdsch->u.format1dAllocInfo = pdcchDci->u.format1dInfo.allocInfo;
4581 case TFU_DCI_FORMAT_2:
4582 pdsch->u.format2AllocInfo = pdcchDci->u.format2Info.allocInfo;
4584 case TFU_DCI_FORMAT_2A:
4585 pdsch->u.format2AAllocInfo = pdcchDci->u.format2AInfo.allocInfo;
4588 case TFU_DCI_FORMAT_B1:
4589 pdsch->u.formatB1Info = pdcchDci->u.formatB1Info;
4591 case TFU_DCI_FORMAT_B2:
4592 pdsch->u.formatB2Info = pdcchDci->u.formatB2Info;
4597 ret = rgSCHEmtcUtlFillPdschDciInfo(pdsch, pdcchDci);
4609 /* LTE_ADV_FLAG_REMOVED_START */
4611 * @brief This function resets temporary variables in Pool
4614 * Function: rgSchSFRResetPoolVariables
4616 * Invoked by: rgSCHSFRUtlTotalPoolInit
4618 * @param[in] RgSchCellCb* cell
4619 * @param[in] RgSubFrm* subFrm
4623 Void rgSchDSFRPwrCheck(RgSchDlSf *sf,Bool *isAllUePwrHigh)
4625 RgSchSFRPoolInfo *sfrCCPool;
4630 l = &sf->sfrTotalPoolInfo.ccPool;
4631 n = cmLListFirst(l);
4634 sfrCCPool = (RgSchSFRPoolInfo*)n->node;
4635 if((sfrCCPool->poolstartRB == sfrCCPool->pwrHiCCRange.startRb) &&
4636 (sfrCCPool->poolendRB == sfrCCPool->pwrHiCCRange.endRb))
4643 *isAllUePwrHigh = TRUE;
4650 /* LTE_ADV_FLAG_REMOVED_END */
4651 /***********************************************************
4653 * Func : rgSCHUtlFillRgInfTbInfo
4655 * Desc : Utility Function to fill the allocation info of each Tb
4661 * Notes: This function should be called while sending a msg from
4662 * scheduler instance to MAC
4666 **********************************************************/
4667 static Void rgSCHUtlFillRgInfTbInfo(RgSchDlHqProcCb *hqP,RgInfUeAlloc *allocInfo,RgSchCellCb *cell)
4671 RgInfUeTbInfo *tbInfo;
4673 /* LTE_ADV_FLAG_REMOVED_START */
4675 static uint32_t tmpCnt = 0;
4676 Bool isAllUePwrHigh = FALSE;
4678 /* LTE_ADV_FLAG_REMOVED_END */
4679 RgSchDlLcCb *dlLcCb = NULLP;
4680 uint16_t rlcHdrEstmt;
4684 uint8_t prbUsed = 0;
4688 CmLteTimingInfo frm;
4690 /* Get Downlink slot */
4691 frm = cell->crntTime;
4692 RGSCH_INCR_SUB_FRAME(frm, RG_SCH_CMN_DL_DELTA);
4693 sf = rgSCHUtlSubFrmGet(cell, frm);
4694 /* Setting of fillCtrlPdu flag
4695 If both P-cell and S-cell are present,
4696 make TRUE for P-cell and FALSE for all s-cells
4697 For all other cases set TRUE */
4699 if ((rgSchCb[cell->instIdx].genCfg.forceCntrlSrbBoOnPCel) &&
4700 !RG_SCH_CMN_IS_PCELL_HQP(hqP))
4702 allocInfo->fillCtrlPdu = FALSE;
4706 allocInfo->fillCtrlPdu = TRUE;
4710 allocInfo->tbStrtIdx = -1;
4714 allocInfo->tbReqInfo.sCellHqPId = 0xff;
4715 rgSCHLaaHndlFillRgInfTbInfo(cell, hqP, allocInfo);
4718 /*TODO:REEMA: Check and fill the isRetx */
4719 for(tbCnt = 0; tbCnt < 2; tbCnt++)
4721 RgSchUeCb *ue = NULLP;
4722 /*Changed as a result of CR timer*/
4723 if ((hqP->hqE->ue != NULLP)/* &&
4724 ((hqP->tbInfo[tbCnt].lchSchdData[0].lcId != 0) || \
4725 (hqP->tbInfo[tbCnt].schdTa.pres == PRSNT_NODEF))*/)
4728 allocInfo->rnti = ue->ueId;
4729 allocInfo->doa = hqP->hqE->ue->mimoInfo.doa;
4730 allocInfo->txMode = (TfuTxMode)(hqP->hqE->ue->mimoInfo.txMode);
4731 allocInfo->puschRptUsd = hqP->hqE->ue->mimoInfo.puschFdbkVld;
4732 allocInfo->puschPmiInfo = hqP->hqE->ue->mimoInfo.puschPmiInfo;
4733 if(hqP->tbInfo[tbCnt].schdTa.pres == PRSNT_NODEF)
4735 hqP->tbInfo[tbCnt].taSnt = TRUE;
4738 if (RG_SCH_IS_PAPRSNT(ue,hqP->hqE->cell))
4740 /*update pA value */
4741 allocInfo->pa = (RG_SCH_CMN_GET_PA(ue,hqP->hqE->cell)).val;
4745 /* LTE_ADV_FLAG_REMOVED_START */
4746 /* If ABS is enabled, calculate resource used */
4747 if((0 == tbCnt) && (RGR_ENABLE == ue->cell->lteAdvCb.absCfg.status))
4749 /* For Macro count number resource used in Non-ABS SF */
4750 if(RGR_ABS_MUTE == ue->cell->lteAdvCb.absCfg.absPatternType)
4752 if(RG_SCH_ABS_ENABLED_NONABS_SF == ue->cell->lteAdvCb.absDlSfInfo)
4754 ue->cell->lteAdvCb.absLoadInfo[ue->cell->lteAdvCb.absPatternDlIdx]+=
4755 hqP->tbInfo[tbCnt].dlGrnt.numRb;
4758 /* For pico count number resource used in ABS SF for ABS UE */
4759 else if(RGR_ABS_TRANSMIT == ue->cell->lteAdvCb.absCfg.absPatternType)
4761 if(RG_SCH_ABS_ENABLED_ABS_SF == ue->cell->lteAdvCb.absDlSfInfo)
4763 if(TRUE == ue->lteAdvUeCb.rgrLteAdvUeCfg.isAbsUe)
4765 ue->cell->lteAdvCb.absLoadInfo[ue->cell->lteAdvCb.absPatternDlIdx]+=
4766 hqP->tbInfo[tbCnt].dlGrnt.numRb;
4773 /*if SFR is enabled*/
4774 allocInfo->isEnbSFR = (uint8_t)RG_SCH_CMN_IS_SFR_ENB(ue->cell); /* KW fix for LTE_ADV */
4775 if((ue->cell->lteAdvCb.dsfrCfg.status == RGR_ENABLE) &&
4776 (ue->lteAdvUeCb.rgrLteAdvUeCfg.isUeCellEdge == FALSE))
4778 rgSchDSFRPwrCheck(sf, &isAllUePwrHigh);
4782 allocInfo->pa = (uint8_t)ue->cell->lteAdvCb.sfrCfg.pwrThreshold.pHigh; /* KW fix for LTE_ADV */
4783 if(tmpCnt++ == 100000)
4785 DU_LOG("\nDEBUG --> SCH : DSFR::ll UEs can go HIGH, PHigh(%d) for UE(%d)",allocInfo->pa, ue->ueId);
4791 if (allocInfo->isEnbSFR)
4793 /*Update pA to Plow if it is cell-centred ,else pA will be pHigh*/
4794 if (ue->lteAdvUeCb.rgrLteAdvUeCfg.isUeCellEdge == TRUE)
4796 allocInfo->pa = ue->cell->lteAdvCb.sfrCfg.pwrThreshold.pHigh;
4797 if(tmpCnt++ == 100000)
4799 DU_LOG("\nDEBUG --> SCH : SFR::UE is CELL EDGE, PHigh(%d) for UE(%d)",allocInfo->pa, ue->ueId);
4806 if(TRUE == ue->lteAdvUeCb.isCCUePHigh)
4808 allocInfo->pa = ue->cell->lteAdvCb.sfrCfg.pwrThreshold.pHigh;
4809 ue->lteAdvUeCb.isCCUePHigh = FALSE;
4813 allocInfo->pa = ue->cell->lteAdvCb.sfrCfg.pwrThreshold.pLow;
4814 if(tmpCnt++ == 100000)
4816 DU_LOG("\nDEBUG --> SCH : SFR::UE is CELL CENTRE, PLow(%d) for UE(%d)\n",allocInfo->pa, ue->ueId);
4823 /* LTE_ADV_FLAG_REMOVED_END */
4831 RgSchCmnDlCell *cellDl = RG_SCH_CMN_GET_DL_CELL(cell);
4834 allocInfo->pdcchRnti = hqP->hqE->raCb->tmpCrnti;
4836 allocInfo->rnti = hqP->hqE->raCb->tmpCrnti;
4838 /*ccpu00132314-ADD-Use a default pA value
4840 allocInfo->pa = cellDl->msg4pAVal;
4844 /* If TB Is scheduled for this SF */
4845 if(hqP->tbInfo[tbCnt].state == HQ_TB_WAITING)
4847 if (allocInfo->tbStrtIdx == -1){
4848 allocInfo->tbStrtIdx = tbCnt;
4850 rgSCHUtlFillPdschDciInfo(&(allocInfo->dciInfo),
4851 &(hqP->pdcch->dci));
4855 rgSCHUtlFillPdschDciInfo(&(allocInfo->dciInfo),
4856 &(hqP->pdcch->dci));
4858 else if ((ue) && (ue->dl.spsOccPdcch.rnti == ue->spsRnti))
4860 rgSCHUtlFillPdschDciInfo(&(allocInfo->dciInfo),
4861 &(ue->dl.spsOccPdcch.dci));
4863 #endif /* ifndef LTEMAC_SPS */
4868 allocInfo->pdcchRnti = hqP->pdcch->rnti;
4872 allocInfo->pdcchRnti = ue->spsRnti;
4875 tbInfo = &(allocInfo->tbInfo[tbCnt]);
4876 allocInfo->nmbOfTBs++;
4877 allocInfo->hqProcId = hqP->procId;
4878 allocInfo->tbInfo[tbCnt].schdTbSz = hqP->tbInfo[tbCnt].tbSz;
4880 tbInfo->disTb = FALSE;
4881 if(!(hqP->tbInfo[tbCnt].txCntr))
4884 if(!((rgSCHLaaCheckIfLAAProc(hqP)) && (TRUE ==
4885 rgSCHLaaSCellEnabled(cell))))
4888 hqP->tbInfo[tbCnt].txCntr++;
4890 for(idx = 0; idx < hqP->tbInfo[tbCnt].numLch; idx++)
4892 tbInfo->schdDat[idx].lcId =\
4893 hqP->tbInfo[tbCnt].lchSchdData[idx].lcId;
4894 tbInfo->schdDat[idx].numBytes =\
4895 hqP->tbInfo[tbCnt].lchSchdData[idx].schdData;
4898 lcId = hqP->tbInfo[tbCnt].lchSchdData[idx].lcId;
4901 dlLcCb = hqP->hqE->ue->dl.lcCb[lcId-1];
4904 RG_SCH_CMN_DL_GET_HDR_EST(dlLcCb, rlcHdrEstmt);
4905 /* Update the totalBo with the scheduled bo */
4906 (hqP->hqE->ue->totalBo <= tbInfo->schdDat[idx].numBytes - rlcHdrEstmt)?\
4907 (hqP->hqE->ue->totalBo = 0):\
4908 (hqP->hqE->ue->totalBo -= tbInfo->schdDat[idx].numBytes-rlcHdrEstmt);
4912 prbUsed = ((hqP->tbInfo[tbCnt].\
4913 lchSchdData[idx].schdData *
4914 hqP->tbInfo[tbCnt].dlGrnt.numRb) /
4915 (hqP->tbInfo[0].tbSz + hqP->tbInfo[1].tbSz));
4916 dlLcCb->qciCb->dlPrbCount += prbUsed;
4917 if(dlLcCb->qciCb->qci > 0)
4919 RG_SCH_CALC_GBR_UTILIZATION(cell, dlLcCb, prbUsed);
4921 #endif /* RRM_RBC_Y */
4924 //if(!(hqP->hqE->ue->pfsStats.lcStats[lcId-1].isLcCntSet))
4928 if (hqP->hqE->ue->cell == hqP->hqE->cell)
4930 idx = RGSCH_PCELL_INDEX;
4934 idx = RG_SCH_GET_SCELL_INDEX((hqP->hqE->ue), (hqP->hqE->cell));
4936 hqP->hqE->ue->pfsStats.lcStats[lcId-1].ueSchdOcc[idx]++;
4937 hqP->hqE->ue->pfsStats.lcStats[lcId-1].perRefresh[ue->pfsStats.lcStats[lcId-1].lastIdx].lcSchdOcc++;
4944 /* Added Dl TB count for SRB/DRB data transmission*/
4946 cell->dlUlTbCnt.tbTransDlTotalCnt++;
4948 tbInfo->ta.pres = hqP->tbInfo[tbCnt].schdTa.pres;
4949 tbInfo->ta.val = hqP->tbInfo[tbCnt].schdTa.val;
4951 tbInfo->sCellActCe = hqP->tbInfo[tbCnt].schdSCellActCe;
4953 tbInfo->numSchLch = hqP->tbInfo[tbCnt].numLch;
4954 if(!(hqP->tbInfo[tbCnt].numLch))
4956 tbInfo->schdDat[tbInfo->numSchLch].numBytes= hqP->tbInfo[tbCnt].tbSz;
4957 /* Fix: If only TA is scheduled, use some dummy LCID */
4958 if (tbInfo->ta.pres)
4959 tbInfo->schdDat[tbInfo->numSchLch].lcId = RG_TA_LCID;
4962 tbInfo->contResCe = hqP->tbInfo[tbCnt].contResCe;
4963 tbInfo->isReTx = FALSE;
4968 if(!((rgSCHLaaCheckIfLAAProc(hqP)) && (TRUE ==
4969 rgSCHLaaSCellEnabled(cell))))
4972 hqP->tbInfo[tbCnt].txCntr++;
4974 tbInfo->isReTx = TRUE;
4976 /* As per 36.314, harq retransmission also considered for
4977 * prb utilization calculation*/
4978 for(idx = 0; idx < hqP->tbInfo[tbCnt].numLch; idx++)
4983 lcId = hqP->tbInfo[tbCnt].lchSchdData[idx].lcId;
4986 dlLcCb = hqP->hqE->ue->dl.lcCb[lcId-1];
4989 prbUsed = ((hqP->tbInfo[tbCnt].\
4990 lchSchdData[idx].schdData *
4991 hqP->tbInfo[tbCnt].dlGrnt.numRb) /
4992 (hqP->tbInfo[0].tbSz + hqP->tbInfo[1].tbSz));
4993 if(dlLcCb->qciCb->qci > 0)
4995 RG_SCH_CALC_GBR_UTILIZATION(cell, dlLcCb, prbUsed);
5007 rgSCHLaaResetDlHqProcCb(hqP);
5012 /***********************************************************
5014 * Func : rgSCHUtlFillRgInfUeInfo
5016 * Desc : Utility Function to fill the allocation info of Ue
5017 * : MIMO : Filling 2TB's of each UE
5022 * Notes: This function should be called while sending a msg from
5023 * scheduler instance to MAC
5027 **********************************************************/
5029 Void rgSCHUtlFillRgInfUeInfo(RgSchDlSf *sf,RgSchCellCb *cell,CmLListCp *dlDrxInactvTmrLst,CmLListCp *dlInActvLst,CmLListCp *ulInActvLst)
5031 RgInfSfAlloc *sfAlloc;
5032 CmLListCp *lnkLst; /* lnkLst assignment */
5035 RgSchUeCb *ue = NULLP;
5036 RgInfUeInfo *ueInfo = NULLP;
5037 RgInfUeAlloc *ueAlloc = NULLP;
5038 RgSchDlHqProcCb *hqCb = NULLP;
5040 /* Since Msg4 is sched only on PCELL, use cell arg's sfAllocArr */
5041 sfAlloc = &(cell->sfAllocArr[cell->crntSfIdx]);
5042 ueInfo = &(sfAlloc->ueInfo);
5043 ueAlloc = sfAlloc->ueInfo.allocInfo;
5045 lnkLst = &(sf->msg4HqPLst);
5046 CM_LLIST_FIRST_NODE(lnkLst, tmp);
5049 DU_LOG("\nINFO --> SCH : 5GTF_ERROR MSG4 Consolidation\n");
5050 hqCb = (RgSchDlHqProcCb *)(tmp->node);
5051 CM_LLIST_NEXT_NODE(lnkLst, tmp);
5053 rgSCHUtlFillRgInfTbInfo(hqCb, &ueAlloc[ueInfo->numUes], cell);
5059 if((!(ue->dl.dlInactvMask & RG_HQENT_INACTIVE)) && (ue->isDrxEnabled))
5061 rgSCHUtlGetDrxSchdUesInDl(cell, ue, hqCb, &ueAlloc[ueInfo->numUes],
5062 dlDrxInactvTmrLst, dlInActvLst, ulInActvLst);
5068 lnkLst = &(sf->ueLst);
5069 CM_LLIST_FIRST_NODE(lnkLst, tmp);
5072 #if defined (TENB_STATS) && defined (RG_5GTF)
5073 cell->tenbStats->sch.dl5gtfPdschCons++;
5075 ue = (RgSchUeCb *)(tmp->node);
5076 CM_LLIST_NEXT_NODE(lnkLst, tmp);
5078 hqPNode = ue->dl.dlSfHqInfo[cell->cellId][sf->dlIdx].hqPLst.first;
5081 hqCb = (RgSchDlHqProcCb *)hqPNode->node;
5082 hqPNode = hqPNode->next;
5084 sfAlloc = &(hqCb->hqE->cell->sfAllocArr[hqCb->hqE->cell->crntSfIdx]);
5085 ueInfo = &(sfAlloc->ueInfo);
5086 ueAlloc = sfAlloc->ueInfo.allocInfo;
5088 rgSCHUtlFillRgInfTbInfo(hqCb, &ueAlloc[ueInfo->numUes],
5091 if(ue->isDrxEnabled)
5093 rgSCHUtlGetDrxSchdUesInDl(cell, ue, hqCb, &ueAlloc[ueInfo->numUes],
5094 dlDrxInactvTmrLst, dlInActvLst, ulInActvLst);
5099 if (rgSchCb[cell->instIdx].genCfg.isSCellActDeactAlgoEnable == TRUE)
5101 /*If remaining BO is left then increment the count*/
5105 /* Check if trigger for Activation is met or not */
5106 if(rgSCHIsActvReqd(cell, ue))
5109 /*Passing primary cell*/
5110 rgSCHSCellSelectAndActDeAct(ue->cell, ue, RGR_SCELL_ACT);
5115 /*If remaining BO is 0 then reset the count*/
5123 } /* end of rgSCHUtlFillRgInfUeInfo */
5127 /** @brief This function shall update the scheduler with the CEs and data rcvd
5131 * Function: rgSCHUtlUpdSch
5134 * - Collate the information of all the SDUs received and inform the
5135 * scheduler rgSCHDataRcvd
5136 * - Send Data indication to the higher layer with the dedicated data
5137 * (rgUIMSndDedDatInd)
5138 * - Inform scheduler with any MAC CEs if present.
5140 * @param [in] RgCellCb *cellCb
5141 * @param [in] RgUeCb *ueCb
5142 * @param [in] RgMacPdu *pdu
5143 * @param [in] RgSchErrInfo *err
5148 S16 rgSCHUtlUpdSch(RgInfSfDatInd *subfrmInfo,RgSchCellCb *cellCb,RgSchUeCb *ueCb,RgInfUeDatInd *pdu,RgSchErrInfo *err)
5153 if (RGSCH_UL_SPS_ACT_PRSENT & pdu->ceInfo.bitMask)
5155 /* SPS to be activated due to data on SPS LCG ID*/
5156 rgSCHUtlSpsActInd(cellCb, ueCb, pdu->ceInfo.spsSduSize);
5159 /* TODO : Temp Fix for crash due to UL SDU corruption*/
5160 if (RGSCH_PHR_CE_PRSNT & pdu->ceInfo.bitMask)
5163 RGSCHCPYTIMEINFO(subfrmInfo->timingInfo, ueCb->macCeRptTime);
5164 if ((ret = rgSCHUtlUpdPhr(cellCb, ueCb, pdu->ceInfo.ces.phr, err)) != ROK)
5167 /* Note: Order of indication to Sch now is
5168 * 1st Indicate the DataInd info for each LCG's
5169 * 2nd Update the BSR reports received along with data
5170 * this is to make sure the effBsr is updated to the latest BSR
5173 cellCb->sc.apis->rgSCHUpdUeDataIndLcg(cellCb, ueCb, pdu);
5175 #ifndef MAC_5GTF_UPDATE
5176 if (RGSCH_TRUNC_BSR_CE_PRSNT & pdu->ceInfo.bitMask)
5178 RGSCHCPYTIMEINFO(subfrmInfo->timingInfo, ueCb->macCeRptTime);
5179 /*ccpu00129922 - MOD - Deleted return value
5180 * checking since it returns void*/
5181 rgSCHUtlUpdBsrTrunc (cellCb, ueCb,
5182 (uint8_t)(pdu->ceInfo.ces.bsr.truncBsr >> 6),
5183 (uint8_t)(pdu->ceInfo.ces.bsr.truncBsr & 0x3F), err);
5187 if (RGSCH_SHORT_BSR_CE_PRSNT & pdu->ceInfo.bitMask)
5189 RGSCHCPYTIMEINFO(subfrmInfo->timingInfo, ueCb->macCeRptTime);
5190 /*ccpu00129922 - MOD - Deleted return value
5191 checking since it returns void*/
5192 rgSCHUtlUpdBsrShort (cellCb, ueCb,
5193 (uint8_t)(pdu->ceInfo.ces.bsr.shortBsr >> 6),
5194 (uint8_t)(pdu->ceInfo.ces.bsr.shortBsr & 0x3F), err);
5198 if (RGSCH_LONG_BSR_CE_PRSNT & pdu->ceInfo.bitMask)
5200 if (RGSCH_BSR_CE_PRSNT & pdu->ceInfo.bitMask)
5203 RGSCHCPYTIMEINFO(subfrmInfo->timingInfo, ueCb->macCeRptTime);
5204 /*ccpu00129922 - MOD - Deleted return value
5205 checking since it returns void*/
5206 rgSCHUtlUpdBsrLong (cellCb, ueCb,
5207 pdu->ceInfo.ces.bsr.longBsr.bs1,
5208 pdu->ceInfo.ces.bsr.longBsr.bs2,
5209 pdu->ceInfo.ces.bsr.longBsr.bs3,
5210 pdu->ceInfo.ces.bsr.longBsr.bs4,
5213 #ifndef MAC_5GTF_UPDATE
5220 } /* end of rgSCHUtlUpdSch */
5223 * @brief Handler for Updating Bo received in StaRsp
5227 * Function : rgSCHUtlAddUeToCcchSduLst
5229 * This function shall be invoked once it receives staRsp on CCCH
5231 * @param[in] RgSchCellCb *cell
5232 * @param[in] RgSchUeCb *ueCb
5236 S16 rgSCHUtlAddUeToCcchSduLst(RgSchCellCb *cell,RgSchUeCb *ueCb)
5238 RgSchCmnDlUe *ueDl = RG_SCH_CMN_GET_DL_UE(ueCb, cell);
5239 RgSchDlHqProcCb *hqP = (RgSchDlHqProcCb *)ueDl->proc;
5241 /* Temp Guard: For back to back CCCH SDU BO
5242 * twice. Hence an extra guard. If already added to scheduling
5243 * queue or if scheduled and waiting for HQ FDBK, ignore */
5244 if ((ueCb->ccchSduLnk.node) ||
5245 ((!(ueCb->dl.dlInactvMask & RG_HQENT_INACTIVE)) &&
5246 ((hqP != NULLP) && (hqP->hqE->ccchSduProc))))
5248 DU_LOG("\nINFO --> SCH : RNTI:%d Unexpected CCCH SDU BO",
5253 ueCb->ccchSduLnk.node = (PTR)(ueCb);
5254 cmLListAdd2Tail(&(cell->ccchSduUeLst), &(ueCb->ccchSduLnk));
5262 * Function : rgSCHUtlUpdtBo
5264 * This function shall be invoked once it receives staRsp on CCCH
5266 * @param[in] RgSchCellCb *cell
5267 * @param[in] RgRguCmnStaRsp *staRsp
5271 S16 rgSCHUtlUpdtBo(RgSchCellCb *cell,RgInfCmnBoRpt *staRsp)
5275 if ((ueCb = rgSCHDbmGetUeCb(cell, staRsp->u.rnti)) == NULLP)
5277 /* Handle Ue fetch failure */
5278 DU_LOG("\nERROR --> SCH : Invalid UEID:%d",staRsp->u.rnti);
5281 /* Update Bo in ueCb */
5282 ueCb->dlCcchInfo.bo = (uint32_t)(staRsp->bo);
5286 rgSCHUtlAddUeToEmtcCcchSduLst(cell,ueCb);
5291 rgSCHUtlAddUeToCcchSduLst(cell, ueCb);
5295 } /* rgSCHUtlUpdtBo */
5301 * Function : rgSCHUtlHndlCcchBoUpdt
5303 * This function shall fetch the raCb with the given rnti and ask RAM to
5307 * @param[in] RgSchCellCb *cell
5308 * @param[in] RgInfCmnBoRpt *boRpt
5313 S16 rgSCHUtlHndlCcchBoUpdt(RgSchCellCb *cell,RgInfCmnBoRpt *boRpt)
5318 if ((raCb = rgSCHDbmGetRaCb(cell, boRpt->u.rnti)) == NULLP)
5321 /* CR timer implementation changes*/
5322 /*If no raCb, schedule ueCb, ueCb is extracted in rgSCHUtlUpdtBo*/
5323 return (rgSCHUtlUpdtBo(cell, boRpt));
5325 /* Handle RaCb fetch failure */
5326 DU_LOG("\nERROR --> SCH : Invalid RNTI:%d to fetch raCb",boRpt->u.rnti);
5333 /*Fix: If RaCb exists, then MSG4 is not completed yet*/
5334 /*Check if guard timer has expired, if not CR CE + CCCH SDU will be scheduled*/
5335 if((raCb->contResTmrLnk.node != NULLP) && \
5336 (raCb->schdLnk.node == NULLP) && (raCb->dlHqE->msg4Proc == NULLP))
5339 /*if contention resolution timer left ,Stop the Contention Resolution Guard Timer ,
5340 add in toBeSchduled list and update the Bo */
5341 if(TRUE == raCb->isEmtcRaCb)
5343 rgSCHRamEmtcUpdtBo(cell, raCb, boRpt);
5348 cmLListDelFrm(&cell->contResGrdTmrLst, &(raCb->contResTmrLnk));
5349 raCb->contResTmrLnk.node=NULLP;
5350 rgSCHRamUpdtBo(cell, raCb, boRpt);
5355 /*Fix:Guard timer has expired */
5356 /*Update the BO in UE CB but dont add it to the scheduling list.
5357 *Should be added to the list after MSG4 completion*/
5358 if ((ueCb = rgSCHDbmGetUeCb(cell, boRpt->u.rnti)) == NULLP)
5360 /* Handle Ue fetch failure */
5361 DU_LOG("\nERROR --> SCH : Invalid RNTI:%d",boRpt->u.rnti);
5364 /* Update Bo in ueCb */
5365 ueCb->dlCcchInfo.bo = (uint32_t)(boRpt->bo);
5369 rgSCHRamUpdtBo(cell, raCb, boRpt);
5373 } /* rgSCHUtlHndlCcchBoUpdt */
5376 * @brief Validates BO received for BCCH or PCCH.
5380 * Function : rgSCHUtlGetAllwdCchTbSz
5382 * This function shall return the tbSz equal to or
5383 * the nearest greater value for a given bo.
5384 * If no such value found return -1. The nPrb value is
5388 * @param[in] uint32_t bo
5389 * @param[out] uint8_t *nPrb
5394 S32 rgSCHUtlGetAllwdCchTbSz(uint32_t bo,uint8_t *nPrb,uint8_t *mcs)
5400 for (lt = 0, rt = 43; lt <= rt;)
5403 if (rgSchUtlBcchPcchTbSzTbl[cn].tbSz == bo)
5405 *nPrb = rgSchUtlBcchPcchTbSzTbl[cn].rbIndex;
5406 *mcs = rgSchUtlBcchPcchTbSzTbl[cn].mcs;
5407 return (rgSchUtlBcchPcchTbSzTbl[cn].tbSz);
5409 else if (rgSchUtlBcchPcchTbSzTbl[cn].tbSz < bo)
5418 *nPrb = rgSchUtlBcchPcchTbSzTbl[lt].rbIndex;
5419 *mcs = rgSchUtlBcchPcchTbSzTbl[lt].mcs;
5420 return (rgSchUtlBcchPcchTbSzTbl[lt].tbSz);
5424 * @brief Handler for BO Updt received for BCCH or PCCH.
5428 * Function : rgSCHUtlHndlBcchPcchBoUpdt
5430 * This function shall store the buffer and time to transmit in lcCb
5433 * @param[in] RgSchCellCb *cell
5434 * @param[in] RgInfCmnBoRpt *boRpt
5439 S16 rgSCHUtlHndlBcchPcchBoUpdt(RgSchCellCb *cell,RgInfCmnBoRpt *boUpdt)
5441 RgSchClcDlLcCb *dlLc;
5442 RgSchClcBoRpt *boRpt;
5443 Inst inst = cell->instIdx;
5447 dlLc = rgSCHDbmGetBcchOnBch(cell);
5450 DU_LOG("\nERROR --> SCH : No Logical Channel dlLc is NULLP for RNTI:%d LCID:%d",boUpdt->u.rnti,boUpdt->lcId);
5453 if (boUpdt->lcId != dlLc->lcId)
5455 /* Added for dropping paging Message*/
5457 if ((rgSCHChkBoUpdate(cell,boUpdt))== ROK) /* Checking if received BO falls within the window of 5120 slots*/
5459 if (rgSCHUtlGetAllwdCchTbSz(boUpdt->bo*8, &nPrb, &mcs)
5462 DU_LOG("\nERROR --> SCH : [%d]BO: does not match any "
5463 "valid TB Size RNTI:%d LCID:%d", boUpdt->bo,boUpdt->u.rnti,boUpdt->lcId);
5466 }/*end of rgSCHChkBoUpdate*/
5472 if ((dlLc = rgSCHDbmGetCmnLcCb(cell, boUpdt->lcId)) == NULLP)
5474 /* Handle lcCb fetch failure */
5475 DU_LOG("\nERROR --> SCH : LCID:%d Invalid for RNTI:%d",boUpdt->lcId,boUpdt->u.rnti);
5478 if (((rgSCHUtlAllocSBuf(inst, (Data **)(&boRpt), sizeof(RgSchClcBoRpt))) ==RFAILED) ||
5481 DU_LOG("\nERROR --> SCH : Allocation of common bo %dreport "
5482 "failed RNTI:%d LCID:%d", boUpdt->bo,boUpdt->u.rnti,boUpdt->lcId);
5486 boRpt->bo = boUpdt->bo;
5488 boRpt->timeToTx = boUpdt->u.timeToTx;
5491 if(cell->emtcEnable)
5493 boRpt->emtcDIReason = boUpdt->emtcDIReason;
5494 boRpt->pnb = boUpdt->pnb;
5497 RG_SCH_ADD_TO_CRNT_TIME(boRpt->timeToTx,
5498 boRpt->maxTimeToTx, cell->siCfg.siWinSize)
5499 if((NULLP != dlLc) && (dlLc->si))
5501 boRpt->retxCnt = cell->siCfg.retxCnt;
5507 rgSCHDbmInsCmnLcBoRpt(dlLc, boRpt);
5510 } /* rgSCHUtlHndlBcchPcchBoUpdt */
5513 * @brief API for sending bind confirm from Scheduler instance to RRM
5517 * Function: rgSCHUtlRgrBndCfm
5519 * This API is invoked to send bind confirm from Scheduler instance to RRM.
5520 * This API fills in Pst structure and SAP Ids and invokes
5521 * bind confirm API towards RRM.
5523 * @param[in] SuId suId
5524 * @param[in] uint8_t status
5529 S16 rgSCHUtlRgrBndCfm(Inst instId,SuId suId,uint8_t status)
5533 ret = RgUiRgrBndCfm(&rgSchCb[instId].rgrSap[suId].sapCfg.sapPst, rgSchCb[instId].rgrSap[suId].sapCfg.suId, status);
5536 DU_LOG("\nERROR --> SCH : rgSCHUtlRgrBndCfm: RgUiRgrBndCfm Failed ");
5540 } /* rgSCHUtlRgrBndCfm*/
5543 * @brief API for sending bind confirm from Scheduler instance to RRM via RGM
5548 * Function: rgSCHUtlRgmBndCfm
5550 * This API is invoked to send bind confirm from Scheduler instance to RRM.
5551 * This API fills in Pst structure and SAP Ids and invokes
5553 * @param[in] SuId suId
5554 * @param[in] uint8_t status
5559 S16 rgSCHUtlRgmBndCfm(Inst instId,SuId suId,uint8_t status)
5563 ret = RgUiRgmBndCfm(&rgSchCb[instId].rgmSap[suId].sapCfg.sapPst, rgSchCb[instId].rgmSap[suId].sapCfg.suId, status);
5566 DU_LOG("\nERROR --> SCH : rgSCHUtlRgmBndCfm: RgUiRgrBndCfm Failed ");
5570 } /* rgSCHUtlRgmBndCfm*/
5575 * @brief API for sending configuration confirm from Scheduler to DU APP
5579 * Function: schSendCfgCfm
5581 * This API is invoked to send configuration confirm from Scheduler to DU
5584 * @param[in] Pst pst
5585 * @param[in] RgrCfgTransId transId
5586 * @param[in] uint8_t status
5591 S16 schSendCfgCfm(Region reg,Pool pool,RgrCfgTransId transId,uint8_t status)
5595 memset((&cfmPst), 0, sizeof(Pst));
5597 cfmPst.srcEnt = (Ent)ENTDUAPP;
5598 cfmPst.srcInst = (Inst) 0;
5599 cfmPst.srcProcId = SFndProcId();
5600 cfmPst.dstEnt = (Ent)ENTMAC;
5601 cfmPst.dstInst = (Inst) 0;
5602 cfmPst.dstProcId = SFndProcId();
5603 cfmPst.selector = ODU_SELECTOR_LC;
5604 cfmPst.region = reg;
5607 if(RgUiRgrCfgCfm(&cfmPst,transId, status) != ROK)
5609 DU_LOG("\nERROR --> SCH : schSendCfgCfm: RgUiRgrCfgCfm Failed ");
5613 } /* schSendCfgCfm*/
5616 * @brief API for sending TTI indication from Scheduler to RRM.
5620 * Function: rgSCHUtlRgrTtiInd
5622 * This API is invoked to send TTI indication from Scheduler instance to RRM.
5623 * This API fills in Pst structure and RgrTtiIndInfo
5625 * @param[in] cell RgSchCellCb
5626 * @param[in] CmLteTimingInfo status
5631 S16 rgSCHUtlRgrTtiInd(RgSchCellCb *cell,RgrTtiIndInfo *rgrTti)
5634 RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
5637 Void mtTmrHdlrPublic(void);
5640 rgrSap = cell->rgrSap;
5641 if (rgrSap->sapSta.sapState != LRG_BND)
5643 DU_LOG("\nERROR --> SCH : rgSCHUtlRgrTtiInd() Upper SAP not bound (%d) ",
5644 rgrSap->sapSta.sapState);
5647 RgUiRgrTtiInd(&(cell->rgrSap->sapCfg.sapPst),
5648 cell->rgrSap->sapCfg.suId, rgrTti);
5656 } /* rgSCHUtlRgrTtiInd*/
5658 /** @brief This function is called by rgMacSchSfRecpInd. This function invokes the
5659 * scheduler with the information of the received Data and any Control Elements
5667 * - Retrieves the RaCb with the rnti provided, if it doesnt exist
5669 * - If UE exists then update the Schduler with any MAC CEs if present.
5670 * - Invoke RAM module to do Msg3 related processing rgSCHRamProcMsg3
5672 * @param [in] RgSchCellCb *cellCb
5673 * @param [in] RgSchUeCb *ueCb
5674 * @param [in] CmLteRnti rnti
5675 * @param [in] RgMacPdu *pdu
5676 * @param [in] RgSchErrInfo *err
5682 S16 rgSCHUtlProcMsg3
5684 RgInfSfDatInd *subfrmInfo,
5685 RgSchCellCb *cellCb,
5695 /* must have an raCb for this case */
5696 raCb = rgSCHDbmGetRaCb (cellCb, rnti);
5699 DU_LOG("\nERROR --> SCH : RNTI:%d Received MSG3, unable to "
5704 /* ccpu00130982: Processing CRNTI MAC CE before Short BSR, if any, such that
5705 * effBsr of current case only will be considered in scheduling of ContResLst*/
5706 ret = rgSCHRamProcMsg3 (cellCb, ueCb, raCb, pdu, err);
5709 DU_LOG("\nERROR --> SCH : Processing failed in the RAM "
5713 /* if ueCb is present */
5716 rgSCHUtlUpdSch (subfrmInfo, cellCb, ueCb, pdu, err);
5722 /** @brief This function is called by RgMacSchSpsRelInd. This function invokes the
5723 * scheduler with the information of the received Data.
5727 * Function: rgSCHUtlSpsRelInd
5732 * @param [in] RgSchCellCb *cellCb
5733 * @param [in] RgSchUeCb *ueCb
5734 * @param [in] Bool *isExplRel
5740 S16 rgSCHUtlSpsRelInd(RgSchCellCb *cellCb,RgSchUeCb *ueCb,Bool isExplRel)
5742 cellCb->sc.apis->rgSCHUlSpsRelInd(cellCb, ueCb, isExplRel);
5744 } /* end of rgSCHUtlSpsRelInd */
5747 /** @brief This function is called by RgMacSchSpsRelInd. This function invokes the
5748 * scheduler with the information of the received Data.
5752 * Function: rgSCHUtlSpsActInd
5757 * @param [in] RgSchCellCb *cellCb
5758 * @param [in] RgSchUeCb *ueCb
5759 * @param [in] uint16_t spsSduSize
5765 S16 rgSCHUtlSpsActInd(RgSchCellCb *cellCb,RgSchUeCb *ueCb,uint16_t spsSduSize)
5767 cellCb->sc.apis->rgSCHUlSpsActInd(cellCb, ueCb, spsSduSize);
5769 } /* end of rgSCHUtlSpsActInd */
5772 #endif /* LTEMAC_SPS */
5776 * @brief This API is invoked to send uplink group power control request to PHY.
5780 * Function : rgSCHUtlTfuGrpPwrCntrlReq
5782 * This API is invoked to send uplink group power control request to PHY.
5783 * It fills in the Pst structure, spId value and invokes group power
5784 * control request primitive at TFU.
5786 * @param[in] TfuGrpPwrCntrlReqInfo *grpPwrCntrlReq
5791 S16 rgSCHUtlTfuGrpPwrCntrlReq(Inst inst,S16 sapId,TfuGrpPwrCntrlReqInfo *grpPwrCntrlReq)
5794 RgSchLowSapCb *tfuSap;
5797 /* Get the lower SAP control block from the layer control block. */
5798 tfuSap = &(rgSchCb[inst].tfuSap[sapId]);
5799 if (tfuSap->sapSta.sapState != LRG_BND)
5801 DU_LOG("\nERROR --> SCH : rgSCHUtlTfuGrpPwrCntrlReq() Lower SAP not bound (%d) ",tfuSap->sapSta.sapState);
5804 memcpy (&pst, &(tfuSap->sapCfg.sapPst), sizeof(Pst));
5805 if((ret = RgLiTfuGrpPwrCntrlReq (&pst, tfuSap->sapCfg.spId, grpPwrCntrlReq)) != ROK)
5807 DU_LOG("\nERROR --> SCH : rgSCHUtlTfuGrpPwrCntrlReq() Call to RgLiTfuGrpPwrCntrlReq() failed");
5810 } /* rgSCHUtlTfuGrpPwrCntrlReq */
5813 /* FOR ACK NACK REP */
5816 * @brief This API is invoked to tell the DL Scheduler to add the UE back into
5817 * its scheduling queues.
5821 * Function : rgSCHUtlDlActvtUe
5823 * This API is invoked from Measurement gap moduled.
5825 * @param[in] RgSchCellCb *cell
5826 * @param[in] RgSchUeCb *ueCb
5832 S16 rgSCHUtlDlActvtUe(RgSchCellCb *cell,RgSchUeCb *ue)
5834 cell->sc.apis->rgSCHActvtDlUe(cell, ue);
5839 * @brief This API is invoked to tell the UL Scheduler to add the UE back into
5840 * its scheduling queues.
5844 * Function : rgSCHUtlUlActvtUe
5846 * This API is invoked from Measurement gap moduled.
5848 * @param[in] RgSchCellCb *cell
5849 * @param[in] RgSchUeCb *ueCb
5855 S16 rgSCHUtlUlActvtUe(RgSchCellCb *cell,RgSchUeCb *ue)
5857 cell->sc.apis->rgSCHActvtUlUe(cell, ue);
5861 /** @brief This function Validates the SAP information received along with the
5862 * primitive from the lower layer.
5864 * Function: rgSCHUtlValidateTfuSap
5866 * Validates SAP information.
5867 * @param suId The SAP Id
5872 S16 rgSCHUtlValidateTfuSap(Inst inst,SuId suId)
5874 RgSchLowSapCb *tfuSap;
5876 if(suId >= rgSchCb[inst].numSaps)
5878 DU_LOG("\nERROR --> SCH : Incorrect SuId");
5881 tfuSap = &(rgSchCb[inst].tfuSap[suId]);
5883 /* First lets check the suId */
5884 if( suId != tfuSap->sapCfg.suId)
5886 DU_LOG("\nERROR --> SCH : Incorrect SuId. Configured (%d) Recieved (%d)",
5887 tfuSap->sapCfg.suId, suId);
5890 if (tfuSap->sapSta.sapState != LRG_BND)
5892 DU_LOG("\nERROR --> SCH : Lower SAP not enabled SuId (%d)",
5893 tfuSap->sapCfg.suId);
5897 } /* end of rgSCHUtlValidateTfuSap */
5901 * Fun: rgSCHUtlAllocEventMem
5903 * Desc: This function allocates event memory
5905 * Ret: ROK - on success
5906 * RFAILED - on failure
5913 S16 rgSCHUtlAllocEventMem(Inst inst,Ptr *memPtr,Size memSize)
5916 volatile uint32_t startTime=0;
5919 sMem.region = rgSchCb[inst].rgSchInit.region;
5920 sMem.pool = rgSchCb[inst].rgSchInit.pool;
5922 #if (ERRCLASS & ERRCLS_DEBUG)
5925 DU_LOG("\nERROR --> SCH : rgAllocEventMem(): memSize invalid\n");
5928 #endif /* ERRCLASS & ERRCLS_DEBUG */
5930 SStartTask(&startTime, PID_SCHUTL_CMALLCEVT);
5932 #ifdef MS_MBUF_CORRUPTION /* Should be enabled when debugging mbuf corruption */
5933 MS_BUF_ADD_ALLOC_CALLER();
5935 #ifdef TFU_ALLOC_EVENT_NO_INIT
5936 if(ROK != cmAllocEvntNoInit(memSize, TFU_MAX_MEMBLK_SIZE, &sMem, memPtr))
5938 if(ROK != cmAllocEvnt(memSize, TFU_MAX_MEMBLK_SIZE, &sMem, memPtr))
5941 DU_LOG("\nERROR --> SCH : cmAllocEvnt Failed.");
5945 SStopTask(startTime, PID_SCHUTL_CMALLCEVT);
5947 } /* end of rgSCHUtlAllocEventMem*/
5951 * Fun: rgGetEventMem
5953 * Desc: This function allocates event memory
5955 * Ret: ROK - on success
5956 * RFAILED - on failure
5963 S16 rgSCHUtlGetEventMem(Ptr *ptr,Size len,Ptr memCp)
5967 #ifdef TFU_ALLOC_EVENT_NO_INIT
5968 ret = cmGetMemNoInit(memCp, len, (Ptr *)ptr);
5970 ret = cmGetMem(memCp, len, (Ptr *)ptr);
5973 } /* end of rgSCHUtlGetEventMem*/
5979 * @brief Handler to allocate memory for ACK/NACk feedback information
5983 * Function : rgSCHUtlAllocUeANFdbkInfo
5985 * It allocates memory for the UE related ACK NACK information.
5987 * @param[in] RgSchUeCb *ue
5990 S16 rgSCHUtlAllocUeANFdbkInfo(RgSchUeCb *ue,uint8_t servCellIdx)
5994 if (rgSCHUtlAllocSBuf(ue->cell->instIdx,
5995 (Data **) &(ue->cellInfo[servCellIdx]->anInfo), sizeof(RgSchTddANInfo) * \
5996 ue->cell->ackNackFdbkArrSize) != ROK)
6001 for(idx=0; idx < ue->cell->ackNackFdbkArrSize; idx++)
6003 rgSCHUtlInitUeANFdbkInfo(&ue->cellInfo[servCellIdx]->anInfo[idx]);
6006 /* Set it to the first index */
6007 ue->cellInfo[servCellIdx]->nextFreeANIdx = 0;
6009 } /* rgSCHUtlAllocUeANFdbkInfo */
6012 * @brief Handler to release memory for ACK/NACk feedback information
6016 * Function : rgSCHUtlDelUeANFdbkInfo
6018 * It releases memory for the UE related ACK NACK information.
6020 * @param[in] RgSchUeCb *ue
6023 Void rgSCHUtlDelUeANFdbkInfo(RgSchUeCb *ue,uint8_t servCellIdx)
6026 /* ccpu00117052 - MOD - Passing double pointer
6027 for proper NULLP assignment*/
6028 rgSCHUtlFreeSBuf(ue->cell->instIdx,
6029 (Data **)(&( ue->cellInfo[servCellIdx]->anInfo)), sizeof(RgSchTddANInfo) * \
6030 ue->cell->ackNackFdbkArrSize);
6033 } /* rgSCHUtlDelUeANFdbkInfo */
6036 * @brief Handler to initialise UE ACK/NACk feedback information
6040 * Function : rgSCHUtlInitUeANFdbkInfo
6042 * It initialises UE related ACK NACK information.
6044 * @param[in] RgSchTddANInfo *anFdInfo
6047 S16 rgSCHUtlInitUeANFdbkInfo(RgSchTddANInfo *anFdInfo)
6050 anFdInfo->sfn = RGSCH_MAX_SFN+1; /* defensively setting invalid sfn */
6052 anFdInfo->ulDai = RG_SCH_INVALID_DAI_VAL;
6053 anFdInfo->dlDai = RG_SCH_INVALID_DAI_VAL;
6054 anFdInfo->latestMIdx = RG_SCH_INVALID_M_VAL;
6057 } /* rgSCHUtlInitUeANFdbkInfo */
6060 * @brief Handler to get UE related ACK NACK feedback information
6064 * Function : rgSCHUtlGetUeANFdbkInfo
6066 * It gets the UE related ACK NACK information based on
6067 * SFN and slot number.
6069 * @param[in] RgSchUeCb *ueCb
6070 * @param[in] CmLteTimingInfo *time
6071 * @return RgSchTddANInfo*
6073 RgSchTddANInfo* rgSCHUtlGetUeANFdbkInfo(RgSchUeCb *ueCb,CmLteTimingInfo *timeInfo,uint8_t servCellIdx)
6077 for (idx = 0; idx < ueCb->cell->ackNackFdbkArrSize; ++idx)
6079 if( (timeInfo->sfn == ueCb->cellInfo[servCellIdx]->anInfo[idx].sfn) &&
6080 (timeInfo->slot == ueCb->cellInfo[servCellIdx]->anInfo[idx].slot))
6082 return (&ueCb->cellInfo[servCellIdx]->anInfo[idx]);
6087 } /* rgSCHUtlGetUeANFdbkInfo */
6090 * @brief To get downlink slot index
6094 * Function: rgSCHUtlGetDlSfIdx
6095 * Purpose: Gets downlink slot index based on SFN and slot no
6097 * @param[in] CmLteTimingInfo *timeInfo
6098 * @param[in] RgSchCellCb *cell
6102 uint8_t rgSCHUtlGetDlSfIdx(RgSchCellCb *cell,CmLteTimingInfo *timeInfo)
6106 idx = RGSCH_NUM_SUB_FRAMES - \
6107 rgSchTddNumUlSubfrmTbl[cell->ulDlCfgIdx][RGSCH_NUM_SUB_FRAMES-1];
6108 idx = ((idx * timeInfo->sfn) + \
6109 rgSchTddNumDlSubfrmTbl[cell->ulDlCfgIdx][timeInfo->slot]) - 1;
6110 idx = idx % cell->numDlSubfrms;
6112 return ((uint8_t)idx);
6116 * @brief To get the next downlink slot
6120 * Function: rgSCHUtlGetNxtDlSfInfo
6121 * Purpose: Gets next downlink slot based on current DL slot
6123 * @param[in] CmLteTimingInfo curDlTime
6124 * @param[in] RgSchCellCb *cell
6125 * @param[in] RgSchDlSf *dlSf
6126 * @param[in] RgSchDlSf **nxtDlsf
6127 * @param[in] CmLteTimingInfo *nxtDlTime
6131 Void rgSCHUtlGetNxtDlSfInfo(CmLteTimingInfo curDlTime,RgSchCellCb *cell,RgSchDlSf *dlSf,RgSchDlSf **nxtDlsf,CmLteTimingInfo *nxtDlTime)
6133 uint16_t idx = curDlTime.slot;
6140 idx = (idx + 1) % RGSCH_NUM_SUB_FRAMES;
6142 }while(rgSchTddUlDlSubfrmTbl[cell->ulDlCfgIdx][idx]
6143 != RG_SCH_TDD_DL_slot);
6144 RG_SCH_ADD_TO_CRNT_TIME(curDlTime, (*nxtDlTime), count);
6145 *nxtDlsf = rgSCHUtlSubFrmGet(cell, *nxtDlTime);
6146 if(dlSf->dlFdbkInfo.slot != (*nxtDlsf)->dlFdbkInfo.slot)
6155 * @brief To get the previous downlink slot
6159 * Function: rgSCHUtlGetPrevDlSfInfo
6160 * Purpose: Gets previous downlink slot based on current DL slot
6162 * @param[in] RgSchCellCb *cell
6163 * @param[in] CmLteTimingInfo curDlTime
6164 * @param[in] CmLteTimingInfo *prevDlTime
6165 * @param[in] uint8_t *numSubfrm
6169 Void rgSCHUtlGetPrevDlSfInfo(RgSchCellCb *cell,CmLteTimingInfo curDlTime,CmLteTimingInfo *prevDlTime,uint8_t *numSubfrm)
6171 S16 idx = curDlTime.slot;
6179 idx = RGSCH_NUM_SUB_FRAMES-1;
6182 }while(rgSchTddUlDlSubfrmTbl[cell->ulDlCfgIdx][idx]
6183 != RG_SCH_TDD_DL_slot);
6185 RGSCHDECRFRMCRNTTIME(curDlTime, (*prevDlTime), count);
6190 /* Added Holes Management functions for Adaptive Re transmission */
6191 /******* </AllocHolesMemMgmnt>: START *****/
6192 /***********************************************************
6194 * Func : rgSCHUtlUlSfInit
6196 * Desc : UL slot init.
6204 **********************************************************/
6205 S16 rgSCHUtlUlSfInit(RgSchCellCb *cell,RgSchUlSf *sf,uint8_t idx,uint8_t maxUePerSf)
6215 if(cell->ulDlCfgIdx == 0)
6217 /* Store the Uplink slot number corresponding to the idx */
6218 sf->ulSfIdx = rgSchTddCfg0UlSfTbl[idx%6];
6221 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&sf->allocDb,
6222 sizeof(RgSchUlAllocDb));
6227 ret = rgSCHUtlUlAllocDbInit(cell, sf->allocDb, maxUePerSf);
6230 /* ccpu00117052 - MOD - Passing double pointer
6231 for proper NULLP assignment*/
6232 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->allocDb)),
6233 sizeof(RgSchUlAllocDb));
6236 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&sf->holeDb,
6237 sizeof(RgSchUlHoleDb));
6240 rgSCHUtlUlAllocDbDeinit(cell, sf->allocDb);
6241 /* ccpu00117052 - MOD - Passing double pointer
6242 for proper NULLP assignment*/
6243 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->allocDb)),
6244 sizeof(RgSchUlAllocDb));
6247 /* Initialize the hole with CFI 1 Pusch Bw Info */
6248 ret = rgSCHUtlUlHoleDbInit(cell, sf->holeDb, (uint8_t)(maxUePerSf + 2), \
6249 0, cell->dynCfiCb.bwInfo[1].numSb);
6253 rgSCHUtlUlAllocDbDeinit(cell, sf->allocDb);
6254 /* ccpu00117052 - MOD - Passing double pointer
6255 for proper NULLP assignment*/
6256 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->allocDb)),
6257 sizeof(RgSchUlAllocDb));
6258 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->holeDb)),
6259 sizeof(RgSchUlHoleDb));
6262 cmLListInit(&sf->reTxLst);
6264 /* Fix ccpu00120610*/
6265 sf->allocCountRef = &sf->allocDb->count;
6267 /* initialize UL available subbands for current sub-frame */
6268 sf->availSubbands = cell->dynCfiCb.bwInfo[1].numSb;
6270 sf->numGrpPerTti = cell->cell5gtfCb.ueGrpPerTti;
6271 sf->numUePerGrp = cell->cell5gtfCb.uePerGrpPerTti;
6272 for(index = 0; index < MAX_5GTF_BEAMS; index++)
6274 sf->sfBeamInfo[index].totVrbgAllocated = 0;
6275 sf->sfBeamInfo[index].totVrbgRequired = 0;
6276 sf->sfBeamInfo[index].vrbgStart = 0;
6284 /***********************************************************
6286 * Func : rgSCHUtlUlSfDeinit
6288 * Desc : Deinitialises a slot
6296 **********************************************************/
6297 Void rgSCHUtlUlSfDeinit(RgSchCellCb *cell,RgSchUlSf *sf)
6301 rgSCHUtlUlAllocDbDeinit(cell, sf->allocDb);
6302 /* ccpu00117052 - MOD - Passing double pointer
6303 for proper NULLP assignment*/
6304 /* ccpu00117052 - MOD - Passing double pointer
6305 for proper NULLP assignment*/
6306 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->allocDb)),
6307 sizeof(RgSchUlAllocDb));
6311 rgSCHUtlUlHoleDbDeinit(cell, sf->holeDb);
6312 /* ccpu00117052 - MOD - Passing double pointer
6313 for proper NULLP assignment*/
6314 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(sf->holeDb)),
6315 sizeof(RgSchUlHoleDb));
6320 /***********************************************************
6322 * Func : rgSCHUtlUlAllocDbInit
6324 * Desc : Initialise allocation DB
6326 * Ret : S16 (ROK/RFAILED)
6332 **********************************************************/
6333 static S16 rgSCHUtlUlAllocDbInit(RgSchCellCb *cell,RgSchUlAllocDb *allocDb,uint8_t maxAllocs)
6335 S16 ret = rgSCHUtlUlAllocMemInit(cell, &allocDb->mem, maxAllocs);
6341 allocDb->first = NULLP;
6345 /***********************************************************
6347 * Func : rgSCHUtlUlAllocDbDeinit
6349 * Desc : Deinitialises allocation DB
6350 * sent to UE, for a UE with accumulation disabled
6358 **********************************************************/
6359 static Void rgSCHUtlUlAllocDbDeinit(RgSchCellCb *cell,RgSchUlAllocDb *allocDb)
6361 rgSCHUtlUlAllocMemDeinit(cell, &allocDb->mem);
6363 allocDb->first = NULLP;
6367 /***********************************************************
6369 * Func : rgSCHUtlUlHoleDbInit
6371 * Desc : Initialise hole DB
6373 * Ret : S16 (ROK/RFAILED)
6379 **********************************************************/
6380 static S16 rgSCHUtlUlHoleDbInit(RgSchCellCb *cell,RgSchUlHoleDb *holeDb,uint8_t maxHoles,uint8_t start,uint8_t num)
6383 RgSchUlHole *hole = NULLP;
6385 ret = rgSCHUtlUlHoleMemInit(cell, &holeDb->mem, maxHoles, &hole);
6391 holeDb->first = hole;
6392 hole->start = start;
6394 hole->prv = hole->nxt = NULLP;
6398 /***********************************************************
6400 * Func : rgSCHUtlUlHoleDbDeinit
6402 * Desc : Deinitialises hole DB
6410 **********************************************************/
6411 static Void rgSCHUtlUlHoleDbDeinit(RgSchCellCb *cell,RgSchUlHoleDb *holeDb)
6413 rgSCHUtlUlHoleMemDeinit(cell, &holeDb->mem);
6415 holeDb->first = NULLP;
6420 /***********************************************************
6422 * Func : rgSCHUtlUlAllocGetHole
6424 * Desc : Get allocation from hole
6426 * Ret : RgSchUlAlloc *
6432 **********************************************************/
6433 RgSchUlAlloc *rgSCHUtlUlAllocGetHole(RgSchUlSf *sf,uint8_t numSb,RgSchUlHole *hole)
6435 if (numSb < hole->num)
6437 return (rgSCHUtlUlAllocGetPartHole(sf, numSb, hole));
6441 return (rgSCHUtlUlAllocGetCompHole(sf, hole));
6446 /***********************************************************
6448 * Func : rgSCHUtlUlAllocGetCompHole
6450 * Desc : Get an allocation corresponding to an entire hole
6452 * Ret : RgSchUlAlloc *
6458 **********************************************************/
6459 RgSchUlAlloc *rgSCHUtlUlAllocGetCompHole(RgSchUlSf *sf,RgSchUlHole *hole)
6461 RgSchUlAlloc *alloc;
6462 /* alloc = rgSCHUtlUlAllocGetAndIns(sf->allocDb, hole->prvAlloc, hole->nxtAlloc); */
6463 /* Calling rgSchCmnUlAllocGetAndIns is ok, but prv alloc needs to have nxtHole
6464 * updated, causing another check for prv */
6465 RgSchUlAlloc *prv = hole->prvAlloc;
6466 RgSchUlAlloc *nxt = hole->nxtAlloc;
6470 if (hole->start == prv->nxtHole->start)
6472 prv->nxtHole = NULLP;
6474 alloc = rgSCHUtlUlAllocGetAdjNxt(sf->allocDb, prv);
6478 alloc = rgSCHUtlUlAllocGetFirst(sf->allocDb);
6481 RGSCH_NULL_CHECK( 0, alloc);
6482 alloc->prvHole = NULLP;
6483 alloc->nxtHole = NULLP;
6485 alloc->sbStart = hole->start;
6486 alloc->numSb = hole->num;
6490 nxt->prvHole = NULLP;
6493 rgSCHUtlUlHoleRls(sf->holeDb, hole);
6495 /* UL_ALLOC_CHANGES*/
6496 alloc->allocDbRef = (void*)sf->allocDb;
6497 alloc->holeDbRef = (void*)sf->holeDb;
6501 /***********************************************************
6503 * Func : rgSCHUtlUlAllocGetPartHole
6505 * Desc : Get an allocation corresponding to a part of a hole.
6506 * The initial 'numSb' part of the hole shall be taken
6507 * away for this alloc.
6509 * Ret : RgSchUlAlloc *
6515 **********************************************************/
6516 RgSchUlAlloc *rgSCHUtlUlAllocGetPartHole(RgSchUlSf *sf,uint8_t numSb,RgSchUlHole *hole)
6518 RgSchUlAlloc *alloc;
6519 /* alloc = rgSCHUtlUlAllocGetAndIns(sf->allocDb, hole->prvAlloc, hole->nxtAlloc); */
6520 /* Calling rgSchCmnUlAllocGetAndIns is ok, but prv alloc needs to have nxtHole
6521 * updated, causing another check for prv */
6522 RgSchUlAlloc *prv = hole->prvAlloc;
6526 if (hole->start == prv->nxtHole->start)
6528 prv->nxtHole = NULLP;
6530 alloc = rgSCHUtlUlAllocGetAdjNxt(sf->allocDb, prv);
6534 alloc = rgSCHUtlUlAllocGetFirst(sf->allocDb);
6537 RGSCH_NULL_CHECK( 0, alloc);
6538 alloc->prvHole = NULLP;
6539 alloc->nxtHole = hole;
6540 hole->prvAlloc = alloc;
6542 alloc->sbStart = hole->start;
6543 alloc->numSb = numSb;
6544 hole->start += numSb;
6547 rgSCHUtlUlHoleDecr(sf->holeDb, hole);
6549 /* UL_ALLOC_CHANGES*/
6550 alloc->allocDbRef = (void*)sf->allocDb;
6551 alloc->holeDbRef = (void*)sf->holeDb;
6556 /***********************************************************
6558 * Func : rgSCHUtlUlAllocFirst
6560 * Desc : Get first alloc in slot
6562 * Ret : RgSchUlAlloc *
6568 **********************************************************/
6569 RgSchUlAlloc *rgSCHUtlUlAllocFirst(RgSchUlSf *sf)
6571 return (sf->allocDb->first);
6574 /***********************************************************
6576 * Func : rgSCHUtlUlAllocNxt
6578 * Desc : Get next alloc
6580 * Ret : RgSchUlAlloc *
6586 **********************************************************/
6587 RgSchUlAlloc *rgSCHUtlUlAllocNxt(RgSchUlSf *sf,RgSchUlAlloc *alloc)
6590 return (alloc->nxt);
6593 /***********************************************************
6595 * Func : rgSCHUtlUlAllocGetAdjNxt
6597 * Desc : Get alloc which is immediately after the passed one.
6598 * 1. Gets alloc from mem.
6599 * 2. Inserts alloc into list (between prv and
6600 * prv->nxt, prv is not NULLP).
6601 * 3. Increments alloc count.
6602 * Note 1: Holes are not dealt with here.
6603 * Note 2: Assumes prv to be NULL.
6605 * Ret : RgSchUlAlloc *
6611 **********************************************************/
6612 RgSchUlAlloc *rgSCHUtlUlAllocGetAdjNxt(RgSchUlAllocDb *db,RgSchUlAlloc *prv)
6614 RgSchUlAlloc *alloc = rgSCHUtlUlAllocMemGet(&db->mem);
6615 RgSchUlAlloc *nxt = prv->nxt;
6617 #if (ERRCLASS & ERRCLS_DEBUG)
6618 if ( alloc == NULLP )
6636 /***********************************************************
6638 * Func : rgSCHUtlUlAllocGetFirst
6640 * Desc : Get alloc which is to be the first one in the alloc list
6641 * 1. Gets alloc from mem.
6642 * 2. Inserts alloc as first element into list.
6643 * 3. Increments alloc count.
6644 * Note 1: Holes are not dealt with here.
6645 * Note 2: prv to necessarily NULLP.
6647 * Ret : RgSchUlAlloc *
6653 **********************************************************/
6654 RgSchUlAlloc *rgSCHUtlUlAllocGetFirst(RgSchUlAllocDb *db)
6656 RgSchUlAlloc *alloc = rgSCHUtlUlAllocMemGet(&db->mem);
6657 RgSchUlAlloc *nxt = db->first;
6659 #if (ERRCLASS & ERRCLS_DEBUG)
6660 if ( alloc == NULLP )
6679 /* UL_ALLOC_ENHANCEMENT */
6680 /***********************************************************
6682 * Func : rgSCHUtlUlHoleAddAllocation
6684 * Desc : On freeing an alloc, add to hole
6692 **********************************************************/
6693 Void rgSCHUtlUlHoleAddAllocation(RgSchUlAlloc *alloc)
6695 /* Note: rgSchCmnUlHoleUpdAllocLnks function that is used should not exist as
6696 * one, if such excessive branching is done (AllocNone, AllocNoPrv etc).
6697 * The excessive branching is meant to utilise the knowledge of whether prv
6698 * and nxt allocs exist or not. Hence for each kind (none, noprv, nonxt,
6699 * both), there should be a rgSchCmnUlHoleUpdAllocLnks... function (such as
6700 * rgSchCmnUlHoleUpdAllocLnksNone/NoPrv etc. */
6701 RgSchUlHoleDb *db = alloc->holeDbRef;
6702 RgSchUlHole *prv = alloc->prvHole;
6703 RgSchUlHole *nxt = alloc->nxtHole;
6709 rgSCHUtlUlHoleJoin(db, prv, nxt, alloc);
6712 rgSCHUtlUlHoleExtndRight(db, prv, alloc);
6718 rgSCHUtlUlHoleExtndLeft(db, nxt, alloc);
6721 rgSCHUtlUlHoleNew(db, alloc);
6727 /***********************************************************
6729 * Func : rgSCHUtlUlAllocRelease
6731 * Desc : Releases an uplink allocation, only take alloc ptr
6739 **********************************************************/
6740 Void rgSCHUtlUlAllocRelease(RgSchUlAlloc *alloc)
6742 RgSchUlAllocDb *allocDb = alloc->allocDbRef;
6743 RgSchUlAlloc *prv = alloc->prv;
6744 RgSchUlAlloc *nxt = alloc->nxt;
6747 alloc->raCb = NULLP;
6748 alloc->isAdaptive = FALSE;
6753 if (nxt) /* general case: this allocation lies btw two */
6760 allocDb->first = nxt;
6767 rgSCHUtlUlHoleAddAllocation(alloc);
6768 rgSCHUtlUlAllocMemRls(&allocDb->mem, alloc);
6774 /***********************************************************
6776 * Func : rgSCHUtlUlAllocRls
6778 * Desc : Releases an uplink allocation
6786 **********************************************************/
6787 Void rgSCHUtlUlAllocRls(RgSchUlSf *sf,RgSchUlAlloc *alloc)
6789 RgSchUlAllocDb *allocDb = sf->allocDb;
6790 RgSchUlAlloc *prv = alloc->prv;
6791 RgSchUlAlloc *nxt = alloc->nxt;
6794 alloc->raCb = NULLP;
6795 alloc->isAdaptive = FALSE;
6802 if (nxt) /* general case: this allocation lies btw two */
6809 allocDb->first = nxt;
6816 rgSCHUtlUlHoleAddAlloc(sf, alloc);
6817 rgSCHUtlUlAllocMemRls(&allocDb->mem, alloc);
6822 DU_LOG("\nERROR --> SCH : allocDb->count is ZERO ");
6825 //DU_LOG("\nallocDb->count:%u\n",allocDb->count);
6830 /***********************************************************
6832 * Func : rgSCHUtlUlHoleFirst
6834 * Desc : Get first (largest) hole
6836 * Ret : RgSchUlHole *
6842 **********************************************************/
6843 RgSchUlHole *rgSCHUtlUlHoleFirst(RgSchUlSf *sf)
6845 return (sf->holeDb->first);
6848 /***********************************************************
6850 * Func : rgSCHUtlUlHoleNxt
6852 * Desc : Get next largest hole
6854 * Ret : RgSchUlHole *
6860 **********************************************************/
6861 RgSchUlHole *rgSCHUtlUlHoleNxt(RgSchUlSf *sf,RgSchUlHole *hole)
6867 /***********************************************************
6869 * Func : rgSCHUtlUlHoleAddAlloc
6871 * Desc : On freeing an alloc, add to hole
6879 **********************************************************/
6880 Void rgSCHUtlUlHoleAddAlloc(RgSchUlSf *sf,RgSchUlAlloc *alloc)
6882 /* Note: rgSchCmnUlHoleUpdAllocLnks function that is used should not exist as
6883 * one, if such excessive branching is done (AllocNone, AllocNoPrv etc).
6884 * The excessive branching is meant to utilise the knowledge of whether prv
6885 * and nxt allocs exist or not. Hence for each kind (none, noprv, nonxt,
6886 * both), there should be a rgSchCmnUlHoleUpdAllocLnks... function (such as
6887 * rgSchCmnUlHoleUpdAllocLnksNone/NoPrv etc. */
6888 RgSchUlHoleDb *db = sf->holeDb;
6889 RgSchUlHole *prv = alloc->prvHole;
6890 RgSchUlHole *nxt = alloc->nxtHole;
6896 rgSCHUtlUlHoleJoin(db, prv, nxt, alloc);
6899 rgSCHUtlUlHoleExtndRight(db, prv, alloc);
6905 rgSCHUtlUlHoleExtndLeft(db, nxt, alloc);
6908 rgSCHUtlUlHoleNew(db, alloc);
6911 /* increment the number of subbands getting freed to total available list */
6912 sf->availSubbands += alloc->numSb;
6917 /***********************************************************
6919 * Func : rgSCHUtlUlHoleJoin
6921 * Desc : Join two holes (due to alloc being deleted)
6929 **********************************************************/
6930 Void rgSCHUtlUlHoleJoin(RgSchUlHoleDb *db,RgSchUlHole *prv,RgSchUlHole *nxt,RgSchUlAlloc *alloc)
6932 prv->num += alloc->numSb + nxt->num;
6933 rgSCHUtlUlHoleRls(db, nxt);
6934 rgSCHUtlUlHoleIncr(db, prv);
6935 rgSCHUtlUlHoleUpdAllocLnks(prv, alloc->prv, alloc->nxt);
6940 /***********************************************************
6942 * Func : rgSCHUtlUlHoleExtndRight
6944 * Desc : Extend hole due to alloc coming 'after' the hole
6953 **********************************************************/
6954 Void rgSCHUtlUlHoleExtndRight(RgSchUlHoleDb *db,RgSchUlHole *prv,RgSchUlAlloc *alloc)
6956 prv->num += alloc->numSb;
6957 rgSCHUtlUlHoleIncr(db, prv);
6958 rgSCHUtlUlHoleUpdAllocLnks(prv, alloc->prv, alloc->nxt);
6962 /***********************************************************
6964 * Func : rgSCHUtlUlHoleExtndLeft
6966 * Desc : Extend hole due to alloc coming 'before' the hole
6975 **********************************************************/
6976 Void rgSCHUtlUlHoleExtndLeft(RgSchUlHoleDb *db,RgSchUlHole *nxt,RgSchUlAlloc *alloc)
6978 nxt->num += alloc->numSb;
6979 nxt->start = alloc->sbStart;
6980 rgSCHUtlUlHoleIncr(db, nxt);
6981 rgSCHUtlUlHoleUpdAllocLnks(nxt, alloc->prv, alloc->nxt);
6985 /***********************************************************
6987 * Func : rgSCHUtlUlHoleNew
6989 * Desc : Create new hole due to alloc being deleted
6997 **********************************************************/
6998 Void rgSCHUtlUlHoleNew(RgSchUlHoleDb *db,RgSchUlAlloc *alloc)
7000 RgSchUlHole *hole = rgSCHUtlUlHoleMemGet(&db->mem);
7001 #if (ERRCLASS & ERRCLS_DEBUG)
7002 if ( hole == NULLP )
7007 hole->start = alloc->sbStart;
7008 hole->num = alloc->numSb;
7010 rgSCHUtlUlHoleIns(db, hole);
7011 rgSCHUtlUlHoleUpdAllocLnks(hole, alloc->prv, alloc->nxt);
7015 /***********************************************************
7017 * Func : rgSCHUtlUlHoleUpdAllocLnks
7019 * Desc : Update alloc links in hole
7027 **********************************************************/
7028 Void rgSCHUtlUlHoleUpdAllocLnks(RgSchUlHole *hole,RgSchUlAlloc *prvAlloc,RgSchUlAlloc *nxtAlloc)
7032 prvAlloc->nxtHole = hole;
7036 nxtAlloc->prvHole = hole;
7038 hole->prvAlloc = prvAlloc;
7039 hole->nxtAlloc = nxtAlloc;
7044 /***********************************************************
7046 * Func : rgSCHUtlUlHoleIns
7048 * Desc : Insert (newly created) hole in sorted list of holes.
7049 * Searches linearly, beginning with the largest hole.
7057 **********************************************************/
7058 Void rgSCHUtlUlHoleIns(RgSchUlHoleDb *db,RgSchUlHole *hole)
7062 if ((cur = db->first) != NULLP)
7065 if (cur->num < hole->num)
7075 for (nxt = cur->nxt; nxt; cur = nxt, nxt = nxt->nxt)
7077 if (nxt->num < hole->num)
7079 /* Insert hole: cur <-> hole <-> nxt */
7095 /* This is the first hole */
7097 hole->prv = NULLP; /* may not be needed */
7103 /***********************************************************
7105 * Func : rgSCHUtlUlHoleIncr
7107 * Desc : hole->num has increeased, reposition in sorted
7116 **********************************************************/
7117 Void rgSCHUtlUlHoleIncr(RgSchUlHoleDb *db,RgSchUlHole *hole)
7121 if ((cur = hole->prv) != NULLP)
7125 if (cur->num > hole->num)
7130 /* Remove hole from current position */
7131 cur->nxt = hole->nxt;
7134 hole->nxt->prv = cur;
7137 for (prv = cur->prv; prv; cur = prv, prv = prv->prv)
7139 if (prv->num > hole->num)
7141 /* Insert hole: prv <-> hole <-> cur */
7160 /***********************************************************
7162 * Func : rgSCHUtlUlHoleDecr
7164 * Desc : hole->num has decreeased, reposition in sorted
7173 **********************************************************/
7174 Void rgSCHUtlUlHoleDecr(RgSchUlHoleDb *db,RgSchUlHole *hole)
7178 if ((cur = hole->nxt) != NULLP)
7182 if (cur->num < hole->num)
7187 /* Remove hole from current position */
7188 cur->prv = hole->prv;
7191 hole->prv->nxt = cur;
7193 else /* no prv, so cur to replace hole as first in list */
7198 for (nxt = cur->nxt; nxt; cur = nxt, nxt = nxt->nxt)
7200 if (nxt->num < hole->num)
7202 /* Insert hole: cur <-> hole <-> nxt */
7220 /***********************************************************
7222 * Func : rgSCHUtlUlHoleRls
7224 * Desc : Releases hole.
7225 * 1. Decrements hole count.
7226 * 2. Deletes hole from list.
7227 * 3. Frees hole (hole memory release).
7235 **********************************************************/
7236 Void rgSCHUtlUlHoleRls(RgSchUlHoleDb *db,RgSchUlHole *hole)
7238 RgSchUlHole *prv = hole->prv;
7239 RgSchUlHole *nxt = hole->nxt;
7259 rgSCHUtlUlHoleMemRls(&db->mem, hole);
7264 /***********************************************************
7266 * Func : rgSCHUtlUlAllocMemInit
7268 * Desc : Initialises alloc free pool
7270 * Ret : S16 (ROK/RFAILED)
7276 **********************************************************/
7277 S16 rgSCHUtlUlAllocMemInit(RgSchCellCb *cell,RgSchUlAllocMem *mem,uint8_t maxAllocs)
7280 RgSchUlAlloc *allocs;
7282 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&allocs,
7283 maxAllocs * sizeof(*allocs));
7288 mem->allocs = allocs;
7289 mem->maxAllocs = maxAllocs;
7290 if (mem->maxAllocs == 1)
7292 allocs[0].prv = NULLP;
7293 allocs[0].nxt = NULLP;
7298 allocs[0].prv = NULLP;
7299 allocs[0].nxt = &allocs[1];
7300 for (i = 1; i < mem->maxAllocs - 1; ++i)
7302 allocs[i].prv = &allocs[i-1];
7303 allocs[i].nxt = &allocs[i+1];
7305 allocs[i].prv = &allocs[i-1];
7306 allocs[i].nxt = NULLP;
7308 mem->firstFree = &allocs[0];
7312 /***********************************************************
7314 * Func : rgSCHUtlUlAllocMemDeinit
7316 * Desc : Deinitialises alloc free pool
7324 **********************************************************/
7325 Void rgSCHUtlUlAllocMemDeinit(RgSchCellCb *cell,RgSchUlAllocMem *mem)
7327 /* ccpu00117052 - MOD - Passing double pointer
7328 for proper NULLP assignment*/
7329 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(mem->allocs)),
7330 mem->maxAllocs * sizeof(*mem->allocs));
7332 mem->firstFree = NULLP;
7336 /***********************************************************
7338 * Func : rgSCHUtlUlHoleMemInit
7340 * Desc : Initialises hole free pool. Assumes maxHoles
7343 * Ret : S16 (ROK/RFAILED)
7349 **********************************************************/
7350 S16 rgSCHUtlUlHoleMemInit(RgSchCellCb *cell,RgSchUlHoleMem *mem,uint8_t maxHoles,RgSchUlHole **holeRef)
7355 ret = rgSCHUtlAllocSBuf(cell->instIdx, (Data **)&holes,
7356 maxHoles * sizeof(*holes));
7363 mem->maxHoles = maxHoles;
7365 /* first hole is taken up */
7366 holes[0].prv = NULLP; /* not needed */
7367 holes[0].nxt = NULLP; /* not needed */
7368 *holeRef = &holes[0];
7370 if (mem->maxHoles == 2)
7372 holes[1].prv = NULLP; /* may not be needed */
7373 holes[1].nxt = NULLP; /* may not be needed */
7378 holes[1].prv = NULLP;
7379 holes[0].nxt = &holes[1];
7380 for (i = 1; i < mem->maxHoles - 1; ++i)
7382 holes[i].prv = &holes[i-1];
7383 holes[i].nxt = &holes[i+1];
7385 holes[i].prv = &holes[i-1];
7386 holes[i].nxt = NULLP;
7388 mem->firstFree = &holes[1];
7393 /***********************************************************
7395 * Func : rgSCHUtlUlHoleMemDeinit
7397 * Desc : Deinitialises hole free pool
7405 **********************************************************/
7406 Void rgSCHUtlUlHoleMemDeinit(RgSchCellCb *cell,RgSchUlHoleMem *mem)
7408 /* ccpu00117052 - MOD - Passing double pointer
7409 for proper NULLP assignment*/
7410 rgSCHUtlFreeSBuf(cell->instIdx, (Data **)(&(mem->holes)),
7411 mem->maxHoles * sizeof(*mem->holes));
7413 mem->firstFree = NULLP;
7417 /***********************************************************
7419 * Func : rgSCHUtlUlAllocMemGet
7421 * Desc : Gets an 'alloc' from the free pool
7423 * Ret : RgSchUlAlloc *
7429 **********************************************************/
7430 RgSchUlAlloc *rgSCHUtlUlAllocMemGet(RgSchUlAllocMem *mem)
7432 RgSchUlAlloc *alloc;
7434 #if (ERRCLASS & ERRCLS_DEBUG)
7435 if (mem->firstFree == NULLP)
7441 alloc = mem->firstFree;
7442 mem->firstFree = alloc->nxt;
7443 alloc->nxt = NULLP; /* probably not needed */
7444 /* alloc->prv might already be NULLP, in case was needed to set it to NULLP */
7449 /***********************************************************
7451 * Func : rgSCHUtlUlAllocMemRls
7453 * Desc : Returns an 'alloc' to the free pool
7461 **********************************************************/
7462 Void rgSCHUtlUlAllocMemRls(RgSchUlAllocMem *mem,RgSchUlAlloc *alloc)
7466 alloc->nxt = mem->firstFree;
7467 if (mem->firstFree != NULLP)
7469 mem->firstFree->prv = alloc;
7471 mem->firstFree = alloc;
7475 /***********************************************************
7477 * Func : rgSCHUtlUlHoleMemGet
7479 * Desc : Gets a 'hole' from the free pool
7481 * Ret : RgSchUlHole *
7487 **********************************************************/
7488 RgSchUlHole *rgSCHUtlUlHoleMemGet(RgSchUlHoleMem *mem)
7492 #if (ERRCLASS & ERRCLS_DEBUG)
7493 if (mem->firstFree == NULLP)
7499 hole = mem->firstFree;
7500 mem->firstFree = hole->nxt;
7501 mem->firstFree->prv = NULLP; /* may not be needed, under error class */
7502 hole->nxt = NULLP; /* probably not needed */
7503 /* hole->prv is might already be NULLP, in case was needed to set it to NULLP */
7508 /***********************************************************
7510 * Func : rgSCHUtlUlHoleMemRls
7512 * Desc : Returns a 'hole' to the free pool
7520 **********************************************************/
7521 Void rgSCHUtlUlHoleMemRls(RgSchUlHoleMem *mem,RgSchUlHole *hole)
7525 hole->nxt = mem->firstFree;
7526 if (mem->firstFree != NULLP)
7528 mem->firstFree->prv = hole;
7530 mem->firstFree = hole;
7535 * @brief Get an alloc from the specified position in the BW.
7539 * Function : rgSCHUtlUlGetSpfcAlloc
7541 * - Return an alloc from the specified position in the BW.
7542 * Note: This function assumes there is always a hole
7543 * Existing which completely has the specified
7544 * allocation. The reason for such an assumption is
7545 * the function's usage as of now guarantees that there
7546 * will always be such hole. And also for efficiency.
7548 * @param[in] RgSchUlSf *sf
7549 * @param[in] uint8_t startSb
7550 * @param[in] uint8_t numSb
7551 * @return RgSchUlAlloc*
7553 RgSchUlAlloc *rgSCHUtlUlGetSpfcAlloc(RgSchUlSf *sf,uint8_t startSb,uint8_t numSb)
7555 RgSchUlHole *hole, *nxtHole;
7556 RgSchUlAlloc *alloc = NULLP;
7558 if ((hole = rgSCHUtlUlHoleFirst(sf)) == NULLP)
7564 nxtHole = rgSCHUtlUlHoleNxt(sf, hole);
7565 if ((startSb >= hole->start) &&
7566 (startSb+numSb <= hole->start+hole->num))
7568 if (startSb != hole->start)
7570 /* Create a new hole to accomodate Subbands between
7571 * hole start and req alloc start */
7572 RgSchUlHole *newHole = rgSCHUtlUlHoleMemGet(&(sf->holeDb->mem));
7574 #if (ERRCLASS & ERRCLS_DEBUG)
7575 if ( newHole == NULLP )
7580 newHole->start = hole->start;
7581 newHole->num = startSb - hole->start;
7582 hole->start = startSb;
7583 /* [ccpu00122847]-MOD- Correctly updating the hole->num */
7584 hole->num -= newHole->num;
7585 ++(sf->holeDb->count);
7586 rgSCHUtlUlHoleIns(sf->holeDb, newHole);
7587 newHole->prvAlloc = hole->prvAlloc;
7588 if (newHole->prvAlloc)
7590 newHole->prvAlloc->nxtHole = newHole;
7592 if (numSb == hole->num)
7594 alloc = rgSCHUtlUlAllocGetCompHole(sf, hole);
7598 alloc = rgSCHUtlUlAllocGetPartHole(sf, numSb, hole);
7600 alloc->prvHole = newHole;
7601 newHole->nxtAlloc = alloc;
7603 else /* Hole start and req alloc start are same */
7605 if (numSb == hole->num)
7607 alloc = rgSCHUtlUlAllocGetCompHole(sf, hole);
7611 alloc = rgSCHUtlUlAllocGetPartHole(sf, numSb, hole);
7616 } while ((hole = nxtHole) != NULLP);
7621 * @brief Validates the qci values
7625 * Function :rgSCHUtlValidateQci
7627 * @param[in] RgSchCellCb *cellCb
7628 * @param[in] uint8_t numQci
7629 * @param[out] uint8_t *qci
7634 static S16 rgSCHUtlValidateQci(RgSchCellCb *cellCb,uint8_t numQci,uint8_t *qci)
7639 for(qciIdx = 0; qciIdx < numQci; qciIdx++)
7641 qciVal = qci[qciIdx];
7642 if(qciVal == 0 || qciVal > 9)
7646 if(qciVal != cellCb->qciArray[qciVal].qci)
7653 }/* rgSCHUtlValidateQci */
7655 * @brief Validates the measurement request parameters.
7659 * Function :rgSCHUtlValidateMeasReq
7661 * @param[in] RgSchCellCb *cellCb
7662 * @param[in] LrgSchMeasReqInfo *schL2MeasInfo
7663 * @param[out] RgSchErrInfo *err
7664 * @return RgSchUlAlloc*
7666 S16 rgSCHUtlValidateMeasReq(RgSchCellCb *cellCb, LrgSchMeasReqInfo *schL2MeasInfo,RgSchErrInfo *err)
7671 measType = schL2MeasInfo->measType;
7672 if((measType == 0) ||
7675 err->errType = RGSCHERR_SCH_INVALID_MEAS_TYPE;
7676 err->errCause = RGSCHERR_SCH_L2MEAS;
7679 if((schL2MeasInfo->timePrd !=0) &&
7680 (measType & LRG_L2MEAS_AVG_PRB_PER_QCI_DL) &&
7681 ((schL2MeasInfo->avgPrbQciDl.numQci > LRG_MAX_QCI_PER_REQ)||
7682 (schL2MeasInfo->avgPrbQciDl.numQci == 0)))
7684 err->errType = RGSCHERR_SCH_INVALID_PARAM_RANGE;
7685 err->errCause = RGSCHERR_SCH_L2MEAS;
7688 if((schL2MeasInfo->timePrd !=0) &&
7689 (measType & LRG_L2MEAS_AVG_PRB_PER_QCI_UL) &&
7690 (schL2MeasInfo->avgPrbQciUl.numQci > LRG_MAX_QCI_PER_REQ))
7692 err->errType = RGSCHERR_SCH_INVALID_PARAM_RANGE;
7693 err->errCause = RGSCHERR_SCH_L2MEAS;
7696 if((measType & LRG_L2MEAS_NMB_ACTV_UE_PER_QCI_DL) &&
7697 ((schL2MeasInfo->nmbActvUeQciDl.numQci > LRG_MAX_QCI_PER_REQ) ||
7698 (schL2MeasInfo->nmbActvUeQciDl.sampPrd == 0)||
7699 ((schL2MeasInfo->timePrd !=0)&&
7700 (schL2MeasInfo->timePrd < schL2MeasInfo->nmbActvUeQciDl.sampPrd)) ||
7701 (schL2MeasInfo->nmbActvUeQciDl.sampPrd > LRG_MAX_SAMP_PRD)))
7703 err->errType = RGSCHERR_SCH_INVALID_PARAM_RANGE;
7704 err->errCause = RGSCHERR_SCH_L2MEAS;
7707 if((measType & LRG_L2MEAS_NMB_ACTV_UE_PER_QCI_UL) &&
7708 ((schL2MeasInfo->nmbActvUeQciUl.numQci > LRG_MAX_QCI_PER_REQ) ||
7709 (schL2MeasInfo->nmbActvUeQciUl.sampPrd == 0)||
7710 ((schL2MeasInfo->timePrd !=0) &&
7711 (schL2MeasInfo->timePrd < schL2MeasInfo->nmbActvUeQciUl.sampPrd)) ||
7712 (schL2MeasInfo->nmbActvUeQciUl.sampPrd > LRG_MAX_SAMP_PRD)))
7714 err->errType = RGSCHERR_SCH_INVALID_PARAM_RANGE;
7715 err->errCause = RGSCHERR_SCH_L2MEAS;
7718 if((schL2MeasInfo->timePrd !=0) &&
7719 (measType & LRG_L2MEAS_AVG_PRB_PER_QCI_DL))
7721 RGSCH_ARRAY_BOUND_CHECK(cellCb->instIdx, schL2MeasInfo->avgPrbQciDl.qci, \
7722 (schL2MeasInfo->avgPrbQciDl.numQci));
7723 ret = rgSCHUtlValidateQci(cellCb, schL2MeasInfo->avgPrbQciDl.numQci,
7724 schL2MeasInfo->avgPrbQciDl.qci);
7727 err->errType = RGSCHERR_SCH_INVALID_QCI_VAL;
7728 err->errCause = RGSCHERR_SCH_L2MEAS;
7733 }/* rgSCHUtlValidateMeasReq */
7734 #endif /* LTE_L2_MEAS */
7735 /******* </AllocHolesMemMgmnt>: END *****/
7738 * @brief API for sending SI configuration confirm from Scheduler to RRM
7742 * Function: rgSCHUtlRgrSiCfgCfm
7744 * This API is invoked to send SI configuration confirm from Scheduler
7746 * This API fills in Pst structure and SAP Ids and invokes
7747 * config confirm API towards RRM.
7749 * @param[in] RgrCfgTransId transId
7750 * @param[in] uint8_t status
7755 S16 rgSCHUtlRgrSiCfgCfm(Inst instId,SpId spId,RgrCfgTransId transId,uint8_t status)
7757 uint8_t prntTrans[RGR_CFG_TRANSID_SIZE+1];
7759 memcpy(prntTrans, transId.trans, RGR_CFG_TRANSID_SIZE);
7760 prntTrans[RGR_CFG_TRANSID_SIZE] = '\0';
7761 if(RgUiRgrSiCfgCfm(&rgSchCb[instId].rgrSap[spId].sapCfg.sapPst,
7762 rgSchCb[instId].rgrSap[spId].sapCfg.suId,
7763 transId, status) != ROK)
7765 DU_LOG("\nERROR --> SCH : rgSCHUtlRgrSiCfgCfm: "
7766 "RgUiRgrSiCfgCfm Failed ");
7771 } /* rgSCHUtlRgrSiCfgCfm */
7775 * @brief API for sending Warning SI configuration confirm from
7781 * This API is invoked to send Warning SI configuration confirm
7782 * from Scheduler to RRM.
7783 * This API fills in Pst structure and SAP Ids and invokes
7784 * config confirm API towards RRM.
7786 * @param[in] RgrCfgTransId transId
7787 * @param[in] uint8_t status
7792 S16 rgSCHUtlRgrWarningSiCfgCfm(Inst instId,SpId spId,uint8_t siId,RgrCfgTransId transId,uint8_t status)
7794 uint8_t prntTrans[RGR_CFG_TRANSID_SIZE+1];
7796 memcpy(prntTrans, transId.trans, RGR_CFG_TRANSID_SIZE);
7797 prntTrans[RGR_CFG_TRANSID_SIZE] = '\0';
7799 if(RgUiRgrWarningSiCfgCfm(&rgSchCb[instId].rgrSap[spId].sapCfg.sapPst,
7800 rgSchCb[instId].rgrSap[spId].sapCfg.suId,
7801 transId, siId, status) != ROK)
7803 DU_LOG("\nERROR --> SCH : rgSCHUtlRgrSiCfgCfm: "
7804 "RgUiRgrSiCfgCfm Failed ");
7809 } /* rgSCHUtlRgrWarningSiCfgCfm */
7811 /***********************************************************
7813 * Func : rgSCHUtlPutSiInfo
7815 * Desc : Utility Function to deallocate SI information
7823 **********************************************************/
7824 Void rgSCHUtlPutSiInfo(RgSchCellCb *cell)
7827 uint32_t sizeOfSiInfo = 0;
7828 /*Free the buffers in crntSiInfo*/
7829 RGSCH_FREE_MSG(cell->siCb.crntSiInfo.mib)
7830 RGSCH_FREE_MSG(cell->siCb.crntSiInfo.sib1Info.sib1)
7832 sizeOfSiInfo = sizeof(cell->siCb.crntSiInfo.siInfo)/sizeof(cell->siCb.crntSiInfo.siInfo[0]);
7834 for(idx=0; idx < sizeOfSiInfo; idx++)
7836 RGSCH_FREE_MSG(cell->siCb.crntSiInfo.siInfo[idx].si)
7839 /*Free the buffers in newSiInfo */
7840 RGSCH_FREE_MSG(cell->siCb.newSiInfo.mib)
7841 RGSCH_FREE_MSG(cell->siCb.newSiInfo.sib1Info.sib1)
7843 sizeOfSiInfo = sizeof(cell->siCb.newSiInfo.siInfo)/sizeof(cell->siCb.newSiInfo.siInfo[0]);
7845 for(idx=0; idx < sizeOfSiInfo; idx++)
7847 RGSCH_FREE_MSG(cell->siCb.newSiInfo.siInfo[idx].si)
7852 #endif /*RGR_SI_SCH */
7856 /***********************************************************
7858 * Func : rgSCHUtlGetDrxSchdUesInDl
7860 * Desc : Utility Function to fill the get the list of
7861 * scheduled UEs. On these UE's, drx-inactivity
7862 * timer will be started/restarted.
7871 **********************************************************/
7872 S16 rgSCHUtlGetDrxSchdUesInDl
7874 RgSchCellCb *cellCb,
7876 RgSchDlHqProcCb *dlHq,
7877 RgInfUeAlloc *allocInfo,
7878 CmLListCp *dlDrxInactvTmrLst,
7879 CmLListCp *dlInActvLst,
7880 CmLListCp *ulInActvLst
7883 Bool isNewTx = FALSE;
7885 RgSchDrxDlHqProcCb *drxHq;
7886 RgSchDRXCellCb *drxCell = cellCb->drxCb;
7887 RgSchDrxUeCb *drxUe;
7888 uint8_t cellIdx = ueCb->cellIdToCellIdxMap[RG_SCH_CELLINDEX(dlHq->hqE->cell)];
7889 uint32_t dlInactvMask;
7890 uint32_t ulInactvMask;
7892 for(idx = 0; idx < allocInfo->nmbOfTBs; idx++)
7894 if(allocInfo->tbInfo[idx].isReTx == FALSE)
7897 /* Removing break here, since in 2 TB case if 2nd TB is proceeding with
7898 retx then drxretx timer should be stopped.*/
7902 /*Stop the DRX retransmission timer as UE scheduled for retx. Here
7903 * we stop the timer and inactivate the UE for both UL and DL.
7904 * This may result in loss of one slot for UL but this trade
7905 * off is taken to avoid the overhead of maintaining a list of UEs
7906 * to be inactivated in the next slot.*/
7907 drxHq = RG_SCH_DRX_GET_DL_HQ(dlHq);
7908 drxUe = RG_SCH_DRX_GET_UE(ueCb);
7909 if(drxHq->reTxIndx != DRX_INVALID)
7911 /* This condition should never occur */
7912 if(drxHq->reTxIndx >= RG_SCH_MAX_DRXQ_SIZE)
7914 DU_LOG("\nERROR --> SCH : [%d]UE:DRXUE RETX IDX[%d]"
7915 "is out of bound,dlInactvMask %d,procId %d\n", ueCb->ueId,
7916 drxHq->reTxIndx,ueCb->dl.dlInactvMask, dlHq->procId);
7919 drxUe->drxDlInactvMaskPerCell[cellIdx] |= (RG_SCH_DRX_DLHQ_BITMASK << dlHq->procId);
7920 drxUe->drxUlInactvMaskPerCell[cellIdx] |= (RG_SCH_DRX_DLHQ_BITMASK << dlHq->procId);
7922 dlInactvMask = RG_SCH_DRX_DLHQ_BITMASK << dlHq->procId;
7923 ulInactvMask = RG_SCH_DRX_DLHQ_BITMASK << dlHq->procId;
7925 for(cellIdx = 0; cellIdx < CM_LTE_MAX_CELLS; cellIdx++)
7927 dlInactvMask &= drxUe->drxDlInactvMaskPerCell[cellIdx];
7928 ulInactvMask &= drxUe->drxUlInactvMaskPerCell[cellIdx];
7931 drxUe->drxDlInactvMask |= dlInactvMask;
7932 drxUe->drxUlInactvMask |= ulInactvMask;
7934 /* if no other condition is keeping ue active,
7937 if(!RG_SCH_DRX_DL_IS_UE_ACTIVE(drxUe))
7939 /* BUG 2 : HARQ_RTT, changed for consistency */
7940 ueCb->dl.dlInactvMask |= (RG_DRX_INACTIVE);
7942 /* Add to DL inactive list */
7943 cmLListAdd2Tail(dlInActvLst,&(ueCb->dlDrxInactvLnk));
7944 ueCb->dlDrxInactvLnk.node = (PTR)ueCb;
7947 if(!RG_SCH_DRX_UL_IS_UE_ACTIVE(drxUe))
7949 /*BUG 2: HARQ_RTT changed for consistency */
7950 ueCb->ul.ulInactvMask |= (RG_DRX_INACTIVE);
7952 cmLListAdd2Tail(ulInActvLst,&(ueCb->ulDrxInactvLnk));
7953 ueCb->ulDrxInactvLnk.node = (PTR)ueCb;
7956 /* Deleting entry from HARQ RTT queue for the same HARQ proc,
7957 * if exist. This is the special case which can happen iF UL
7958 * scheduling is done later. */
7959 if(drxHq->rttIndx != DRX_INVALID)
7961 cmLListDelFrm (&(cellCb->drxCb->drxQ[drxHq->rttIndx].harqRTTQ),
7962 &(drxHq->harqRTTEnt));
7964 drxHq->rttIndx = DRX_INVALID;
7967 cmLListDelFrm (&(drxCell->drxQ[drxHq->reTxIndx].harqRetxQ),
7968 &(drxHq->harqRetxEnt));
7969 drxHq->reTxIndx = DRX_INVALID;
7976 if(ueCb->drxCb->raRcvd == TRUE)
7978 ueCb->drxCb->raRcvd = FALSE;
7980 /* mark the ra bit */
7981 ueCb->drxCb->drxUlInactvMask |= RG_SCH_DRX_RA_BITMASK;
7982 ueCb->drxCb->drxDlInactvMask |= RG_SCH_DRX_RA_BITMASK;
7984 }/*if(ra->rcvd) == TRUE */
7986 if(ueCb->dlDrxInactvTmrLnk.node == NULLP)
7988 cmLListAdd2Tail(dlDrxInactvTmrLst,&(ueCb->dlDrxInactvTmrLnk));
7989 ueCb->dlDrxInactvTmrLnk.node = (PTR)ueCb;
7991 }/*if(isNewTx == TRUE) */
7994 }/* rgSCHUtlGetSchdUes*/
7996 /* ccpu00117452 - MOD - Changed macro name from
7997 RGR_RRM_DLPWR_CNTRL to RGR_CQI_REPT */
8000 * @brief This function fills StaInd struct
8004 * Function: rgSCHUtlFillSndStaInd
8005 * Purpose: Fills StaInd struct and sends the
8008 * @param[in] RgSchCellCb *cell pointer to Cell Control block
8009 * @param[in] RgSchUeCb *ue pointer to Ue Control block
8010 * @param[in] RgrStaIndInfo *staInfo Sta Ind struct to be filled
8011 * @param[in] uint8_t numCqiRept NUmber of reports to be filled
8015 S16 rgSCHUtlFillSndStaInd(RgSchCellCb *cell,RgSchUeCb *ue,RgrStaIndInfo *staInfo,uint8_t numCqiRept)
8019 /* Fill StaInd for sending collated Latest N CQI rpeorts */
8020 /* Find index in the array from where Latest N
8021 reports needs to be fetched. Use this value to index in the array
8022 and copy the reports into staInfo */
8024 /* Fill the Cell Id of PCC of the UE */
8025 staInfo->cellId = ue->cell->cellId;
8026 staInfo->crnti = ue->ueId;
8028 idxStart = ue->schCqiInfo.cqiCount - numCqiRept;
8030 memcpy (&(staInfo->ueCqiInfo.cqiRept),
8031 &(ue->schCqiInfo.cqiRept[idxStart]),
8032 numCqiRept * sizeof(RgrUeCqiRept));
8034 staInfo->ueCqiInfo.numCqiRept = numCqiRept;
8036 ue->schCqiInfo.cqiCount = 0;
8038 /* Call utility function (rgSCHUtlRgrStaInd) to send rpts to RRM */
8039 if(rgSCHUtlRgrStaInd(cell, staInfo) != ROK)
8041 DU_LOG("\nERROR --> SCH : Could not send "
8042 "CQI reports for RNTI:%d",ue->ueId);
8048 }/* End of rgSCHUtlFillSndStaInd */
8053 * @brief API for sending STA indication from Scheduler to RRM.
8057 * Function: rgSCHUtlRgrStaInd
8059 * This API is invoked to send STA indication from Scheduler instance to RRM.
8060 * This API fills in Pst structure and RgrStaIndInfo
8061 * and calls the Sta primitive API towards RRM.
8063 * @param[in] cell RgSchCellCb
8064 * @param[in] RgrStsIndInfo *rgrSta
8069 S16 rgSCHUtlRgrStaInd(RgSchCellCb *cell,RgrStaIndInfo *rgrSta)
8072 RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
8074 rgrSap = cell->rgrSap;
8075 if (rgrSap->sapSta.sapState != LRG_BND)
8077 DU_LOG("\nERROR --> SCH : rgSCHUtlRgrStaInd() Upper SAP not bound (%d) ",
8078 rgrSap->sapSta.sapState);
8081 RgUiRgrStaInd(&(cell->rgrSap->sapCfg.sapPst),
8082 cell->rgrSap->sapCfg.suId, rgrSta);
8084 } /* rgSCHUtlRgrStaInd*/
8085 #endif /* End of RGR_CQI_REPT */
8087 /* Fix : syed HO UE does not have a valid ue->rntiLnk */
8089 * @brief Indicates MAC to release any rnti context it has.
8092 * Function : rgSCHUtlIndRntiRls2Mac
8093 * This function indicates MAC for this rnti release.
8094 * In case of ueId change it will indicate MAC
8095 * about the new rnti to be updated.
8096 * It will post a release RNTI indication to MAC.
8100 * @param[in] RgSchCellCb *cell
8101 * @param[in] CmLteRnti rnti
8102 * @param[in] Bool ueIdChng
8103 * @param[in] CmLteRnti newRnti
8107 Void rgSCHUtlIndRntiRls2Mac(RgSchCellCb *cell,CmLteRnti rnti,Bool ueIdChng,CmLteRnti newRnti)
8110 Inst inst = cell->instIdx;
8111 RgInfRlsRnti rntiInfo;
8114 /* Copy the info to rntiInfo */
8115 rntiInfo.cellId = cell->cellId;
8116 rntiInfo.rnti = rnti;
8117 /* Fix : syed ueId change as part of reestablishment.
8118 * Now SCH to trigger this. CRG ueRecfg for ueId change
8120 rntiInfo.ueIdChng = ueIdChng;
8121 rntiInfo.newRnti = newRnti;
8123 rntiInfo.isUeSCellDel = FALSE;
8125 /* Invoke MAC to release the rnti */
8126 rgSCHUtlGetPstToLyr(&pst, &rgSchCb[inst], cell->macInst);
8127 RgSchMacRlsRnti(&pst, &rntiInfo);
8131 /* LTE_ADV_FLAG_REMOVED_START */
8133 * @brief API for sending LOAD INF indication from Scheduler to RRM.
8136 * Function: rgSCHUtlRgrLoadInfInd
8138 * This API is invoked to send LOAD INF indication from Scheduler instance to RRM.
8139 * This API fills in Pst structure and RgrLoadInfIndInfo
8140 * and calls the Sta primitive API towards RRM.
8142 * @param[in] cell RgSchCellCb
8143 * @param[in] RgrLoadInfIndInfo *rgrLoadInf
8148 S16 rgSCHUtlRgrLoadInfInd(RgSchCellCb *cell,RgrLoadInfIndInfo *rgrLoadInf)
8151 RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
8153 rgrSap = cell->rgrSap;
8154 if (rgrSap->sapSta.sapState != LRG_BND)
8156 DU_LOG("\nERROR --> SCH : rgSCHUtlRgrLoadInfInd() Upper SAP not bound (%d) ",
8157 rgrSap->sapSta.sapState);
8160 RgUiRgrLoadInfInd(&(cell->rgrSap->sapCfg.sapPst),
8161 cell->rgrSap->sapCfg.suId, rgrLoadInf);
8163 } /* rgSCHUtlRgrLoadInfInd*/
8164 /* LTE_ADV_FLAG_REMOVED_END */
8166 /* MS_FIX : syed SCH to act as MASTER in maintaining
8167 * rnti related context. Trigger to rnti del/Chng at SCH
8168 * will result in a Indication to MAC to release its
8169 * RNTI context. MAC inturn indicates the context cleared
8170 * indication to SCH, upon which SCH would set this
8172 * @brief API for sending STA indication from Scheduler to RRM.
8176 * Function: rgSCHUtlRlsRnti
8178 * This API is invoked to indicate MAC to release rnti
8180 * @param[in] RgSchCellCb *cellCb
8181 * @param[in] RgSchRntiLnk *rntiLnk,
8182 * @param[in] Bool ueIdChngd,
8183 * @param[in] CmLteRnti newRnti
8187 Void rgSCHUtlRlsRnti(RgSchCellCb *cell,RgSchRntiLnk *rntiLnk,Bool ueIdChngd,CmLteRnti newRnti)
8190 uint8_t isLegacy = 0;
8192 if(cell->emtcEnable)
8194 rgSCHEmtcUtlRlsRnti(cell, rntiLnk, &isLegacy);
8199 /*Add to Guard Pool*/
8200 cmLListAdd2Tail(&cell->rntiDb.rntiGuardPool, &rntiLnk->rntiGrdPoolLnk);
8201 rntiLnk->rntiGrdPoolLnk.node = (PTR)rntiLnk;
8203 /* Fix: syed Explicitly Inidcate MAC to release RNTI */
8204 rgSCHUtlIndRntiRls2Mac(cell, rntiLnk->rnti, ueIdChngd, newRnti);
8211 * @brief This function fills StaInd struct
8215 * Function: rgSCHUtlFillSndUeStaInd
8216 * Purpose: Fills StaInd struct and sends the
8219 * @param[in] RgSchCellCb *cell pointer to Cell Control block
8220 * @param[in] RgSchUeCb *ue pointer to Ue Control block
8221 * @param[in] uint8_t numCqiRept NUmber of reports to be filled
8225 S16 rgSCHUtlFillSndUeStaInd(RgSchCellCb *cell,RgSchUeCb *ue,RgrUeStaIndInfo *ueStaInfo)
8228 ueStaInfo->cellId = cell->cellId;
8229 ueStaInfo->crnti = ue->ueId;
8231 /* Call utility function (rgSCHUtlRgrUeStaInd) to send rpts to RRM */
8232 if(rgSCHUtlRgrUeStaInd(cell, ueStaInfo) != ROK)
8234 DU_LOG("\nERROR --> SCH : Could not send "
8235 "UE Sta reports CRNTI:%d",ue->ueId);
8241 }/* End of rgSCHUtlFillSndStaInd */
8246 * @brief API for sending STA indication from Scheduler to RRM.
8250 * Function: rgSCHUtlRgrStaInd
8252 * This API is invoked to send STA indication from Scheduler instance to RRM.
8253 * This API fills in Pst structure and RgrStaIndInfo
8254 * and calls the Sta primitive API towards RRM.
8256 * @param[in] cell RgSchCellCb
8257 * @param[in] RgrStsIndInfo *rgrSta
8262 S16 rgSCHUtlRgrUeStaInd(RgSchCellCb *cell,RgrUeStaIndInfo *rgrUeSta)
8265 RgSchUpSapCb *rgrSap; /*!< RGR SAP Control Block */
8267 rgrSap = cell->rgrSap;
8268 if (rgrSap->sapSta.sapState != LRG_BND)
8270 DU_LOG("\nERROR --> SCH : rgSCHUtlRgrUeStaInd() Upper SAP not bound (%d) ",
8271 rgrSap->sapSta.sapState);
8274 RgUiRgrUeStaInd(&(cell->rgrSap->sapCfg.sapPst),
8275 cell->rgrSap->sapCfg.suId, rgrUeSta);
8277 } /* rgSCHUtlRgrStaInd*/
8281 * @brief function to report DL and UL PRB usage to RRM.
8284 * Function: rgSCHUtlUpdAvgPrbUsage
8285 * This function sends the PRB usage report to
8286 * RRM with the interval configured by RRM.
8288 * @param[in] cell *RgSchCellCb
8293 S16 rgSCHUtlUpdAvgPrbUsage(RgSchCellCb *cell)
8295 CmLteTimingInfo frm;
8296 RgmPrbRprtInd *prbRprtInd;
8299 #ifdef DBG_MAC_RRM_PRB_PRINT
8300 static uint32_t count = 0;
8301 const uint32_t reprotForEvery20Sec = 20000/cell->prbUsage.rprtPeriod;
8306 frm = cell->crntTime;
8307 RGSCH_INCR_SUB_FRAME(frm, RG_SCH_CMN_DL_DELTA);
8313 if(cell->prbUsage.rprtPeriod >= RGSCH_NUM_SUB_FRAMES)
8315 /* Get the total number of DL and UL slots within the reporting period*/
8316 numDlSf = (cell->prbUsage.rprtPeriod *
8317 rgSchTddNumDlSubfrmTbl[cell->ulDlCfgIdx][RGSCH_NUM_SUB_FRAMES-1])
8318 / RGSCH_NUM_SUB_FRAMES;
8319 numUlSf = (cell->prbUsage.rprtPeriod *
8320 rgSchTddNumUlSubfrmTbl[cell->ulDlCfgIdx][RGSCH_NUM_SUB_FRAMES-1])
8321 / RGSCH_NUM_SUB_FRAMES;
8325 /* Get the total number of DL and UL slots < 10 ms interval */
8326 numDlSf = rgSchTddNumDlSubfrmTbl[cell->ulDlCfgIdx][frm.slot];
8327 numUlSf = rgSchTddNumUlSubfrmTbl[cell->ulDlCfgIdx][frm.slot];
8330 numDlSf = cell->prbUsage.rprtPeriod;
8331 numUlSf = cell->prbUsage.rprtPeriod;
8334 if(SGetSBuf(cell->rgmSap->sapCfg.sapPst.region,
8335 cell->rgmSap->sapCfg.sapPst.pool, (Data**)&prbRprtInd,
8336 sizeof(RgmPrbRprtInd)) != ROK)
8341 memset(&prbRprtInd->stQciPrbRpts[0],
8343 (RGM_MAX_QCI_REPORTS * sizeof(RgmPrbRptPerQci)));
8345 prbRprtInd->bCellId = cell->cellId;
8349 prbRprtInd->bPrbUsageMask |= RGM_PRB_USAGE_DL;
8350 for (idx = 0; idx < RGM_MAX_QCI_REPORTS; idx++ )
8352 prbRprtInd->stQciPrbRpts[idx].bAvgPrbDlUsage =
8353 RGSCH_DIV_ROUND((cell->prbUsage.qciPrbRpts[idx].dlTotPrbUsed*100),
8354 (numDlSf * cell->bwCfg.dlTotalBw));
8355 prbRprtInd->stQciPrbRpts[idx].bQci = cell->prbUsage.qciPrbRpts[idx].qci;
8356 cell->prbUsage.qciPrbRpts[idx].dlTotPrbUsed = 0;
8362 prbRprtInd->bPrbUsageMask |= RGM_PRB_USAGE_UL;
8363 for (idx = 0; idx < RGM_MAX_QCI_REPORTS; idx++ )
8365 prbRprtInd->stQciPrbRpts[idx].bAvgPrbUlUsage =
8366 RGSCH_DIV_ROUND((cell->prbUsage.qciPrbRpts[idx].ulTotPrbUsed*100),
8367 (numUlSf * cell->ulAvailBw));
8368 prbRprtInd->stQciPrbRpts[idx].bQci = cell->prbUsage.qciPrbRpts[idx].qci;
8369 cell->prbUsage.qciPrbRpts[idx].ulTotPrbUsed = 0;
8373 #ifdef DBG_MAC_RRM_PRB_PRINT
8374 if((count % reprotForEvery20Sec) == 0 )
8376 DU_LOG("\n====================================================================");
8377 DU_LOG("\nINFO --> SCH : QCI-1[DL:UL] | QCI-2[DL:UL] | QCI-3[DL:UL] | QCI-4[DL:UL] \n");
8378 DU_LOG("======================================================================\n");
8379 DU_LOG(" [%d: %d]\t | [%d: %d]\t | [%d: %d]\t| [%d: %d]\t\n",
8380 prbRprtInd->stQciPrbRpts[0].bAvgPrbDlUsage,
8381 prbRprtInd->stQciPrbRpts[0].bAvgPrbUlUsage,
8382 prbRprtInd->stQciPrbRpts[1].bAvgPrbDlUsage,
8383 prbRprtInd->stQciPrbRpts[1].bAvgPrbUlUsage,
8384 prbRprtInd->stQciPrbRpts[2].bAvgPrbDlUsage,
8385 prbRprtInd->stQciPrbRpts[2].bAvgPrbUlUsage,
8386 prbRprtInd->stQciPrbRpts[3].bAvgPrbDlUsage,
8387 prbRprtInd->stQciPrbRpts[3].bAvgPrbUlUsage);
8390 RgUiRgmSendPrbRprtInd(&(cell->rgmSap->sapCfg.sapPst),
8391 cell->rgmSap->sapCfg.suId, prbRprtInd);
8399 * @brief This function resends the Ta in case of
8400 * max retx failure or DTX for the Ta transmitted
8404 * Function: rgSCHUtlReTxTa
8407 * @param[in] RgSchCellCb *cell
8408 * @param[in] RgSchUeCb *ue
8412 Void rgSCHUtlReTxTa(RgSchCellCb *cellCb,RgSchUeCb *ueCb)
8415 /* If TA Timer is running. Stop it */
8416 if (ueCb->taTmr.tmrEvnt != TMR_NONE)
8418 rgSCHTmrStopTmr(cellCb, ueCb->taTmr.tmrEvnt, ueCb);
8420 /*[ccpu00121813]-ADD-If maxretx is reached then
8421 * use outstanding TA val for scheduling again */
8422 if(ueCb->dl.taCb.outStndngTa == TRUE)
8424 ueCb->dl.taCb.ta = ueCb->dl.taCb.outStndngTaval;
8425 ueCb->dl.taCb.outStndngTaval = RGSCH_NO_TA_RQD;
8426 ueCb->dl.taCb.outStndngTa = FALSE;
8429 /* Fix : syed TA state updation missing */
8430 ueCb->dl.taCb.state = RGSCH_TA_TOBE_SCHEDULED;
8431 rgSCHUtlDlTARpt(cellCb, ueCb);
8436 /* Added function for dropping Paging Message*/
8438 * @brief Handler for BO Updt received for BCCH or PCCH.
8442 * Function : rgSCHChkBoUpdate
8444 * This function shall check for BO received falls within the scheduling window or not
8447 * @param[in] RgSchCellCb *cell
8452 static S16 rgSCHChkBoUpdate(RgSchCellCb *cell,RgInfCmnBoRpt *boUpdt)
8455 uint32_t crntTimeInSubFrms = 0;
8456 uint32_t boUpdTimeInSubFrms = 0;
8457 uint32_t distance = 0;
8459 crntTimeInSubFrms = (cell->crntTime.sfn * RGSCH_NUM_SUB_FRAMES_5G) + cell->crntTime.slot +
8460 RG_SCH_CMN_DL_DELTA + 2; /* As bo received will scheduled in next TTI
8461 so incrementing with +1 more */
8462 boUpdTimeInSubFrms = (boUpdt->u.timeToTx.sfn * RGSCH_NUM_SUB_FRAMES_5G)+ boUpdt->u.timeToTx.slot;
8465 distance = boUpdTimeInSubFrms > crntTimeInSubFrms ? \
8466 boUpdTimeInSubFrms - crntTimeInSubFrms : \
8467 (RGSCH_MAX_SUBFRM_5G - crntTimeInSubFrms + boUpdTimeInSubFrms);
8469 if (distance > RGSCH_PCCHBCCH_WIN)
8475 }/*rgSCHChkBoUpdate*/
8480 * @brief Utility function to calculate the UL reTxIdx in TDD cfg0
8484 * Function : rgSchUtlCfg0ReTxIdx
8486 * Update the reTxIdx according to the rules mentioned
8487 * in 3GPP TS 36.213 section 8 for TDD Cfg0
8489 * @param[in] RgSchCellCb *cell
8490 * @param[in] CmLteTimingInfo phichTime
8491 * @param[in] uint8_t hqFdbkIdx
8494 uint8_t rgSchUtlCfg0ReTxIdx(RgSchCellCb *cell,CmLteTimingInfo phichTime,uint8_t hqFdbkIdx)
8496 uint8_t reTxIdx = RGSCH_INVALID_INFO;
8498 RgSchCmnUlCell *cellUl = RG_SCH_CMN_GET_UL_CELL(cell);
8500 uint8_t ulSF; /* UL SF in the TDD frame */
8502 ulSf = &cellUl->ulSfArr[hqFdbkIdx];
8503 ulSF = ulSf->ulSfIdx;
8505 /* Check for the UL SF 4 or 9 */
8506 if(ulSF == 9 || ulSF == 4)
8510 if(phichTime.slot == 0 || phichTime.slot == 5)
8514 /* Retx will happen according to the Pusch k table */
8515 reTxIdx = cellUl->schdIdx;
8519 /* Retx will happen at n+7 */
8520 RGSCHCMNADDTOCRNTTIME(phichTime, phichTime, 7);
8521 /* Fetch the corresponding UL slot Idx in UL sf array */
8522 reTxIdx = rgSCHCmnGetUlSfIdx(&phichTime, cell);
8525 else if(phichTime.slot == 1 || phichTime.slot == 6)
8527 /* Retx will happen at n+7 */
8528 RGSCHCMNADDTOCRNTTIME(phichTime, phichTime, 7);
8529 /* Fetch the corresponding UL slot Idx in UL sf array */
8530 reTxIdx = rgSCHCmnGetUlSfIdx(&phichTime, cell);
8537 * @brief Utility function to calculate total num of PRBs required to
8538 * satisfy DL BO for TM1/TM2/TM6/TM7
8542 * Function : rgSchUtlDlCalc1CwPrb
8544 * Calculate PRBs required for UE to satisfy BO in DL
8546 * Note : Total calculated PRBs will be assigned to *prbReqrd
8549 * @param[in] RgSchCellCb *cell
8550 * @param[in] RgSchUeCb *ue
8551 * @param[in] uint32_t bo
8552 * @param[out] uint32_t *prbReqrd
8555 Void rgSchUtlDlCalc1CwPrb(RgSchCellCb *cell,RgSchUeCb *ue,uint32_t bo,uint32_t *prbReqrd)
8557 RgSchCmnDlCell *dlCell = RG_SCH_CMN_GET_DL_CELL(cell);
8558 RgSchCmnDlUe *dlUe = RG_SCH_CMN_GET_DL_UE(ue, cell);
8562 uint8_t cfi = dlCell->currCfi;
8564 iTbs = dlUe->mimoInfo.cwInfo[0].iTbs[0];
8565 eff = (*(RgSchCmnTbSzEff *)(dlCell->cqiToEffTbl[0][cfi]))[iTbs];
8567 /* Optimization to convert totalBo (which is in-terms of bytes) to bits
8568 * i.e, << 3 and multiply with 1024 i.e, << 10 */
8569 noRes = ((uint64_t)((bo << 3) << 10)) / (eff);
8570 /* Get the number of RBs needed for this transmission */
8571 /* Number of RBs = No of REs / No of REs per RB */
8572 *prbReqrd = RGSCH_CEIL(noRes, dlCell->noResPerRb[cfi]);
8575 } /* rgSchUtlDlCalc1CwPrb*/
8578 * @brief Utility function to calculate total num of PRBs required to
8579 * satisfy DL BO(BO sum of all logical channels for that UE or an LC BO)
8584 * Function : rgSchUtlDlCalc2CwPrb
8586 * Calculate PRBs required for UE to satisfy BO in DL
8588 * Note : Total calculated PRBs will be assigned to *prbReqrd
8591 * @param[in] RgSchCellCb *cell
8592 * @param[in] RgSchUeCb *ue
8593 * @param[in] uint32_t bo
8594 * @param[out] uint32_t *prbReqrd
8597 Void rgSchUtlDlCalc2CwPrb(RgSchCellCb *cell,RgSchUeCb *ue,uint32_t bo,uint32_t *prbReqrd)
8599 RgSchCmnDlCell *dlCell = RG_SCH_CMN_GET_DL_CELL(cell);
8600 RgSchCmnDlUe *dlUe = RG_SCH_CMN_GET_DL_UE(ue, cell);
8601 uint32_t eff1, eff2;
8603 uint8_t noLyr1, noLyr2;
8604 uint8_t iTbs1, iTbs2;
8605 uint8_t cfi = dlCell->currCfi;
8607 if ((dlUe->mimoInfo.forceTD) ||/* Transmit Diversity (TD) */
8608 (dlUe->mimoInfo.ri < 2))/* 1 layer precoding */
8610 iTbs1 = dlUe->mimoInfo.cwInfo[0].iTbs[0];
8611 eff1 = (*(RgSchCmnTbSzEff *)(dlCell->cqiToEffTbl[0][cfi]))[iTbs1];
8613 /* Optimization to convert totalBo (which is in-terms of bytes) to bits
8614 * i.e, << 3 and multiply with 1024 i.e, << 10 */
8615 noRes = ((uint64_t)((bo << 3) << 10)) / (eff1);
8616 /* Get the number of RBs needed for this transmission */
8617 /* Number of RBs = No of REs / No of REs per RB */
8618 *prbReqrd = RGSCH_CEIL(noRes, dlCell->noResPerRb[cfi]);
8622 noLyr1 = dlUe->mimoInfo.cwInfo[0].noLyr;
8623 noLyr2 = dlUe->mimoInfo.cwInfo[1].noLyr;
8624 iTbs1 = dlUe->mimoInfo.cwInfo[0].iTbs[noLyr1 - 1];
8625 iTbs2 = dlUe->mimoInfo.cwInfo[1].iTbs[noLyr2 - 1];
8626 eff1 = (*(RgSchCmnTbSzEff *)(dlCell->cqiToEffTbl[noLyr1 - 1][cfi]))[iTbs1];
8627 eff2 = (*(RgSchCmnTbSzEff *)(dlCell->cqiToEffTbl[noLyr2 - 1][cfi]))[iTbs2];
8629 /* Optimization to convert totalBo (which is in-terms of bytes) to bits
8630 * i.e, << 3 and multiply with 1024 i.e, << 10 */
8631 noRes = ((uint64_t)((bo << 3) << 10)) / (eff1 + eff2);
8632 /* Get the number of RBs needed for this transmission */
8633 /* Number of RBs = No of REs / No of REs per RB */
8634 *prbReqrd = RGSCH_CEIL(noRes, dlCell->noResPerRb[cfi]);
8637 } /* rgSchUtlDlCalc2CwPrb */
8640 * @brief Utility function to calculate total num of PRBs required to
8641 * satisfy DL BO(BO sum of all logical channels for that UE or an LC BO)
8645 * Function : rgSchUtlCalcTotalPrbReq
8647 * This function calls TM specific routine to calculate PRB
8650 * @param[in] RgSchCellCb *cell
8651 * @param[in] RgSchUeCb *ue
8652 * @param[in] uint32_t bo
8653 * @param[out] uint32_t *prbReqrd
8656 Void rgSchUtlCalcTotalPrbReq(RgSchCellCb *cell,RgSchUeCb *ue,uint32_t bo,uint32_t *prbReqrd)
8658 /* Call TM specific Prb calculation routine */
8659 (dlCalcPrbFunc[ue->mimoInfo.txMode - 1])(cell, ue, bo, prbReqrd);
8662 } /* rgSchUtlCalcTotalPrbReq */
8665 /***********************************************************
8667 * Func : rgSCHUtlFetchPcqiBitSz
8670 * Desc : Fetch the CQI/PMI bits for a UE based on the mode, periodicity.
8679 **********************************************************/
8680 static uint8_t rgSCHUtlFetchPcqiBitSz(RgSchCellCb *cell, RgSchUeCb *ueCb,uint8_t numTxAnt)
8682 uint8_t confRepMode;
8685 RgSchUePCqiCb *cqiCb = RG_SCH_GET_UE_CELL_CQI_CB(ueCb,cell);
8687 confRepMode = cqiCb->cqiCfg.cqiSetup.prdModeEnum;
8688 if((ueCb->mimoInfo.txMode != RGR_UE_TM_3) &&
8689 (ueCb->mimoInfo.txMode != RGR_UE_TM_4))
8695 ri = cqiCb->perRiVal;
8699 case RGR_PRD_CQI_MOD10:
8705 case RGR_PRD_CQI_MOD11:
8718 else if(numTxAnt == 4)
8731 /* This is number of antenna case 1.
8732 * This is not applicable for Mode 1-1.
8733 * So setting it to invalid value */
8739 case RGR_PRD_CQI_MOD20:
8747 pcqiSz = 4 + cqiCb->label;
8752 case RGR_PRD_CQI_MOD21:
8767 else if(numTxAnt == 4)
8780 /* This might be number of antenna case 1.
8781 * For mode 2-1 wideband case only antenna port 2 or 4 is supported.
8782 * So setting invalid value.*/
8790 pcqiSz = 4 + cqiCb->label;
8794 pcqiSz = 7 + cqiCb->label;
8810 * @brief Utility function to returns the number of subbands based on the
8815 * Function : rgSchUtlGetNumSbs
8817 * Calculate the number of PRBs
8818 * Update the subbandRequired based on the nPrbs and subband size
8820 * @param[in] RgSchCellCb *cell
8821 * @param[in] RgSchUeCb *ue
8822 * @param[in] uint32_t *numSbs
8825 uint8_t rgSchUtlGetNumSbs(RgSchCellCb *cell,RgSchUeCb *ue,uint32_t *numSbs)
8828 //Currently hardcoding MAX prb for each UE
8829 nPrb = ue->ue5gtfCb.maxPrb;
8830 (*numSbs) = RGSCH_CEIL(nPrb, MAX_5GTF_VRBG_SIZE);
8835 * @brief Utility function to insert the UE node into UE Lst based on the
8836 * number of subbands allocated for the UE for the current TTI.
8840 * Function : rgSchUtlSortInsUeLst
8842 * If subbandRequired < Min, then insert at head
8843 * Else If subbandRequired > Max, then insert at tail
8844 * Else, traverse the list and place the node at the appropriate place
8846 * @param[in] RgSchCellCb *cell
8847 * @param[in] RgSchUeCb *ue
8850 uint8_t rgSchUtlSortInsUeLst(RgSchCellCb *cell,CmLListCp *ueLst,CmLList *node,uint8_t vrbgRequired)
8853 CmLList *firstUeInLst;
8854 CmLList *lastUeInLst;
8858 //firstUeInLst = cmLListFirst(ueLst);
8859 CM_LLIST_FIRST_NODE(ueLst,firstUeInLst);
8860 if(NULLP == firstUeInLst)
8862 /* first node to be added to the list */
8863 cmLListAdd2Tail(ueLst, node);
8867 /* Sb Required for the UE is less than the first node in the list */
8868 tempUe = (RgSchUeCb *)(firstUeInLst->node);
8869 ueUl = RG_SCH_CMN_GET_UL_UE(tempUe, cell);
8871 if(vrbgRequired <= ueUl->vrbgRequired)
8873 cmLListInsCrnt(ueLst, (node));
8877 /* Sb Required for this UE is higher than the UEs in the list */
8878 lastUeInLst = cmLListLast(ueLst);
8879 tempUe = (RgSchUeCb *)(lastUeInLst->node);
8880 if(vrbgRequired >= ueUl->vrbgRequired)
8882 cmLListAdd2Tail(ueLst, (node));
8886 /* This UE needs to be in the middle. Search and insert the UE */
8887 ueInLst = cmLListFirst(ueLst);
8890 tempUe = (RgSchUeCb *)(ueInLst->node);
8892 if(vrbgRequired <= ueUl->vrbgRequired)
8894 cmLListInsCrnt(ueLst, (node));
8898 ueInLst = cmLListNext(ueLst);
8900 } while(NULLP != ueInLst && ueInLst != firstUeInLst);
8909 * @brief Function to Send LCG GBR register to MAC
8913 * Function: rgSCHUtlBuildNSendLcgReg
8915 * Handler for sending LCG GBR registration
8922 * @param[in] RgSchCellCb *cell
8923 * @param[in] CmLteRnti crnti
8924 * @param[in] uint8_t lcgId
8925 * @param[in] Bool isGbr
8929 S16 rgSCHUtlBuildNSendLcgReg(RgSchCellCb *cell,CmLteRnti crnti,uint8_t lcgId,Bool isGbr)
8932 RgInfLcgRegReq lcgRegReq;
8934 memset(&pst, 0, sizeof(Pst));
8935 lcgRegReq.isGbr = isGbr;
8936 lcgRegReq.cellId = cell->cellId;
8937 lcgRegReq.crnti = crnti;
8938 lcgRegReq.lcgId = lcgId;
8939 rgSCHUtlGetPstToLyr(&pst, &rgSchCb[cell->instIdx], cell->macInst);
8940 /* code Coverage portion of the test case */
8941 RgSchMacLcgReg(&pst, &lcgRegReq);
8950 * @brief Function to map RGR pucch type to TFU type
8954 * Function: rgSchUtlGetFdbkMode
8962 * @param[in] RgrSchFrmt1b3TypEnum
8963 * @return TfuAckNackMode
8966 TfuAckNackMode rgSchUtlGetFdbkMode(RgrSchFrmt1b3TypEnum fdbkType)
8969 TfuAckNackMode mode = TFU_UCI_FORMAT_1A_1B;
8973 case RG_SCH_UCI_FORMAT_NON_CA:
8974 case RG_SCH_UCI_FORMAT1A_1B:
8976 mode = TFU_UCI_FORMAT_1A_1B;
8979 case RG_SCH_UCI_FORMAT1B_CS:
8981 mode = TFU_UCI_FORMAT_1B_CS;
8984 case RG_SCH_UCI_FORMAT3:
8986 mode = TFU_UCI_FORMAT_3;
8992 #endif /* TFU_TDD */
8993 #endif /* LTE_ADV */
8994 #endif /*TFU_UPGRADE */
8998 * @brief Send Ue SCell delete to SMAC.
9002 * Function : rgSCHUtlSndUeSCellDel2Mac
9003 * This function populates the struct RgInfRlsRnti and
9004 * get the pst for SMac and mark field isUeSCellDel to TRUE which
9005 * indicates that it is a Ue SCell delete.
9009 * @param[in] RgSchCellCb *cell
9010 * @param[in] CmLteRnti rnti
9014 Void rgSCHUtlSndUeSCellDel2Mac(RgSchCellCb *cell,CmLteRnti rnti)
9017 Inst inst = cell->instIdx;
9018 RgInfRlsRnti rntiInfo;
9020 DU_LOG("\nINFO --> SCH : RNTI Release IND for UE(%d)\n", rnti);
9021 /* Copy the info to rntiInfo */
9022 rntiInfo.cellId = cell->cellId;
9023 rntiInfo.rnti = rnti;
9024 /* Fix : syed ueId change as part of reestablishment.
9025 * Now SCH to trigger this. CRG ueRecfg for ueId change
9027 rntiInfo.ueIdChng = FALSE;
9028 rntiInfo.newRnti = rnti;
9029 rntiInfo.isUeSCellDel = TRUE;
9030 /* Invoke MAC to release the rnti */
9031 rgSCHUtlGetPstToLyr(&pst, &rgSchCb[inst], cell->macInst);
9032 RgSchMacRlsRnti(&pst, &rntiInfo);
9037 * @brief Returns max TB supported by a given txMode
9041 * Function : rgSCHUtlGetMaxTbSupp
9042 * Max TB supported for TM Modes (1,2,5,6 and 7) is 1
9046 * @param[in] RgrTxMode txMode
9047 * @return uint8_t maxTbCount;
9050 uint8_t rgSCHUtlGetMaxTbSupp(RgrTxMode txMode)
9076 return (maxTbCount);
9080 * @brief Send Ue SCell delete to SMAC.
9084 * Function : rgSCHTomUtlGetTrigSet
9085 * This function gets the triggerset based on cqiReq
9087 * @param[in] RgSchCellCb *cell
9088 * @param[in] RgSchUeCb ueCb
9089 * @param[in] uint8_t cqiReq,
9090 * @param[out] uint8_t *triggerSet
9095 Void rgSCHTomUtlGetTrigSet(RgSchCellCb *cell,RgSchUeCb *ueCb,uint8_t cqiReq,uint8_t *triggerSet)
9097 RgSchUeCellInfo *pCellInfo = RG_SCH_CMN_GET_PCELL_INFO(ueCb);
9100 case RG_SCH_APCQI_SERVING_CC:
9102 /* APeriodic CQI request for Current Carrier.*/
9103 uint8_t sCellIdx = ueCb->cellIdToCellIdxMap[RG_SCH_CELLINDEX(cell)];
9104 *triggerSet = 1 << (7 - sCellIdx);
9107 case RG_SCH_APCQI_1ST_SERVING_CCS_SET:
9109 *triggerSet = pCellInfo->acqiCb.aCqiCfg.triggerSet1;
9112 case RG_SCH_APCQI_2ND_SERVING_CCS_SET:
9114 *triggerSet = pCellInfo->acqiCb.aCqiCfg.triggerSet2;
9127 * @brief This function updates the value of UE specific DCI sizes
9131 * Function: rgSCHUtlUpdUeDciSize
9132 * Purpose: This function calculates and updates DCI Sizes in bits.
9134 * Invoked by: Scheduler
9136 * @param[in] RgSchCellCb *cell
9137 * @param[in] RgSchUeCb *ueCb
9138 * @param[in] isCsi2Bit *isCsi2Bit: is 1 bit or 2 bit CSI
9142 Void rgSCHUtlUpdUeDciSize(RgSchCellCb *cell,RgSchUeCb *ueCb,Bool isCsi2Bit)
9144 uint8_t dci01aCmnSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_0];
9145 uint8_t dci01aDedSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_0];
9146 if ((ueCb->accessStratumRls >= RGR_REL_10) && (cell->bwCfg.dlTotalBw >= cell->bwCfg.ulTotalBw))
9148 dci01aCmnSize += 1; /* Resource Allocation Type DCI 0 */
9149 dci01aDedSize += 1; /* Resource Allocation Type DCI 0 */
9151 if (isCsi2Bit == TRUE)
9153 dci01aDedSize += 2; /* 2 bit CSI DCI 0 */
9157 dci01aDedSize += 1; /* 1 bit CSI DCI 0 */
9160 /* Common CSI is always 1 bit DCI 0 */
9161 dci01aCmnSize += 1; /* 1 bit CSI DCI 0 */
9163 /* Compare the sizes of DCI 0 with DCI 1A and consider the greater */
9164 if (dci01aCmnSize < cell->dciSize.baseSize[TFU_DCI_FORMAT_1A])
9166 dci01aCmnSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_1A];
9168 if (dci01aDedSize < cell->dciSize.baseSize[TFU_DCI_FORMAT_1A])
9170 dci01aDedSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_1A];
9173 /* Remove the Ambiguous Sizes as mentioned in table Table 5.3.3.1.2-1 Spec 36.212-a80 Sec 5.3.3.1.3 */
9174 dci01aCmnSize += rgSchDciAmbigSizeTbl[dci01aCmnSize];
9175 dci01aDedSize += rgSchDciAmbigSizeTbl[dci01aDedSize];
9177 ueCb->dciSize.cmnSize[TFU_DCI_FORMAT_0] = dci01aCmnSize;
9178 ueCb->dciSize.cmnSize[TFU_DCI_FORMAT_1A] = dci01aCmnSize;
9180 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_0] = dci01aDedSize;
9181 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1A] = dci01aDedSize;
9183 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] = cell->dciSize.baseSize[TFU_DCI_FORMAT_1];
9185 /* Spec 36.212-a80 Sec 5.3.3.1.2: If the UE is configured to decode PDCCH with CRC scrambled
9186 * by the C-RNTI and the number of information bits in format 1 is equal to that for format 0/1A
9187 * for scheduling the same serving cell and mapped onto the UE specific search space given by the
9188 * C-RNTI as defined in [3], one bit of value zero shall be appended to format 1. */
9189 if (ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] == ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1A])
9191 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] += 1;
9194 /* Spec 36.212-a80 Sec 5.3.3.1.2: If the number of information bits in format 1 belongs
9195 * to one of the sizes in Table 5.3.3.1.2-1, one or more zero bit(s) shall be appended
9196 * to format 1 until the payload size of format 1 does not belong to one of the sizes in
9197 * Table 5.3.3.1.2-1 and is not equal to that of format 0/1A mapped onto the same search space. */
9198 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] += rgSchDciAmbigSizeTbl[ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1]];
9199 } while (ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1] == ueCb->dciSize.dedSize[TFU_DCI_FORMAT_1A]);
9201 /* Just copying the value of 2/2A to avoid multiple checks at PDCCH allocations. This values never change.*/
9202 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_2] = cell->dciSize.size[TFU_DCI_FORMAT_2];
9203 ueCb->dciSize.dedSize[TFU_DCI_FORMAT_2A] = cell->dciSize.size[TFU_DCI_FORMAT_2A];
9204 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_2] = cell->dciSize.size[TFU_DCI_FORMAT_2];
9205 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_2A] = cell->dciSize.size[TFU_DCI_FORMAT_2A];
9207 /* Spec 36.212-a80 Sec 5.3.3.1.3: except when format 1A assigns downlink resource
9208 * on a secondary cell without an uplink configuration associated with the secondary cell */
9209 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A] = cell->dciSize.baseSize[TFU_DCI_FORMAT_1A];
9210 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A] += rgSchDciAmbigSizeTbl[ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A]];
9211 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] = cell->dciSize.baseSize[TFU_DCI_FORMAT_1];
9213 /* Spec 36.212-a80 Sec 5.3.3.1.2: If the UE is configured to decode PDCCH with CRC scrambled
9214 * by the C-RNTI and the number of information bits in format 1 is equal to that for format 0/1A
9215 * for scheduling the same serving cell and mapped onto the UE specific search space given by the
9216 * C-RNTI as defined in [3], one bit of value zero shall be appended to format 1. */
9217 if (ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] == ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A])
9219 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] += 1;
9222 /* Spec 36.212-a80 Sec 5.3.3.1.2: If the number of information bits in format 1 belongs
9223 * to one of the sizes in Table 5.3.3.1.2-1, one or more zero bit(s) shall be appended
9224 * to format 1 until the payload size of format 1 does not belong to one of the sizes in
9225 * Table 5.3.3.1.2-1 and is not equal to that of format 0/1A mapped onto the same search space. */
9226 ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] += rgSchDciAmbigSizeTbl[ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1]];
9227 } while (ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1] == ueCb->dciSize.noUlCcSize[TFU_DCI_FORMAT_1A]);
9229 rgSCHEmtcUtlUpdUeDciSize(cell, ueCb);
9234 * @brief This function initialises the DCI Size table
9238 * Function: rgSCHUtlCalcDciSizes
9239 * Purpose: This function calculates and initialises DCI Sizes in bits.
9241 * Invoked by: Scheduler
9243 * @param[in] RgSchCellCb *cell
9247 Void rgSCHUtlCalcDciSizes(RgSchCellCb *cell)
9249 uint8_t dciSize = 0;
9250 uint8_t dci01aSize = 0;
9251 uint32_t bits = 0, idx = 0;
9253 switch(TFU_DCI_FORMAT_0) /* Switch case for the purpose of readability */
9255 case TFU_DCI_FORMAT_0:
9257 /* DCI 0: Spec 36.212 Section 5.3.3.1.1 */
9259 /*-- Calculate resource block assignment bits need to be set
9260 Which is ln(N(N+1)/2) 36.212 5.3.3.1 --*/
9261 bits = (cell->bwCfg.ulTotalBw * (cell->bwCfg.ulTotalBw + 1) / 2);
9262 while ((bits & 0x8000) == 0)
9269 dciSize = 1 /* DCI 0 bit indicator */ + \
9270 1 /* Frequency hoping enable bit field */ + \
9271 (uint8_t)bits /* For frequency Hopping */ + \
9278 2 /* UL Index Config 0 or DAI Config 1-6 */
9282 cell->dciSize.baseSize[TFU_DCI_FORMAT_0] = dciSize;
9284 /* If hoping flag is enabled */
9285 if (cell->bwCfg.ulTotalBw <= 49) /* Spec 36.213 Table 8.4-1, N UL_hop, if hopping is enabled */
9287 cell->dciSize.dci0HopSize = 1;
9291 cell->dciSize.dci0HopSize = 2;
9294 /* Update common non-CRNTI scrambled DCI 0/1A flag */
9295 dci01aSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_0] + 1; /* 1 bit CSI */
9297 case TFU_DCI_FORMAT_1A:
9299 /* DCI 1A: Spec 36.212 Section 5.3.3.1.3 */
9302 /* Calculate resource block assignment bits need to be set
9303 Which is ln(N(N+1)/2) */
9304 bits = (cell->bwCfg.dlTotalBw * (cell->bwCfg.dlTotalBw + 1) / 2);
9305 while ((bits & 0x8000) == 0)
9312 dciSize += 1 /* Format 1A */ + \
9313 1 /* Local or Distributed */ + \
9314 (uint8_t)bits /* Resource block Assignment */ + \
9317 4 /* HARQ Proc Id */ +
9319 3 /* HARQ Proc Id */ +
9329 cell->dciSize.baseSize[TFU_DCI_FORMAT_1A] = dciSize;
9331 /* If the UE is not configured to decode PDCCH with CRC scrambled by the C-RNTI,
9332 * and the number of information bits in format 1A is less than that of format 0,
9333 * zeros shall be appended to format 1A until the payload size equals that of format 0. */
9334 /* Compare the size with DCI 1A and DCI 0 and consider the greater one */
9335 if (dci01aSize < cell->dciSize.baseSize[TFU_DCI_FORMAT_1A])
9337 dci01aSize = cell->dciSize.baseSize[TFU_DCI_FORMAT_1A];
9339 /* If the number of information bits in format 1A belongs to one of the sizes in
9340 * Table 5.3.3.1.2-1, one zero bit shall be appended to format 1A. */
9341 dci01aSize += rgSchDciAmbigSizeTbl[dci01aSize];
9342 cell->dciSize.size[TFU_DCI_FORMAT_1A] = cell->dciSize.size[TFU_DCI_FORMAT_0] = dci01aSize;
9344 case TFU_DCI_FORMAT_1:
9346 /* DCI 1: Spec 36.212 Section 5.3.3.1.2 */
9348 if (cell->bwCfg.dlTotalBw > 10)
9350 dciSize = 1; /* Resource Allocation header bit */
9353 /* Resouce allocation bits Type 0 and Type 1 */
9354 bits = (cell->bwCfg.dlTotalBw/cell->rbgSize);
9355 if ((cell->bwCfg.dlTotalBw % cell->rbgSize) != 0)
9360 dciSize += (uint8_t)bits /* Resource Allocation bits */ + \
9368 2 /* Redunancy Version */ + \
9377 cell->dciSize.baseSize[TFU_DCI_FORMAT_1] = dciSize;
9379 cell->dciSize.size[TFU_DCI_FORMAT_1] = dciSize;
9382 /* If the UE is not configured to decode PDCCH with CRC
9383 * scrambled by the C-RNTI and the number of information bits in format 1
9384 * is equal to that for format 0/1A, one bit of value zero shall be appended
9386 if (dci01aSize == cell->dciSize.size[TFU_DCI_FORMAT_1])
9388 cell->dciSize.size[TFU_DCI_FORMAT_1] += 1;
9391 /* If the number of information bits in format 1 belongs to one of the sizes in
9392 * Table 5.3.3.1.2-1, one or more zero bit(s) shall be appended to format 1 until
9393 * the payload size of format 1 does not belong to one of the sizes in Table 5.3.3.1.2-1
9394 * and is not equal to that of format 0/1A mapped onto the same search space. */
9395 cell->dciSize.size[TFU_DCI_FORMAT_1] += rgSchDciAmbigSizeTbl[cell->dciSize.size[TFU_DCI_FORMAT_1]];
9396 } while (cell->dciSize.size[TFU_DCI_FORMAT_1] == dci01aSize);
9398 case TFU_DCI_FORMAT_2:
9400 /* DCI 2: Spec 36.212 Section 5.3.3.1.5 */
9402 if (cell->bwCfg.dlTotalBw > 10)
9404 dciSize = 1; /* Resource Allocation bit */
9407 dciSize += (uint8_t)bits /* Resource Allocation bits */ + \
9415 1 /* CW Swap Flag */ + \
9416 5 /* MCS for TB1 */+ \
9417 1 /* NDI for TB1 */+ \
9418 2 /* RV for TB1 */ + \
9419 5 /* MCS for TB2 */+ \
9420 1 /* NDI for TB2 */+ \
9422 if (cell->numTxAntPorts == 2)
9426 else if (cell->numTxAntPorts == 4)
9430 cell->dciSize.size[TFU_DCI_FORMAT_2] = dciSize;
9431 cell->dciSize.size[TFU_DCI_FORMAT_2] += rgSchDciAmbigSizeTbl[cell->dciSize.size[TFU_DCI_FORMAT_2]];
9433 case TFU_DCI_FORMAT_2A:
9435 /* DCI 2A: Spec 36.212 Section 5.3.3.1.5A */
9437 if (cell->bwCfg.dlTotalBw > 10)
9439 dciSize = 1; /* Resource Allocation bit */
9442 dciSize += (uint8_t)bits /* Resource Allocation bits */ + \
9450 1 /* CW Swap Flag */ + \
9451 5 /* MCS for TB1 */+ \
9452 1 /* NDI for TB1 */+ \
9453 2 /* RV for TB1 */ + \
9454 5 /* MCS for TB2 */+ \
9455 1 /* NDI for TB2 */+ \
9457 if (cell->numTxAntPorts == 4)
9461 cell->dciSize.size[TFU_DCI_FORMAT_2A] = dciSize;
9462 cell->dciSize.size[TFU_DCI_FORMAT_2A] += \
9463 rgSchDciAmbigSizeTbl[cell->dciSize.size[TFU_DCI_FORMAT_2A]]; /* Spec 39.212 Table 5.3.3.1.2-1 */
9465 case TFU_DCI_FORMAT_3:
9467 /* DCI 3: Spec 36.212 Section 5.3.3.1.6 */
9468 cell->dciSize.size[TFU_DCI_FORMAT_3] = cell->dciSize.size[TFU_DCI_FORMAT_1A] / 2;
9469 if (cell->dciSize.size[TFU_DCI_FORMAT_3] % 2)
9471 cell->dciSize.size[TFU_DCI_FORMAT_3]++;
9474 case TFU_DCI_FORMAT_3A:
9476 /* DCI 3A: Spec 36.212 Section 5.3.3.1.7 */
9477 cell->dciSize.size[TFU_DCI_FORMAT_3A] = cell->dciSize.size[TFU_DCI_FORMAT_1A];
9480 case TFU_DCI_FORMAT_6_0A:
9482 rgSCHEmtcGetDciFrmt60ASize(cell);
9484 case TFU_DCI_FORMAT_6_1A:
9486 rgSCHEmtcGetDciFrmt61ASize(cell);
9491 /* DCI format not supported */
9498 * @brief Handler for the CPU OvrLd related state adjustment.
9502 * Function : rgSCHUtlCpuOvrLdAdjItbsCap
9505 * - Record dl/ulTpts
9506 * - Adjust maxItbs to acheive target throughputs
9508 * @param[in] RgSchCellCb *cell
9511 Void rgSCHUtlCpuOvrLdAdjItbsCap( RgSchCellCb *cell)
9515 if ((cell->cpuOvrLdCntrl.cpuOvrLdIns) & (RGR_CPU_OVRLD_DL_TPT_UP |
9516 RGR_CPU_OVRLD_DL_TPT_DOWN))
9518 /* Regulate DL Tpt for CPU overload */
9519 if (cell->measurements.dlTpt > cell->cpuOvrLdCntrl.tgtDlTpt)
9521 tptDelta = cell->measurements.dlTpt - cell->cpuOvrLdCntrl.tgtDlTpt;
9522 /* Upto 0.5% drift in measured vs target tpt is ignored */
9523 if (((tptDelta*1000)/cell->cpuOvrLdCntrl.tgtDlTpt) > 5)
9525 cell->thresholds.maxDlItbs = RGSCH_MAX((cell->thresholds.maxDlItbs-1), 1);
9530 tptDelta = cell->cpuOvrLdCntrl.tgtDlTpt - cell->measurements.dlTpt;
9531 /* Upto 0.5% drift in measured vs target tpt is ignored */
9532 if (((tptDelta*1000)/cell->cpuOvrLdCntrl.tgtDlTpt) > 5)
9534 cell->thresholds.maxDlItbs = RGSCH_MIN((cell->thresholds.maxDlItbs+1), RG_SCH_DL_MAX_ITBS);
9537 #ifdef CPU_OL_DBG_PRINTS
9538 DU_LOG("\nINFO --> SCH : DL CPU OL ADJ = %lu, %lu, %d\n", cell->measurements.dlTpt, cell->cpuOvrLdCntrl.tgtDlTpt,
9539 cell->thresholds.maxDlItbs);
9543 if ((cell->cpuOvrLdCntrl.cpuOvrLdIns) & (RGR_CPU_OVRLD_UL_TPT_UP |
9544 RGR_CPU_OVRLD_UL_TPT_DOWN))
9546 /* Regualte DL Tpt for CPU overload */
9547 if (cell->measurements.ulTpt > cell->cpuOvrLdCntrl.tgtUlTpt)
9549 tptDelta = cell->measurements.ulTpt - cell->cpuOvrLdCntrl.tgtUlTpt;
9550 /* Upto 1% drift in measured vs target tpt is ignored */
9551 if (((tptDelta*1000)/cell->cpuOvrLdCntrl.tgtUlTpt) > 10)
9553 cell->thresholds.maxUlItbs = RGSCH_MAX((cell->thresholds.maxUlItbs-1), 1);
9558 tptDelta = cell->cpuOvrLdCntrl.tgtUlTpt - cell->measurements.ulTpt;
9559 /* Upto 1% drift in measured vs target tpt is ignored */
9560 if (((tptDelta*1000)/cell->cpuOvrLdCntrl.tgtUlTpt) > 10)
9562 cell->thresholds.maxUlItbs = RGSCH_MIN((cell->thresholds.maxUlItbs+1), RG_SCH_UL_MAX_ITBS);
9565 #ifdef CPU_OL_DBG_PRINTS
9566 DU_LOG("\nDEBUG --> SCH : UL CPU OL ADJ = %lu, %lu, %d\n", cell->measurements.ulTpt, cell->cpuOvrLdCntrl.tgtUlTpt,
9567 cell->thresholds.maxUlItbs);
9574 * @brief Handler for the num UE per TTI based CPU OvrLd instr updating
9578 * Function : rgSCHUtlChkAndUpdNumUePerTtiCpuOvInstr
9581 * - Validate the config params.
9582 * - Update numUEperTTi CPU OL related information.
9583 * - If successful, return ROK else RFAILED.
9585 * @param[in] RgSchCellCb *cell
9586 * @param[in] uint8_t cnrtCpuOvrLdIns
9589 static Void rgSCHUtlChkAndUpdNumUePerTtiCpuOvInstr(RgSchCellCb *cell,uint8_t crntCpuOvrLdIns)
9591 RgSchCpuOvrLdCntrlCb *cpuInstr = &(cell->cpuOvrLdCntrl);
9592 RgSchCmnCell *cellSch;
9593 uint8_t maxUeNewDlTxPerTti;
9594 uint8_t maxUeNewUlTxPerTti;
9595 uint8_t tmpslot = 0;
9596 #ifdef CPU_OL_DBG_PRINTS
9599 uint8_t maxDlDecCnt;
9600 uint8_t maxUlDecCnt;
9602 cellSch = RG_SCH_CMN_GET_CELL(cell);
9604 maxUeNewDlTxPerTti = cellSch->dl.maxUeNewTxPerTti;
9605 maxUeNewUlTxPerTti = cellSch->ul.maxUeNewTxPerTti;
9607 /* Calculate Maximum Decremen */
9608 maxDlDecCnt = (10*(maxUeNewDlTxPerTti - 1))-(10-RGR_MAX_PERC_NUM_UE_PER_TTI_RED);
9609 maxUlDecCnt = (10*(maxUeNewUlTxPerTti - 1))-(10-RGR_MAX_PERC_NUM_UE_PER_TTI_RED);
9611 /* Check for DL CPU Commands */
9612 if ( crntCpuOvrLdIns & RGR_CPU_OVRLD_DL_DEC_NUM_UE_PER_TTI )
9614 /* Decrement till 90% of maxUeNewDlTxPerTti */
9615 if ( cpuInstr->dlNxtIndxDecNumUeTti < maxDlDecCnt )
9617 tmpslot = (cpuInstr->dlNxtIndxDecNumUeTti) % 10;
9618 cpuInstr->dlNxtIndxDecNumUeTti++;
9619 if ( cpuInstr->maxUeNewTxPerTti[tmpslot] > 1 )
9621 cpuInstr->maxUeNewTxPerTti[tmpslot]--;
9625 #ifdef CPU_OL_DBG_PRINTS
9626 DU_LOG("\nERROR --> SCH : CPU_OL_TTI__ERROR\n");
9628 DU_LOG("\nERROR --> SCH : Invalid CPU OL");
9631 #ifdef CPU_OL_DBG_PRINTS
9632 DU_LOG("\nDEBUG --> SCH : dlNxtIndxDecNumUeTti = %d\n", cpuInstr->dlNxtIndxDecNumUeTti);
9634 DU_LOG("\nDEBUG --> SCH : dlNxtIndxDecNumUeTti = %d",
9635 cpuInstr->dlNxtIndxDecNumUeTti);
9637 else if ( crntCpuOvrLdIns & RGR_CPU_OVRLD_DL_INC_NUM_UE_PER_TTI )
9639 if ( cpuInstr->dlNxtIndxDecNumUeTti > 0)
9641 cpuInstr->dlNxtIndxDecNumUeTti--;
9642 tmpslot = (cpuInstr->dlNxtIndxDecNumUeTti) % 10;
9643 if ( cpuInstr->maxUeNewTxPerTti[tmpslot] < maxUeNewDlTxPerTti )
9645 cpuInstr->maxUeNewTxPerTti[tmpslot]++;
9649 #ifdef CPU_OL_DBG_PRINTS
9650 DU_LOG("\nERROR --> SCH : CPU_OL_TTI__ERROR\n");
9652 DU_LOG("\nERROR --> SCH : Invalid CPU OL");
9655 #ifdef CPU_OL_DBG_PRINTS
9656 DU_LOG("\nDEBUG --> SCH : dlNxtIndxDecNumUeTti = %d\n", cpuInstr->dlNxtIndxDecNumUeTti);
9658 DU_LOG("\nERROR --> SCH : dlNxtIndxDecNumUeTti = %d",
9659 cpuInstr->dlNxtIndxDecNumUeTti);
9661 /* Check for UL CPU commands */
9662 if ( crntCpuOvrLdIns & RGR_CPU_OVRLD_UL_DEC_NUM_UE_PER_TTI )
9664 /* Decrement till 90% of maxUeNewDlTxPerTti */
9665 if ( cpuInstr->ulNxtIndxDecNumUeTti < maxUlDecCnt )
9667 tmpslot = (cpuInstr->ulNxtIndxDecNumUeTti) % 10;
9668 cpuInstr->ulNxtIndxDecNumUeTti++;
9669 if ( cpuInstr->maxUeNewRxPerTti[tmpslot] > 1 )
9671 cpuInstr->maxUeNewRxPerTti[tmpslot]--;
9675 #ifdef CPU_OL_DBG_PRINTS
9676 DU_LOG("\nERROR --> SCH : CPU_OL_TTI__ERROR\n");
9678 DU_LOG("\nERROR --> SCH : Invalid CPU OL");
9681 #ifdef CPU_OL_DBG_PRINTS
9682 DU_LOG("\nDEBUG --> SCH : ulNxtIndxDecNumUeTti = %d\n", cpuInstr->ulNxtIndxDecNumUeTti);
9684 DU_LOG("\nDEBUG --> SCH : dlNxtIndxDecNumUeTti = %d",
9685 cpuInstr->dlNxtIndxDecNumUeTti);
9687 else if ( crntCpuOvrLdIns & RGR_CPU_OVRLD_UL_INC_NUM_UE_PER_TTI )
9689 if ( cpuInstr->ulNxtIndxDecNumUeTti > 0)
9691 cpuInstr->ulNxtIndxDecNumUeTti--;
9692 tmpslot = (cpuInstr->ulNxtIndxDecNumUeTti) % 10;
9693 if ( cpuInstr->maxUeNewRxPerTti[tmpslot] < maxUeNewUlTxPerTti )
9695 cpuInstr->maxUeNewRxPerTti[tmpslot]++;
9699 #ifdef CPU_OL_DBG_PRINTS
9700 DU_LOG("\nERROR --> SCH : CPU_OL_TTI__ERROR\n");
9702 DU_LOG("\nERROR --> SCH : Invalid CPU OL");
9705 #ifdef CPU_OL_DBG_PRINTS
9706 DU_LOG("\nDEBUG --> SCH : ulNxtIndxDecNumUeTti = %d\n", cpuInstr->ulNxtIndxDecNumUeTti);
9708 DU_LOG("\nDEBUG --> SCH : dlNxtIndxDecNumUeTti = %d",
9709 cpuInstr->dlNxtIndxDecNumUeTti);
9711 #ifdef CPU_OL_DBG_PRINTS
9712 /* TODO: Debug Information - Shall be moved under CPU_OL_DBG_PRINTS */
9713 DU_LOG("\nDEBUG --> SCH : maxUeNewDlTxPerTti = %d, maxUeNewUlTxPerTti = %d\n", maxUeNewDlTxPerTti, maxUeNewUlTxPerTti);
9714 DU_LOG("\nINFO --> SCH : DL Sf numUePerTti:");
9715 for ( idx = 0; idx < 10 ; idx ++ )
9717 DU_LOG(" %d", cpuInstr->maxUeNewTxPerTti[idx]);
9719 DU_LOG("\nINFO --> SCH : UL Sf numUePerTti:");
9720 for ( idx = 0; idx < 10 ; idx ++ )
9722 DU_LOG(" %d", cpuInstr->maxUeNewRxPerTti[idx]);
9728 } /* rgSCHUtlChkAndUpdNumUePerTtiCpuOvInstr */
9731 * @brief Handler for the CPU OvrLd related cell Recfg.
9735 * Function : rgSCHUtlResetCpuOvrLdState
9738 * - Validate the config params.
9739 * - Update CPU OL related state information.
9740 * - If successful, return ROK else RFAILED.
9742 * @param[in] RgSchCellCb *cell
9743 * @param[in] uint8_t cnrtCpuOvrLdIns
9748 S16 rgSCHUtlResetCpuOvrLdState(RgSchCellCb *cell,uint8_t crntCpuOvrLdIns)
9750 uint8_t crntDlCpuOL=0;
9751 uint8_t crntUlCpuOL=0;
9752 RgSchCmnCell *schCmnCell = (RgSchCmnCell *)(cell->sc.sch);
9755 #ifdef CPU_OL_DBG_PRINTS
9756 DU_LOG("\nDEBUG --> SCH : CPU OVR LD Ins Rcvd = %d\n", (int)crntCpuOvrLdIns);
9758 DU_LOG("\nINFO --> SCH : CPU OVR LD Ins Rcvd");
9760 if ( RGR_CPU_OVRLD_RESET == crntCpuOvrLdIns )
9762 /* The CPU OL instruction received with RESET (0), hence reset it */
9763 #ifdef CPU_OL_DBG_PRINTS
9764 DU_LOG("\nDEBUG --> SCH : rgSCHUtlResetCpuOvrLdState: RESET CPU OL instr\n");
9766 DU_LOG("\nINFO --> SCH : RESET CPU OVR LD");
9767 cell->cpuOvrLdCntrl.cpuOvrLdIns = 0;
9768 /* Reset the max UL and DL itbs to 26 */
9769 cell->thresholds.maxUlItbs = RG_SCH_UL_MAX_ITBS;
9770 cell->thresholds.maxDlItbs = RG_SCH_DL_MAX_ITBS;
9771 /* Reset the num UE per TTI intructions */
9772 cell->cpuOvrLdCntrl.dlNxtIndxDecNumUeTti = 0;
9773 cell->cpuOvrLdCntrl.ulNxtIndxDecNumUeTti = 0;
9774 for ( idx = 0; idx < 10; idx++ )
9776 cell->cpuOvrLdCntrl.maxUeNewTxPerTti[idx] =
9777 schCmnCell->dl.maxUeNewTxPerTti;
9778 cell->cpuOvrLdCntrl.maxUeNewRxPerTti[idx] =
9779 schCmnCell->ul.maxUeNewTxPerTti;
9784 /* Check and Update numUEPer TTI based CPU overload instruction before
9785 * going for TP based CPU OL
9786 * TTI based intrcuctions shall be > 0xF */
9787 if ( crntCpuOvrLdIns > 0xF )
9789 rgSCHUtlChkAndUpdNumUePerTtiCpuOvInstr(cell, crntCpuOvrLdIns);
9790 /* If need to have both TP and numUePerTti instrcution together in
9791 * one command then dont return from here */
9795 crntDlCpuOL = (crntCpuOvrLdIns & RGR_CPU_OVRLD_DL_TPT_UP) +\
9796 (crntCpuOvrLdIns & RGR_CPU_OVRLD_DL_TPT_DOWN);
9797 if ((crntDlCpuOL) && (crntDlCpuOL != RGR_CPU_OVRLD_DL_TPT_UP) &&
9798 (crntDlCpuOL != RGR_CPU_OVRLD_DL_TPT_DOWN))
9800 /* Cfg validation failed. Invalid Command. Either UP/DOWN is allowed */
9803 crntUlCpuOL = (crntCpuOvrLdIns & RGR_CPU_OVRLD_UL_TPT_UP) +\
9804 (crntCpuOvrLdIns & RGR_CPU_OVRLD_UL_TPT_DOWN);
9805 if ((crntUlCpuOL) && (crntUlCpuOL != RGR_CPU_OVRLD_UL_TPT_UP) &&
9806 (crntUlCpuOL != RGR_CPU_OVRLD_UL_TPT_DOWN))
9808 /* Cfg validation failed. Invalid Command. Either UP/DOWN is allowed */
9811 if ((crntDlCpuOL == 0) && (crntUlCpuOL == 0))
9813 /* Cfg validation failed. Invalid Command. Either UP/DOWN is allowed */
9817 cell->cpuOvrLdCntrl.cpuOvrLdIns = crntCpuOvrLdIns;
9821 if (crntUlCpuOL == RGR_CPU_OVRLD_UL_TPT_DOWN)
9823 cell->cpuOvrLdCntrl.tgtUlTpt = cell->measurements.ulTpt - \
9824 (cell->measurements.ulTpt * 3 )/100;
9828 cell->cpuOvrLdCntrl.tgtUlTpt = cell->measurements.ulTpt + \
9829 (cell->measurements.ulTpt * 2 )/100;
9831 DU_LOG("\nDEBUG --> SCH : CPU OVR LD UL Reset to "
9832 "%d, %u, %u", (int)crntUlCpuOL, cell->cpuOvrLdCntrl.tgtUlTpt,cell->measurements.ulTpt);
9833 #ifdef CPU_OL_DBG_PRINTS
9834 DU_LOG("\nDEBUG --> SCH : CPU OVR LD UL Reset to= %d, %u, %u\n", (int)crntUlCpuOL, cell->cpuOvrLdCntrl.tgtUlTpt,
9835 cell->measurements.ulTpt);
9841 if (crntDlCpuOL == RGR_CPU_OVRLD_DL_TPT_DOWN)
9843 cell->cpuOvrLdCntrl.tgtDlTpt = cell->measurements.dlTpt - \
9844 (cell->measurements.dlTpt * 1 )/100;
9848 cell->cpuOvrLdCntrl.tgtDlTpt = cell->measurements.dlTpt + \
9849 (cell->measurements.dlTpt * 1 )/100;
9851 DU_LOG("\nDEBUG --> SCH : CPU OVR LD DL Reset to "
9852 "%d, %u, %u", (int)crntDlCpuOL, cell->cpuOvrLdCntrl.tgtDlTpt,cell->measurements.dlTpt);
9854 #ifdef CPU_OL_DBG_PRINTS
9855 DU_LOG("\nDEBUG --> SCH : CPU OVR LD DL Reset to= %d, %lu, %lu\n", (int)crntDlCpuOL, cell->cpuOvrLdCntrl.tgtDlTpt,
9856 cell->measurements.dlTpt);
9859 rgSCHUtlCpuOvrLdAdjItbsCap(cell);
9863 S16 rgSCHUtlAddToResLst
9869 cmLListAdd2Tail(cp, &iotRes->resLnk);
9870 iotRes->resLnk.node = (PTR)iotRes;
9873 S16 rgSCHUtlDelFrmResLst
9879 CmLListCp *cp = NULLP;
9880 RgSchEmtcUeInfo *emtcUe = NULLP;
9881 emtcUe = RG_GET_EMTC_UE_CB(ue);
9882 if(iotRes->resType == RG_SCH_EMTC_PUCCH_RES)
9884 cp = &emtcUe->ulResLst;
9885 }else if(iotRes->resType == RG_SCH_EMTC_PDSCH_RES)
9887 cp = &emtcUe->dlResLst;
9890 DU_LOG("\nINFO --> SCH : *****restype mismatch");
9896 DU_LOG("\nINFO --> SCH : ****error count*****\n");
9900 cmLListDelFrm(cp, &iotRes->resLnk);
9901 iotRes->resLnk.node = NULLP;
9905 /**********************************************************************
9908 **********************************************************************/