1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /**********************************************************************
20 Name: LTE MAC SC1 scheduler
24 Desc: Defines required by SC1 scheduler
28 *********************************************************************21*/
38 /***********************************************************************
40 ***********************************************************************/
42 /* Scheduler1 tunable params */
43 #define RG_SCH_CMN_GET_DL_SCHED_TYPE(cell) rgSchCb[cell->instIdx].rgrSchedEnbCfg.dlSchdType
44 #define RG_SCH_CMN_GET_UL_SCHED_TYPE(cell) rgSchCb[cell->instIdx].rgrSchedEnbCfg.ulSchdType
45 #define RG_SCH_CMN_GET_SCHED_CFG(cell) rgSchCb[cell->instIdx].rgrSchedEnbCfg
46 #define RG_SCH_CMN_GET_ANT_PORTS(cell) rgSchCb[cell->instIdx].rgrSchedEnbCfg.numTxAntPorts
47 #define RG_SCH_CMN_GET_CELL(cell) ((RgSchCmnCell *)((cell)->sc.sch))
48 #define RG_SCH_CMN_GET_UL_CELL(cell) &(((RgSchCmnCell *)((cell)->sc.sch))->ul)
49 #define RG_SCH_CMN_GET_DL_CELL(cell) &(((RgSchCmnCell *)((cell)->sc.sch))->dl)
50 #define RG_SCH_CMN_GET_CMN_UE(ue) &(((RgSchCmnUe *)(((ue)->cellInfo[0])->sch))->cmn)
51 #define RG_SCH_CMN_GET_UE(_ue,_cell) ((RgSchCmnUe *)((_ue->cellInfo[(_ue->cellIdToCellIdxMap\
52 [RG_SCH_CELLINDEX(_cell)])])->sch))
53 #define RG_SCH_CMN_GET_UL_UE(_ue,_cell) (&(((RgSchCmnUe *)((_ue->cellInfo[_ue->cellIdToCellIdxMap\
54 [RG_SCH_CELLINDEX(_cell)]])->sch))->ul))
55 #define RG_SCH_CMN_GET_DL_UE(_ue,_cell) (&(((RgSchCmnUe *)((_ue->cellInfo[_ue->cellIdToCellIdxMap\
56 [RG_SCH_CELLINDEX(_cell)]])->sch))->dl))
57 #define RG_SCH_CMN_GET_UE_HQE(_ue,_cell) (_ue->cellInfo[_ue->cellIdToCellIdxMap\
58 [RG_SCH_CELLINDEX(_cell)]]->hqEnt)
60 #define RG_SCH_CMN_GET_DL_HQP(hqP) ((RgSchCmnDlHqProc *)((hqP)->sch))
61 #define RG_SCH_CMN_GET_DL_SVC(svc) ((RgSchCmnDlSvc *)((svc)->sch))
62 #define RG_SCH_CMN_GET_UL_LCG(lcg) ((RgSchCmnLcg *)((lcg)->sch))
65 #define RG_SCH_IS_CELL_SEC(ue,cell) (((ue)->cellInfo[0]->sCellId != cell->cellId)? TRUE: FALSE)
66 /*#define RG_SCH_IS_CELL_SEC(_ue,_cell) (((_ue)->cell != _cell)? TRUE: FALSE)*/
69 #define RG_SCH_CMN_GET_LC_SCH_SPFC(_ue,_svc,_cell) (((RgSchCmnDlSvc *)(_svc->sch))->schSpfc[\
70 _ue->cellIdToCellIdxMap[RG_SCH_CELLINDEX(_cell)]])
71 #define RG_SCH_CMN_GET_PA(_ue,_cell) (_ue->cellInfo[_ue->cellIdToCellIdxMap\
72 [RG_SCH_CELLINDEX(_cell)]]->pA)
73 /* Changing the check for retransmission - now checking if alloc
74 * is non NULL instead of using the isRetx field of the harq Proc.
76 #define RG_SCH_CMN_IS_UL_UE_RETX(_ue, _cell) ((&RG_SCH_CMN_GET_UL_UE(_ue, _cell)->hqEnt.hqProcCb[\
77 ((RgSchCmnCell *)(ue->cell->sc.sch))->ul.schdHqProcIdx])->alloc)
79 /* Get acqiCb from appropiate ScellInfo */
80 #define RG_SCH_CMN_GET_ACQICB(_ue,_cell) &(((_ue->cellInfo[_ue->cellIdToCellIdxMap\
81 [RG_SCH_CELLINDEX(_cell)]])->acqiCb))
83 #define RG_SCH_CMN_GET_SCELL_INFO(_ue,_cell) (_ue->cellInfo[_ue->cellIdToCellIdxMap\
84 [RG_SCH_CELLINDEX(_cell)]])
86 #define RG_SCH_CMN_GET_PCELL_INFO(_ue) (_ue->cellInfo[0])
88 /* Added support for SPS*/
90 #define RGSCH_SPS_MAX_SPS_ACTVN_BO 400
91 #define RGSCH_SPS_MAX_DL_HQP_TX 4
92 #define RGSCH_SPS_MAX_UL_ACT_CRC_FAIL 3
93 #define RGSCH_SPS_MAX_UL_SPS_OCC_CRC_FAIL 3
94 #define RGSCH_SPS_MAX_UL_REL_PDCCH 2
95 #define RG_SCH_CMN_GET_UL_SPS_CELL(cell) &(((RgSchCmnCell *)((cell)->sc.sch))->ul.ulSpsInfo)
96 #define RG_SCH_CMN_GET_UL_SPS_UE(_ue,_cell) &(_ue->ul.ulSpsInfo)
97 #define RG_SCH_CMN_SID_PACKET_SIZE 10
98 #define RG_SCH_CMN_SPS_BSR_HEADROOM 6 /* PHR 2 bytes + Long BSR 4 bytes*/
101 #define RGSCH_CMN_MIN_SCALABLE_CQI RGSCH_SPS_CQI_SCALE_FACTOR+1
102 /* Introduced timing delta for DL control in FDD */
104 #define RGSCH_SPS_UL_LCM 40 /* Default lcm to start the spsSfTbl with */
106 #define RGSCH_SPS_UL_DELTA (TFU_DLCNTRL_DLDELTA + RGSCH_PDCCH_PUSCH_DELTA)
107 #define RGSCH_SPS_UL_LCM 20 /* Default lcm to start the spsSfTbl with */
112 #define RG_SCH_CMN_IS_SPS_SCHD(_ue, _cell) (((((&RG_SCH_CMN_GET_UL_UE(_ue, _ue->cell)->hqEnt.hqProcCb[\
113 ((RgSchCmnCell *)(_ue->cell->sc.sch))->ul.schdHqProcIdx])->alloc) &&\
114 ((&RG_SCH_CMN_GET_UL_UE(_ue, _ue->cell)->hqEnt.hqProcCb[\
115 ((RgSchCmnCell *)(_ue->cell->sc.sch))->ul.schdHqProcIdx])->alloc->rnti == _ue->spsRnti) ? TRUE:FALSE)) || \
116 (_ue->ul.relPdcchSchdTime.sfn == _cell->crntTime.sfn && _ue->ul.relPdcchSchdTime.subframe == _cell->crntTime.subframe))
117 #endif /* LTEMAC_SPS */
120 #define RG_SCH_CALC_GBR_UTILIZATION(_cell, _lcCb, _prbUsed) {\
121 if(_lcCb->qciCb->qci <= RGM_MAX_QCI_REPORTS)\
123 _cell->prbUsage.qciPrbRpts[_lcCb->qciCb->qci-1].dlTotPrbUsed += _prbUsed;\
124 _cell->prbUsage.qciPrbRpts[_lcCb->qciCb->qci-1].qci = _lcCb->qciCb->qci;\
130 /* This is added due to the limitation in BRDCM Platform
131 * BRDCM support only one Aperiodic Cqi reception in one UL Sf at lower MCS
132 * Note: Should be removed once BRDCM provides support for this */
133 #define RG_SCH_MAX_ACQI_PER_ULSF 1
135 #define RG_SCH_CMN_IS_UE_SCHDLD(_ue, _cell) (((RgSchCmnUe *)((_ue->cellInfo[_ue->cellIdToCellIdxMap\
136 [RG_SCH_CELLINDEX(_cell)]])->sch))->dl.proc != NULLP)
137 #define RG_SCH_CMN_PROC_SLCTD_FOR_RETX(proc) ((proc->tbInfo[0].txCntr!=0) ||\
138 (proc->tbInfo[1].txCntr!=0))
139 #define RG_SCH_CMN_DL_IS_UE_ACTIVE(ue) (ue->dl.dlInactvMask == 0)
140 #define RG_SCH_CMN_UL_IS_UE_ACTIVE(ue) (ue->ul.ulInactvMask == 0)
141 /* ulInactvMask and dlInactvMask are simulataneously set/reset
142 * hence check against one suffices */
143 #define RG_SCH_CMN_IS_UE_PDCCHODR_INACTV(ue) (ue->ul.ulInactvMask & RG_PDCCHODR_INACTIVE)
145 /* Adding routines to check Ue's Active state before triggering UE's Active transition */
146 #define RG_SCH_CMN_DL_UPDT_INACTV_MASK( cellCb, ue, maskElmnt) \
147 if(RG_SCH_CMN_DL_IS_UE_ACTIVE(ue)) \
149 ue->dl.dlInactvMask &= ~maskElmnt; \
153 ue->dl.dlInactvMask &= ~maskElmnt; \
154 if(RG_SCH_CMN_DL_IS_UE_ACTIVE(ue)) \
156 rgSCHUtlDlActvtUe(cellCb, ue); \
160 #define RG_SCH_CMN_UL_UPDT_INACTV_MASK( cellCb, ue, maskElmnt) \
161 if(RG_SCH_CMN_UL_IS_UE_ACTIVE(ue)) \
163 ue->ul.ulInactvMask &= ~maskElmnt; \
167 ue->ul.ulInactvMask &= ~maskElmnt; \
168 if(RG_SCH_CMN_UL_IS_UE_ACTIVE(ue)) \
170 rgSCHUtlUlActvtUe(cellCb, ue); \
174 #define RG_SCH_CMN_CSG_REFRESH_TIME 16
175 #define RG_SCH_CMN_OVRLDCTRL_REFRESH_TIME 50
177 /* totPrbCnt is set to 1 to avoid division by zero */
178 #define RG_SCH_RESET_HCSG_DL_PRB_CNTR(_cmnDlCell) \
180 (_cmnDlCell)->ncsgPrbCnt = 0; \
181 (_cmnDlCell)->totPrbCnt = 1; \
184 #define RG_SCH_RESET_HCSG_UL_PRB_CNTR(_cmnUlCell) \
186 (_cmnUlCell)->ncsgPrbCnt = 0; \
187 (_cmnUlCell)->totPrbCnt = 1; \
190 #define RG_SCH_CMN_DL_SVC_IS_GBR(svc) ((((RgSchCmnDlSvc*)(svc->sch))->qci >= RG_SCH_CMN_GBR_QCI_START) && \
191 (((RgSchCmnDlSvc*)(svc->sch))->qci <= RG_SCH_CMN_GBR_QCI_END))
193 /* Moved the below tables to rg_env_*.h files */
196 #define RG_SCH_CMN_SET_FORCE_TD(_ue,_cell, _event)\
198 RgSchCmnDlUe *_ueDl = RG_SCH_CMN_GET_DL_UE(_ue,_cell);\
199 _ueDl->mimoInfo.forceTD |= (_event);\
201 #define RG_SCH_CMN_UNSET_FORCE_TD(_ue,_cell, _event)\
203 RgSchCmnDlUe *_ueDl = RG_SCH_CMN_GET_DL_UE(_ue,_cell);\
204 _ueDl->mimoInfo.forceTD &= ~(_event);\
206 #define RG_SCH_CMN_INIT_FORCE_TD(_ue,_cell, _val)\
208 RgSchCmnDlUe *_ueDl = RG_SCH_CMN_GET_DL_UE(_ue,_cell);\
209 _ueDl->mimoInfo.forceTD = (_val);\
212 #define RG_SCH_CMN_DL_TBS_TO_MCS(x, y) do {\
214 else if (x <= 15) y = x + 1; \
218 #define RG_SCH_CMN_DL_MCS_TO_TBS(x, y) do {\
220 else if (x <= 16) y = x - 1; \
224 #define RG_SCH_CMN_UL_TBS_TO_MCS(x, y) do {\
225 if (x <= 10) y = x; \
226 else if (x <= 19) y = x + 1; \
231 #define RG_SCH_CMN_CHK_DL_DATA_ALLOWED(_cell, _idx)\
232 (rgSchTddUlDlSubfrmTbl[_cell->ulDlCfgIdx][_idx] == RG_SCH_TDD_DL_SUBFRAME) ||\
233 ((rgSchTddUlDlSubfrmTbl[_cell->ulDlCfgIdx][_idx] == RG_SCH_TDD_SPL_SUBFRAME) &&\
234 (_cell->splSubfrmCfg.isDlDataAllowed == TRUE))
235 #define RG_SCH_CMN_ADJ_DWPTS_ITBS(_cellDl, _iTbs) \
239 _iTbs += rgSchCmnSplSfDeltaItbs[_cellDl->splSfCfg];\
253 /* minimum grant, in bytes, to be given to HO and pdcchOrdered UEs */
254 #define RG_SCH_MIN_GRNT_HOPO 2
255 /* maximum dedPrmbls */
256 #define RG_SCH_MAX_DED_PRMBLS 60
257 /* is PDCCH order generation supported */
258 #define RG_SCH_CMN_IS_PO_SPRTD(cell) (cell->rachCfg.raOccasion.sfnEnum != RGR_SFN_NA)
259 /* Min gap value between crntTime and time of PRACH Oppurtunity */
260 /* RG_SCH_CMN_DL_DELTA is the number of SFs from crntTime at which
261 * UE is expected to recieve PDCCH Order.
262 * n+6 as per 213 6.1.1 last para */
263 #define RG_SCH_CMN_MIN_PRACH_OPPR_GAP (6+RG_SCH_CMN_DL_DELTA)
264 /* Idle time threshold in terms of subframes, implies
265 * the max duration between a TA expiry and latest UL
266 * data/Signal transmission time */
267 /* Fix : syed Ignore if TaTmr is not configured */
268 #define RG_SCH_CMN_UE_IDLE_THRSLD(ue) (RG_SCH_CMN_UE_IDLETIME_FCTR * ue->dl.taCb.cfgTaTmr)
270 #define RG_SCH_CMN_GET_BI_VAL(prevVal,numUe) ( prevVal + ( numUe * RG_SCH_CMN_BI_NUMUE_FACTOR ))
271 #define RG_SCH_CMN_NUMUE_FACTOR 1
272 #define RG_SCH_CMN_BITBL_INDEX(x) ((x/RG_SCH_CMN_NUMUE_FACTOR)>=12)? 12:(x/RG_SCH_CMN_NUMUE_FACTOR)
273 #define RG_SCH_CMN_GET_BI(numUe) rgSchCmnBiTbl[RG_SCH_CMN_BITBL_INDEX((numUe))]
276 #define RG_SCH_CMN_SVC_IS_GBR(svc) ((((RgSchCmnDlSvc*)(svc->sch))->qci >= RG_SCH_CMN_GBR_QCI_START) && \
277 (((RgSchCmnDlSvc*)(svc->sch))->qci <= RG_SCH_CMN_GBR_QCI_END))
279 #define RG_SCH_CMN_SVC_IS_AMBR(svc) ((((RgSchCmnDlSvc*)(svc->sch))->qci > RG_SCH_CMN_GBR_QCI_END) && \
280 (((RgSchCmnDlSvc*)(svc->sch))->qci <= RG_SCH_CMN_MAX_QCI))
282 #define RG_SCH_CMN_TBS_TO_MODODR(x, y) do {\
284 else if (x <= 10) y = 4; \
288 /* To include the length and ModOrder in DataRecp Req. */
289 #define RG_SCH_UL_MCS_TO_MODODR(x, y) do {\
290 RGSCH_ARRAY_BOUND_CHECK(0, rgUlIMcsTbl, x); \
291 y = (TfuModScheme)rgUlIMcsTbl[x].qm;\
294 #define RG_SCH_CMN_ITBS_TO_RETX_IMCS(iTbs, iMcs) do {\
295 if ((iTbs) <= 9) (iMcs) = 29; \
296 else if ((iTbs) <= 15) (iMcs) = 30; \
300 /* Fix for ccpu00123919: In case of RETX TB scheduling avoiding recomputation of RB
301 * and Tbs. Set all parameters same as Init TX except RV(only for NACKED) and
303 #define RG_SCH_CMN_GET_MCS_FOR_RETX(tb, retxMcs) do {\
304 if ((tb->isAckNackDtx == TFU_HQFDB_DTX)) { \
305 retxMcs = tb->dlGrnt.iMcs; \
308 if (tb->dlGrnt.iMcs < 29) {\
310 RG_SCH_CMN_DL_MCS_TO_TBS(tb->dlGrnt.iMcs, _iTbs);\
311 RG_SCH_CMN_ITBS_TO_RETX_IMCS(_iTbs, retxMcs); \
314 retxMcs = tb->dlGrnt.iMcs; \
319 #define RG_SCH_CMN_DL_TBS_TO_MCS_DTX(proc, iTbs, imcs) do {\
320 if ((proc->isAckNackDtx == TFU_HQFDB_DTX)) { \
321 RG_SCH_CMN_DL_TBS_TO_MCS(iTbs, imcs); \
324 RG_SCH_CMN_ITBS_TO_RETX_IMCS(iTbs, imcs); \
328 #define RG_SCH_CMN_UL_IS_CQI_VALID(cqi) ((cqi) > 0 && (cqi) < RG_SCH_CMN_UL_NUM_CQI)
331 #define RG_SCH_CMN_DL_GET_HDR_EST(svc, hdrEst) do {\
332 hdrEst = svc->estRlcHdrSz;\
333 hdrEst += RG_SCH_CMN_DED_MAX_HDRSIZE * RG_SCH_CMN_MAX_DED_SDU;\
334 if (svc->staPduPrsnt) \
336 hdrEst += RG_SCH_CMN_DED_MAX_HDRSIZE;\
340 #define RG_SCH_CMN_DL_GET_HDR_EST(svc, hdrEst) do {\
341 hdrEst = RG_SCH_CMN_DED_MAX_HDRSIZE * RG_SCH_CMN_MAX_DED_SDU;\
345 #define RGSCH_CMN_MIN_GRNT_HDR (RG_SCH_CMN_DED_MAX_HDRSIZE * RG_SCH_CMN_MAX_DED_SDU + 1)
347 #define RG_SCH_CMN_MAX_UL_CONTRES_GRNT 4
348 #define RG_SCH_CMN_UL_PRIOS RG_SCH_CMN_MAX_PRIO + 1
349 #define RG_SCH_CMN_MAX_ALLOC_TRACK 10
350 /* Introduced timing delta for UL control in FDD*/
351 #define RG_SCH_CMN_MIN_BSR_RECP_INTRVL (TFU_ULCNTRL_DLDELTA + RGSCH_PDCCH_PUSCH_DELTA)
352 #define RG_SCH_CMN_MIN_MSG3_RECP_INTRVL RG_SCH_CMN_DL_DELTA + RGSCH_RARSP_MSG3_DELTA
353 /* Introduced timing delta for DL control in FDD */
354 /* This interval RG_SCH_CMN_MIN_RETXMSG3_RECP_INTRVL is used in FDD only */
356 #define RG_SCH_CMN_MIN_RETXMSG3_RECP_INTRVL (TFU_DLCNTRL_DLDELTA + RGSCH_PDCCH_PUSCH_DELTA)
358 /* Fixing the priority table to be more in line with the spec 23.203,table
360 #define RG_SCH_CMN_QCI_TO_PRIO {1, 3, 2, 4, 0, 5, 6, 7, 8}
361 #define RG_SCH_CMN_DCCH_PRIO 0
363 #define RG_SCH_CMN_GBR_QCI_START 1
364 #define RG_SCH_CMN_GBR_QCI_END 4
365 #define RG_SCH_CMN_NGBR_QCI_START 6
366 #define RG_SCH_CMN_NGBR_QCI_END 9
369 #define RG_SCH_CMN_UL_GBR_PRIO_START 1
370 #define RG_SCH_CMN_UL_GBR_PRIO_END 4
371 /* Introduced min & max qci for validation of qci */
372 #define RG_SCH_CMN_MIN_QCI 1
373 #define RG_SCH_CMN_MAX_QCI 9
374 #define RG_SCH_CMN_NUM_QCI 9
375 #define RG_SCH_CMN_MAX_CP 2
376 #define RG_SCH_CMN_NOR_CP 0
377 #define RG_SCH_CMN_EXT_CP 1
378 #define RG_SCH_CMN_NUM_TBS 27
379 #define RG_SCH_CMN_MAX_CQI 16
380 #define RG_SCH_CMN_NUM_DCI 5 /* 6-0A, 6-1A, 6-0B, 6-1B and 6-2 */
381 #define RB_SCH_CMN_NUM_SCS_PER_RB 12
382 #define RG_SCH_CMN_NUM_RBS 110
383 #define RG_SCH_CMN_UL_NUM_SF RGSCH_NUM_UL_HQ_PROC+8
384 #define RG_SCH_CMN_UL_NUM_RE_PER_RB(cell) ((cell)->ulNumRePerRb)
386 #define RG_SCH_CMN_MAX_CMN_PDCCH 6
388 #define RG_SCH_CMN_MAX_CMN_PDCCH 4
390 #define RG_SCH_CMN_UL_MAX_CQI 16
391 #define RG_SCH_CMN_UL_SR_BYTES 1
392 /* Refresh Timer Defines */
393 /* MS_WORKAROUND : syed tuning refresh time to 100ms for PFS */
394 #define RG_SCH_CMN_REFRESH_TIME 32 /* Refresh time/cycle in frames (10ms) */
395 /* Fix: syed align multiple UEs to refresh at same time */
396 #define RG_SCH_CMN_REFRESH_TIMERES 10
397 #define RG_SCH_CMN_NUM_REFRESH_Q 16
398 #define RG_SCH_CMN_EVNT_UE_REFRESH 1
400 #define RG_SCH_CMN_TPC_ACC_DEC_THRESHOLD 1
401 #define RG_SCH_CMN_TPC_ACC_INC_1DB_THRESHOLD 1
402 #define RG_SCH_CMN_TPC_ACC_INC_3DB_THRESHOLD 3
403 #define RG_SCH_CMN_TPC_ABS_DEC_4DB_THRESHOLD 4
404 #define RG_SCH_CMN_TPC_ABS_DEC_1DB_THRESHOLD 1
405 #define RG_SCH_CMN_TPC_ABS_INC_1DB_THRESHOLD 4
406 #define RG_SCH_CMN_TPC_ABS_INC_4DB_THRESHOLD 4
408 /* ccpu00117606 - ADD - Include CRS REs while calculating Efficiency */
409 #define RG_SCH_CMN_MAX_ANT_CONF 3
410 #define RG_SCH_CMN_NUM_SLOTS_PER_SF 2
411 /* ccpu00117606 - ADD - Defines for Effective Cell RS for different Tx Ant Ports */
412 #define RG_SCH_CMN_EFF_CRS_ONE_ANT_PORT 6
413 #define RG_SCH_CMN_EFF_CRS_TWO_ANT_PORT 12
414 #define RG_SCH_CMN_EFF_CRS_FOUR_ANT_PORT 16
416 /* ADD-new defines for Min & Max RI values */
417 #define RG_SCH_CMN_MIN_RI 1
418 #define RG_SCH_CMN_MAX_RI 4
420 #define RG_SCH_CMN_MAX_CW_PER_UE 2
422 #define RG_SCH_CMN_IS_RI_VALID(ri) \
423 (ri >= RG_SCH_CMN_MIN_RI && ri <= RG_SCH_CMN_MAX_RI)
425 #define RGSCHCMNADDTOCRNTTIME(crntTime, toFill, incr) \
428 absoluteTime = crntTime.sfn * RGSCH_NUM_SUB_FRAMES_5G + crntTime.subframe;\
429 absoluteTime += incr;\
430 toFill.sfn = (absoluteTime /RGSCH_NUM_SUB_FRAMES_5G)% 1024;\
431 toFill.subframe = absoluteTime % RGSCH_NUM_SUB_FRAMES_5G;\
435 #define RG_SCH_CMN_PWR_USE_CFG_MAX_PWR (-128)
437 #define RG_SCH_CMN_RARSP_WAIT_PRD 3
439 #define RG_SCH_CMN_MAX_SPL_CFI 2
440 #define RG_SCH_CMN_INVALID_INFO 0xff
441 #define RG_SCH_CMN_NUM_SUBCAR 12
443 #define RG_SCH_CMN_SUBFRM_0 0
444 #define RG_SCH_CMN_SPL_SUBFRM_1 1
445 #define RG_SCH_CMN_SUBFRM_5 5
446 #define RG_SCH_CMN_SPL_SUBFRM_6 6
448 #define RG_SCH_CMN_VALUE_ONE 1
450 #define RG_SCH_CMN_IS_ODD(x) ((x) & 0x01)
452 #define RG_SCH_CMN_MAX_NUM_OF_SFN 10240
453 #define RG_SCH_CMN_MAX_SFN_NUM 1023
455 #define RG_SCH_CMN_NUM_DL_AT_SWTCHPT 2
457 #define RG_SCH_CMN_10_MS_PRD 10
458 #define RG_SCH_CMN_5_MS_PRD 5
460 #define RG_SCH_CMN_DECR_FRAME(_x, _y) {\
461 S16 _tmpNo = (_x) - (_y); \
463 (_x) = _tmpNo + RGSCH_MAX_SFN; \
471 /* ADD-new hash define for max msg3 mcs val */
472 #define RG_SCH_CMN_MAX_EMTC_MSG3_IMCS 7
475 #define RG_SCH_CMN_MAX_MSG3_IMCS 15
477 #define RG_SCH_CMN_CALC_RARSPLST_SIZE(cell, raArrsz) {\
479 /* Get the last UL subframe no */ \
480 for(_sfNum=RGSCH_NUM_SUB_FRAMES-1; _sfNum >= 0; _sfNum--) \
482 if(rgSchTddUlDlSubfrmTbl[(cell)->ulDlCfgIdx][_sfNum] == \
483 RG_SCH_TDD_UL_SUBFRAME) \
488 (raArrSz) = (_sfNum + ((RgSchCmnCell *)(cell)->sc.sch)->dl.numRaSubFrms \
489 + RG_SCH_CMN_RARSP_WAIT_PRD + \
490 (cell)->rachCfg.raWinSize - 1) / RGSCH_NUM_SUB_FRAMES + 1; \
493 /* Resource allocation type MACROs */
494 #define RG_SCH_CMN_RA_TYPE0 0
495 #define RG_SCH_CMN_RA_TYPE1 1
496 #define RG_SCH_CMN_RA_TYPE2 2
497 /* Added support for SPS*/
499 #define RG_SCH_SPS_CONS_DYN_SCHD 5
500 #define RG_SCH_SPS_CONS_RED_BO 5
501 #define RG_SCH_DL_SPS_ADDTL_BO RGSCH_TA_SIZE /* 2 Bytes for TA */
502 /* RBG subset MACROs for RA type 1 */
503 #define RG_SCH_CMN_RBG_SUBSET0 0
504 #define RG_SCH_CMN_RBG_SUBSET1 1
505 #define RG_SCH_CMN_RBG_SUBSET2 2
506 #define RG_SCH_CMN_RBG_SUBSET3 3
507 #define RG_SCH_CMN_DL_NUM_ALLOCMASK 9
508 #define RG_SCH_CMN_SPS_MAX_PRD 640
509 #define RG_SCH_SPS_SID_INTERVAL 80
510 #define RG_SCH_CMN_SPS_DL_ACTV (1 << 0)
511 #define RG_SCH_CMN_SPS_DL_REACTV_FREQ (1 << 1)
512 #define RG_SCH_CMN_SPS_DL_REACTV_TIME (1 << 2)
513 #define RG_SCH_CMN_SPS_DL_REACTV \
514 (RG_SCH_CMN_SPS_DL_REACTV_FREQ | RG_SCH_CMN_SPS_DL_REACTV_TIME)
515 #define RG_SCH_CMN_SPS_DL_REL (1 << 3)
516 #define RG_SCH_CMN_SPS_DL_MAX_N1PUCCH_IDX_PER_UE 4
517 /* Number of 32 bit bitmasks for marking measurement gap for SPS */
518 #define RG_SCH_CMN_SPS_DL_MEASGAP_32BITMASK_SIZE 3
520 /* 32 Bit mask size for n1Pucch: RG_SCH_SPS_DL_MAX_N1PUCCH_PER_SF/32 */
521 #define RG_SCH_CMN_SPS_DL_N1PUCCH_32BITMASK_SIZE \
522 ((RG_SCH_SPS_DL_MAX_N1PUCCH_PER_SF + 31)/32)
523 #define RG_SCH_CMN_SPS_DL_INVALIDCQI_VAL 20
525 /* Maximum number of feasible periodicity values for SPS, SRS, CQI and SR */
526 #define RG_SCH_CMN_SPS_MAX_NUM_PRD 21
528 /* Maximum value of iMcs for SPS UE */
529 #define RG_SCH_CMN_SPS_DL_MAX_MCS 15
531 /* Minimum gap between SPEECH_GOOD packet and SID packet */
532 #define RG_SCH_CMN_MIN_GAP_FOR_SID 60
534 /* DL SPS function MACROs */
537 #define RG_SCH_CMN_SPS_GET_DL_CELL(cell) &(((RgSchCmnCell *)((cell)->sc.sch))->dl.dlSpsInfo)
538 #define RG_SCH_CMN_SPS_GET_DL_UE(_ue) &(((RgSchCmnUe *)(((_ue)->cellInfo[0])->sch))->dl.dlSpsInfo)
539 #define RG_SCH_CMN_SPS_GET_DL_SVC(svc) &(((RgSchCmnDlSvc *)((svc)->sch))->dlSvcSpsInfo)
540 #define RG_SCH_CMN_SPS_DL_IS_SPS_HQP(hqP) (((RgSchCmnDlHqProc *)((hqP)->sch))->isSpsSvcSchd)
541 #define RG_SCH_CMN_SPS_DL_IS_SPS_TX_HQP(hqP) (((RgSchCmnDlHqProc *)((hqP)->sch))->isSpsActv)
542 #define RG_SCH_CMN_IS_UE_SPS_SCHDLD(_ue, _cell, _schdTime)\
543 ((((_ue)->cellInfo[(_ue->cellIdToCellIdxMap[RG_SCH_CELLINDEX(_cell)])])->dlAllocCb.spsSchdTime.sfn == _schdTime.sfn) &&\
544 (((_ue)->cellInfo[(_ue->cellIdToCellIdxMap[RG_SCH_CELLINDEX(_cell)])])->dlAllocCb.spsSchdTime.subframe == _schdTime.subframe))
546 #define RG_SCH_CMN_DL_COUNT_ONES(_bitMask, _size, _numOnes)\
550 for (_pos = 0; _pos < _size; ++_pos)\
552 *_numOnes += (_bitMask & (1 << (31 - _pos))) ? 1: 0;\
556 #define RG_SCH_CMN_DL_GET_START_POS(_allocedBitmask, _size, _startPos)\
559 for (_pos = 0; _pos < _size; ++_pos)\
561 if ((_allocedBitmask & (1 << (31 -_pos))))\
573 /* This macros returns position of idx in a 32 bit bitmask from LSB */
574 #define RG_SCH_CMN_DL_GET_POS_FRM_LSB(_idx) (31 - (_idx))
576 #define RG_SCH_CMN_SPS_GET_PRD_IDX(_prdVal, _prdIdx)\
580 case 2: *_prdIdx = RG_SCH_CMN_SPS_PRD_2SF; break;\
581 case 5: *_prdIdx = RG_SCH_CMN_SPS_PRD_5SF; break;\
582 case 10: *_prdIdx = RG_SCH_CMN_SPS_PRD_10SF; break;\
583 case 20: *_prdIdx = RG_SCH_CMN_SPS_PRD_20SF; break;\
584 case 30: *_prdIdx = RG_SCH_CMN_SPS_PRD_30SF; break;\
585 case 32: *_prdIdx = RG_SCH_CMN_SPS_PRD_32SF; break;\
586 case 40: *_prdIdx = RG_SCH_CMN_SPS_PRD_40SF; break;\
587 case 60: *_prdIdx = RG_SCH_CMN_SPS_PRD_60SF; break;\
588 case 64: *_prdIdx = RG_SCH_CMN_SPS_PRD_64SF; break;\
589 case 80: *_prdIdx = RG_SCH_CMN_SPS_PRD_80SF; break;\
590 case 120: *_prdIdx = RG_SCH_CMN_SPS_PRD_120SF; break;\
591 case 128: *_prdIdx = RG_SCH_CMN_SPS_PRD_128SF; break;\
592 case 160: *_prdIdx = RG_SCH_CMN_SPS_PRD_160SF; break;\
593 case 256: *_prdIdx = RG_SCH_CMN_SPS_PRD_256SF; break;\
594 case 320: *_prdIdx = RG_SCH_CMN_SPS_PRD_320SF; break;\
595 case 512: *_prdIdx = RG_SCH_CMN_SPS_PRD_512SF; break;\
596 case 640: *_prdIdx = RG_SCH_CMN_SPS_PRD_640SF; break;\
597 case 1024: *_prdIdx = RG_SCH_CMN_SPS_PRD_1024SF; break;\
598 case 1280: *_prdIdx = RG_SCH_CMN_SPS_PRD_1280SF; break;\
599 case 2048: *_prdIdx = RG_SCH_CMN_SPS_PRD_2048SF; break;\
600 case 2560: *_prdIdx = RG_SCH_CMN_SPS_PRD_2560SF; break;\
601 default: *_prdIdx = RG_SCH_CMN_SPS_PRD_INVALID;break;\
605 /* To be part of rg_env.h */
606 /* Maximum n1Pucch values per sub-frame: multiple of 32 */
607 #define RG_SCH_SPS_DL_MAX_N1PUCCH_PER_SF 96
608 #define RG_SCH_SPS_DFLT_PRD 20
609 #define RG_SCH_SPS_CQI_DECR_VAL 2
612 /* Added RgrSpsPrd casting to overcome G++ compilation warning*/
613 #define RGSCH_SPS_GET_PRDCTY(_prdEnum, _prd) \
617 case RGR_SPS_PRD_10SF: \
618 (_prd) = (RgrSpsPrd)10; \
620 case RGR_SPS_PRD_20SF: \
621 (_prd) = (RgrSpsPrd)20; \
623 case RGR_SPS_PRD_32SF: \
624 (_prd) = (RgrSpsPrd)30; \
626 case RGR_SPS_PRD_40SF: \
627 (_prd) = (RgrSpsPrd)40; \
629 case RGR_SPS_PRD_64SF: \
630 (_prd) =(RgrSpsPrd)60; \
632 case RGR_SPS_PRD_80SF: \
633 (_prd) = (RgrSpsPrd)80; \
635 case RGR_SPS_PRD_128SF: \
636 (_prd) = (RgrSpsPrd)120; \
638 case RGR_SPS_PRD_160SF: \
639 (_prd) = (RgrSpsPrd)160; \
641 case RGR_SPS_PRD_320SF: \
642 (_prd) = (RgrSpsPrd)320; \
644 case RGR_SPS_PRD_640SF: \
645 (_prd) = (RgrSpsPrd)640; \
648 (_prd) = RGR_SPS_PRD_INVALID;\
652 /* ADD-hash define for actual transmission time */
653 /* Feedback for RelPdcch should be received at MAC by HARQ_INTERVAL+
654 * RG_TFU_HQ_IND_DELTA time.*/
655 #define RG_SCH_CMN_SPS_TX_TIME (RG_SCH_CMN_HARQ_INTERVAL + TFU_HQFBKIND_ULDELTA)
656 #endif /* LTEMAC_SPS */
658 /* LTE_ADV_FLAG_REMOVED_START */
659 #define RG_SCH_CMN_IS_UE_CELL_EDGE(_ue) _ue->lteAdvUeCb.rgrLteAdvUeCfg.isUeCellEdge;
660 #define RG_SCH_CMN_IS_SFR_ENB(_rgSchCellCb) _rgSchCellCb->lteAdvCb.sfrCfg.status;
661 #define RG_SCH_CMN_SFR_POOL(_subFrm) _subFrm->sfrTotalPoolInfo;
663 #define RG_SCH_MAX_RNTP_SAMPLES 10000
664 /* LTE_ADV_FLAG_REMOVED_END */
667 #define RG_SCH_CMN_IS_SCELL_ACTV(_ue,_sCellIdx) (((_ue)->cellInfo[_sCellIdx] != NULLP) && \
668 ((_ue)->cellInfo[_sCellIdx]->sCellState == RG_SCH_SCELL_ACTIVE))
670 /* As per spec 36.133 sec 7.7.3*/
671 #define RG_SCH_CMN_MAX_SCELL_ACT_DELAY 24
673 #define RG_SCH_CMN_SCELL_ACT_DELAY_TMR (RG_SCH_CMN_MAX_SCELL_ACT_DELAY - TFU_HQFBKIND_ULDELTA - RG_SCH_CMN_HARQ_INTERVAL)
676 /* Is this harq proc belongs to P-cell or S-cell */
677 #define RG_SCH_CMN_IS_PCELL_HQP(hqP) (((hqP->hqE->ue)&&(hqP->hqE->ue->cell == hqP->hqE->cell))?TRUE:FALSE)
678 #define RG_SCH_CMN_GET_CELL_IDX_FROM_HQP(hqP) hqP->hqE->ue->cellIdToCellIdxMap[hqP->hqE->cell->cellId]
681 /* DL allocation MACROs */
683 #define RG_SCH_CMN_GET_ALLOCCB_FRM_UE(_ue,_cell) &(((_ue)->cellInfo[(_ue)->cellIdToCellIdxMap\
684 [RG_SCH_CELLINDEX(_cell)]])->dlAllocCb);
685 #define RG_SCH_CMN_GET_ALLOCCB_FRM_RACB(_raCb) &((_raCb)->rbAllocInfo);
686 #define RG_SCH_CMN_INIT_SCHD_LNK(_schdLstLnk, _node)\
688 (_schdLstLnk)->node = (PTR)_node;\
689 (_schdLstLnk)->prev = NULLP;\
690 (_schdLstLnk)->next = NULLP;\
693 /* Changes for MIMO feature addition */
694 #define RG_SCH_CMN_FILL_DL_TXINFO(_allocInfo, _rb, _sFlg, _prcInf, _numLyr, _sf)\
696 _allocInfo->rbsReq = _rb;\
697 _allocInfo->mimoAllocInfo.swpFlg = _sFlg;\
698 _allocInfo->mimoAllocInfo.precIdxInfo = _prcInf;\
699 _allocInfo->mimoAllocInfo.numTxLyrs = _numLyr;\
700 _allocInfo->dlSf = _sf;\
703 #define RG_SCH_CMN_FILL_DL_TBINFO(_tbInfo, _bytsReq, _iTbs, _imcs, _tbCb, _noLyr)\
705 (_tbInfo)->schdlngForTb = TRUE;\
706 (_tbInfo)->bytesReq = _bytsReq;\
707 (_tbInfo)->iTbs = _iTbs;\
708 (_tbInfo)->imcs = _imcs;\
709 (_tbInfo)->tbCb = _tbCb;\
710 (_tbInfo)->noLyr = _noLyr;\
713 /* Bit Masks to Force Transmit diversity scheme */
714 #define RG_SCH_CMN_TD_RI_1 0x01 /* Transmit Diversity due to RI==1 in case
716 #define RG_SCH_CMN_TD_NO_PMI 0x02 /* Transmit Diversity due to No PMI */
717 #define RG_SCH_CMN_TD_TXMODE_RECFG 0x04 /* Transmit Diversity due to TXMODE ReCfg */
718 #define RG_SCH_CMN_TD_TXSCHEME_CHNG 0x08 /* Transmit Diversity due to TX scheme
720 #define RG_SCH_CMN_TD_LAA_SINGLE_TB 0x10 /* Transmit Diversity due to one LAA TB
723 #define RG_SCH_MAX_UL_TX_ANT 2
725 /*Maximum achievable code rate for non 64QAM UEs.
726 *Value should NEVER be > than 93. Refer to 36.213, Table 7.2.3-1*/
727 #define RG_SCH_CMN_MAX_CODE_RATE_16QAM 85 /* 85% code rate*/
728 #define RG_SCH_CMN_MAX_EFF_BITS 4096
730 /* Refer BI table from 36.321 Table 7.2.1 */
731 #define RG_SCH_CMN_NUM_BI_VAL 13
733 /*New macro to determine UE Category. We use the stored "ueCat" to
734 * index a UE category array. Therefore, the stored ueCat is 1 less
735 * than actual UE cateogry.*/
736 #define RG_SCH_CMN_GET_UE_CTGY(ue) ((RG_SCH_CMN_GET_CMN_UE(ue))->ueCat + 1)
737 /*ccpu00117270-ADD-END*/
739 #define RG_SCH_CMN_UPD_RBS_TO_ADD(_CELL,_DLSF,_ALLCINFO,_RBSREQ,_RBSTOADD) \
742 addtlRbsAvl = rgSCHCmnFindNumAddtlRbsAvl(_CELL,_DLSF,_ALLCINFO);\
743 if(_RBSREQ > addtlRbsAvl)\
745 _RBSTOADD = addtlRbsAvl;\
749 _RBSTOADD = _RBSREQ;\
752 /* ccpu00126002 ADD macro added to check wrap around when index is reached
753 MAX_CQI_RI_RPT_BUFF*/
754 #define RG_SCH_INCR_CQIRI_INDEX(idx)\
757 if(MAX_CQI_RI_RPT_BUFF == idx)\
761 if(MAX_CQI_RI_RPT_BUFF <= idx)\
763 printf("\n Invalid CQI write index:%d ",idx);\
766 #define RG_SCH_DECR_CQIRI_INDEX(idx)\
770 idx = (MAX_CQI_RI_RPT_BUFF -1 );\
776 printf("\n Invalid CQI write index:%d ",idx);\
781 #define RG_SCH_CHK_ITBS_RANGE(_iTbs, _maxiTbs) \
787 else if (_iTbs > (_maxiTbs))\
794 /* LTE_ADV_FLAG_REMOVED_START */
795 #define RG_SCH_CMN_SFR_UPD_RBS_TO_ADD_IN_POOL(_CELL,_DLSF,_POOLINFO,_ALLCINFO,_RBSREQ,_RBSTOADD) \
798 addtlRbsAvl = rgSCHCmnSFRFindNumAddtlRbsAvl(_CELL,_DLSF,_POOLINFO,_ALLCINFO);\
799 if(_RBSREQ > addtlRbsAvl)\
801 _RBSTOADD = addtlRbsAvl;\
805 _RBSTOADD = _RBSREQ;\
808 /* LTE_ADV_FLAG_REMOVED_END */
810 /* DELTA for CFI applying */
811 #define RG_SCH_CFI_APPLY_DELTA 4
812 #define RG_SCH_MAX_TX_LYRS_4 4 /*CA dev*/
814 #define RG_SCH_CFI_STEP_UP(_cell, _cellSch, _currCfi)\
816 _cellSch->dl.newCfi = ((_currCfi) < _cell->dynCfiCb.maxCfi) ? \
817 (_currCfi + 1):_cell->dynCfiCb.maxCfi; \
818 _cell->dynCfiCb.cfiIncr++; \
821 #define RG_SCH_CFI_STEP_DOWN(_cell, _cellSch, _currCfi)\
823 _cellSch->dl.newCfi = _currCfi-1; \
824 _cell->dynCfiCb.cfiDecr++; \
827 #define RG_SCH_UPDT_CW2_CQI(_cqiCw1,_cqiCw2,_diffCqi)\
828 if (_cqiCw1 > rgSchCmnDlCqiDiffOfst[_diffCqi]) \
830 _cqiCw2 = _cqiCw1 - rgSchCmnDlCqiDiffOfst[_diffCqi]; \
838 /* TM Mode Step Up/Down Factor macros */
839 #define RG_SCH_MODE_CHNG_STEPUP_FACTOR 1
840 #define RG_SCH_MODE_CHNG_STEPDOWN_FACTOR 1
841 #define RG_SCH_MODE_CHNG_STEPUP_THRSHD 150
842 #define RG_SCH_MODE_CHNG_STEPDOWN_CHECK_FACTOR 10
843 #define RG_SCH_MODE_CHNG_STEPDOWN_THRSHD 100
845 #define RG_SCH_TXSCHEME_CHNG_THRSHD 5
846 #define RG_SCH_TXSCHEME_CHNG_ITBS_FACTOR 5
848 #define RG_SCH_FILL_RGM_TRANSMODE_IND(_ueId, _cellId, _mode, _txModChgInd)\
850 _txModChgInd->usCrnti = _ueId;\
851 _txModChgInd->bCellId = _cellId;\
852 _txModChgInd->eMode = _mode - 1;\
858 #endif /* __RGSCHCMNH__ */
860 /********************************************************************30**
863 **********************************************************************/