1 /******************************************************************************
2 * Copyright (c) 2019 Intel.
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
16 *******************************************************************************/
19 * This file consist of FAPI configuration APIs macros, structure typedefs and
24 #ifndef _NR5G_FAPI_INTELNAL_H_
25 #define _NR5G_FAPI_INTELNAL_H_
27 #include "fapi_interface.h"
28 #include "nr5g_fapi_common_types.h"
30 #define MAX_UL_SLOT_INFO_COUNT 20 //Maximum no of Slots for which UL_TTI.request info has to
31 #define MAX_UL_SYMBOL_INFO_COUNT FAPI_MAX_NR_OF_SYMBOLS
32 //Maximum no of symbols which may be configured with separate UL_TTI.request (URLLC)
33 #define FAPI_MAX_NUM_PUSCH_PDU 255 //as per Table 3-44
34 #define FAPI_MAX_NUM_PUCCH_PDU 255 //as per Table 3-44
35 #define FAPI_MAX_NUM_SRS_PDU 255 //as per Table 3-73
36 #define FAPI_MAX_NUM_RACH_PDU 255 //as per Table 3-74
37 #define FAPI_MAX_PHY_INSTANCES 24
38 #define FAPI_MAX_SLOT_INFO_URLLC 2
40 // CONFIGURATION INFORMATION CARRIER CONFIGURATION BANDWIDTH
41 #define FAPI_BANDWIDTH_5_MHZ 5
42 #define FAPI_BANDWIDTH_10_MHZ 10
43 #define FAPI_BANDWIDTH_15_MHZ 15
44 #define FAPI_BANDWIDTH_20_MHZ 20
45 #define FAPI_BANDWIDTH_25_MHZ 25
46 #define FAPI_BANDWIDTH_30_MHZ 30
47 #define FAPI_BANDWIDTH_40_MHZ 40
48 #define FAPI_BANDWIDTH_50_MHZ 50
49 #define FAPI_BANDWIDTH_60_MHZ 60
50 #define FAPI_BANDWIDTH_70_MHZ 70
51 #define FAPI_BANDWIDTH_80_MHZ 80
52 #define FAPI_BANDWIDTH_90_MHZ 90
53 #define FAPI_BANDWIDTH_100_MHZ 100
54 #define FAPI_BANDWIDTH_200_MHZ 200
55 #define FAPI_BANDWIDTH_400_MHZ 400
57 #define FAPI_SUBCARRIER_SPACING_15 0
58 #define FAPI_SUBCARRIER_SPACING_30 1
59 #define FAPI_SUBCARRIER_SPACING_60 2
60 #define FAPI_SUBCARRIER_SPACING_120 3
62 #define FAPI_FFT_SIZE_512 512
63 #define FAPI_FFT_SIZE_1024 1024
64 #define FAPI_FFT_SIZE_2048 2048
65 #define FAPI_FFT_SIZE_4096 4096
67 #define FAPI_MAX_DL_LAYERS MAX_NUM_DL_LAYERS
68 #define FAPI_MAX_UL_LAYERS 4
69 // FAPI Supports MAX 12; Mapping to Intel Phys capabilities
70 #define FAPI_MAX_DMRS_PORTS MAX_DL_PER_UE_DMRS_PORT_NUM
71 // FAPI Supports MAX 12; Mapping to Intel Phys capabilities
72 #define FAPI_MAX_PTRS_PORTS MAX_DL_PER_UE_PTRS_PORT_NUM
76 * FAPI state is maintained per fapi instance. If FAPI messages are received in
77 * wrong state an ERROR.indication message will be sent by FAPI.
79 typedef enum _fapi_states {
81 FAPI_STATE_CONFIGURED,
86 FAPI_PUCCH_FORMAT_TYPE_0 = 0,
87 FAPI_PUCCH_FORMAT_TYPE_1,
88 FAPI_PUCCH_FORMAT_TYPE_2,
89 FAPI_PUCCH_FORMAT_TYPE_3,
90 FAPI_PUCCH_FORMAT_TYPE_4,
91 } nr5g_fapi_uci_format_t;
95 uint16_t initial_cyclic_shift;
96 uint8_t nr_of_symbols;
97 uint8_t start_symbol_index;
98 uint8_t time_domain_occ_idx;
99 } nr5g_fapi_pucch_resources_t;
103 MEM_STAT_CONFIG_REQ = 0,
106 MEM_STAT_SHUTDOWN_REQ,
107 MEM_STAT_DL_CONFIG_REQ,
108 MEM_STAT_UL_CONFIG_REQ,
111 MEM_STAT_DL_IQ_SAMPLES,
112 MEM_STAT_UL_IQ_SAMPLES,
117 #define RELEASE_15 0x0001
119 #define FAPI_NORMAL_CYCLIC_PREFIX_MASK 0x01
120 #define FAPI_EXTENDED_CYCLIC_PREFIX_MASK 0x02
123 #define FAPI_CCE_MAPPING_INTERLEAVED_MASK 0x01
124 #define FAPI_CCE_MAPPING_NONINTERLVD_MASK 0x02
125 // Upper Bound for PDCCH Channels per Slot
126 #define FAPI_MAX_PDCCHS_PER_SLOT_MASK 0xff
129 #define FAPI_FORMAT_0_MASK 0x01
130 #define FAPI_FORMAT_1_MASK 0x02
131 #define FAPI_FORMAT_2_MASK 0x04
132 #define FAPI_FORMAT_3_MASK 0x08
133 #define FAPI_FORMAT_4_MASK 0x10
134 // Upper Bound for PUCCH Channels per Slot
135 #define FAPI_MAX_PUCCHS_PER_SLOT_MASK 0xff
138 #define FAPI_PDSCH_MAPPING_TYPE_A_MASK 0x01
139 #define FAPI_PDSCH_MAPPING_TYPE_B_MASK 0x02
140 #define FAPI_PDSCH_ALLOC_TYPE_0_MASK 0x01
141 #define FAPI_PDSCH_ALLOC_TYPE_1_MASK 0x02
142 #define FAPI_PDSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK 0x01
143 #define FAPI_PDSCH_VRB_TO_PRB_MAP_INTLVD_MASK 0x02
144 #define FAPI_PDSCH_DMRS_CONFIG_TYPE_1_MASK 0x01
145 #define FAPI_PDSCH_DMRS_CONFIG_TYPE_2_MASK 0x02
146 #define FAPI_PDSCH_DMRS_MAX_LENGTH_1 0
147 #define FAPI_PDSCH_DMRS_MAX_LENGTH_2 1
148 #define FAPI_DMRS_ADDITIONAL_POS_0_MASK 0x01
149 #define FAPI_DMRS_ADDITIONAL_POS_1_MASK 0x02
150 #define FAPI_DMRS_ADDITIONAL_POS_2_MASK 0x04
151 #define FAPI_DMRS_ADDITIONAL_POS_3_MASK 0x08
152 // Upper Limit for PDSCHS TBs per Slot
153 #define FAPI_MAX_PDSCHS_TBS_PER_SLOT_MASK 0xff
154 #define FAPI_MAX_NUMBERMIMO_LAYERS_PDSCH 2
156 // Subcarrier spacing information
157 #define FAPI_15KHZ_MASK 0x01
158 #define FAPI_30KHZ_MASK 0x02
159 #define FAPI_60KHZ_MASK 0x04
160 #define FAPI_120KHZ_MASK 0x08
162 // Bandwitdth information
163 #define FAPI_5MHZ_BW_MASK 0x0001
164 #define FAPI_10MHZ_BW_MASK 0x0002
165 #define FAPI_15MHZ_BW_MASK 0x0004
166 #define FAPI_20MHZ_BW_MASK 0x0010
167 #define FAPI_40MHZ_BW_MASK 0x0020
168 #define FAPI_50MHZ_BW_MASK 0x0040
169 #define FAPI_60MHZ_BW_MASK 0x0080
170 #define FAPI_70MHZ_BW_MASK 0x0100
171 #define FAPI_80MHZ_BW_MASK 0x0200
172 #define FAPI_90MHZ_BW_MASK 0x0400
173 #define FAPI_100MHZ_BW_MASK 0x0800
174 #define FAPI_200MHZ_BW_MASK 0x1000
175 #define FAPI_400MHZ_BW_MASK 0x2000
177 #define FAPI_MAX_MUMIMO_USERS_MASK 0xff
180 #define FAPI_PUSCH_MAPPING_TYPE_A_MASK 0x01
181 #define FAPI_PUSCH_MAPPING_TYPE_B_MASK 0x02
182 #define FAPI_PUSCH_ALLOC_TYPE_0_MASK 0x01
183 #define FAPI_PUSCH_ALLOC_TYPE_1_MASK 0x02
184 #define FAPI_PUSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK 0x01
185 #define FAPI_PUSCH_VRB_TO_PRB_MAP_INTLVD_MASK 0x02
186 #define FAPI_PUSCH_DMRS_CONFIG_TYPE_1_MASK 0x01
187 #define FAPI_PUSCH_DMRS_CONFIG_TYPE_2_MASK 0x02
188 #define FAPI_PUSCH_DMRS_MAX_LENGTH_1 0
189 #define FAPI_PUSCH_DMRS_MAX_LENGTH_2 1
190 // Upper limit for PUSCHMAXPTRSPORTS
191 #define FAPI_PUSCH_MAX_PTRS_PORTS_UB 2
192 //Upper Limit for PDSCHS TBs per Slot
193 #define FAPI_MAX_PUSCHS_TBS_PER_SLOT_MASK 0xff
196 #define FAPI_PRACH_LF_FORMAT_0_MASK 0x01
197 #define FAPI_PRACH_LF_FORMAT_1_MASK 0x02
198 #define FAPI_PRACH_LF_FORMAT_2_MASK 0x04
199 #define FAPI_PRACH_LF_FORMAT_3_MASK 0x08
201 #define FAPI_PRACH_SF_FORMAT_A1_MASK 0x01
202 #define FAPI_PRACH_SF_FORMAT_A2_MASK 0x02
203 #define FAPI_PRACH_SF_FORMAT_A3_MASK 0x04
204 #define FAPI_PRACH_SF_FORMAT_B1_MASK 0x08
205 #define FAPI_PRACH_SF_FORMAT_B2_MASK 0x10
206 #define FAPI_PRACH_SF_FORMAT_B3_MASK 0x20
207 #define FAPI_PRACH_SF_FORMAT_B4_MASK 0x40
208 #define FAPI_PRACH_SF_FORMAT_C0_MASK 0x80
209 #define FAPI_PRACH_SF_FORMAT_C2_MASK 0x100
211 // Measurement Parameters
212 #define FAPI_RSSI_REPORT_IN_DBM_MASK 0x01
213 #define FAPI_RSSI_REPORT_IN_DBFS_MASK 0x02
215 // Frequency needs to track 38.104 Section 5.2 and 38.211 Section 5.3.1
217 #define FAPI_MIN_FREQUENCY_PT_A 450000
219 #define FAPI_MAX_FREQUENCY_PT_A 52600000
220 // dlk0, ulk0 per 38.211 Section 5.3.1
222 #define FAPI_K0_MAX 23699
223 // dlGridSize, ulGridSize per 38.211 Section 4.4.2
225 #define FAPI_GRIDSIZE_MAX 275
226 // Number of Transmit Antennas
227 // Define upper mask based on variable type
228 #define FAPI_NUM_ANT_MASK 0xffff
229 // CELL CONFIGURATION
230 // Physical Cell ID from 38.211 Section 7.4.2.1
232 #define FAPI_MAX_CELL_ID 1007
234 // SSB POWER RANGE in dBm
235 #define FAPI_SS_PBCH_LOWEST_POWER -60
236 #define FAPI_SS_PBCH_MAX_POWER 50
237 // BCH PAYLOAD for 5G the MAC always generates the BCH Payload
238 #define FAPI_BCH_PAYLOAD_GEN_BY_MAC 0
239 #define FAPI_BCH_PAYLOAD_WITH_PHY_GEN_TIMING 1
240 #define FAPI_BCH_PAYLOAD_ENTIRELY_GEN_BY_PHY 2
242 #define FAPI_SCSCOMMON_MASK 0x03
243 // PRACH CONFIGURATION
244 #define FAPI_PRACH_LONG_SEQUENCE 0
245 #define FAPI_PRACH_SHORT_SEQUENCE 1
246 #define FAPI_PRACH_SUBC_SPACING_MAX 4
247 // Restricted Set Configuration
248 #define FAPI_PRACH_RESTRICTED_SET_UNRESTRICTED 0
249 #define FAPI_PRACH_RESTRICTED_SET_TYPE_A 1
250 #define FAPI_PRACH_RESTRICTED_SET_TYPE_B 2
251 // Root Sequence Index
253 #define FAPI_PRACH_ROOT_SEQ_INDEX_MAX 837
256 #define FAPI_K1_UPPER_BOUND 272
257 // PRACH Zero Corr Configuration
259 #define FAPI_PRACHZEROCORRCONF_MASK 0x0f
260 // Number of Unused Root Sequences Mask
261 #define FAPI_UNUSEDROOTSEQUENCES_MASK 0x0f
263 #define FAPI_SSB_SUB6_THRESHOLD 6000000
264 // Ssb Offset Point A max
265 #define FAPI_SSB_OFFSET_POINTA_MAX 2199
266 // betaPSS i.e. PSS EPRE to SSS EPRE in a SS/PBCH Block per 38.213 Section 4.1
267 #define FAPI_BETAPSS_0_DB 0
268 #define FAPI_BETAPSS_3_DB 1
270 #define FAPI_SSB_PERIOD_5_MS 0
271 #define FAPI_SSB_PERIOD_10_MS 1
272 #define FAPI_SSB_PERIOD_20_MS 2
273 #define FAPI_SSB_PERIOD_40_MS 3
274 #define FAPI_SSB_PERIOD_80_MS 4
275 #define FAPI_SSB_PERIOD_160_MS 5
276 // Ssb Subcarrier Offset per 38.211 Section 7.4.3.1
277 // SsbSubcarrierOffset mask
278 #define FAPI_SSB_SUBCARRIER_OFFSET_MASK 0x1f
280 #define MIB_PAYLOAD_MASK 0xfff0
282 #define FAPI_BEAM_ID_MASK 0x3f
285 #define FAPI_TDD_PERIOD_0_P_5_MS 0
286 #define FAPI_TDD_PERIOD_0_P_625_MS 1
287 #define FAPI_TDD_PERIOD_1_MS 2
288 #define FAPI_TDD_PERIOD_1_P_25_MS 3
289 #define FAPI_TDD_PERIOD_2_MS 4
290 #define FAPI_TDD_PERIOD_2_P_5_MS 5
291 #define FAPI_TDD_PERIOD_5_MS 6
292 #define FAPI_TDD_PERIOD_10_MS 7
293 // Slot Configuration
294 #define FAPI_DL_SLOT 0
295 #define FAPI_UL_SLOT 1
296 #define FAPI_GUARD_SLOT 2
297 // Measurement configuration
298 #define FAPI_NO_RSSI_REPORTING 0
299 #define FAPI_RSSI_REPORTED_IN_DBM 1
300 #define FAPI_RSSI_REPORTED_IN_DBFS 2
302 #define FAPI_SFN_MASK 0x03ff
304 #define FAPI_SLOT_MAX_VALUE 159
306 #define FAPI_U16_MASK 0xffff
307 #define FAPI_U8_MASK 0xff
308 // Define Maximum number of Ues per Group
309 #define FAPI_MAX_NUMBER_OF_UES_PER_GROUP 12
312 #define FAPI_BWPSIZE_MAX 275
313 #define FAPI_BWPSIZE_START_MAX 274
314 #define FAPI_SUBCARRIER_SPACING_MAX 4
315 #define FAPI_CYCLIC_PREFIX_NORMAL 0
316 #define FAPI_CYCLIC_PREFIX_EXTENDED 1
317 #define FAPI_MAX_SYMBOL_START_INDEX 13
319 #define FAPI_CORESET_DURATION_1_SYMBOL 1
320 #define FAPI_CORESET_DURATION_2_SYMBOLS 2
321 #define FAPI_CORESET_DURATION_3_SYMBOLS 3
323 #define FAPI_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0
324 #define FAPI_CCE_REG_MAPPING_TYPE_INTERLEAVED 1
325 #define FAPI_REG_BUNDLE_SIZE_2 2
326 #define FAPI_REG_BUNDLE_SIZE_3 3
327 #define FAPI_REG_BUNDLE_SIZE_6 6
329 #define FAPI_INTERLEAVER_SIZE_2 2
330 #define FAPI_INTERLEAVER_SIZE_3 3
331 #define FAPI_INTERLEAVER_SIZE_6 6
333 #define FAPI_CORESET_TYPE_0_CONF_BY_PBCH_OR_SIB1 0
334 #define FAPI_CORESET_TYPE_1 1
336 #define FAPI_PREC_GRANULARITY_SAME_AS_REG_BUNDLE 0
337 #define FAPI_PREC_GRANULARITY_ALL_CONTIG_RBS 1
339 #define FAPI_CCE_INDEX_MAX 135
340 #define FAPI_PDCCH_AGG_LEVEL_1 1
341 #define FAPI_PDCCH_AGG_LEVEL_2 2
342 #define FAPI_PDCCH_AGG_LEVEL_4 4
343 #define FAPI_PDCCH_AGG_LEVEL_8 8
344 #define FAPI_PDCCH_AGG_LEVEL_16 16
346 #define FAPI_BETA_PDCCH_1_0_MAX 17
348 #define FAPI_POWER_CTRL_OFF_SS_MINUS_3_DB 0
349 #define FAPI_POWER_CTRL_OFF_SS_0_DB 1
350 #define FAPI_POWER_CTRL_OFF_SS_3_DB 2
351 #define FAPI_POWER_CTRL_OFF_SS_6_DB 3
353 #define FAPI_MAX_NUMBER_OF_CODEWORDS 2
355 #define FAPI_MAX_MCS_INDEX 31
356 #define FAPI_MCS_INDEX_MASK 0x1f
358 #define FAPI_MCS_TABLE_NOT_QAM_256 0
359 #define FAPI_MCS_TABLE_QAM_256 1
360 #define FAPI_MCS_TABLE_QAM_64_LOW_SE 2
362 #define FAPI_REDUNDANCY_INDEX_MASK 0x03
364 #define FAPI_REF_POINT_FOR_PDSCH_DMRS_AT_PT_A 0
365 #define FAPI_REF_POINT_FOR_PDSCH_DMRS_AT_LOWEST_ALLOC 1
367 #define FAPI_DL_DMRS_SYMB_POS_MASK 0x3fff
369 #define FAPI_MAX_DMRS_CDM_GRPS_WO_DATA 3
371 #define FAPI_DMRS_PORTS_MASK 0x0fff
373 #define FAPI_RES_ALLOC_TYPE_0 0
374 #define FAPI_RES_ALLOC_TYPE_1 1
376 #define FAPI_VRB_TO_PRB_MAP_NON_INTERLVD 0
377 #define FAPI_VRB_TO_PRB_MAP_INTERLVD_RB_SIZE_2 1
378 #define FAPI_VRB_TO_PRB_MAP_INTERLVD_RB_SIZE_4 2
380 #define FAPI_MAX_START_SYMBOL_INDEX 13
381 #define FAPI_MAX_NR_OF_SYMBOLS 14
382 #define FAPI_PTRS_PORT_INDEX_MASK 0x3f
383 #define FAPI_PTRS_TIME_DENSITY_1 0
384 #define FAPI_PTRS_TIME_DENSITY_2 1
385 #define FAPI_PTRS_TIME_DENSITY_4 2
386 #define FAPI_PTRS_FREQ_DENSITY_2 0
387 #define FAPI_PTRS_FREQ_DENSITY_4 1
388 #define FAPI_PTRS_RE_OFFSET_MASK 0x03
389 #define FAPI_EPRE_RATIO_PDSCH_PTRS_MASK 0x03
391 // PDSCH Power Control Offset
392 #define FAPI_PWR_CTRL_OFFSET_MINUS_8_DB 0
393 #define FAPI_PWR_CTRL_OFFSET_MINUS_7_DB 1
394 #define FAPI_PWR_CTRL_OFFSET_MINUS_6_DB 2
395 #define FAPI_PWR_CTRL_OFFSET_MINUS_5_DB 3
396 #define FAPI_PWR_CTRL_OFFSET_MINUS_4_DB 4
397 #define FAPI_PWR_CTRL_OFFSET_MINUS_3_DB 5
398 #define FAPI_PWR_CTRL_OFFSET_MINUS_2_DB 6
399 #define FAPI_PWR_CTRL_OFFSET_MINUS_1_DB 7
400 #define FAPI_PWR_CTRL_OFFSET_0_DB 8
401 #define FAPI_PWR_CTRL_OFFSET_1_DB 9
402 #define FAPI_PWR_CTRL_OFFSET_2_DB 10
403 #define FAPI_PWR_CTRL_OFFSET_3_DB 11
404 #define FAPI_PWR_CTRL_OFFSET_4_DB 12
405 #define FAPI_PWR_CTRL_OFFSET_5_DB 13
406 #define FAPI_PWR_CTRL_OFFSET_6_DB 14
407 #define FAPI_PWR_CTRL_OFFSET_7_DB 15
408 #define FAPI_PWR_CTRL_OFFSET_8_DB 16
409 #define FAPI_PWR_CTRL_OFFSET_9_DB 17
410 #define FAPI_PWR_CTRL_OFFSET_10_DB 18
411 #define FAPI_PWR_CTRL_OFFSET_11_DB 19
412 #define FAPI_PWR_CTRL_OFFSET_12_DB 20
413 #define FAPI_PWR_CTRL_OFFSET_13_DB 21
414 #define FAPI_PWR_CTRL_OFFSET_14_DB 22
415 #define FAPI_PWR_CTRL_OFFSET_15_DB 23
416 // Power Control Offset SS
417 #define FAPI_PWR_CTRL_OFFSET_SS_MINUS_3_DB 0
418 #define FAPI_PWR_CTRL_OFFSET_SS_0_DB 1
419 #define FAPI_PWR_CTRL_OFFSET_SS_3_DB 2
420 #define FAPI_PWR_CTRL_OFFSET_SS_6_DB 3
422 #define FAPI_CSI_TRS 0
423 #define FAPI_CSI_NON_ZERO_POWER 1
424 #define FAPI_CSI_ZERO_POWER 2
425 // Row entry into CSI Resource Location Table
426 #define FAPI_CSIRLT_ROW_MAX_VALUE 18
427 #define FAPI_CSI_FREQ_DOMAIN_MASK 0x0fff
428 #define FAPI_CSI_SYMB_L1_MIN 2
429 #define FAPI_CSI_SYMB_L1_MAX 12
431 #define FAPI_CDM_TYPE_NO_CDM 0
432 #define FAPI_CDM_TYPE_FD_CDM 1
433 #define FAPI_CDM_TYPE_CDM4_FD2_TD2 2
434 #define FAPI_CDM_TYPE_CDM8_FD2_TD4 3
436 #define FAPI_FD_DOT5_EVEN_RB 0
437 #define FAPI_FD_DOT5_ODD_RB 1
438 #define FAPI_FD_ONE 2
439 #define FAPI_FD_THREE 3
442 #define FAPI_SSB_BLOCK_INDEX_MASK 0x3f
443 #define FAPI_SSB_SC_OFFSET_MASK 0x1f
446 #define FAPI_MAX_NUM_UE_GROUPS_INCLUDED 8
447 #define FAPI__MAX_NUM_UE_IN_GROUP 6
449 #define FAPI_MAX_NUM_PRACH_OCAS 7
451 #define FAPI_PRACH_FORMAT_A1 0
452 #define FAPI_PRACH_FORMAT_A2 1
453 #define FAPI_PRACH_FORMAT_A3 2
454 #define FAPI_PRACH_FORMAT_B1 3
455 #define FAPI_PRACH_FORMAT_B2 4
456 #define FAPI_PRACH_FORMAT_B3 5
457 #define FAPI_PRACH_FORMAT_B4 6
458 #define FAPI_PRACH_FORMAT_C0 7
459 #define FAPI_PRACH_FORMAT_C2 8
461 #define FAPI_MAX_PRACH_FD_OCCASION_INDEX 7
462 #define FAPI_MAX_ZC_ZONE_CONFIG_NUMBER 419
465 #define FAPI_PUSCH_BIT_DATA_PRESENT_MASK 0x0001
466 #define FAPI_PUSCH_UCI_DATA_PRESENT_MASK 0x0002
467 #define FAPI_PUSCH_PTRS_INCLUDED_FR2_MASK 0x0004
468 #define FAPI_PUSCH_DFTS_OFDM_TX_MASK 0x0008
470 #define FAPI_MAX_QAM_MOD_ORDER 8
471 #define FAPI_MCS_INDEX_MASK 0x1f
473 #define FAPI_MCS_TABLE_NOT_QAM256 0
474 #define FAPI_MCS_TABLE_QAM256 1
475 #define FAPI_MCS_TABLE_QAM64_LOWSE 2
476 #define FAPI_MCS_TABLE_NOT_QAM256_W_XFRM_PRECOD 3
477 #define FAPI_MCS_TABLE_QAM64_LOWSE_W_XFRM_PRECOD 4
478 #define FAPI_PUSCH_MAX_NUM_LAYERS 4
480 #define FAPI_UL_DMRS_SYMB_POS_MASK 0x3fff
481 #define FAPI_UL_DMRS_CONFIG_TYPE_1 0
482 #define FAPI_UL_DMRS_CONFIG_TYPE_2 1
483 #define FAPI_MAX_DMRS_CDM_GRPS_NO_DATA 3
484 #define FAPI_UL_DMRS_PORTS_MASK 0x07ff
485 #define FAPI_UL_TX_DIRECT_CURR_LOCATION_MAX 3299
486 #define FAPI_UL_TX_DIRECT_CURR_LOC_OUTSIDE_CARRIER 3300
487 #define FAPI_UL_TX_DIRECT_CURR_LOC_UNDETERMINED 3301
489 #define FAPI_RV_INDEX_MASK 0x03
490 #define FAPI_HARQ_PROCESS_ID_MASK 0x0f
492 #define FAPI_HARQ_ACK_CSI_PX_BIT_LEN_SMALL_BLOCK_MAX 11
493 #define FAPI_HARQ_ACK_CSI_PX_BIT_LEN_POLAR_MAX 1706
495 #define FAPI_ALPHA_SCALE_0_5 0
496 #define FAPI_ALPHA_SCALE_0_65 1
497 #define FAPI_ALPHA_SCALE_0_8 2
498 #define FAPI_ALPHA_SCALE_1_0 3
499 // BETA OFFSET HARQ ACK
500 #define FAPI_BETA_OFFSET_HARQ_ACK_MAX 15
501 #define FAPI_BETA_OFFSET_CSIX_MAX 18
503 // PUSCH PTRS INFORMATION 38.212 Section 7.3.1.1.2
504 #define FAPI_MAX_NUMBER_PTRS_PORT_INDEX 11 // 0..11
505 // UL PTRS POWER 5G FAPI Table 3-49
506 #define FAPI_UL_PTRS_PWR_0_DB 0
507 #define FAPI_UL_PTRS_PWR_3_DB 1
508 #define FAPI_UL_PTRS_PWR_4_77_DB 2
509 #define FAPI_UL_PTRS_PWR_6_DB 3
510 // DFTSOFDM INFO 5g FAPI Table 3-50
511 #define FAPI_MAX_LOW_PAPR_GROUP_NUMBER 29 // 0..29
512 #define FAPI_MAX_LOW_PAPR_SEQ_NUMBER 87 // 3*LOW_PAPR_GRP_NUM
513 #define FAPI_MAX_UL PTRS_SAMP_DENSITY 8
514 #define FAPI_MAX_UL_PTRS_TD_XFRM_PRECOD 4
516 // PUCCH PDU Table 3-51
517 #define FAPI_MAX_PUCCH_FORMAT_TYPE 4
518 #define FAPI_MULTI_SLOT_TX_IND_NO_MULTI_SLOT 0
519 #define FAPI_MULTI_SLOT_TX_IND_TX_START 1
520 #define FAPI_MULTI_SLOT_TX_IND_TX_CONT 2
521 #define FAPI_MULTI_SLOT_TX_IND_TX_END 3
522 #define FAPI_MAX_NUM_PRB_FOR_A_PUCCH 16
523 #define FAPI_MAX_PUCCH_DUR_F0_AND_F2 2
524 #define FAPI_MIN_PUCCH_DUR_F1_F3_F4 4
525 #define FAPI_MAX_PUCCH_DUR_F1_F3_F4 14
526 #define FAPI_MAX_INIT_CYCLIC_SHIFT_F0_F1_F3_F4 11
527 #define FAPI_MAX_OCC_INDEX_F1 6
528 #define FAPI_MAX_PRE_DFT_OCC_IDX_F4 3
529 #define FAPI_MAX_PRE_DFT_OCC_LEN_F4 4
530 #define FAPI_MAX_DMRS_CYC_SHIFT_F4 9
531 #define FAPI_BIT_LEN_HARQ_PL_ZERO 0
532 #define FAPI_BIT_LEN_HARQ_PL_F0_F1_2_BITS 1
533 #define FAPI_BIT_LEN_HARQ_PL_F2_F3_F4_1706_BITS 2
534 #define FAPI_BIT_LEN_CSI_PX_PL_NO_CSI 0
535 #define FAPI_BIT_LEN_CSI_PX_PL_1706_BITS 1
538 #define FAPI_1_SRS_ANT_PORT 0
539 #define FAPI_2_SRS_ANT_PORTS 1
540 #define FAPI_4_SRS_ANT_PORTS 2
541 #define FAPI_SRS_NO_REPETITIONS 0
542 #define FAPI_SRS_2_REPETITIONS 2
543 #define FAPI_SRS_4_REPETITIONS 4
544 #define FAPI_SRS_CONFIG_INDEX_MASK 0x3f
545 #define FAPI_SRS_BW_INDEX_MASK 0x03
546 #define FAPI_TX_COMB_SIZE_2 0
547 #define FAPI_TX_COMB_SIZE_4 1
548 #define FAPI_MAX_SRS_FREQ_POSITION 67
549 #define FAPI_MAX_SRS_FD_SHIFT 268
550 #define FAPI_SRS_FREQ_HOPPING_MASK 0x03
551 #define FAPI_SRS_NO_HOPPING 0
552 #define FAPI_SRS_GRP_OR_SEQ_HOPPING 1
553 #define FAPI_SRS_SEQ_HOPPING 2
554 #define FAPI_SRS_RES_ALLOC_APERIODIC 0
555 #define FAPI_SRS_RES_ALLOC_SEMI_PERSISTENT 1
556 #define FAPI_SRS_RES_ALLOC_PERIODIC 2
557 #define FAPI_MAX_LSOT_OFFSET_VALUE 2559
559 // RX_DATA Indication
560 #define FAPI_UL_CQI_INVALID 255
561 #define FAPI_TIMING_ADVANCE_INVALID 0xffff
562 #define FAPI_MAX_TIMING_ADVANCE 63
563 #define FAPI_MAX_RSSI 1280
566 #define FAPI_RACH_FREQ_INDEX_MAX 7
567 #define FAPI_RACH_DETECTED_PREAMBLES_MASK 0x3f
568 #define FAPI_RACH_TIMING_ADVANCE_MAX 3846
569 #define FAPI_RACH_PREAMBLE_POWER_INVALID 0xffffffff
570 #define FAPI_RACH_PREAMBLE_TIMING_ADVANCE_INVALID 0xffff
571 #define FAPI_RACH_PREAMBLE_POWER_MAX 170000
573 // SR, HARQ, and CSI Part 1/2 PDUs Table 3-66
574 #define FAPI_SR_MASK 0x01
575 #define FAPI_HARQ_MASK 0x02
576 #define FAPI_CSI_PART1 0x04
577 #define FAPI_CSI_PART2 0x08
578 #define FAPI_PUCCH_FORMAT2 0
579 #define FAPI_PUCCH_FORMAT3 1
580 #define FAPI_PUCCH_FORMAT4 2
581 #define FAPI_PUCCH_FORMAT_MASK 0x03
583 // SR PDU For Format 0 or 1 Table 3-67
584 #define FAPI_SR_CONFIDENCE_LEVEL_GOOD 0
585 #define FAPI_SR_CONFIDENCE_LEVEL_BAD 1
586 #define FAPI_SR_CONFIDENCE_LEVEL_INVALID 0xff
588 // HARQ PDU for Format 0 or 1 Table 3-68
589 #define FAPI_HARQ_VALUE_PASS 0
590 #define FAPI_HARQ_VALUE_FAIL 1
591 #define FAPI_HARQ_VALUE_NOT_PRESENT 2
593 // SR PDU for Format 2,3 or 4 Table 3-69
594 #define FAPI_SR_PAYLOAD_MAX 1
596 // HARQ PDU for Format 2,3 or 4 Table 3-70
597 #define FAPI_HARQ_CRC_PASS 0
598 #define FAPI_HARQ_CRC_FAIL 1
599 #define FAPI_HARQ_CRC_NOT_PRESENT 2
600 #define FAPI_HARQ_PAYLOAD_MAX 214
602 // CSI Part 1 PDU Table 3-71 and 3-72
603 #define FAPI_CSI_PARTX_CRC_PASS 0
604 #define FAPI_CSI_PARTX_CRC_FAIL 1
605 #define FAPI_CSI_PARTX_CRC_NOT_PRESENT 2
606 #define FAPI_CSI_PARTX_PAYLOAD_MAX 214
610 FAPI_CRC_CORRECT = 0,
614 // Release/Features support
616 FAPI_NOT_SUPPORTED = 0,
620 // Information of optional and mandatory status for a TLV
622 FAPI_IDLE_STATE_ONLY_OPTIONAL = 0,
623 FAPI_IDLE_STATE_ONLY_MANDATORY,
624 FAPI_IDLE_AND_CONFIGURED_STATES_OPTIONAL,
625 FAPI_IDLE_STATE_MANDATORY_CONFIGURED_STATE_OPTIONAL,
626 FAPI_IDLE_CONFIGURED_AND_RUNNING_STATES_OPTIONAL,
627 FAPI_IDLE_STATE_MANDATORY_CONFIGURED_AND_RUNNING_STATES_OPTIONAL
630 typedef enum modulationOrder {
639 FAPI_SSB_PER_RACH_1_OVER_8 = 0,
640 FAPI_SSB_PER_RACH_1_OVER_4,
641 FAPI_SSB_PER_RACH_1_OVER_2,
649 #endif //_NR5G_FAPI_INTELNAL_H_