1 /******************************************************************************
3 * Copyright (c) 2019 Intel.
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
9 * http://www.apache.org/licenses/LICENSE-2.0
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
17 *******************************************************************************/
20 * @file This file consist of FAPI internal functions.
24 #ifndef _NR5G_FAPI_FRAMEWORK_H_
25 #define _NR5G_FAPI_FRAMEWORK_H_
28 #include "fapi_interface.h"
29 #include "nr5g_fapi_log.h"
30 #include "nr5g_fapi_internal.h"
31 #include "nr5g_fapi_std.h"
32 #include "nr5g_fapi_common_types.h"
33 #include "nr5g_fapi_config_loader.h"
35 // FAPI CONFIG.request parameters
36 typedef struct _nr5g_fapi_phy_config {
38 uint8_t n_nr_of_rx_ant;
39 uint8_t use_vendor_EpreXSSB;
42 } nr5g_fapi_phy_config_t,
43 *pnr5g_fapi_phy_config_t;
45 typedef struct _nr5g_fapi_rach_info {
47 } nr5g_fapi_rach_info_t;
49 typedef struct _nr5g_fapi_srs_info {
51 } nr5g_fapi_srs_info_t;
53 typedef struct _nr5g_fapi_pusch_info {
55 uint8_t harq_process_id;
57 uint16_t timing_advance;
58 } nr5g_fapi_pusch_info_t;
60 typedef struct _nr5g_fapi_pucch_info {
63 } nr5g_fapi_pucch_info_t;
65 typedef struct _nr5g_fapi_ul_slot_info {
66 uint16_t cookie; //set this to frame_no at UL_TTI.Request and compare the
67 //same during uplink indications.
73 uint8_t rach_presence;
74 nr5g_fapi_rach_info_t rach_info; //Only One RACH PDU will be reported for RACH.Indication message
75 nr5g_fapi_srs_info_t srs_info[FAPI_MAX_NUMBER_SRS_PDUS_PER_SLOT];
76 nr5g_fapi_pucch_info_t pucch_info[FAPI_MAX_NUMBER_UCI_PDUS_PER_SLOT];
77 nr5g_fapi_pusch_info_t pusch_info[FAPI_MAX_NUMBER_OF_ULSCH_PDUS_PER_SLOT];
78 } nr5g_fapi_ul_slot_info_t;
80 typedef struct _nr5g_fapi_stats_info_t {
81 uint8_t fapi_param_req;
82 uint8_t fapi_param_res;
83 uint8_t fapi_config_req;
84 uint8_t fapi_config_res;
85 uint8_t fapi_start_req;
86 uint8_t fapi_stop_req;
87 uint8_t fapi_stop_ind;
88 uint8_t fapi_vendor_msg;
89 uint8_t fapi_vext_shutdown_req;
90 uint8_t fapi_vext_shutdown_res;
92 uint8_t fapi_vext_start_res;
94 uint64_t fapi_dl_tti_req;
95 uint64_t fapi_ul_tti_req;
96 uint64_t fapi_ul_dci_req;
97 uint64_t fapi_tx_data_req;
99 uint64_t fapi_slot_ind;
100 uint64_t fapi_error_ind;
101 uint64_t fapi_crc_ind;
102 uint64_t fapi_rx_data_ind;
103 uint64_t fapi_uci_ind;
104 uint64_t fapi_srs_ind;
105 uint64_t fapi_rach_ind;
107 uint64_t fapi_dl_tti_pdus;
108 uint64_t fapi_dl_tti_pdcch_pdus;
109 uint64_t fapi_dl_tti_pdsch_pdus;
110 uint64_t fapi_dl_tti_csi_rs_pdus;
111 uint64_t fapi_dl_tti_ssb_pdus;
113 uint64_t fapi_ul_dci_pdus;
115 uint64_t fapi_ul_tti_pdus;
116 uint64_t fapi_ul_tti_prach_pdus;
117 uint64_t fapi_ul_tti_pusch_pdus;
118 uint64_t fapi_ul_tti_pucch_pdus;
119 uint64_t fapi_ul_tti_srs_pdus;
120 uint64_t fapi_crc_ind_pdus;
121 uint64_t fapi_rx_data_ind_pdus;
122 uint64_t fapi_uci_ind_pdus;
123 uint64_t fapi_srs_ind_pdus;
124 uint64_t fapi_rach_ind_pdus;
125 } nr5g_fapi_stats_info_t;
127 typedef struct _nr5g_iapi_stats_info_t {
128 uint8_t iapi_param_req;
129 uint8_t iapi_param_res;
130 uint8_t iapi_config_req;
131 uint8_t iapi_config_res;
132 uint8_t iapi_start_req;
133 uint8_t iapi_start_res;
134 uint8_t iapi_stop_req;
135 uint8_t iapi_stop_ind;
136 uint8_t iapi_shutdown_req;
137 uint8_t iapi_shutdown_res;
138 uint64_t iapi_dl_config_req;
139 uint64_t iapi_ul_config_req;
140 uint64_t iapi_ul_dci_req;
141 uint64_t iapi_tx_req;
143 uint64_t iapi_slot_ind;
144 uint64_t iapi_error_ind;
145 uint64_t iapi_crc_ind;
146 uint64_t iapi_rx_data_ind;
147 uint64_t iapi_uci_ind;
148 uint64_t iapi_srs_ind;
149 uint64_t iapi_rach_ind;
151 uint64_t iapi_dl_tti_pdus;
152 uint64_t iapi_dl_tti_pdcch_pdus;
153 uint64_t iapi_dl_tti_pdsch_pdus;
154 uint64_t iapi_dl_tti_csi_rs_pdus;
155 uint64_t iapi_dl_tti_ssb_pdus;
157 uint64_t iapi_ul_dci_pdus;
159 uint64_t iapi_ul_tti_pdus;
160 uint64_t iapi_ul_tti_prach_pdus;
161 uint64_t iapi_ul_tti_pusch_pdus;
162 uint64_t iapi_ul_tti_pucch_pdus;
163 uint64_t iapi_ul_tti_srs_pdus;
164 uint64_t iapi_crc_ind_pdus;
165 uint64_t iapi_rx_data_ind_pdus;
166 uint64_t iapi_uci_ind_pdus;
167 uint64_t iapi_srs_ind_pdus;
168 uint64_t iapi_rach_preambles;
169 } nr5g_iapi_stats_info_t;
171 typedef struct _nr5g_fapi_stats_t {
172 nr5g_fapi_stats_info_t fapi_stats;
173 nr5g_iapi_stats_info_t iapi_stats;
176 // FAPI phy instance structure
177 typedef struct _nr5g_fapi_phy_instance {
179 uint8_t shutdown_retries;
180 uint32_t shutdown_test_type;
181 fapi_states_t state; // FAPI state
182 nr5g_fapi_phy_config_t phy_config; // place holder to store,
183 // parameters from config request
184 nr5g_fapi_stats_t stats;
185 nr5g_fapi_ul_slot_info_t ul_slot_info[FAPI_MAX_SLOT_INFO_URLLC][MAX_UL_SLOT_INFO_COUNT][MAX_UL_SYMBOL_INFO_COUNT];
186 } nr5g_fapi_phy_instance_t,
187 *p_nr5g_fapi_phy_instance_t;
190 typedef struct _nr5g_fapi_phy_context {
191 uint8_t num_phy_instance;
192 uint8_t mac2phy_worker_core_id;
193 uint8_t phy2mac_worker_core_id;
194 uint8_t urllc_worker_core_id;
195 pthread_t phy2mac_tid;
196 pthread_t mac2phy_tid;
198 sem_t urllc_sem_process;
199 sem_t urllc_sem_done;
200 volatile uint64_t process_exit;
201 nr5g_fapi_phy_instance_t phy_instance[FAPI_MAX_PHY_INSTANCES];
202 } nr5g_fapi_phy_ctx_t,
203 *p_nr5g_fapi_phy_ctx_t;
205 // Function Declarations
206 inline p_nr5g_fapi_phy_ctx_t nr5g_fapi_get_nr5g_fapi_phy_ctx(
208 uint8_t nr5g_fapi_framework_init(
210 uint8_t nr5g_fapi_framework_stop(
212 uint8_t nr5g_fapi_framework_finish(
214 uint8_t nr5g_fapi_dpdk_init(
215 p_nr5g_fapi_cfg_t cfg);
216 uint8_t nr5g_fapi_dpdk_wait(
217 p_nr5g_fapi_cfg_t cfg);
218 void *nr5g_fapi_phy2mac_thread_func(
220 void *nr5g_fapi_mac2phy_thread_func(
222 void *nr5g_fapi_urllc_thread_func(
224 nr5g_fapi_ul_slot_info_t *nr5g_fapi_get_ul_slot_info(
229 p_nr5g_fapi_phy_instance_t p_phy_instance);
230 void nr5g_fapi_set_ul_slot_info(
234 nr5g_fapi_ul_slot_info_t * p_ul_slot_info);
235 #endif // _NR5G_FAPI_FRAMEWORK_H_