1 /******************************************************************************
3 * Copyright (c) 2019 Intel.
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
9 * http://www.apache.org/licenses/LICENSE-2.0
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
17 *******************************************************************************/
20 * @file This file consist of FAPI internal functions.
24 #ifndef _NR5G_FAPI_FRAMEWORK_H_
25 #define _NR5G_FAPI_FRAMEWORK_H_
28 #include "fapi_interface.h"
29 #include "nr5g_fapi_log.h"
30 #include "nr5g_fapi_internal.h"
31 #include "nr5g_fapi_std.h"
32 #include "nr5g_fapi_common_types.h"
33 #include "nr5g_fapi_config_loader.h"
35 // FAPI CONFIG.request parameters
36 typedef struct _nr5g_fapi_phy_config {
37 uint8_t n_nr_of_rx_ant;
39 uint8_t nSSBPrbOffset;
40 } nr5g_fapi_phy_config_t,
41 *pnr5g_fapi_phy_config_t;
43 typedef struct _nr5g_fapi_rach_info {
45 } nr5g_fapi_rach_info_t;
47 typedef struct _nr5g_fapi_srs_info {
49 } nr5g_fapi_srs_info_t;
51 typedef struct _nr5g_fapi_pusch_info {
53 uint8_t harq_process_id;
55 uint16_t timing_advance;
56 } nr5g_fapi_pusch_info_t;
58 typedef struct _nr5g_fapi_pucch_info {
61 } nr5g_fapi_pucch_info_t;
63 typedef struct _nr5g_fapi_ul_slot_info {
64 uint16_t cookie; //set this to frame_no at UL_TTI.Request and compare the
65 //same during uplink indications.
70 uint8_t rach_presence;
71 nr5g_fapi_rach_info_t rach_info; //Only One RACH PDU will be reported for RACH.Indication message
72 nr5g_fapi_srs_info_t srs_info[FAPI_MAX_NUMBER_SRS_PDUS_PER_SLOT];
73 nr5g_fapi_pucch_info_t pucch_info[FAPI_MAX_NUMBER_UCI_PDUS_PER_SLOT];
74 nr5g_fapi_pusch_info_t pusch_info[FAPI_MAX_NUMBER_OF_ULSCH_PDUS_PER_SLOT];
75 } nr5g_fapi_ul_slot_info_t;
77 typedef struct _nr5g_fapi_stats_info_t {
78 uint8_t fapi_param_req;
79 uint8_t fapi_param_res;
80 uint8_t fapi_config_req;
81 uint8_t fapi_config_res;
82 uint8_t fapi_start_req;
83 uint8_t fapi_stop_req;
84 uint8_t fapi_stop_ind;
85 uint8_t fapi_vendor_msg;
86 uint8_t fapi_vext_shutdown_req;
87 uint8_t fapi_vext_shutdown_res;
89 uint8_t fapi_vext_start_res;
91 uint64_t fapi_dl_tti_req;
92 uint64_t fapi_ul_tti_req;
93 uint64_t fapi_ul_dci_req;
94 uint64_t fapi_tx_data_req;
96 uint64_t fapi_slot_ind;
97 uint64_t fapi_error_ind;
98 uint64_t fapi_crc_ind;
99 uint64_t fapi_rx_data_ind;
100 uint64_t fapi_uci_ind;
101 uint64_t fapi_srs_ind;
102 uint64_t fapi_rach_ind;
104 uint64_t fapi_dl_tti_pdus;
105 uint64_t fapi_dl_tti_pdcch_pdus;
106 uint64_t fapi_dl_tti_pdsch_pdus;
107 uint64_t fapi_dl_tti_csi_rs_pdus;
108 uint64_t fapi_dl_tti_ssb_pdus;
110 uint64_t fapi_ul_dci_pdus;
112 uint64_t fapi_ul_tti_pdus;
113 uint64_t fapi_ul_tti_prach_pdus;
114 uint64_t fapi_ul_tti_pusch_pdus;
115 uint64_t fapi_ul_tti_pucch_pdus;
116 uint64_t fapi_ul_tti_srs_pdus;
117 uint64_t fapi_crc_ind_pdus;
118 uint64_t fapi_rx_data_ind_pdus;
119 uint64_t fapi_uci_ind_pdus;
120 uint64_t fapi_srs_ind_pdus;
121 uint64_t fapi_rach_ind_pdus;
122 } nr5g_fapi_stats_info_t;
124 typedef struct _nr5g_iapi_stats_info_t {
125 uint8_t iapi_param_req;
126 uint8_t iapi_param_res;
127 uint8_t iapi_config_req;
128 uint8_t iapi_config_res;
129 uint8_t iapi_start_req;
130 uint8_t iapi_start_res;
131 uint8_t iapi_stop_req;
132 uint8_t iapi_stop_ind;
133 uint8_t iapi_shutdown_req;
134 uint8_t iapi_shutdown_res;
135 uint64_t iapi_dl_config_req;
136 uint64_t iapi_ul_config_req;
137 uint64_t iapi_ul_dci_req;
138 uint64_t iapi_tx_req;
140 uint64_t iapi_slot_ind;
141 uint64_t iapi_error_ind;
142 uint64_t iapi_crc_ind;
143 uint64_t iapi_rx_data_ind;
144 uint64_t iapi_uci_ind;
145 uint64_t iapi_srs_ind;
146 uint64_t iapi_rach_ind;
148 uint64_t iapi_dl_tti_pdus;
149 uint64_t iapi_dl_tti_pdcch_pdus;
150 uint64_t iapi_dl_tti_pdsch_pdus;
151 uint64_t iapi_dl_tti_csi_rs_pdus;
152 uint64_t iapi_dl_tti_ssb_pdus;
154 uint64_t iapi_ul_dci_pdus;
156 uint64_t iapi_ul_tti_pdus;
157 uint64_t iapi_ul_tti_prach_pdus;
158 uint64_t iapi_ul_tti_pusch_pdus;
159 uint64_t iapi_ul_tti_pucch_pdus;
160 uint64_t iapi_ul_tti_srs_pdus;
161 uint64_t iapi_crc_ind_pdus;
162 uint64_t iapi_rx_data_ind_pdus;
163 uint64_t iapi_uci_ind_pdus;
164 uint64_t iapi_srs_ind_pdus;
165 uint64_t iapi_rach_preambles;
166 } nr5g_iapi_stats_info_t;
168 typedef struct _nr5g_fapi_stats_t {
169 nr5g_fapi_stats_info_t fapi_stats;
170 nr5g_iapi_stats_info_t iapi_stats;
173 // FAPI phy instance structure
174 typedef struct _nr5g_fapi_phy_instance {
176 uint8_t shutdown_retries;
177 uint32_t shutdown_test_type;
178 fapi_states_t state; // FAPI state
179 nr5g_fapi_phy_config_t phy_config; // place holder to store,
180 // parameters from config request
181 nr5g_fapi_stats_t stats;
182 nr5g_fapi_ul_slot_info_t ul_slot_info[MAX_UL_SLOT_INFO_COUNT];
183 } nr5g_fapi_phy_instance_t,
184 *p_nr5g_fapi_phy_instance_t;
187 typedef struct _nr5g_fapi_phy_context {
188 uint8_t num_phy_instance;
189 uint8_t mac2phy_worker_core_id;
190 uint8_t phy2mac_worker_core_id;
191 pthread_t phy2mac_tid;
192 pthread_t mac2phy_tid;
193 volatile uint64_t process_exit;
194 nr5g_fapi_phy_instance_t phy_instance[FAPI_MAX_PHY_INSTANCES];
195 } nr5g_fapi_phy_ctx_t,
196 *p_nr5g_fapi_phy_ctx_t;
198 // Function Declarations
199 inline p_nr5g_fapi_phy_ctx_t nr5g_fapi_get_nr5g_fapi_phy_ctx(
201 uint8_t nr5g_fapi_framework_init(
203 uint8_t nr5g_fapi_framework_stop(
205 uint8_t nr5g_fapi_framework_finish(
207 uint8_t nr5g_fapi_dpdk_init(
208 p_nr5g_fapi_cfg_t cfg);
209 uint8_t nr5g_fapi_dpdk_wait(
210 p_nr5g_fapi_cfg_t cfg);
211 void *nr5g_fapi_phy2mac_thread_func(
213 void *nr5g_fapi_mac2phy_thread_func(
215 nr5g_fapi_ul_slot_info_t *nr5g_fapi_get_ul_slot_info(
218 p_nr5g_fapi_phy_instance_t p_phy_instance);
219 void nr5g_fapi_set_ul_slot_info(
222 nr5g_fapi_ul_slot_info_t * p_ul_slot_info);
223 #endif // _NR5G_FAPI_FRAMEWORK_H_