1 .. Copyright (c) 2019-2022 Intel
3 .. Licensed under the Apache License, Version 2.0 (the "License");
4 .. you may not use this file except in compliance with the License.
5 .. You may obtain a copy of the License at
7 .. http://www.apache.org/licenses/LICENSE-2.0
9 .. Unless required by applicable law or agreed to in writing, software
10 .. distributed under the License is distributed on an "AS IS" BASIS,
11 .. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 .. See the License for the specific language governing permissions and
13 .. limitations under the License.
22 A.1 Setup Configuration
23 -----------------------
24 The configuration shown in Figure 26 shows how to set up a test
25 environment to execute O-RAN scenarios where O-DU and 0-RU are simulated
26 using the sample application. This setup allows development and
27 prototyping as well as testing of O-RAN specific functionality. The O-DU
28 side can be instantiated with a full 5G NR L1 reference as well. The
29 configuration differences of the 5G NR l1app configuration are provided
30 below. Steps for running the sample application on the O-DU side and
31 0-RU side are the same, except configuration file options may be
34 .. image:: images/Setup-for-xRAN-Testing.jpg
36 :alt: Figure 26. Setup for O-RAN Testing
38 Figure 26. Setup for O-RAN Testing
40 .. image:: images/Setup-for-xRAN-Testing-with-PHY-and-Configuration-C3.jpg
42 :alt: Figure 27. Setup for O-RAN Testing with PHY and Configuration C3
44 Figure 27. Setup for O-RAN Testing with PHY and Configuration C3
48 Each server in Figure 26 requires the following:
50 - Wolfpass server according to recommended BOM for FlexRAN such as
51 Intel® Xeon® Skylake Gold 6148 FC-LGA3647 2.4 GHz 27.5 MB 150W 20
56 - Intel® Virtualization Technology Enabled
58 - Intel® VT for Directed I/O - Enabled
60 - ACS Control - Enabled
62 - Coherency Support - Disabled
64 - Front Haul networking cards:
66 - Intel® Ethernet Converged Network Adapter XL710-QDA2
68 - Intel® Ethernet Converged Network Adapter XXV710-DA2
70 - Intel® Ethernet Converged Network Adapter E810-CQDA2
72 - Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000
74 - Back (Mid) Haul networking card can be either:
76 - Intel® Ethernet Connection X722 for 10GBASE-T
78 - Intel® 82599ES 10-Gigabit SFI/SFP+ Network Connection
80 - Other networking cards capable of HW timestamping for PTP synchronization.
82 - Both Back (mid) Haul and Front Haul NIC require support for PTP HW timestamping.
84 The recommended configuration for NICs is::
89 firmware-version: 8.20 0x80009bd4 1.2879.0
90 expansion-rom-version:
91 bus-info: 0000:21:00.0
92 supports-statistics: yes
94 supports-eeprom-access: yes
95 supports-register-dump: yes
96 supports-priv-flags: yes
98 Time stamping parameters for enp33s0f0:
100 hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
101 software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)
102 hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
103 software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)
104 software-system-clock (SOF_TIMESTAMPING_SOFTWARE)
105 hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
106 PTP Hardware Clock: 4
107 Hardware Transmit Timestamp Modes:
108 off (HWTSTAMP_TX_OFF)
110 Hardware Receive Filter Modes:
111 none (HWTSTAMP_FILTER_NONE)
112 ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC)
113 ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ)
114 ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)
115 ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC)
116 ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ)
117 ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT)
118 ptpv2-l2-sync (HWTSTAMP_FILTER_PTP_V2_L2_SYNC)
119 ptpv2-l2-delay-req (HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ)
120 ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)
121 ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC)
122 ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ)
124 The recommended configuration for Columbiaville NICs (base on Intel®
125 Ethernet 800 Series (Columbiaville) CVL 2.3 release is::
130 firmware-version: 2.3 0x80005D18
131 expansion-rom-version:
132 bus-info: 0000:51:00.0
133 supports-statistics: yes
135 supports-eeprom-access: yes
136 supports-register-dump: yes
137 supports-priv-flags: yes
139 Time stamping parameters for enp81s0f0:
141 hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
142 software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)
143 hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
144 software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)
145 software-system-clock (SOF_TIMESTAMPING_SOFTWARE)
146 hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
147 PTP Hardware Clock: 1
148 Hardware Transmit Timestamp Modes:
149 off (HWTSTAMP_TX_OFF)
151 Hardware Receive Filter Modes:
152 none (HWTSTAMP_FILTER_NONE)
153 all (HWTSTAMP_FILTER_ALL)
155 Recommended version of
157 ICE COMMS Package version 1.3.24.0
159 *Note*. If your firmware version does not match with the ones in the output
160 images, you can download the correct version from the Intel Download
161 Center. It is Intel's repository for the latest software and drivers
162 for Intel products. The NVM Update Packages for Windows*, Linux*,
163 ESX*, FreeBSD*, and EFI/EFI2 are located at:
167 https://downloadmirror.intel.com/682037/readme_8_50.txt
170 https://downloadmirror.intel.com/709693/readme_3.10.txt
173 PTP Grand Master is required to be available in the network to provide
174 synchronization of both O-DU and RU to GPS time.
176 The software package includes Linux\* CentOS\* operating system and RT
177 patch according to FlexRAN Reference Solution Cloud-Native Setup
178 document (refer to Table 2). Only real-time HOST is required.
180 1. Install Intel® C++ Compiler v19.0.3
182 2. Download DPDK v20.11.1
184 3. Patch DPDK with FlexRAN BBDev patch as per given release.
186 4. Double check that FlexRAN DPDK patch includes changes below relevant
187 to O-RAN Front haul::
190 diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
191 index 85a6a86..236fbe0 100644
192 --- a/drivers/net/i40e/i40e_ethdev.c
193 +++ b/drivers/net/i40e/i40e_ethdev.c
194 @@ -2207,7 +2207,7 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
195 /* Map queues with MSIX interrupt */
196 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
197 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
198 - i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
199 + i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_NONE);
200 i40e_vsi_enable_queues_intr(main_vsi);
202 /* Map VMDQ VSI queues with MSIX interrupt */
203 @@ -2218,6 +2218,10 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
204 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
206 + i40e_aq_debug_write_global_register(hw,
210 /* enable FDIR MSIX interrupt */
211 if (pf->fdir.fdir_vsi) {
212 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
213 diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c
214 index 001c301..6f9ffdb 100644
215 --- a/drivers/net/i40e/i40e_ethdev_vf.c
216 +++ b/drivers/net/i40e/i40e_ethdev_vf.c
217 @@ -640,7 +640,7 @@ struct rte_i40evf_xstats_name_off {
219 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
220 map_info->num_vectors = 1;
221 - map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
222 + map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_NONE;
223 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
224 /* Alway use default dynamic MSIX interrupt */
225 map_info->vecmap[0].vector_id = vector_id;
226 diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
227 index 26b1927..018eb8f 100644
228 --- a/drivers/net/ixgbe/ixgbe_ethdev.c
229 +++ b/drivers/net/ixgbe/ixgbe_ethdev.c
230 @@ -3705,7 +3705,7 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
231 * except for 82598EB, which remains constant.
233 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
234 - hw->mac.type != ixgbe_mac_82598EB)
235 + hw->mac.type != ixgbe_mac_82598EB && hw->mac.type != ixgbe_mac_82599EB)
236 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
238 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
239 diff --git a/lib/librte_eal/common/include/rte_dev.h b/lib/librte_eal/common/include/rte_dev.h
244 diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
245 index de189daba..d9aff341c 100644
246 --- a/drivers/net/ice/ice_ethdev.c
247 +++ b/drivers/net/ice/ice_ethdev.c
248 @@ -2604,8 +2604,13 @@ __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
250 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
251 base_queue + i, msix_vect);
252 - /* set ITR0 value */
253 - ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
255 + * Empirical configuration for optimal real time latency
256 + * reduced interrupt throttling to 2 ms
257 + * Columbiaville pre-PRQ : local patch subject to change
259 + ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1);
260 + ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), QRX_ITR_NO_EXPR_M);
261 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
262 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
265 5.Build and install DPDK::
267 See https://doc.dpdk.org/guides/prog_guide/build-sdk-meson.html
269 6.Make below file changes in dpdk that assure i40e to get best
270 latency of packet processing::
272 --- i40e.h 2018-11-30 11:27:00.000000000 +0000
273 +++ i40e_patched.h 2019-03-06 15:49:06.877522427 +0000
276 #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \
277 (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \
278 - (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \
279 + (I40E_ITR_NONE << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \
280 ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \
281 ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \
282 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT))
284 --- i40e_main.c 2018-11-30 11:27:00.000000000 +0000
285 +++ i40e_main_patched.c 2019-03-06 15:46:13.521518062 +0000
286 @@ -15296,6 +15296,9 @@
287 pf->hw_features |= I40E_HW_HAVE_CRT_RETIMER;
288 /* print a string summarizing features */
289 i40e_print_features(pf);
291 + /* write to this register to clear rx descriptor */
292 + i40e_aq_debug_write_register(hw, 0x0012A504, 0, NULL);
296 A.3 Configuration of System
297 ---------------------------
298 1.Boot Linux with the following arguments::
301 BOOT_IMAGE=/vmlinuz-3.10.0-1062.12.1.rt56.1042.el7.x86_64 root=/dev/mapper/centos-root ro
302 crashkernel=auto rd.lvm.lv=centos/root rd.lvm.lv=centos/swap intel_iommu=on iommu=pt
303 usbcore.autosuspend=-1 selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0
304 intel_pstate=disable cgroup_memory=1 cgroup_enable=memory mce=off idle=poll
305 hugepagesz=1G hugepages=16 hugepagesz=2M hugepages=0 default_hugepagesz=1G
306 isolcpus=1-19,21-39 rcu_nocbs=1-19,21-39 kthread_cpus=0,20 irqaffinity=0,20
309 2. Boot Linux with the following arguments for Icelake CPU::
312 BOOT_IMAGE=/vmlinuz-3.10.0-957.10.1.rt56.921.el7.x86_64
313 root=/dev/mapper/centos-root ro crashkernel=auto rd.lvm.lv=centos/root
314 rd.lvm.lv=centos/swap rhgb quiet intel_iommu=off usbcore.autosuspend=-1
315 selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0
316 intel_pstate=disable cgroup_disable=memory mce=off hugepagesz=1G
317 hugepages=40 hugepagesz=2M hugepages=0 default_hugepagesz=1G
318 isolcpus=1-23,25-47 rcu_nocbs=1-23,25-47 kthread_cpus=0 irqaffinity=0
321 3. Download from Intel Website and install updated version of i40e
322 driver if needed. The current recommended version of i40e is 2.14.13.
323 However, any latest version of i40e after 2.9.21 expected to be
324 functional for O-RAN FH.
326 4. For Columbiaville download Intel® Ethernet 800 Series (Columbiaville)
327 CVL2.3 B0/C0 Sampling Sample Validation Kit (SVK) from Intel Customer
328 Content Library. The current recommended version of ICE driver is
329 1.3.2 with ICE COMMS Package version 1.3.24.0. IAVF recommended
332 5. Identify PCIe Bus address of the Front Haul NIC (Fortville)::
335 86:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
336 86:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
337 88:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
338 88:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
340 6. Identify PCIe Bus address of the Front Haul NIC (Columbiaville)::
343 18:00.0 Ethernet controller: Intel Corporation Device 1593 (rev 02)
344 18:00.1 Ethernet controller: Intel Corporation Device 1593 (rev 02)
345 18:00.2 Ethernet controller: Intel Corporation Device 1593 (rev 02)
346 18:00.3 Ethernet controller: Intel Corporation Device 1593 (rev 02)
347 51:00.0 Ethernet controller: Intel Corporation Device 1593 (rev 02)
348 51:00.1 Ethernet controller: Intel Corporation Device 1593 (rev 02)
349 51:00.2 Ethernet controller: Intel Corporation Device 1593 (rev 02)
350 51:00.3 Ethernet controller: Intel Corporation Device 1593 (rev 02)
352 7. Identify the Ethernet device name::
357 firmware-version: 8.20 0x80009bd4 1.2879.0
358 expansion-rom-version:
359 bus-info: 0000:21:00.0
360 supports-statistics: yes
362 supports-eeprom-access: yes
363 supports-register-dump: yes
364 supports-priv-flags: yesEnable
371 firmware-version: 2.3 0x80005D18
372 expansion-rom-version:
373 bus-info: 0000:51:00.0
374 supports-statistics: yes
376 supports-eeprom-access: yes
377 supports-register-dump: yes
378 supports-priv-flags: yes
380 8. Enable 3 virtual functions (VFs) on the each of two ports of each
385 echo 0 > /sys/bus/pci/devices/0000\:88\:00.0/sriov_numvfs
386 echo 0 > /sys/bus/pci/devices/0000\:88\:00.1/sriov_numvfs
388 echo 0 > /sys/bus/pci/devices/0000\:86\:00.0/sriov_numvfs
389 echo 0 > /sys/bus/pci/devices/0000\:86\:00.1/sriov_numvfs
394 echo 3 > /sys/bus/pci/devices/0000\:88\:00.0/sriov_numvfs
395 echo 3 > /sys/bus/pci/devices/0000\:88\:00.1/sriov_numvfs
397 echo 3 > /sys/bus/pci/devices/0000\:86\:00.0/sriov_numvfs
398 echo 3 > /sys/bus/pci/devices/0000\:86\:00.1/sriov_numvfs
409 echo " Usage $0 qos with 0<= qos <= 7 with 0 as a default if no qos is provided"
414 ip link set enp136s0f0 vf 0 mac 00:11:22:33:00:00 vlan 1 qos $b
415 ip link set enp136s0f1 vf 0 mac 00:11:22:33:00:10 vlan 1 qos $b
417 ip link set enp136s0f0 vf 1 mac 00:11:22:33:01:00 vlan 2 qos $b
418 ip link set enp136s0f1 vf 1 mac 00:11:22:33:01:10 vlan 2 qos $b
420 ip link set enp136s0f0 vf 2 mac 00:11:22:33:02:00 vlan 3 qos $b
421 ip link set enp136s0f1 vf 2 mac 00:11:22:33:02:10 vlan 3 qos $b
424 ip link set enp134s0f0 vf 0 mac 00:11:22:33:00:01 vlan 1 qos $b
425 ip link set enp134s0f1 vf 0 mac 00:11:22:33:00:11 vlan 1 qos $b
427 ip link set enp134s0f0 vf 1 mac 00:11:22:33:01:01 vlan 2 qos $b
428 ip link set enp134s0f1 vf 1 mac 00:11:22:33:01:11 vlan 2 qos $b
430 ip link set enp134s0f0 vf 2 mac 00:11:22:33:02:01 vlan 3 qos $b
431 ip link set enp134s0f1 vf 2 mac 00:11:22:33:02:11 vlan 3 qos $b
433 where output is next::
437 9: enp134s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
438 link/ether 3c:fd:fe:b9:f9:60 brd ff:ff:ff:ff:ff:ff
439 vf 0 MAC 00:11:22:33:00:01, vlan 1, spoof checking on, link-state auto, trust off
440 vf 1 MAC 00:11:22:33:01:01, vlan 2, spoof checking on, link-state auto, trust off
441 vf 2 MAC 00:11:22:33:02:01, vlan 3, spoof checking on, link-state auto, trust off
442 11: enp134s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
443 link/ether 3c:fd:fe:b9:f9:61 brd ff:ff:ff:ff:ff:ff
444 vf 0 MAC 00:11:22:33:00:11, vlan 1, spoof checking on, link-state auto, trust off
445 vf 1 MAC 00:11:22:33:01:11, vlan 2, spoof checking on, link-state auto, trust off
446 vf 2 MAC 00:11:22:33:02:11, vlan 3, spoof checking on, link-state auto, trust off
447 12: enp136s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
448 link/ether 3c:fd:fe:b9:f8:b4 brd ff:ff:ff:ff:ff:ff
449 vf 0 MAC 00:11:22:33:00:00, vlan 1, spoof checking on, link-state auto, trust off
450 vf 1 MAC 00:11:22:33:01:00, vlan 2, spoof checking on, link-state auto, trust off
451 vf 2 MAC 00:11:22:33:02:00, vlan 3, spoof checking on, link-state auto, trust off
452 14: enp136s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
453 link/ether 3c:fd:fe:b9:f8:b5 brd ff:ff:ff:ff:ff:ff
454 vf 0 MAC 00:11:22:33:00:10, vlan 1, spoof checking on, link-state auto, trust off
455 vf 1 MAC 00:11:22:33:01:10, vlan 2, spoof checking on, link-state auto, trust off
456 vf 2 MAC 00:11:22:33:02:10, vlan 3, spoof checking on, link-state auto, trust off
462 More information about VFs supported by Intel NICs can be found at
463 https://doc.dpdk.org/guides/nics/intel_vf.html.
465 The resulting configuration can look like the listing below, where six
466 new VFs were added for each O-DU and O-RU port:::
469 86:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
470 86:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
471 86:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
472 86:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
473 86:02.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
474 86:0a.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
475 86:0a.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
476 86:0a.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
477 88:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
478 88:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
479 88:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
480 88:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
481 88:02.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
482 88:0a.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
483 88:0a.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
484 88:0a.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
486 9. Example where O-DU and O-RU simulation run on the same system:
494 echo 1 > /proc/sys/kernel/core_uses_pid
496 ./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/301/usecase_du.cfg --num_eth_vfs 6 \
497 --vf_addr_o_xu_a "0000:88:02.0,0000:88:0a.0" \
498 --vf_addr_o_xu_b "0000:88:02.1,0000:88:0a.1" \
499 --vf_addr_o_xu_c "0000:88:02.2,0000:88:0a.2"
507 echo 1 > /proc/sys/kernel/core_uses_pid
509 ./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/301/usecase_ru.cfg --num_eth_vfs 6 \
510 --vf_addr_o_xu_a "0000:86:02.0,0000:86:0a.0" \
511 --vf_addr_o_xu_b "0000:86:02.1,0000:86:0a.1" \
512 --vf_addr_o_xu_c "0000:86:02.2,0000:86:0a.2"
515 Install and Configure Sample Application
516 ========================================
518 To install and configure the sample application:
520 1. Set up the environment::
522 For Skylake and Cascadelake
523 export GTEST_ROOT=pwd/gtest-1.7.0
524 export RTE_SDK=pwd/dpdk-20.11.1
525 export RTE_TARGET=x86_64-native-linuxapp-icc
526 export DIR_WIRELESS_SDK_ROOT=pwd/wireless_sdk
527 export WIRELESS_SDK_TARGET_ISA=avx512
528 export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc
529 export DIR_WIRELESS_SDK=${DIR_WIRELESS_SDK_ROOT}/${SDK_BUILD}
530 export MLOG_DIR=pwd/flexran_l1_sw/libs/mlog
531 export XRAN_DIR=pwd/flexran_xran
534 export GTEST_ROOT=pwd/gtest-1.7.0
535 export RTE_SDK=pwd/dpdk-20.11.1
536 export RTE_TARGET=x86_64-native-linuxapp-icc
537 export DIR_WIRELESS_SDK_ROOT=pwd/wireless_sdk
538 export WIRELESS_SDK_TARGET_ISA=snc
539 export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc
540 export DIR_WIRELESS_SDK=${DIR_WIRELESS_SDK_ROOT}/${SDK_BUILD}
541 export MLOG_DIR=pwd/flexran_l1_sw/libs/mlog
542 export XRAN_DIR=pwd/flexran_xran
544 2. export FLEXRAN_SDK=${DIR_WIRELESS_SDK}/install Compile mlog library::
546 [turner@xran home]$ cd $MLOG_DIR
547 [turner@xran xran]$ ./build.sh
549 3. Compile O-RAN library and test the application::
551 [turner@xran home]$ cd $XRAN_DIR
552 [turner@xran xran]$ ./build.sh
554 4. Configure the sample app.
556 IQ samples can be generated using Octave\* and script
557 libs/xran/app/gen_test.m. (CentOS\* has octave-3.8.2-20.el7.x86_64
558 compatible with get_test.m)
560 Other IQ sample test vectors can be used as well. The format of IQ
561 samples is binary int16_t I and Q for N slots of the OTA RF signal. For
562 example, for mmWave, it corresponds to 792RE*2*14symbol*8slots*10 ms =
563 3548160 bytes per antenna. Refer to comments in gen_test.m to correctly
564 specify the configuration for IQ test vector generation.
566 Update usecase_du.dat (or usecase_ru.cfg) with a suitable configuration
569 Update config_file_o_du.dat (or config_file_o_ru.dat) with a suitable
570 configuration for your scenario.
572 Update run_o_du.sh (run_o_ru.sh) with PCIe bus address of VF0 and VF1
573 used for U-plane and C-plane correspondingly.
575 5. Run the application using run_o_du.sh (run_o_ru.sh).
577 Install and Configure FlexRAN 5G NR L1 Application
578 ==================================================
580 The 5G NR layer 1 application can be used for executing the scenario for
581 mmWave with either the RU sample application or just the O-DU side. The
582 current release supports the constant configuration of the slot pattern
583 and RB allocation on the PHY side.
585 1. O-RAN library is enabled by default l1 application:
587 2. Get the FlexRAN L1 binary from https://github.com/intel/FlexRAN. Look for the l1/bin/nr5g/gnb/l1 folder for the
588 l1app binary and the corresponding phycfg and xrancfg files.
590 3. Configure the L1app using bin/nr5g/gnb/l1/phycfg_xran.xml and
591 xrancfg_sub6.xml (or other xml if it is mmwave or massive MIMO). ::
594 <version>oran_e_maintenance_release_v1.0</version>
595 <!-- numbers of O-RU connected to O-DU. All O-RUs are the same capabilities. Max O-RUs is per XRAN_PORTS_NUM i.e. 4 -->
597 <!-- # 10G,25G,40G,100G speed of Physical connection on O-RU -->
598 <oRuEthLinkSpeed>25</oRuEthLinkSpeed>
599 <!-- # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link in IOT spec) -->
600 <oRuLinesNumber>1</oRuLinesNumber>
603 <PciBusAddoRu0Vf0>0000:51:01.0</PciBusAddoRu0Vf0>
604 <PciBusAddoRu0Vf1>0000:51:01.1</PciBusAddoRu0Vf1>
605 <PciBusAddoRu0Vf2>0000:51:01.2</PciBusAddoRu0Vf2>
606 <PciBusAddoRu0Vf3>0000:51:01.3</PciBusAddoRu0Vf3>
609 <PciBusAddoRu1Vf0>0000:51:01.4</PciBusAddoRu1Vf0>
610 <PciBusAddoRu1Vf1>0000:51:01.5</PciBusAddoRu1Vf1>
611 <PciBusAddoRu1Vf2>0000:51:01.6</PciBusAddoRu1Vf2>
612 <PciBusAddoRu1Vf3>0000:51:01.7</PciBusAddoRu1Vf3>
615 <PciBusAddoRu2Vf0>0000:51:02.0</PciBusAddoRu2Vf0>
616 <PciBusAddoRu2Vf1>0000:51:02.1</PciBusAddoRu2Vf1>
617 <PciBusAddoRu2Vf2>0000:51:02.2</PciBusAddoRu2Vf2>
618 <PciBusAddoRu2Vf3>0000:51:02.3</PciBusAddoRu2Vf3>
621 <PciBusAddoRu3Vf0>0000:00:00.0</PciBusAddoRu3Vf0>
622 <PciBusAddoRu3Vf1>0000:00:00.0</PciBusAddoRu3Vf1>
623 <PciBusAddoRu3Vf2>0000:00:00.0</PciBusAddoRu3Vf2>
624 <PciBusAddoRu3Vf3>0000:00:00.0</PciBusAddoRu3Vf3>
626 <!-- remote O-RU 0 Eth Link 0 VF0, VF1-->
627 <oRuRem0Mac0>00:11:22:33:00:01<oRuRem0Mac0>
628 <oRuRem0Mac1>00:11:22:33:00:11<oRuRem0Mac1>
629 <!-- remote O-RU 0 Eth Link 1 VF2, VF3 -->
630 <oRuRem0Mac2>00:11:22:33:00:21<oRuRem0Mac2>
631 <oRuRem0Mac3>00:11:22:33:00:31<oRuRem0Mac3>
633 <!-- remote O-RU 1 Eth Link 0 VF4, VF5-->
634 <oRuRem1Mac0>00:11:22:33:01:01<oRuRem1Mac0>
635 <oRuRem1Mac1>00:11:22:33:01:11<oRuRem1Mac1>
636 <!-- remote O-RU 1 Eth Link 1 VF6, VF7 -->
637 <oRuRem1Mac2>00:11:22:33:01:21<oRuRem1Mac2>
638 <oRuRem1Mac3>00:11:22:33:01:31<oRuRem1Mac3>
640 <!-- remote O-RU 2 Eth Link 0 VF8, VF9 -->
641 <oRuRem2Mac0>00:11:22:33:02:01<oRuRem2Mac0>
642 <oRuRem2Mac1>00:11:22:33:02:11<oRuRem2Mac1>
643 <!-- remote O-RU 2 Eth Link 1 VF10, VF11-->
644 <oRuRem2Mac2>00:11:22:33:02:21<oRuRem2Mac2>
645 <oRuRem2Mac3>00:11:22:33:02:31<oRuRem2Mac3>
647 <!-- remote O-RU 2 Eth Link 0 VF12, VF13 -->
648 <oRuRem3Mac0>00:11:22:33:03:01<oRuRem3Mac0>
649 <oRuRem3Mac1>00:11:22:33:03:11<oRuRem3Mac1>
650 <!-- remote O-RU 2 Eth Link 1 VF14, VF15-->
651 <oRuRem3Mac2>00:11:22:33:03:21<oRuRem3Mac2>
652 <oRuRem3Mac3>00:11:22:33:03:31<oRuRem3Mac3>
654 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
655 <oRu0NumCc>12</oRu0NumCc>
656 <!-- First Phy instance ID mapped to this O-RU CC0 -->
657 <oRu0Cc0PhyId>0</oRu0Cc0PhyId>
658 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
659 <oRu0Cc1PhyId>1</oRu0Cc1PhyId>
660 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
661 <oRu0Cc2PhyId>2</oRu0Cc2PhyId>
662 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
663 <oRu0Cc3PhyId>3</oRu0Cc3PhyId>
664 <!-- First Phy instance ID mapped to this O-RU CC0 -->
665 <oRu0Cc4PhyId>4</oRu0Cc4PhyId>
666 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
667 <oRu0Cc5PhyId>5</oRu0Cc5PhyId>
668 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
669 <oRu0Cc6PhyId>6</oRu0Cc6PhyId>
670 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
671 <oRu0Cc7PhyId>7</oRu0Cc7PhyId>
672 <!-- First Phy instance ID mapped to this O-RU CC0 -->
673 <oRu0Cc8PhyId>8</oRu0Cc8PhyId>
674 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
675 <oRu0Cc9PhyId>9</oRu0Cc9PhyId>
676 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
677 <oRu0Cc10PhyId>10</oRuCc10PhyId>
678 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
679 <oRu0Cc11PhyId>11</oRu0Cc11PhyId>
681 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
682 <oRu1NumCc>1</oRu1NumCc>
683 <!-- First Phy instance ID mapped to this O-RU CC0 -->
684 <oRu1Cc0PhyId>1</oRu1Cc0PhyId>
685 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
686 <oRu1Cc1PhyId>1</oRu1Cc1PhyId>
687 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
688 <oRu1Cc2PhyId>2</oRu1Cc2PhyId>
689 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
690 <oRu1Cc3PhyId>3</oRu1Cc3PhyId>
692 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
693 <oRu2NumCc>1</oRu2NumCc>
694 <!-- First Phy instance ID mapped to this O-RU CC0 -->
695 <oRu2Cc0PhyId>2</oRu2Cc0PhyId>
696 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
697 <oRu2Cc1PhyId>1</oRu2Cc1PhyId>
698 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
699 <oRu2Cc2PhyId>2</oRu2Cc2PhyId>
700 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
701 <oRu2Cc3PhyId>3</oRu2Cc3PhyId>
703 <!-- XRAN Thread (core where the XRAN polling function is pinned: Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->
704 <xRANThread>19, 96, 0</xRANThread>
706 <!-- core mask for XRAN Packets Worker (core where the XRAN packet processing is pinned): Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->
707 <xRANWorker>0x8000000000, 96, 0</xRANWorker>
708 <!-- XRAN: Category of O-RU 0 - Category A, 1 - Category B -->
709 <Category>0</Category>
711 <!-- XRAN: enable sleep on PMD cores -->
712 <xranPmdSleep>0</xranPmdSleep>
715 <Tadv_cp_dl>25</Tadv_cp_dl>
716 <!-- Reception Window C-plane DL-->
717 <T2a_min_cp_dl>285</T2a_min_cp_dl>
718 <T2a_max_cp_dl>429</T2a_max_cp_dl>
719 <!-- Reception Window C-plane UL-->
720 <T2a_min_cp_ul>285</T2a_min_cp_ul>
721 <T2a_max_cp_ul>429</T2a_max_cp_ul>
722 <!-- Reception Window U-plane -->
723 <T2a_min_up>71</T2a_min_up>
724 <T2a_max_up>428</T2a_max_up>
725 <!-- Transmission Window U-plane -->
726 <Ta3_min>20</Ta3_min>
727 <Ta3_max>32</Ta3_max>
729 <!-- O-DU Settings -->
732 <!-- VLAN Tag used for C-Plane -->
733 <c_plane_vlan_tag>1</c_plane_vlan_tag>
734 <u_plane_vlan_tag>2</u_plane_vlan_tag>
736 <!-- Transmission Window Fast C-plane DL -->
737 <T1a_min_cp_dl>258</T1a_min_cp_dl>
738 <T1a_max_cp_dl>470</T1a_max_cp_dl>
739 <!-- Transmission Window Fast C-plane UL -->
740 <T1a_min_cp_ul>285</T1a_min_cp_ul>
741 <T1a_max_cp_ul>429</T1a_max_cp_ul>
742 <!-- Transmission Window U-plane -->
743 <T1a_min_up>50</T1a_min_up>
744 <T1a_max_up>196</T1a_max_up>
745 <!-- Reception Window U-Plane-->
747 <Ta4_max>75</Ta4_max>
749 <!-- Enable Control Plane -->
750 <EnableCp>1</EnableCp>
752 <DynamicSectionEna>0</DynamicSectionEna>
753 <!-- Enable Dynamic section allocation for UL -->
754 <DynamicSectionEnaUL>0</DynamicSectionEnaUL>
755 <xRANSFNWrap>1</xRANSFNWrap>
756 <!-- Total Number of DL PRBs per symbol (starting from RB 0) that is transmitted (used for testing. If 0, then value is used from PHY_CONFIG_API) -->
757 <xRANNumDLPRBs>0</xRANNumDLPRBs>
758 <!-- Total Number of UL PRBs per symbol (starting from RB 0) that is received (used for testing. If 0, then value is used from PHY_CONFIG_API) -->
759 <xRANNumULPRBs>0</xRANNumULPRBs>
760 <!-- refer to alpha as defined in section 9.7.2 of ORAN spec. this value should be alpha*(1/1.2288ns), range 0 - 1e7 (ns) -->
761 <Gps_Alpha>0</Gps_Alpha>
762 <!-- beta value as defined in section 9.7.2 of ORAN spec. range -32767 ~ +32767 -->
763 <Gps_Beta>0</Gps_Beta>
765 <!-- XRAN: Compression mode on O-DU <-> O-RU 0 - no comp 1 - BFP -->
766 <xranCompMethod>1</xranCompMethod>
767 <!-- XRAN: iqWidth when DynamicSectionEna and BFP Compression enabled -->
768 <xraniqWidth>8</xraniqWidth>
769 <!-- Whether Modulation Compression mode is enabled or not for DL only -->
770 <xranModCompEna>0</xranModCompEna>
772 <oRu0nPrbElemDl>1</oRu0nPrbElemDl>
773 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
774 <!-- weight base beams -->
775 <oRu0PrbElemDl0>0,273,0,14,0,0,1,8,0,0,0</oRu0PrbElemDl0>
776 <oRu0PrbElemDl1>50,25,0,14,1,1,0,16,1,0,0</oRu0PrbElemDl1>
777 <oRu0PrbElemDl2>72,36,0,14,3,1,1,9,1,0,0</oRu0PrbElemDl2>
778 <oRu0PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemDl3>
779 <oRu0PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu0PrbElemDl4>
780 <oRu0PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu0PrbElemDl5>
781 <oRu0PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu0PrbElemDl6>
782 <oRu0PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemDl7>
785 <oRu0nPrbElemUl>1</oRu0nPrbElemUl>
786 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask-->
787 <!-- weight base beams -->
788 <oRu0PrbElemUl0>0,273,0,14,0,0,1,8,0,0,0</oRu0PrbElemUl0>
789 <oRu0PrbElemUl1>0,273,0,14,0,0,1,8,0,0,0</oRu0PrbElemUl1>
790 <oRu0PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu0PrbElemUl2>
791 <oRu0PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu0PrbElemUl3>
792 <oRu0PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu0PrbElemUl4>
793 <oRu0PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu0PrbElemUl5>
794 <oRu0PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu0PrbElemUl6>
795 <oRu0PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemUl7>
798 <oRu1MaxSectionsPerSlot>6</oRu1MaxSectionsPerSlot>
799 <oRu1MaxSectionsPerSymbol>6</oRu1MaxSectionsPerSymbol>
800 <oRu1nPrbElemDl>1</oRu1nPrbElemDl>
801 <oRu1PrbElemDl0>0,273,0,14,0,0,1,8,0,0,0</oRu1PrbElemDl0>
802 <oRu1PrbElemDl1>53,53,0,14,2,1,1,8,1,0,0</oRu1PrbElemDl1>
803 <oRu1nPrbElemUl>1</oRu1nPrbElemUl>
804 <oRu1PrbElemUl0>0,273,0,14,0,0,1,8,0,0,0</oRu1PrbElemUl0>
805 <oRu1PrbElemUl1>53,53,0,14,2,1,1,8,1,0,0</oRu1PrbElemUl1>
807 <oRu2MaxSectionsPerSlot>6</oRu2MaxSectionsPerSlot>
808 <oRu2MaxSectionsPerSymbol>6</oRu2MaxSectionsPerSymbol>
809 <oRu2nPrbElemDl>1</oRu2nPrbElemDl>
810 <oRu2PrbElemDl0>0,273,0,14,0,0,1,8,0,0,0</oRu2PrbElemDl0>
811 <oRu2PrbElemDl1>53,53,0,14,2,1,1,8,1,0,0</oRu2PrbElemDl1>
812 <oRu2nPrbElemUl>1</oRu2nPrbElemUl>
813 <oRu2PrbElemUl0>0,273,0,14,0,0,1,8,0,0,0</oRu2PrbElemUl0>
814 <oRu2PrbElemUl1>53,53,0,14,2,1,1,8,1,0,0</oRu2PrbElemUl1>
820 4. Modify bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs). ::
822 $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:21:02.0
823 $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:21:02.1
825 5. Use configuration of test mac per::
827 /bin/nr5g/gnb.testmac/cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg
829 <!-- mmWave mu 3 100MHz -->
830 TEST_FD, 1002, 1, fd/mu3_100mhz/2/fd_testconfig_tst2.cfg
833 6. To execute l1app with O-DU functionality according to O-RAN Fronthaul specification, enter::
835 [root@xran flexran] cd ./bin/nr5g/gnb/l1
836 [root@xran l1]#./l1.sh –xran
838 where output corresponding L1 is
842 7. To execute testmac with O-DU functionality according to O-RAN Fronthaul specification, enter::
844 [root@xran flexran] cd ./bin/nr5g/gnb/testmac
847 8. To execute test case type::
850 --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg
853 where output corresponding to Test MAC::
855 [root@sc12-xran-sub6 testmac]# ./l2.sh --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg
858 Configure FlexRAN 5G NR L1 Application for multiple O-RUs with multiple numerologies
859 ====================================================================================
861 The 5G NR layer 1 application can be used for executing the scenario for
862 multiple cells with multiple numerologies. The current release supports
863 the constant configuration of different numerologies on different O-RU
864 ports. It is required that the first O-RU (O-RU0) to be configured with
865 highest numerology. The configuration procedure is similar as described
866 in above section. Please refer to the configuration file located in
867 bin\nr5g\gnb\l1\orancfg\sub3_mu0_20mhz_sub6_mu1_100mhz_4x4\gnb\xrancfg_sub6_oru.xml
869 Install and Configure FlexRAN 5G NR L1 Application for Massive - MIMO
870 =====================================================================
872 The 5G NR layer 1 application can be used for executing the scenario for
873 Massive-MIMO with either the RU sample application or just the O-DU
874 side. 3 cells scenario with 64T64R Massive MIMO is targeted for Icelake
875 system with Columbiavile NIC. The current release supports the constant
876 configuration of the slot pattern and RB allocation on the PHY side.
877 Please follow the general build process in the FlexRAN 5G NR Reference
878 Solution L1 User Guide (refer to Table 2.)
880 1. O-RAN library is enabled by default l1 application
882 2. 5G NR L1 application available from https://github.com/intel/FlexRAN.
883 Look for the l1/bin/nr5g/gnb/l1 folder for the
884 l1app binary and the corresponding phycfg and xrancfg files.
886 3. Configure the L1app using bin/nr5g/gnb/l1/xrancfg_sub6_mmimo.xml.
889 <version>oran_e_maintenance_release_v1.0<</version>
890 <!-- numbers of O-RU connected to O-DU. All O-RUs are the same capabilities. Max O-RUs is per XRAN_PORTS_NUM i.e. 4 -->
892 <!-- # 10G,25G,40G,100G speed of Physical connection on O-RU -->
893 <oRuEthLinkSpeed>25</oRuEthLinkSpeed>
894 <!-- # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link in IOT spec) -->
895 <oRuLinesNumber>2</oRuLinesNumber>
896 <!-- (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs -->
897 <oRuCUon1Vf>1</oRuCUon1Vf>
900 <PciBusAddoRu0Vf0>0000:51:01.0</PciBusAddoRu0Vf0>
901 <PciBusAddoRu0Vf1>0000:51:09.0</PciBusAddoRu0Vf1>
902 <PciBusAddoRu0Vf2>0000:51:01.2</PciBusAddoRu0Vf2>
903 <PciBusAddoRu0Vf3>0000:51:01.3</PciBusAddoRu0Vf3>
906 <PciBusAddoRu1Vf0>0000:51:11.0</PciBusAddoRu1Vf0>
907 <PciBusAddoRu1Vf1>0000:51:19.0</PciBusAddoRu1Vf1>
908 <PciBusAddoRu1Vf2>0000:51:01.6</PciBusAddoRu1Vf2>
909 <PciBusAddoRu1Vf3>0000:51:01.7</PciBusAddoRu1Vf3>
912 <PciBusAddoRu2Vf0>0000:18:01.0</PciBusAddoRu2Vf0>
913 <PciBusAddoRu2Vf1>0000:18:09.0</PciBusAddoRu2Vf1>
914 <PciBusAddoRu2Vf2>0000:51:02.2</PciBusAddoRu2Vf2>
915 <PciBusAddoRu2Vf3>0000:51:02.3</PciBusAddoRu2Vf3>
918 <PciBusAddoRu3Vf0>0000:00:00.0</PciBusAddoRu3Vf0>
919 <PciBusAddoRu3Vf1>0000:00:00.0</PciBusAddoRu3Vf1>
920 <PciBusAddoRu3Vf2>0000:00:00.0</PciBusAddoRu3Vf2>
921 <PciBusAddoRu3Vf3>0000:00:00.0</PciBusAddoRu3Vf3>
923 <!-- remote O-RU 0 Eth Link 0 VF0, VF1-->
924 <oRuRem0Mac0>00:11:22:33:00:01<oRuRem0Mac0>
925 <oRuRem0Mac1>00:11:22:33:00:11<oRuRem0Mac1>
926 <!-- remote O-RU 0 Eth Link 1 VF2, VF3 -->
927 <oRuRem0Mac2>00:11:22:33:00:21<oRuRem0Mac2>
928 <oRuRem0Mac3>00:11:22:33:00:31<oRuRem0Mac3>
930 <!-- remote O-RU 1 Eth Link 0 VF4, VF5-->
931 <oRuRem1Mac0>00:11:22:33:01:01<oRuRem1Mac0>
932 <oRuRem1Mac1>00:11:22:33:01:11<oRuRem1Mac1>
933 <!-- remote O-RU 1 Eth Link 1 VF6, VF7 -->
934 <oRuRem1Mac2>00:11:22:33:01:21<oRuRem1Mac2>
935 <oRuRem1Mac3>00:11:22:33:01:31<oRuRem1Mac3>
937 <!-- remote O-RU 2 Eth Link 0 VF8, VF9 -->
938 <oRuRem2Mac0>00:11:22:33:02:01<oRuRem2Mac0>
939 <oRuRem2Mac1>00:11:22:33:02:11<oRuRem2Mac1>
940 <!-- remote O-RU 2 Eth Link 1 VF10, VF11-->
941 <oRuRem2Mac2>00:11:22:33:02:21<oRuRem2Mac2>
942 <oRuRem2Mac3>00:11:22:33:02:31<oRuRem2Mac3>
944 <!-- remote O-RU 2 Eth Link 0 VF12, VF13 -->
945 <oRuRem3Mac0>00:11:22:33:03:01<oRuRem3Mac0>
946 <oRuRem3Mac1>00:11:22:33:03:11<oRuRem3Mac1>
947 <!-- remote O-RU 2 Eth Link 1 VF14, VF15-->
948 <oRuRem3Mac2>00:11:22:33:03:21<oRuRem3Mac2>
949 <oRuRem3Mac3>00:11:22:33:03:31<oRuRem3Mac3>
951 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
952 <oRu0NumCc>1</oRu0NumCc>
953 <!-- First Phy instance ID mapped to this O-RU CC0 -->
954 <oRu0Cc0PhyId>0</oRu0Cc0PhyId>
955 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
956 <oRu0Cc1PhyId>1</oRu0Cc1PhyId>
957 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
958 <oRu0Cc2PhyId>2</oRu0Cc2PhyId>
959 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
960 <oRu0Cc3PhyId>3</oRu0Cc3PhyId>
962 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
963 <oRu1NumCc>1</oRu1NumCc>
964 <!-- First Phy instance ID mapped to this O-RU CC0 -->
965 <oRu1Cc0PhyId>1</oRu1Cc0PhyId>
966 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
967 <oRu1Cc1PhyId>1</oRu1Cc1PhyId>
968 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
969 <oRu1Cc2PhyId>2</oRu1Cc2PhyId>
970 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
971 <oRu1Cc3PhyId>3</oRu1Cc3PhyId>
973 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
974 <oRu2NumCc>1</oRu2NumCc>
975 <!-- First Phy instance ID mapped to this O-RU CC0 -->
976 <oRu2Cc0PhyId>2</oRu2Cc0PhyId>
977 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
978 <oRu2Cc1PhyId>1</oRu2Cc1PhyId>
979 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
980 <oRu2Cc2PhyId>2</oRu2Cc2PhyId>
981 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
982 <oRu2Cc3PhyId>3</oRu2Cc3PhyId>
984 <!-- XRAN Thread (core where the XRAN polling function is pinned: Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->
985 <xRANThread>22, 96, 0</xRANThread>
987 <!-- core mask for XRAN Packets Worker (core where the XRAN packet processing is pinned): Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->
988 <xRANWorker>0x3800000, 96, 0</xRANWorker>
989 <!-- XRAN: Category of O-RU 0 - Category A, 1 - Category B -->
990 <Category>1</Category>
992 <!-- XRAN: enable sleep on PMD cores -->
993 <xranPmdSleep>0</xranPmdSleep>
996 <Tadv_cp_dl>25</Tadv_cp_dl>
997 <!-- Reception Window C-plane DL-->
998 <T2a_min_cp_dl>285</T2a_min_cp_dl>
999 <T2a_max_cp_dl>429</T2a_max_cp_dl>
1000 <!-- Reception Window C-plane UL-->
1001 <T2a_min_cp_ul>285</T2a_min_cp_ul>
1002 <T2a_max_cp_ul>429</T2a_max_cp_ul>
1003 <!-- Reception Window U-plane -->
1004 <T2a_min_up>71</T2a_min_up>
1005 <T2a_max_up>428</T2a_max_up>
1006 <!-- Transmission Window U-plane -->
1007 <Ta3_min>20</Ta3_min>
1008 <Ta3_max>32</Ta3_max>
1010 <!-- O-DU Settings -->
1013 <!-- VLAN Tag used for C-Plane -->
1014 <c_plane_vlan_tag>1</c_plane_vlan_tag>
1015 <u_plane_vlan_tag>2</u_plane_vlan_tag>
1017 <!-- Transmission Window Fast C-plane DL -->
1018 <T1a_min_cp_dl>258</T1a_min_cp_dl>
1019 <T1a_max_cp_dl>429</T1a_max_cp_dl>
1020 <!-- Transmission Window Fast C-plane UL -->
1021 <T1a_min_cp_ul>285</T1a_min_cp_ul>
1022 <T1a_max_cp_ul>300</T1a_max_cp_ul>
1023 <!-- Transmission Window U-plane -->
1024 <T1a_min_up>96</T1a_min_up>
1025 <T1a_max_up>196</T1a_max_up>
1026 <!-- Reception Window U-Plane-->
1027 <Ta4_min>0</Ta4_min>
1028 <Ta4_max>75</Ta4_max>
1030 <!-- Enable Control Plane -->
1031 <EnableCp>1</EnableCp>
1033 <DynamicSectionEna>0</DynamicSectionEna>
1034 <!-- Enable Dynamic section allocation for UL -->
1035 <DynamicSectionEnaUL>0</DynamicSectionEnaUL>
1036 <xRANSFNWrap>1</xRANSFNWrap>
1037 <!-- Total Number of DL PRBs per symbol (starting from RB 0) that is transmitted (used for testing. If 0, then value is used from PHY_CONFIG_API) -->
1038 <xRANNumDLPRBs>0</xRANNumDLPRBs>
1039 <!-- Total Number of UL PRBs per symbol (starting from RB 0) that is received (used for testing. If 0, then value is used from PHY_CONFIG_API) -->
1040 <xRANNumULPRBs>0</xRANNumULPRBs>
1041 <!-- refer to alpha as defined in section 9.7.2 of ORAN spec. this value should be alpha*(1/1.2288ns), range 0 - 1e7 (ns) -->
1042 <Gps_Alpha>0</Gps_Alpha>
1043 <!-- beta value as defined in section 9.7.2 of ORAN spec. range -32767 ~ +32767 -->
1044 <Gps_Beta>0</Gps_Beta>
1046 <!-- XRAN: Compression mode on O-DU <-> O-RU 0 - no comp 1 - BFP -->
1047 <xranCompMethod>1</xranCompMethod>
1048 <!-- XRAN: iqWidth when DynamicSectionEna and BFP Compression enabled -->
1049 <xraniqWidth>9</xraniqWidth>
1051 <!-- M-plane values of O-RU configuration -->
1052 <oRu0MaxSectionsPerSlot>6<oRu0MaxSectionsPerSlot>
1053 <oRu0MaxSectionsPerSymbol>6<oRu0MaxSectionsPerSymbol>
1055 <oRu0nPrbElemDl>6</oRu0nPrbElemDl>
1056 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1057 <!-- weight base beams -->
1058 <oRu0PrbElemDl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemDl0>
1059 <oRu0PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemDl1>
1060 <oRu0PrbElemDl2>96,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemDl2>
1061 <oRu0PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemDl3>
1062 <oRu0PrbElemDl4>192,48,0,14,5,1,1,9,1,0,0</oRu0PrbElemDl4>
1063 <oRu0PrbElemDl5>240,33,0,14,6,1,1,9,1,0,0</oRu0PrbElemDl5>
1064 <oRu0PrbElemDl6>240,33,0,14,7,1,1,9,1,0,0</oRu0PrbElemDl6>
1065 <oRu0PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemDl7>
1067 <!-- extType = 11 -->
1068 <oRu0ExtBfwDl0>2,24,0,0,9,1</oRu0ExtBfwDl0>
1069 <oRu0ExtBfwDl1>2,24,0,0,9,1</oRu0ExtBfwDl1>
1070 <oRu0ExtBfwDl2>2,24,0,0,9,1</oRu0ExtBfwDl2>
1071 <oRu0ExtBfwDl3>2,24,0,0,9,1</oRu0ExtBfwDl3>
1072 <oRu0ExtBfwDl4>2,24,0,0,9,1</oRu0ExtBfwDl4>
1073 <oRu0ExtBfwDl5>2,17,0,0,9,1</oRu0ExtBfwDl5>
1075 <oRu0nPrbElemUl>6</oRu0nPrbElemUl>
1076 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1077 <!-- weight base beams -->
1078 <oRu0PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemUl0>
1079 <oRu0PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemUl1>
1080 <oRu0PrbElemUl2>96,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemUl2>
1081 <oRu0PrbElemUl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemUl3>
1082 <oRu0PrbElemUl4>192,48,0,14,5,1,1,9,1,0,0</oRu0PrbElemUl4>
1083 <oRu0PrbElemUl5>240,33,0,14,6,1,1,9,1,0,0</oRu0PrbElemUl5>
1084 <oRu0PrbElemUl6>240,33,0,14,7,1,1,9,1,0,0</oRu0PrbElemUl6>
1085 <oRu0PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemUl7>
1087 <!-- extType = 11 -->
1088 <oRu0ExtBfwUl0>2,24,0,0,9,1</oRu0ExtBfwUl0>
1089 <oRu0ExtBfwUl1>2,24,0,0,9,1</oRu0ExtBfwUl1>
1090 <oRu0ExtBfwUl2>2,24,0,0,9,1</oRu0ExtBfwUl2>
1091 <oRu0ExtBfwUl3>2,24,0,0,9,1</oRu0ExtBfwUl3>
1092 <oRu0ExtBfwUl4>2,24,0,0,9,1</oRu0ExtBfwUl4>
1093 <oRu0ExtBfwUl5>2,17,0,0,9,1</oRu0ExtBfwUl5>
1095 <oRu0nPrbElemSrs>1</oRu0nPrbElemSrs>
1096 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1097 <!-- weight base beams -->
1098 <oRu0PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu0PrbElemSrs0>
1099 <oRu0PrbElemSrs1>0,273,0,14,1,1,1,9,1,0,0</oRu0PrbElemSrs1>
1101 <!-- M-plane values of O-RU configuration -->
1102 <oRu10MaxSectionsPerSlot>6<oRu1MaxSectionsPerSlot>
1103 <oRu1MaxSectionsPerSymbol>6<oRu1MaxSectionsPerSymbol>
1105 <oRu1nPrbElemDl>2</oRu1nPrbElemDl>
1106 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1107 <!-- weight base beams -->
1108 <oRu1PrbElemDl0>0,48,0,14,0,1,1,9,1,0,0</oRu1PrbElemDl0>
1109 <oRu1PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu1PrbElemDl1>
1110 <oRu1PrbElemDl2>96,48,0,14,3,1,1,9,1,0,0</oRu1PrbElemDl2>
1111 <oRu1PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu1PrbElemDl3>
1112 <oRu1PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu1PrbElemDl4>
1113 <oRu1PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu1PrbElemDl5>
1114 <oRu1PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu1PrbElemDl6>
1115 <oRu1PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu1PrbElemDl7>
1117 <!-- extType = 11 -->
1118 <oRu1ExtBfwDl0>2,24,0,0,9,1</oRu1ExtBfwDl0>
1119 <oRu1ExtBfwDl1>2,24,0,0,9,1</oRu1ExtBfwDl1>
1121 <oRu1nPrbElemUl>2</oRu1nPrbElemUl>
1122 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1123 <!-- weight base beams -->
1124 <oRu1PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu1PrbElemUl0>
1125 <oRu1PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu1PrbElemUl1>
1126 <oRu1PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu1PrbElemUl2>
1127 <oRu1PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu1PrbElemUl3>
1128 <oRu1PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu1PrbElemUl4>
1129 <oRu1PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu1PrbElemUl5>
1130 <oRu1PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu1PrbElemUl6>
1131 <oRu1PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu1PrbElemUl7>
1133 <!-- extType = 11 -->
1134 <oRu1ExtBfwUl0>2,24,0,0,9,1</oRu1ExtBfwUl0>
1135 <oRu1ExtBfwUl1>2,24,0,0,9,1</oRu1ExtBfwUl1>
1137 <oRu1nPrbElemSrs>1</oRu1nPrbElemSrs>
1138 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1139 <!-- weight base beams -->
1140 <oRu1PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu1PrbElemSrs0>
1141 <oRu1PrbElemSrs1>0,273,0,14,1,1,1,9,1,0,0</oRu1PrbElemSrs1>
1143 <!-- M-plane values of O-RU configuration -->
1144 <oRu20MaxSectionsPerSlot>6<oRu2MaxSectionsPerSlot>
1145 <oRu2MaxSectionsPerSymbol>6<oRu2MaxSectionsPerSymbol>
1147 <oRu2nPrbElemDl>2</oRu2nPrbElemDl>
1148 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1149 <!-- weight base beams -->
1150 <oRu2PrbElemDl0>0,48,0,14,1,1,1,9,1,0,0</oRu2PrbElemDl0>
1151 <oRu2PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu2PrbElemDl1>
1152 <oRu2PrbElemDl2>96,48,0,14,3,1,1,9,1,0,0</oRu2PrbElemDl2>
1153 <oRu2PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu2PrbElemDl3>
1154 <oRu2PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu2PrbElemDl4>
1155 <oRu2PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu2PrbElemDl5>
1156 <oRu2PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu2PrbElemDl6>
1157 <oRu2PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu2PrbElemDl7>
1159 <!-- extType = 11 -->
1160 <oRu2ExtBfwDl0>2,24,0,0,9,1</oRu2ExtBfwDl0>
1161 <oRu2ExtBfwDl1>2,24,0,0,9,1</oRu2ExtBfwDl1>
1163 <oRu2nPrbElemUl>2</oRu2nPrbElemUl>
1164 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1165 <!-- weight base beams -->
1166 <oRu2PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu2PrbElemUl0>
1167 <oRu2PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu2PrbElemUl1>
1168 <oRu2PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu2PrbElemUl2>
1169 <oRu2PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu2PrbElemUl3>
1170 <oRu2PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu2PrbElemUl4>
1171 <oRu2PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu2PrbElemUl5>
1172 <oRu2PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu2PrbElemUl6>
1173 <oRu2PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu2PrbElemUl7>
1175 <!-- extType = 11 -->
1176 <oRu2ExtBfwUl0>2,24,0,0,9,1</oRu2ExtBfwUl0>
1177 <oRu2ExtBfwUl1>2,24,0,0,9,1</oRu2ExtBfwUl1>
1179 <oRu2nPrbElemSrs>1</oRu2nPrbElemSrs>
1180 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1181 <!-- weight base beams -->
1182 <oRu2PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu2PrbElemSrs0>
1183 <oRu2PrbElemSrs1>0,273,0,14,1,1,1,9,1,0,0</oRu2PrbElemSrs1>
1188 4. Modify ./bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs). ::
1190 ethDevice0=0000:51:01.0
1191 ethDevice1=0000:51:01.1
1192 ethDevice2=0000:51:01.2
1193 ethDevice3=0000:51:01.3
1194 ethDevice4=0000:51:01.4
1195 ethDevice5=0000:51:01.5
1202 fecDevice0=0000:92:00.0
1204 5. Use configuration of test mac per::
1206 /bin/nr5g/gnb/testmac/icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg
1208 TEST_FD, 3370, 3, fd/mu1_100mhz/376/fd_testconfig_tst376.cfg,
1209 fd/mu1_100mhz/377/fd_testconfig_tst377.cfg,
1210 fd/mu1_100mhz/377/fd_testconfig_tst377.cfg
1212 6. To execute l1app with O-DU functionality according to O-RAN Fronthaul specification, enter::
1214 [root@xran flexran] cd ./bin/nr5g/gnb/l1
1216 Radio mode with XRAN - Sub6 100Mhz Massive-MIMO (CatB)
1218 7. To execute testmac with O-DU functionality according to O-RAN Fronthaul specification, enter::
1220 [root@xran flexran] cd ./bin/nr5g/gnb/testmac
1222 8. To execute test case type::
1224 ./l2.sh --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg
1226 where output corresponding to Test MAC::
1228 root@icelake-scs1-1 testmac]# ./l2.sh --testfile=./icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg