1 .. Copyright (c) 2019-2022 Intel
3 .. Licensed under the Apache License, Version 2.0 (the "License");
4 .. you may not use this file except in compliance with the License.
5 .. You may obtain a copy of the License at
7 .. http://www.apache.org/licenses/LICENSE-2.0
9 .. Unless required by applicable law or agreed to in writing, software
10 .. distributed under the License is distributed on an "AS IS" BASIS,
11 .. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 .. See the License for the specific language governing permissions and
13 .. limitations under the License.
22 A.1 Setup Configuration
23 -----------------------
24 The configuration shown in Figure 26 shows how to set up a test
25 environment to execute O-RAN scenarios where O-DU and 0-RU are simulated
26 using the sample application. This setup allows development and
27 prototyping as well as testing of O-RAN specific functionality. The O-DU
28 side can be instantiated with a full 5G NR L1 reference as well. The
29 configuration differences of the 5G NR l1app configuration are provided
30 below. Steps for running the sample application on the O-DU side and
31 0-RU side are the same, except configuration file options may be
34 .. image:: images/Setup-for-O-RAN-Testing.jpg
36 :alt: Figure 27. Setup for O-RAN Testing
38 Figure 27. Setup for O-RAN Testing
42 .. image:: images/Setup-for-O-RAN-Testing-with-PHY-and-Configuration-C3.jpg
44 :alt: Figure 28. Setup for O-RAN Testing with PHY and Configuration C3
46 Figure 28. Setup for O-RAN Testing with PHY and Configuration C3
50 .. image:: images/Setup-for-O-RAN-Testing-with-PHY-and-Configuration-C3-for-Massive-MIMO.jpg
52 :alt: Figure 29. Setup for O-RAN Testing with PHY and Configuration C3 for
54 Figure 29. Setup for O-RAN Testing with PHY and Configuration C3 for
62 Each server in *Figure 27* requires the following:
64 - Wolfpass server according to recommended BOM for FlexRAN such as
65 Intel® Xeon® Skylake Gold 6148 FC-LGA3647 2.4 GHz 27.5 MB 150W 20
66 cores (two sockets) or higher
68 - Wilson City or Coyote Pass server with Intel® Xeon® Icelake CPU for
69 Massive-MIMO with L1 pipeline testing
73 - Intel® Virtualization Technology Enabled
75 - Intel® VT for Directed I/O - Enabled
77 - ACS Control - Enabled
79 - Coherency Support - Disabled
81 - Front Haul networking cards:
83 - Intel® Ethernet Converged Network Adapter XL710-QDA2
85 - Intel® Ethernet Converged Network Adapter XXV710-DA2
87 - Intel® Ethernet Converged Network Adapter E810-CQDA2
89 - Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000
91 - Back (Mid) Haul networking card can be either:
93 - Intel® Ethernet Connection X722 for 10GBASE-T
95 - Intel® 82599ES 10-Gigabit SFI/SFP+ Network Connection
97 - Other networking cards capable of HW timestamping for PTP synchronization.
99 - Both Back (mid) Haul and Front Haul NIC require support for PTP HW timestamping.
101 The recommended configuration for NICs is::
106 firmware-version: 8.20 0x80009bd4 1.2879.0
107 expansion-rom-version:
108 bus-info: 0000:21:00.0
109 supports-statistics: yes
111 supports-eeprom-access: yes
112 supports-register-dump: yes
113 supports-priv-flags: yes
115 Time stamping parameters for enp33s0f0:
117 hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
118 software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)
119 hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
120 software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)
121 software-system-clock (SOF_TIMESTAMPING_SOFTWARE)
122 hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
123 PTP Hardware Clock: 4
124 Hardware Transmit Timestamp Modes:
125 off (HWTSTAMP_TX_OFF)
127 Hardware Receive Filter Modes:
128 none (HWTSTAMP_FILTER_NONE)
129 ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC)
130 ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ)
131 ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)
132 ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC)
133 ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ)
134 ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT)
135 ptpv2-l2-sync (HWTSTAMP_FILTER_PTP_V2_L2_SYNC)
136 ptpv2-l2-delay-req (HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ)
137 ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)
138 ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC)
139 ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ)
141 The recommended configuration for Columbiaville NICs (base on Intel®
142 Ethernet 800 Series (Columbiaville) CVL 2.3 release is::
147 firmware-version: 2.3 0x80005D18
148 expansion-rom-version:
149 bus-info: 0000:51:00.0
150 supports-statistics: yes
152 supports-eeprom-access: yes
153 supports-register-dump: yes
154 supports-priv-flags: yes
156 Time stamping parameters for enp81s0f0:
158 hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
159 software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)
160 hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
161 software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)
162 software-system-clock (SOF_TIMESTAMPING_SOFTWARE)
163 hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
164 PTP Hardware Clock: 1
165 Hardware Transmit Timestamp Modes:
166 off (HWTSTAMP_TX_OFF)
168 Hardware Receive Filter Modes:
169 none (HWTSTAMP_FILTER_NONE)
170 all (HWTSTAMP_FILTER_ALL)
172 Recommended version of
174 ICE COMMS Package version 1.3.24.0
176 *Note*. If your firmware version does not match with the ones in the output
177 images, you can download the correct version from the Intel Download
178 Center. It is Intel's repository for the latest software and drivers
179 for Intel products. The NVM Update Packages for Windows*, Linux*,
180 ESX*, FreeBSD*, and EFI/EFI2 are located at:
184 https://downloadcenter.intel.com/download/24769 (700 series)
186 https://downloadcenter.intel.com/download/29736 (E810 series)
188 PTP Grand Master is required to be available in the network to provide
189 synchronization of both O-DU and RU to GPS time.
191 The software package includes Linux\* CentOS\* operating system and RT
192 patch according to FlexRAN Reference Solution Cloud-Native Setup
193 document (refer to Table 2). Only real-time HOST is required.
195 1. Install Intel® C++ Compiler v19.0.3 or OneAPI compiler (preferred)
197 2. Download DPDK v20.11.3
199 3. Patch DPDK with FlexRAN BBDev patch as per given release.
201 4. Double check that FlexRAN DPDK patch includes changes below relevant
202 to O-RAN Front haul::
205 diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
206 index 85a6a86..236fbe0 100644
207 --- a/drivers/net/i40e/i40e_ethdev.c
208 +++ b/drivers/net/i40e/i40e_ethdev.c
209 @@ -2207,7 +2207,7 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
210 /* Map queues with MSIX interrupt */
211 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
212 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
213 - i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
214 + i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_NONE);
215 i40e_vsi_enable_queues_intr(main_vsi);
217 /* Map VMDQ VSI queues with MSIX interrupt */
218 @@ -2218,6 +2218,10 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
219 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
221 + i40e_aq_debug_write_global_register(hw,
225 /* enable FDIR MSIX interrupt */
226 if (pf->fdir.fdir_vsi) {
227 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
228 diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c
229 index 001c301..6f9ffdb 100644
230 --- a/drivers/net/i40e/i40e_ethdev_vf.c
231 +++ b/drivers/net/i40e/i40e_ethdev_vf.c
232 @@ -640,7 +640,7 @@ struct rte_i40evf_xstats_name_off {
234 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
235 map_info->num_vectors = 1;
236 - map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
237 + map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_NONE;
238 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
239 /* Alway use default dynamic MSIX interrupt */
240 map_info->vecmap[0].vector_id = vector_id;
241 diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
242 index 26b1927..018eb8f 100644
243 --- a/drivers/net/ixgbe/ixgbe_ethdev.c
244 +++ b/drivers/net/ixgbe/ixgbe_ethdev.c
245 @@ -3705,7 +3705,7 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
246 * except for 82598EB, which remains constant.
248 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
249 - hw->mac.type != ixgbe_mac_82598EB)
250 + hw->mac.type != ixgbe_mac_82598EB && hw->mac.type != ixgbe_mac_82599EB)
251 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
253 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
254 diff --git a/lib/librte_eal/common/include/rte_dev.h b/lib/librte_eal/common/include/rte_dev.h
259 diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
260 index de189daba..d9aff341c 100644
261 --- a/drivers/net/ice/ice_ethdev.c
262 +++ b/drivers/net/ice/ice_ethdev.c
263 @@ -2604,8 +2604,13 @@ __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
265 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
266 base_queue + i, msix_vect);
267 - /* set ITR0 value */
268 - ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
270 + * Empirical configuration for optimal real time latency
271 + * reduced interrupt throttling to 2 ms
272 + * Columbiaville pre-PRQ : local patch subject to change
274 + ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1);
275 + ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), QRX_ITR_NO_EXPR_M);
276 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
277 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
280 5.Build and install the DPDK::
282 See https://doc.dpdk.org/guides/prog_guide/build-sdk-meson.html
284 6.Make below file changes in dpdk that assure i40e to get best
285 latency of packet processing::
287 --- i40e.h 2018-11-30 11:27:00.000000000 +0000
288 +++ i40e_patched.h 2019-03-06 15:49:06.877522427 +0000
291 #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \
292 (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \
293 - (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \
294 + (I40E_ITR_NONE << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \
295 ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \
296 ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \
297 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT))
299 --- i40e_main.c 2018-11-30 11:27:00.000000000 +0000
300 +++ i40e_main_patched.c 2019-03-06 15:46:13.521518062 +0000
301 @@ -15296,6 +15296,9 @@
302 pf->hw_features |= I40E_HW_HAVE_CRT_RETIMER;
303 /* print a string summarizing features */
304 i40e_print_features(pf);
306 + /* write to this register to clear rx descriptor */
307 + i40e_aq_debug_write_register(hw, 0x0012A504, 0, NULL);
311 A.3 Configuration of System
312 ---------------------------
313 1.Boot Linux with the following arguments::
316 BOOT_IMAGE=/vmlinuz-3.10.0-1062.12.1.rt56.1042.el7.x86_64 root=/dev/mapper/centos-root ro
317 crashkernel=auto rd.lvm.lv=centos/root rd.lvm.lv=centos/swap intel_iommu=on iommu=pt
318 usbcore.autosuspend=-1 selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0
319 intel_pstate=disable cgroup_memory=1 cgroup_enable=memory mce=off idle=poll
320 hugepagesz=1G hugepages=16 hugepagesz=2M hugepages=0 default_hugepagesz=1G
321 isolcpus=1-19,21-39 rcu_nocbs=1-19,21-39 kthread_cpus=0,20 irqaffinity=0,20
324 2. Boot Linux with the following arguments for Icelake CPU::
327 BOOT_IMAGE=/vmlinuz-3.10.0-957.10.1.rt56.921.el7.x86_64
328 root=/dev/mapper/centos-root ro crashkernel=auto rd.lvm.lv=centos/root
329 rd.lvm.lv=centos/swap rhgb quiet intel_iommu=off usbcore.autosuspend=-1
330 selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0
331 intel_pstate=disable cgroup_disable=memory mce=off hugepagesz=1G
332 hugepages=40 hugepagesz=2M hugepages=0 default_hugepagesz=1G
333 isolcpus=1-23,25-47 rcu_nocbs=1-23,25-47 kthread_cpus=0 irqaffinity=0
336 3. Download from Intel Website and install updated version of i40e
337 driver if needed. The current recommended version of i40e is 2.14.13.
338 However, any latest version of i40e after 2.9.21 expected to be
339 functional for O-RAN FH.
341 4. For Columbiaville download Intel® Ethernet 800 Series (Columbiaville)
342 CVL2.3 B0/C0 Sampling Sample Validation Kit (SVK) from Intel Customer
343 Content Library. The current recommended version of ICE driver is
344 1.3.2 with ICE COMMS Package version 1.3.24.0. IAVF recommended
347 5. Identify PCIe Bus address of the Front Haul NIC (Fortville)::
350 86:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
351 86:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
352 88:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
353 88:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
355 6. Identify PCIe Bus address of the Front Haul NIC (Columbiaville)::
358 18:00.0 Ethernet controller: Intel Corporation Device 1593 (rev 02)
359 18:00.1 Ethernet controller: Intel Corporation Device 1593 (rev 02)
360 18:00.2 Ethernet controller: Intel Corporation Device 1593 (rev 02)
361 18:00.3 Ethernet controller: Intel Corporation Device 1593 (rev 02)
362 51:00.0 Ethernet controller: Intel Corporation Device 1593 (rev 02)
363 51:00.1 Ethernet controller: Intel Corporation Device 1593 (rev 02)
364 51:00.2 Ethernet controller: Intel Corporation Device 1593 (rev 02)
365 51:00.3 Ethernet controller: Intel Corporation Device 1593 (rev 02)
367 7. Identify the Ethernet device name::
372 firmware-version: 8.20 0x80009bd4 1.2879.0
373 expansion-rom-version:
374 bus-info: 0000:21:00.0
375 supports-statistics: yes
377 supports-eeprom-access: yes
378 supports-register-dump: yes
379 supports-priv-flags: yesEnable
386 firmware-version: 2.3 0x80005D18
387 expansion-rom-version:
388 bus-info: 0000:51:00.0
389 supports-statistics: yes
391 supports-eeprom-access: yes
392 supports-register-dump: yes
393 supports-priv-flags: yes
395 8. Enable 3 virtual functions (VFs) on the each of two ports of each
400 echo 0 > /sys/bus/pci/devices/0000\:88\:00.0/sriov_numvfs
401 echo 0 > /sys/bus/pci/devices/0000\:88\:00.1/sriov_numvfs
403 echo 0 > /sys/bus/pci/devices/0000\:86\:00.0/sriov_numvfs
404 echo 0 > /sys/bus/pci/devices/0000\:86\:00.1/sriov_numvfs
409 echo 3 > /sys/bus/pci/devices/0000\:88\:00.0/sriov_numvfs
410 echo 3 > /sys/bus/pci/devices/0000\:88\:00.1/sriov_numvfs
412 echo 3 > /sys/bus/pci/devices/0000\:86\:00.0/sriov_numvfs
413 echo 3 > /sys/bus/pci/devices/0000\:86\:00.1/sriov_numvfs
424 echo " Usage $0 qos with 0<= qos <= 7 with 0 as a default if no qos is provided"
429 ip link set enp136s0f0 vf 0 mac 00:11:22:33:00:00 vlan 1 qos $b
430 ip link set enp136s0f1 vf 0 mac 00:11:22:33:00:10 vlan 1 qos $b
432 ip link set enp136s0f0 vf 1 mac 00:11:22:33:01:00 vlan 2 qos $b
433 ip link set enp136s0f1 vf 1 mac 00:11:22:33:01:10 vlan 2 qos $b
435 ip link set enp136s0f0 vf 2 mac 00:11:22:33:02:00 vlan 3 qos $b
436 ip link set enp136s0f1 vf 2 mac 00:11:22:33:02:10 vlan 3 qos $b
439 ip link set enp134s0f0 vf 0 mac 00:11:22:33:00:01 vlan 1 qos $b
440 ip link set enp134s0f1 vf 0 mac 00:11:22:33:00:11 vlan 1 qos $b
442 ip link set enp134s0f0 vf 1 mac 00:11:22:33:01:01 vlan 2 qos $b
443 ip link set enp134s0f1 vf 1 mac 00:11:22:33:01:11 vlan 2 qos $b
445 ip link set enp134s0f0 vf 2 mac 00:11:22:33:02:01 vlan 3 qos $b
446 ip link set enp134s0f1 vf 2 mac 00:11:22:33:02:11 vlan 3 qos $b
448 where output is next::
452 9: enp134s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
453 link/ether 3c:fd:fe:b9:f9:60 brd ff:ff:ff:ff:ff:ff
454 vf 0 MAC 00:11:22:33:00:01, vlan 1, spoof checking on, link-state auto, trust off
455 vf 1 MAC 00:11:22:33:01:01, vlan 2, spoof checking on, link-state auto, trust off
456 vf 2 MAC 00:11:22:33:02:01, vlan 3, spoof checking on, link-state auto, trust off
457 11: enp134s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
458 link/ether 3c:fd:fe:b9:f9:61 brd ff:ff:ff:ff:ff:ff
459 vf 0 MAC 00:11:22:33:00:11, vlan 1, spoof checking on, link-state auto, trust off
460 vf 1 MAC 00:11:22:33:01:11, vlan 2, spoof checking on, link-state auto, trust off
461 vf 2 MAC 00:11:22:33:02:11, vlan 3, spoof checking on, link-state auto, trust off
462 12: enp136s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
463 link/ether 3c:fd:fe:b9:f8:b4 brd ff:ff:ff:ff:ff:ff
464 vf 0 MAC 00:11:22:33:00:00, vlan 1, spoof checking on, link-state auto, trust off
465 vf 1 MAC 00:11:22:33:01:00, vlan 2, spoof checking on, link-state auto, trust off
466 vf 2 MAC 00:11:22:33:02:00, vlan 3, spoof checking on, link-state auto, trust off
467 14: enp136s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
468 link/ether 3c:fd:fe:b9:f8:b5 brd ff:ff:ff:ff:ff:ff
469 vf 0 MAC 00:11:22:33:00:10, vlan 1, spoof checking on, link-state auto, trust off
470 vf 1 MAC 00:11:22:33:01:10, vlan 2, spoof checking on, link-state auto, trust off
471 vf 2 MAC 00:11:22:33:02:10, vlan 3, spoof checking on, link-state auto, trust off
477 More information about VFs supported by Intel NICs can be found at
478 https://doc.dpdk.org/guides/nics/intel_vf.html.
480 The resulting configuration can look like the listing below, where six
481 new VFs were added for each O-DU and O-RU port:::
484 86:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
485 86:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
486 86:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
487 86:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
488 86:02.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
489 86:0a.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
490 86:0a.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
491 86:0a.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
492 88:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
493 88:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
494 88:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
495 88:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
496 88:02.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
497 88:0a.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
498 88:0a.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
499 88:0a.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
501 9. Example where O-DU and O-RU simulation run on the same system:
509 echo 1 > /proc/sys/kernel/core_uses_pid
511 ./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/301/usecase_du.cfg --num_eth_vfs 6 \
512 --vf_addr_o_xu_a "0000:88:02.0,0000:88:0a.0" \
513 --vf_addr_o_xu_b "0000:88:02.1,0000:88:0a.1" \
514 --vf_addr_o_xu_c "0000:88:02.2,0000:88:0a.2"
522 echo 1 > /proc/sys/kernel/core_uses_pid
524 ./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/301/usecase_ru.cfg --num_eth_vfs 6 \
525 --vf_addr_o_xu_a "0000:86:02.0,0000:86:0a.0" \
526 --vf_addr_o_xu_b "0000:86:02.1,0000:86:0a.1" \
527 --vf_addr_o_xu_c "0000:86:02.2,0000:86:0a.2"
530 Install and Configure Sample Application
531 ========================================
533 To install and configure the sample application:
535 1. Set up the environment(shown for icc change for icx)::
537 For Skylake and Cascadelake
538 export GTEST_ROOT=pwd/gtest-1.7.0
539 export RTE_SDK=pwd/dpdk-20.11.3
540 export RTE_TARGET=x86_64-native-linuxapp-icc
541 export DIR_WIRELESS_SDK_ROOT=pwd/wireless_sdk
542 export WIRELESS_SDK_TARGET_ISA=avx512
543 export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc
544 export DIR_WIRELESS_SDK=${DIR_WIRELESS_SDK_ROOT}/${SDK_BUILD}
545 export MLOG_DIR=`pwd`/flexran_l1_sw/libs/mlog
546 export XRAN_DIR=`pwd`/flexran_xran
549 export GTEST_ROOT=`pwd`/gtest-1.7.0
550 export RTE_SDK=`pwd`/dpdk-20.11
551 export RTE_TARGET=x86_64-native-linuxapp-icc
552 export DIR_WIRELESS_SDK_ROOT=`pwd`/wireless_sdk
553 export WIRELESS_SDK_TARGET_ISA=snc
554 export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc
555 export DIR_WIRELESS_SDK=${DIR_WIRELESS_SDK_ROOT}/${SDK_BUILD}
556 export MLOG_DIR=`pwd`/flexran_l1_sw/libs/mlog
557 export XRAN_DIR=`pwd`/flexran_xran
559 2. export FLEXRAN_SDK=${DIR_WIRELESS_SDK}/install Compile mlog library::
561 [turner@xran home]$ cd $MLOG_DIR
562 [turner@xran xran]$ ./build.sh
564 3. Compile O-RAN library and test the application::
566 [turner@xran home]$ cd $XRAN_DIR
567 [turner@xran xran]$ ./build.sh
569 4. Configure the sample app.
571 IQ samples can be generated using Octave\* and script
572 libs/xran/app/gen_test.m. (CentOS\* has octave-3.8.2-20.el7.x86_64
573 compatible with get_test.m)
575 Other IQ sample test vectors can be used as well. The format of IQ
576 samples is binary int16_t I and Q for N slots of the OTA RF signal. For
577 example, for mmWave, it corresponds to 792RE*2*14symbol*8slots*10 ms =
578 3548160 bytes per antenna. Refer to comments in gen_test.m to correctly
579 specify the configuration for IQ test vector generation.
581 Update usecase_du.dat (or usecase_ru.cfg) with a suitable configuration
584 Update config_file_o_du.dat (or config_file_o_ru.dat) with a suitable
585 configuration for your scenario.
587 Update run_o_du.sh (run_o_ru.sh) with PCIe bus address of VF0 and VF1
588 used for U-plane and C-plane correspondingly.
590 5. Run the application using run_o_du.sh (run_o_ru.sh).
592 Install and Configure FlexRAN 5G NR L1 Application
593 ==================================================
595 The 5G NR layer 1 application can be used for executing the scenario for
596 mmWave with either the RU sample application or just the O-DU side. The
597 current release supports the constant configuration of the slot pattern
598 and RB allocation on the PHY side. The build process follows the same
599 basic steps as for the sample application above and is similar to
600 compiling 5G NR l1app for mmWave with Front Haul FPGA. Please follow the
601 general build process in the FlexRAN 5G NR Reference Solution L1 User
602 Guide (refer to *Table 2*.) (For information only as a FlexRAN binary blob
603 is delivered to the community)
605 1. O-RAN library is enabled by default l1 application
607 2. Get the FlexRAN L1 binary from https://github.com/intel/FlexRAN. Look for the l1/bin/nr5g/gnb/l1 folder for the
608 l1app binary and the corresponding phycfg and xrancfg files.
610 3. Configure the L1app using bin/nr5g/gnb/l1/phycfg_xran.xml and
611 xrancfg_sub6.xml (or other xml if it is mmW or massive MIMO). ::
614 <version>oran_f_release_v1.0</version>
615 <!-- numbers of O-RU connected to O-DU. All O-RUs are the same
616 capabilities. Max O-RUs is per XRAN_PORTS_NUM i.e. 4 -->
618 <!-- # 10G,25G,40G,100G speed of Physical connection on O-RU -->
619 <oRuEthLinkSpeed>25</oRuEthLinkSpeed>
620 <!-- # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link
622 <oRuLinesNumber>1</oRuLinesNumber>
625 <PciBusAddoRu0Vf0>0000:51:01.0</PciBusAddoRu0Vf0>
626 <PciBusAddoRu0Vf1>0000:51:01.1</PciBusAddoRu0Vf1>
627 <PciBusAddoRu0Vf2>0000:51:01.2</PciBusAddoRu0Vf2>
628 <PciBusAddoRu0Vf3>0000:51:01.3</PciBusAddoRu0Vf3>
631 <PciBusAddoRu1Vf0>0000:51:01.4</PciBusAddoRu1Vf0>
632 <PciBusAddoRu1Vf1>0000:51:01.5</PciBusAddoRu1Vf1>
633 <PciBusAddoRu1Vf2>0000:51:01.6</PciBusAddoRu1Vf2>
634 <PciBusAddoRu1Vf3>0000:51:01.7</PciBusAddoRu1Vf3>
637 <PciBusAddoRu2Vf0>0000:51:02.0</PciBusAddoRu2Vf0>
638 <PciBusAddoRu2Vf1>0000:51:02.1</PciBusAddoRu2Vf1>
639 <PciBusAddoRu2Vf2>0000:51:02.2</PciBusAddoRu2Vf2>
640 <PciBusAddoRu2Vf3>0000:51:02.3</PciBusAddoRu2Vf3>
643 <PciBusAddoRu3Vf0>0000:00:00.0</PciBusAddoRu3Vf0>
644 <PciBusAddoRu3Vf1>0000:00:00.0</PciBusAddoRu3Vf1>
645 <PciBusAddoRu3Vf2>0000:00:00.0</PciBusAddoRu3Vf2>
646 <PciBusAddoRu3Vf3>0000:00:00.0</PciBusAddoRu3Vf3>
648 <!-- remote O-RU 0 Eth Link 0 VF0, VF1-->
649 <oRuRem0Mac0>00:11:22:33:00:01<oRuRem0Mac0>
650 <oRuRem0Mac1>00:11:22:33:00:11<oRuRem0Mac1>
651 <!-- remote O-RU 0 Eth Link 1 VF2, VF3 -->
652 <oRuRem0Mac2>00:11:22:33:00:21<oRuRem0Mac2>
653 <oRuRem0Mac3>00:11:22:33:00:31<oRuRem0Mac3>
655 <!-- remote O-RU 1 Eth Link 0 VF4, VF5-->
656 <oRuRem1Mac0>00:11:22:33:01:01<oRuRem1Mac0>
657 <oRuRem1Mac1>00:11:22:33:01:11<oRuRem1Mac1>
658 <!-- remote O-RU 1 Eth Link 1 VF6, VF7 -->
659 <oRuRem1Mac2>00:11:22:33:01:21<oRuRem1Mac2>
660 <oRuRem1Mac3>00:11:22:33:01:31<oRuRem1Mac3>
662 <!-- remote O-RU 2 Eth Link 0 VF8, VF9 -->
663 <oRuRem2Mac0>00:11:22:33:02:01<oRuRem2Mac0>
664 <oRuRem2Mac1>00:11:22:33:02:11<oRuRem2Mac1>
665 <!-- remote O-RU 2 Eth Link 1 VF10, VF11-->
666 <oRuRem2Mac2>00:11:22:33:02:21<oRuRem2Mac2>
667 <oRuRem2Mac3>00:11:22:33:02:31<oRuRem2Mac3>
669 <!-- remote O-RU 2 Eth Link 0 VF12, VF13 -->
670 <oRuRem3Mac0>00:11:22:33:03:01<oRuRem3Mac0>
671 <oRuRem3Mac1>00:11:22:33:03:11<oRuRem3Mac1>
672 <!-- remote O-RU 2 Eth Link 1 VF14, VF15-->
673 <oRuRem3Mac2>00:11:22:33:03:21<oRuRem3Mac2>
674 <oRuRem3Mac3>00:11:22:33:03:31<oRuRem3Mac3>
676 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
677 <oRu0NumCc>12</oRu0NumCc>
678 <!-- First Phy instance ID mapped to this O-RU CC0 -->
679 <oRu0Cc0PhyId>0</oRu0Cc0PhyId>
680 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
681 <oRu0Cc1PhyId>1</oRu0Cc1PhyId>
682 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
683 <oRu0Cc2PhyId>2</oRu0Cc2PhyId>
684 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
685 <oRu0Cc3PhyId>3</oRu0Cc3PhyId>
686 <!-- First Phy instance ID mapped to this O-RU CC0 -->
687 <oRu0Cc4PhyId>4</oRu0Cc4PhyId>
688 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
689 <oRu0Cc5PhyId>5</oRu0Cc5PhyId>
690 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
691 <oRu0Cc6PhyId>6</oRu0Cc6PhyId>
692 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
693 <oRu0Cc7PhyId>7</oRu0Cc7PhyId>
694 <!-- First Phy instance ID mapped to this O-RU CC0 -->
695 <oRu0Cc8PhyId>8</oRu0Cc8PhyId>
696 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
697 <oRu0Cc9PhyId>9</oRu0Cc9PhyId>
698 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
699 <oRu0Cc10PhyId>10</oRuCc10PhyId>
700 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
701 <oRu0Cc11PhyId>11</oRu0Cc11PhyId>
703 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
704 <oRu1NumCc>1</oRu1NumCc>
705 <!-- First Phy instance ID mapped to this O-RU CC0 -->
706 <oRu1Cc0PhyId>1</oRu1Cc0PhyId>
707 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
708 <oRu1Cc1PhyId>1</oRu1Cc1PhyId>
709 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
710 <oRu1Cc2PhyId>2</oRu1Cc2PhyId>
711 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
712 <oRu1Cc3PhyId>3</oRu1Cc3PhyId>
714 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
715 <oRu2NumCc>1</oRu2NumCc>
716 <!-- First Phy instance ID mapped to this O-RU CC0 -->
717 <oRu2Cc0PhyId>2</oRu2Cc0PhyId>
718 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
719 <oRu2Cc1PhyId>1</oRu2Cc1PhyId>
720 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
721 <oRu2Cc2PhyId>2</oRu2Cc2PhyId>
722 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
723 <oRu2Cc3PhyId>3</oRu2Cc3PhyId>
725 <!-- XRAN Thread (core where the XRAN polling function is pinned: Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->
726 <xRANThread>19, 96, 0</xRANThread>
728 <!-- core mask for XRAN Packets Worker (core where the XRAN packet processing is pinned): Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->
729 <xRANWorker>0x8000000000, 96, 0</xRANWorker>
730 <xRANWorker_64_127>0x0000000000, 96, 0</xRANWorker_64_127>
731 <!-- XRAN: Category of O-RU 0 - Category A, 1 - Category B -->
732 <Category>0</Category>
733 <!-- Slot setup processing offload to pipeline BBU cores: [0: USE XRAN CORES 1: USE BBU CORES] -->
734 <xRANOffload>0</xRANOffload>
735 <!-- XRAN MLOG: [0: DISABLE 1: ENABLE] -->
736 <xRANMLog>0</xRANMLog>
738 <!-- XRAN: enable sleep on PMD cores -->
739 <xranPmdSleep>0</xranPmdSleep>
742 <Tadv_cp_dl>25</Tadv_cp_dl>
743 <!-- Reception Window C-plane DL-->
744 <T2a_min_cp_dl>285</T2a_min_cp_dl>
745 <T2a_max_cp_dl>429</T2a_max_cp_dl>
746 <!-- Reception Window C-plane UL-->
747 <T2a_min_cp_ul>285</T2a_min_cp_ul>
748 <T2a_max_cp_ul>429</T2a_max_cp_ul>
749 <!-- Reception Window U-plane -->
750 <T2a_min_up>71</T2a_min_up>
751 <T2a_max_up>428</T2a_max_up>
752 <!-- Transmission Window U-plane -->
753 <Ta3_min>20</Ta3_min>
754 <Ta3_max>32</Ta3_max>
756 <!-- O-DU Settings -->
759 <!-- VLAN Tag used for C-Plane -->
760 <c_plane_vlan_tag>1</c_plane_vlan_tag>
761 <u_plane_vlan_tag>2</u_plane_vlan_tag>
763 <!-- Transmission Window Fast C-plane DL -->
764 <T1a_min_cp_dl>258</T1a_min_cp_dl>
765 <T1a_max_cp_dl>470</T1a_max_cp_dl>
766 <!-- Transmission Window Fast C-plane UL -->
767 <T1a_min_cp_ul>285</T1a_min_cp_ul>
768 <T1a_max_cp_ul>429</T1a_max_cp_ul>
769 <!-- Transmission Window U-plane -->
770 <T1a_min_up>50</T1a_min_up>
771 <T1a_max_up>196</T1a_max_up>
772 <!-- Reception Window U-Plane-->
774 <Ta4_max>75</Ta4_max>
776 <!-- Enable Control Plane -->
777 <EnableCp>1</EnableCp>
779 <DynamicSectionEna>0</DynamicSectionEna>
780 <!-- Enable Dynamic section allocation for UL -->
781 <DynamicSectionEnaUL>0</DynamicSectionEnaUL>
782 <!-- Enable muti section for C-Plane -->
783 <DynamicMultiSectionEna>0</DynamicMultiSectionEna>
785 <xRANSFNWrap>1</xRANSFNWrap>
786 <!-- Total Number of DL PRBs per symbol (starting from RB 0) that is transmitted (used for testing. If 0, then value is used from PHY_CONFIG_API) -->
787 <xRANNumDLPRBs>0</xRANNumDLPRBs>
788 <!-- Total Number of UL PRBs per symbol (starting from RB 0) that is received (used for testing. If 0, then value is used from PHY_CONFIG_API) -->
789 <xRANNumULPRBs>0</xRANNumULPRBs>
790 <!-- refer to alpha as defined in section 9.7.2 of ORAN spec. this value should be alpha*(1/1.2288ns), range 0 - 1e7 (ns) -->
791 <Gps_Alpha>0</Gps_Alpha>
792 <!-- beta value as defined in section 9.7.2 of ORAN spec. range -32767 ~ +32767 -->
793 <Gps_Beta>0</Gps_Beta>
795 <!-- XRAN: Compression mode on O-DU <-> O-RU 0 - no comp 1 - BFP -->
796 <xranCompMethod>1</xranCompMethod>
797 <!-- XRAN: Uplane Compression Header type 0 - dynamic 1 - static -->
798 <xranCompHdrType>0</xranCompHdrType>
799 <!-- XRAN: iqWidth when DynamicSectionEna and BFP Compression enabled -->
800 <xraniqWidth>9</xraniqWidth>
801 <!-- Whether Modulation Compression mode is enabled or not for DL only -->
802 <xranModCompEna>0</xranModCompEna>
803 <!-- XRAN: Prach Compression mode on O-DU <-> O-RU 0 - no comp 1 - BFP -->
804 <xranPrachCompMethod>0</xranPrachCompMethod>
805 <!-- Whether Prach iqWidth when DynamicSectionEna and BFP Compression enabled -->
806 <xranPrachiqWidth>16</xranPrachiqWidth>
808 <oRu0MaxSectionsPerSlot>6</oRu0MaxSectionsPerSlot>
809 <oRu0MaxSectionsPerSymbol>6</oRu0MaxSectionsPerSymbol>
810 <oRu0nPrbElemDl>1</oRu0nPrbElemDl>
811 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
812 <!-- weight base beams -->
813 <oRu0PrbElemDl0>0,273,0,14,0,0,1,8,0,0,0</oRu0PrbElemDl0>
814 <oRu0PrbElemDl1>50,25,0,14,1,1,0,16,1,0,0</oRu0PrbElemDl1>
815 <oRu0PrbElemDl2>72,36,0,14,3,1,1,9,1,0,0</oRu0PrbElemDl2>
816 <oRu0PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemDl3>
817 <oRu0PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu0PrbElemDl4>
818 <oRu0PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu0PrbElemDl5>
819 <oRu0PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu0PrbElemDl6>
820 <oRu0PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemDl7>
823 <oRu0nPrbElemUl>1</oRu0nPrbElemUl>
824 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask-->
825 <!-- weight base beams -->
826 <oRu0PrbElemUl0>0,273,0,14,0,0,1,8,0,0,0</oRu0PrbElemUl0>
827 <oRu0PrbElemUl1>0,273,0,14,0,0,1,8,0,0,0</oRu0PrbElemUl1>
828 <oRu0PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu0PrbElemUl2>
829 <oRu0PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu0PrbElemUl3>
830 <oRu0PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu0PrbElemUl4>
831 <oRu0PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu0PrbElemUl5>
832 <oRu0PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu0PrbElemUl6>
833 <oRu0PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemUl7>
836 <oRu1MaxSectionsPerSlot>6</oRu1MaxSectionsPerSlot>
837 <oRu1MaxSectionsPerSymbol>6</oRu1MaxSectionsPerSymbol>
838 <oRu1nPrbElemDl>1</oRu1nPrbElemDl>
839 <oRu1PrbElemDl0>0,273,0,14,0,0,1,8,0,0,0</oRu1PrbElemDl0>
840 <oRu1PrbElemDl1>53,53,0,14,2,1,1,8,1,0,0</oRu1PrbElemDl1>
841 <oRu1nPrbElemUl>1</oRu1nPrbElemUl>
842 <oRu1PrbElemUl0>0,273,0,14,0,0,1,8,0,0,0</oRu1PrbElemUl0>
843 <oRu1PrbElemUl1>53,53,0,14,2,1,1,8,1,0,0</oRu1PrbElemUl1>
845 <oRu2MaxSectionsPerSlot>6</oRu2MaxSectionsPerSlot>
846 <oRu2MaxSectionsPerSymbol>6</oRu2MaxSectionsPerSymbol>
847 <oRu2nPrbElemDl>1</oRu2nPrbElemDl>
848 <oRu2PrbElemDl0>0,273,0,14,0,0,1,8,0,0,0</oRu2PrbElemDl0>
849 <oRu2PrbElemDl1>53,53,0,14,2,1,1,8,1,0,0</oRu2PrbElemDl1>
850 <oRu2nPrbElemUl>1</oRu2nPrbElemUl>
851 <oRu2PrbElemUl0>0,273,0,14,0,0,1,8,0,0,0</oRu2PrbElemUl0>
852 <oRu2PrbElemUl1>53,53,0,14,2,1,1,8,1,0,0</oRu2PrbElemUl1>
858 4. Modify l1/bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs). ::
860 $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:21:02.0
861 $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:21:02.1
863 5. Use configuration of test mac per::
865 l1//bin/nr5g/gnb.testmac/cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg (info only N/A)
867 <!-- mmWave mu 3 100MHz -->
868 TEST_FD, 1002, 1, fd/mu3_100mhz/2/fd_testconfig_tst2.cfg
871 6. To execute l1app with O-DU functionality according to O-RAN Fronthaul specification, enter::
873 [root@xran flexran] cd ./l1/bin/nr5g/gnb/l1
874 [root@xran l1]#./l1.sh –xran
879 7. To execute testmac with O-DU functionality according to O-RAN Fronthaul specification, enter::
881 [root@xran flexran] cd ./l1/bin/nr5g/gnb/testmac
884 8. To execute test case type (info only as file not available)::
887 --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg
891 Configure FlexRAN 5G NR L1 Application for multiple O-RUs with multiple numerologies
892 ====================================================================================
894 The 5G NR layer 1 application can be used for executing the scenario for
895 multiple cells with multiple numerologies. The current release supports
896 the constant configuration of different numerologies on different O-RU
897 ports. It is required that the first O-RU (O-RU0) to be configured with
898 highest numerology. The configuration procedure is similar as described
899 in above section. Please refer to the configuration file located in
900 bin\nr5g\gnb\l1\orancfg\sub3_mu0_20mhz_sub6_mu1_100mhz_4x4\gnb\xrancfg_sub6_oru.xml
902 Install and Configure FlexRAN 5G NR L1 Application for Massive - MIMO
903 =====================================================================
905 The 5G NR layer 1 application can be used for executing the scenario for
906 Massive-MIMO with either the RU sample application or just the O-DU
907 side. 3 cells scenario with 64T64R Massive MIMO is targeted for Icelake
908 system with Columbiavile NIC. The current release supports the constant
909 configuration of the slot pattern and RB allocation on the PHY side.
910 Please follow the general build process in the FlexRAN 5G NR Reference
911 Solution L1 User Guide (refer to Table 2.)
913 1. O-RAN library is enabled by default l1 application
915 2. 5G NR L1 application available from https://github.com/intel/FlexRAN.
916 Look for the l1/bin/nr5g/gnb/l1 folder for the
917 l1app binary and the corresponding phycfg and xrancfg files.
919 3. Configure the L1app using bin/nr5g/gnb/l1/xrancfg_sub6_mmimo.xml.::
922 <version>oran_f_release_v1.0<</version>
923 <!-- numbers of O-RU connected to O-DU. All O-RUs are the same capabilities. Max O-RUs is per XRAN_PORTS_NUM i.e. 4 -->
925 <!-- # 10G,25G,40G,100G speed of Physical connection on O-RU -->
926 <oRuEthLinkSpeed>25</oRuEthLinkSpeed>
927 <!-- # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link in IOT spec) -->
928 <oRuLinesNumber>2</oRuLinesNumber>
929 <!-- (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs -->
930 <oRuCUon1Vf>1</oRuCUon1Vf>
933 <PciBusAddoRu0Vf0>0000:51:01.0</PciBusAddoRu0Vf0>
934 <PciBusAddoRu0Vf1>0000:51:09.0</PciBusAddoRu0Vf1>
935 <PciBusAddoRu0Vf2>0000:51:01.2</PciBusAddoRu0Vf2>
936 <PciBusAddoRu0Vf3>0000:51:01.3</PciBusAddoRu0Vf3>
939 <PciBusAddoRu1Vf0>0000:51:11.0</PciBusAddoRu1Vf0>
940 <PciBusAddoRu1Vf1>0000:51:19.0</PciBusAddoRu1Vf1>
941 <PciBusAddoRu1Vf2>0000:51:01.6</PciBusAddoRu1Vf2>
942 <PciBusAddoRu1Vf3>0000:51:01.7</PciBusAddoRu1Vf3>
945 <PciBusAddoRu2Vf0>0000:18:01.0</PciBusAddoRu2Vf0>
946 <PciBusAddoRu2Vf1>0000:18:09.0</PciBusAddoRu2Vf1>
947 <PciBusAddoRu2Vf2>0000:51:02.2</PciBusAddoRu2Vf2>
948 <PciBusAddoRu2Vf3>0000:51:02.3</PciBusAddoRu2Vf3>
951 <PciBusAddoRu3Vf0>0000:00:00.0</PciBusAddoRu3Vf0>
952 <PciBusAddoRu3Vf1>0000:00:00.0</PciBusAddoRu3Vf1>
953 <PciBusAddoRu3Vf2>0000:00:00.0</PciBusAddoRu3Vf2>
954 <PciBusAddoRu3Vf3>0000:00:00.0</PciBusAddoRu3Vf3>
956 <!-- remote O-RU 0 Eth Link 0 VF0, VF1-->
957 <oRuRem0Mac0>00:11:22:33:00:01<oRuRem0Mac0>
958 <oRuRem0Mac1>00:11:22:33:00:11<oRuRem0Mac1>
959 <!-- remote O-RU 0 Eth Link 1 VF2, VF3 -->
960 <oRuRem0Mac2>00:11:22:33:00:21<oRuRem0Mac2>
961 <oRuRem0Mac3>00:11:22:33:00:31<oRuRem0Mac3>
963 <!-- remote O-RU 1 Eth Link 0 VF4, VF5-->
964 <oRuRem1Mac0>00:11:22:33:01:01<oRuRem1Mac0>
965 <oRuRem1Mac1>00:11:22:33:01:11<oRuRem1Mac1>
966 <!-- remote O-RU 1 Eth Link 1 VF6, VF7 -->
967 <oRuRem1Mac2>00:11:22:33:01:21<oRuRem1Mac2>
968 <oRuRem1Mac3>00:11:22:33:01:31<oRuRem1Mac3>
970 <!-- remote O-RU 2 Eth Link 0 VF8, VF9 -->
971 <oRuRem2Mac0>00:11:22:33:02:01<oRuRem2Mac0>
972 <oRuRem2Mac1>00:11:22:33:02:11<oRuRem2Mac1>
973 <!-- remote O-RU 2 Eth Link 1 VF10, VF11-->
974 <oRuRem2Mac2>00:11:22:33:02:21<oRuRem2Mac2>
975 <oRuRem2Mac3>00:11:22:33:02:31<oRuRem2Mac3>
977 <!-- remote O-RU 2 Eth Link 0 VF12, VF13 -->
978 <oRuRem3Mac0>00:11:22:33:03:01<oRuRem3Mac0>
979 <oRuRem3Mac1>00:11:22:33:03:11<oRuRem3Mac1>
980 <!-- remote O-RU 2 Eth Link 1 VF14, VF15-->
981 <oRuRem3Mac2>00:11:22:33:03:21<oRuRem3Mac2>
982 <oRuRem3Mac3>00:11:22:33:03:31<oRuRem3Mac3>
984 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
985 <oRu0NumCc>1</oRu0NumCc>
986 <!-- First Phy instance ID mapped to this O-RU CC0 -->
987 <oRu0Cc0PhyId>0</oRu0Cc0PhyId>
988 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
989 <oRu0Cc1PhyId>1</oRu0Cc1PhyId>
990 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
991 <oRu0Cc2PhyId>2</oRu0Cc2PhyId>
992 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
993 <oRu0Cc3PhyId>3</oRu0Cc3PhyId>
995 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
996 <oRu1NumCc>1</oRu1NumCc>
997 <!-- First Phy instance ID mapped to this O-RU CC0 -->
998 <oRu1Cc0PhyId>1</oRu1Cc0PhyId>
999 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
1000 <oRu1Cc1PhyId>1</oRu1Cc1PhyId>
1001 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
1002 <oRu1Cc2PhyId>2</oRu1Cc2PhyId>
1003 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
1004 <oRu1Cc3PhyId>3</oRu1Cc3PhyId>
1006 <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->
1007 <oRu2NumCc>1</oRu2NumCc>
1008 <!-- First Phy instance ID mapped to this O-RU CC0 -->
1009 <oRu2Cc0PhyId>2</oRu2Cc0PhyId>
1010 <!-- Second Phy instance ID mapped to this O-RU CC1 -->
1011 <oRu2Cc1PhyId>1</oRu2Cc1PhyId>
1012 <!-- Third Phy instance ID mapped to this O-RU CC2 -->
1013 <oRu2Cc2PhyId>2</oRu2Cc2PhyId>
1014 <!-- Forth Phy instance ID mapped to this O-RU CC3 -->
1015 <oRu2Cc3PhyId>3</oRu2Cc3PhyId>
1017 <!-- XRAN Thread (core where the XRAN polling function is pinned: Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->
1018 <xRANThread>22, 96, 0</xRANThread>
1020 <!-- core mask for XRAN Packets Worker (core where the XRAN packet processing is pinned): Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->
1021 <xRANWorker>0x3800000, 96, 0</xRANWorker>
1022 <!-- XRAN: Category of O-RU 0 - Category A, 1 - Category B -->
1023 <Category>1</Category>
1025 <!-- XRAN: enable sleep on PMD cores -->
1026 <xranPmdSleep>0</xranPmdSleep>
1028 <!-- RU Settings -->
1029 <Tadv_cp_dl>25</Tadv_cp_dl>
1030 <!-- Reception Window C-plane DL-->
1031 <T2a_min_cp_dl>285</T2a_min_cp_dl>
1032 <T2a_max_cp_dl>429</T2a_max_cp_dl>
1033 <!-- Reception Window C-plane UL-->
1034 <T2a_min_cp_ul>285</T2a_min_cp_ul>
1035 <T2a_max_cp_ul>429</T2a_max_cp_ul>
1036 <!-- Reception Window U-plane -->
1037 <T2a_min_up>71</T2a_min_up>
1038 <T2a_max_up>428</T2a_max_up>
1039 <!-- Transmission Window U-plane -->
1040 <Ta3_min>20</Ta3_min>
1041 <Ta3_max>32</Ta3_max>
1043 <!-- O-DU Settings -->
1046 <!-- VLAN Tag used for C-Plane -->
1047 <c_plane_vlan_tag>1</c_plane_vlan_tag>
1048 <u_plane_vlan_tag>2</u_plane_vlan_tag>
1050 <!-- Transmission Window Fast C-plane DL -->
1051 <T1a_min_cp_dl>258</T1a_min_cp_dl>
1052 <T1a_max_cp_dl>429</T1a_max_cp_dl>
1053 <!-- Transmission Window Fast C-plane UL -->
1054 <T1a_min_cp_ul>285</T1a_min_cp_ul>
1055 <T1a_max_cp_ul>300</T1a_max_cp_ul>
1056 <!-- Transmission Window U-plane -->
1057 <T1a_min_up>96</T1a_min_up>
1058 <T1a_max_up>196</T1a_max_up>
1059 <!-- Reception Window U-Plane-->
1060 <Ta4_min>0</Ta4_min>
1061 <Ta4_max>75</Ta4_max>
1063 <!-- Enable Control Plane -->
1064 <EnableCp>1</EnableCp>
1066 <DynamicSectionEna>0</DynamicSectionEna>
1067 <!-- Enable Dynamic section allocation for UL -->
1068 <DynamicSectionEnaUL>0</DynamicSectionEnaUL>
1069 <xRANSFNWrap>1</xRANSFNWrap>
1070 <!-- Total Number of DL PRBs per symbol (starting from RB 0) that is transmitted (used for testing. If 0, then value is used from PHY_CONFIG_API) -->
1071 <xRANNumDLPRBs>0</xRANNumDLPRBs>
1072 <!-- Total Number of UL PRBs per symbol (starting from RB 0) that is received (used for testing. If 0, then value is used from PHY_CONFIG_API) -->
1073 <xRANNumULPRBs>0</xRANNumULPRBs>
1074 <!-- refer to alpha as defined in section 9.7.2 of ORAN spec. this value should be alpha*(1/1.2288ns), range 0 - 1e7 (ns) -->
1075 <Gps_Alpha>0</Gps_Alpha>
1076 <!-- beta value as defined in section 9.7.2 of ORAN spec. range -32767 ~ +32767 -->
1077 <Gps_Beta>0</Gps_Beta>
1079 <!-- XRAN: Compression mode on O-DU <-> O-RU 0 - no comp 1 - BFP -->
1080 <xranCompMethod>1</xranCompMethod>
1081 <!-- XRAN: iqWidth when DynamicSectionEna and BFP Compression enabled -->
1082 <xraniqWidth>9</xraniqWidth>
1084 <!-- M-plane values of O-RU configuration -->
1085 <oRu0MaxSectionsPerSlot>6<oRu0MaxSectionsPerSlot>
1086 <oRu0MaxSectionsPerSymbol>6<oRu0MaxSectionsPerSymbol>
1088 <oRu0nPrbElemDl>6</oRu0nPrbElemDl>
1089 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1090 <!-- weight base beams -->
1091 <oRu0PrbElemDl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemDl0>
1092 <oRu0PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemDl1>
1093 <oRu0PrbElemDl2>96,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemDl2>
1094 <oRu0PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemDl3>
1095 <oRu0PrbElemDl4>192,48,0,14,5,1,1,9,1,0,0</oRu0PrbElemDl4>
1096 <oRu0PrbElemDl5>240,33,0,14,6,1,1,9,1,0,0</oRu0PrbElemDl5>
1097 <oRu0PrbElemDl6>240,33,0,14,7,1,1,9,1,0,0</oRu0PrbElemDl6>
1098 <oRu0PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemDl7>
1100 <!-- extType = 11 -->
1101 <oRu0ExtBfwDl0>2,24,0,0,9,1</oRu0ExtBfwDl0>
1102 <oRu0ExtBfwDl1>2,24,0,0,9,1</oRu0ExtBfwDl1>
1103 <oRu0ExtBfwDl2>2,24,0,0,9,1</oRu0ExtBfwDl2>
1104 <oRu0ExtBfwDl3>2,24,0,0,9,1</oRu0ExtBfwDl3>
1105 <oRu0ExtBfwDl4>2,24,0,0,9,1</oRu0ExtBfwDl4>
1106 <oRu0ExtBfwDl5>2,17,0,0,9,1</oRu0ExtBfwDl5>
1108 <oRu0nPrbElemUl>6</oRu0nPrbElemUl>
1109 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1110 <!-- weight base beams -->
1111 <oRu0PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemUl0>
1112 <oRu0PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemUl1>
1113 <oRu0PrbElemUl2>96,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemUl2>
1114 <oRu0PrbElemUl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemUl3>
1115 <oRu0PrbElemUl4>192,48,0,14,5,1,1,9,1,0,0</oRu0PrbElemUl4>
1116 <oRu0PrbElemUl5>240,33,0,14,6,1,1,9,1,0,0</oRu0PrbElemUl5>
1117 <oRu0PrbElemUl6>240,33,0,14,7,1,1,9,1,0,0</oRu0PrbElemUl6>
1118 <oRu0PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemUl7>
1120 <!-- extType = 11 -->
1121 <oRu0ExtBfwUl0>2,24,0,0,9,1</oRu0ExtBfwUl0>
1122 <oRu0ExtBfwUl1>2,24,0,0,9,1</oRu0ExtBfwUl1>
1123 <oRu0ExtBfwUl2>2,24,0,0,9,1</oRu0ExtBfwUl2>
1124 <oRu0ExtBfwUl3>2,24,0,0,9,1</oRu0ExtBfwUl3>
1125 <oRu0ExtBfwUl4>2,24,0,0,9,1</oRu0ExtBfwUl4>
1126 <oRu0ExtBfwUl5>2,17,0,0,9,1</oRu0ExtBfwUl5>
1128 <oRu0nPrbElemSrs>1</oRu0nPrbElemSrs>
1129 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1130 <!-- weight base beams -->
1131 <oRu0PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu0PrbElemSrs0>
1132 <oRu0PrbElemSrs1>0,273,0,14,1,1,1,9,1,0,0</oRu0PrbElemSrs1>
1134 <!-- M-plane values of O-RU configuration -->
1135 <oRu10MaxSectionsPerSlot>6<oRu1MaxSectionsPerSlot>
1136 <oRu1MaxSectionsPerSymbol>6<oRu1MaxSectionsPerSymbol>
1138 <oRu1nPrbElemDl>2</oRu1nPrbElemDl>
1139 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1140 <!-- weight base beams -->
1141 <oRu1PrbElemDl0>0,48,0,14,0,1,1,9,1,0,0</oRu1PrbElemDl0>
1142 <oRu1PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu1PrbElemDl1>
1143 <oRu1PrbElemDl2>96,48,0,14,3,1,1,9,1,0,0</oRu1PrbElemDl2>
1144 <oRu1PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu1PrbElemDl3>
1145 <oRu1PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu1PrbElemDl4>
1146 <oRu1PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu1PrbElemDl5>
1147 <oRu1PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu1PrbElemDl6>
1148 <oRu1PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu1PrbElemDl7>
1150 <!-- extType = 11 -->
1151 <oRu1ExtBfwDl0>2,24,0,0,9,1</oRu1ExtBfwDl0>
1152 <oRu1ExtBfwDl1>2,24,0,0,9,1</oRu1ExtBfwDl1>
1154 <oRu1nPrbElemUl>2</oRu1nPrbElemUl>
1155 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1156 <!-- weight base beams -->
1157 <oRu1PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu1PrbElemUl0>
1158 <oRu1PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu1PrbElemUl1>
1159 <oRu1PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu1PrbElemUl2>
1160 <oRu1PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu1PrbElemUl3>
1161 <oRu1PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu1PrbElemUl4>
1162 <oRu1PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu1PrbElemUl5>
1163 <oRu1PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu1PrbElemUl6>
1164 <oRu1PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu1PrbElemUl7>
1166 <!-- extType = 11 -->
1167 <oRu1ExtBfwUl0>2,24,0,0,9,1</oRu1ExtBfwUl0>
1168 <oRu1ExtBfwUl1>2,24,0,0,9,1</oRu1ExtBfwUl1>
1170 <oRu1nPrbElemSrs>1</oRu1nPrbElemSrs>
1171 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1172 <!-- weight base beams -->
1173 <oRu1PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu1PrbElemSrs0>
1174 <oRu1PrbElemSrs1>0,273,0,14,1,1,1,9,1,0,0</oRu1PrbElemSrs1>
1176 <!-- M-plane values of O-RU configuration -->
1177 <oRu20MaxSectionsPerSlot>6<oRu2MaxSectionsPerSlot>
1178 <oRu2MaxSectionsPerSymbol>6<oRu2MaxSectionsPerSymbol>
1180 <oRu2nPrbElemDl>2</oRu2nPrbElemDl>
1181 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1182 <!-- weight base beams -->
1183 <oRu2PrbElemDl0>0,48,0,14,1,1,1,9,1,0,0</oRu2PrbElemDl0>
1184 <oRu2PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu2PrbElemDl1>
1185 <oRu2PrbElemDl2>96,48,0,14,3,1,1,9,1,0,0</oRu2PrbElemDl2>
1186 <oRu2PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu2PrbElemDl3>
1187 <oRu2PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu2PrbElemDl4>
1188 <oRu2PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu2PrbElemDl5>
1189 <oRu2PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu2PrbElemDl6>
1190 <oRu2PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu2PrbElemDl7>
1192 <!-- extType = 11 -->
1193 <oRu2ExtBfwDl0>2,24,0,0,9,1</oRu2ExtBfwDl0>
1194 <oRu2ExtBfwDl1>2,24,0,0,9,1</oRu2ExtBfwDl1>
1196 <oRu2nPrbElemUl>2</oRu2nPrbElemUl>
1197 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1198 <!-- weight base beams -->
1199 <oRu2PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu2PrbElemUl0>
1200 <oRu2PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu2PrbElemUl1>
1201 <oRu2PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu2PrbElemUl2>
1202 <oRu2PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu2PrbElemUl3>
1203 <oRu2PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu2PrbElemUl4>
1204 <oRu2PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu2PrbElemUl5>
1205 <oRu2PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu2PrbElemUl6>
1206 <oRu2PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu2PrbElemUl7>
1208 <!-- extType = 11 -->
1209 <oRu2ExtBfwUl0>2,24,0,0,9,1</oRu2ExtBfwUl0>
1210 <oRu2ExtBfwUl1>2,24,0,0,9,1</oRu2ExtBfwUl1>
1212 <oRu2nPrbElemSrs>1</oRu2nPrbElemSrs>
1213 <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->
1214 <!-- weight base beams -->
1215 <oRu2PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu2PrbElemSrs0>
1216 <oRu2PrbElemSrs1>0,273,0,14,1,1,1,9,1,0,0</oRu2PrbElemSrs1>
1221 4. Modify ./bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs). ::
1223 ethDevice0=0000:51:01.0
1224 ethDevice1=0000:51:01.1
1225 ethDevice2=0000:51:01.2
1226 ethDevice3=0000:51:01.3
1227 ethDevice4=0000:51:01.4
1228 ethDevice5=0000:51:01.5
1235 fecDevice0=0000:92:00.0
1237 5. Use configuration of test mac per::
1239 (Info only as these files not avilable)
1240 /bin/nr5g/gnb/testmac/icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg
1242 TEST_FD, 3370, 3, fd/mu1_100mhz/376/fd_testconfig_tst376.cfg,
1243 fd/mu1_100mhz/377/fd_testconfig_tst377.cfg,
1244 fd/mu1_100mhz/377/fd_testconfig_tst377.cfg
1246 6. To execute l1app with O-DU functionality according to O-RAN Fronthaul specification, enter::
1248 [root@xran flexran] cd ./l1/bin/nr5g/gnb/l1
1250 Radio mode with XRAN - Sub6 100Mhz Massive-MIMO (CatB)
1253 7. To execute testmac with O-DU functionality according to O-RAN Fronthaul specification, enter::
1255 [root@xran flexran] cd ./l1/bin/nr5g/gnb/testmac
1257 8. To execute test case type::
1259 (Info only as file not available)
1260 ./l2.sh --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg