1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
12 # distributed under the License is distributed on an "AS IS" BASIS, #
13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
15 # limitations under the License. #
16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for Entry point fucntions
29 **********************************************************************/
31 /** @file sch_common.c
32 @brief This module performs common scheduling
34 #include "common_def.h"
41 #include "du_app_mac_inf.h"
42 #include "mac_sch_interface.h"
44 #include "sch_utils.h"
46 SchCb schCb[SCH_MAX_INST];
47 uint16_t prachCfgIdxTable[MAX_PRACH_CONFIG_IDX][8];
48 uint16_t numRbForPrachTable[MAX_RACH_NUM_RB_IDX][5];
49 uint8_t pucchResourceSet[MAX_PUCCH_RES_SET_IDX][4];
51 SchMacUlSchInfoFunc schMacUlSchInfoOpts[] =
59 * @brief common resource allocation for SSB
63 * Function : schBroadcastAlloc
65 * This function handles common scheduling for DL
67 * @param[in] SchCellCb *cell, cell cb
68 * @param[in] DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
71 uint8_t schBroadcastAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc,
75 uint8_t ssbStartPrb, ssbStartSymb, idx;
76 SchDlSlotInfo *schDlSlotInfo;
79 schDlSlotInfo = cell->schDlSlotInfo[slot];
80 if(dlBrdcstAlloc->ssbTrans)
82 ssbStartPrb = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
83 ssbStartSymb = cell->ssbStartSymbArr[dlBrdcstAlloc->ssbIdxSupported-1]; /*since we are
84 supporting only 1 ssb beam */
86 /* Assign interface structure */
87 for(idx=0; idx<dlBrdcstAlloc->ssbIdxSupported; idx++)
90 ssbInfo.fdAlloc.startPrb = ssbStartPrb;
91 ssbInfo.fdAlloc.numPrb = SCH_SSB_NUM_PRB;
92 ssbInfo.tdAlloc.startSymb = ssbStartSymb;
93 ssbInfo.tdAlloc.numSymb = SCH_SSB_NUM_SYMB;
94 dlBrdcstAlloc->ssbInfo[idx] = ssbInfo;
95 schDlSlotInfo->ssbInfo[idx] = ssbInfo;
98 schDlSlotInfo->ssbPres = true;
99 schDlSlotInfo->ssbIdxSupported = dlBrdcstAlloc->ssbIdxSupported;
100 for(idx=ssbStartSymb; idx<ssbStartSymb+SCH_SSB_NUM_SYMB; idx++)
102 schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1; /* +1 for kSsb */
106 /* SIB1 allocation */
107 if(dlBrdcstAlloc->sib1Trans)
110 uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
111 uint8_t mcs = 4; /* MCS fixed to 4 */
112 uint8_t numSib1Prb = 0;
113 schDlSlotInfo->sib1Pres = true;
115 tbSize = schCalcTbSize(cell->cellCfg.sib1SchCfg.sib1PduLen); /* send this value to the func in bytes when considering sib1 size */
116 numSib1Prb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
117 for(idx=0; idx<SCH_SYMBOL_PER_SLOT; idx++)
119 schDlSlotInfo->assignedPrb[idx] = ssbStartPrb + SCH_SSB_NUM_PRB + 1 + numSib1Prb; /* 10 PRBs for sib1 */
121 memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->cellCfg.sib1SchCfg.bwp, sizeof(BwpCfg));
122 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg));
123 memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(PdschCfg));
124 dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg.dci.pdschCfg = &dlBrdcstAlloc->sib1Alloc.sib1PdschCfg;
129 /*******************************************************************
131 * @brief Handles sending UL scheduler info to MAC
135 * Function : sendUlSchInfoToMac
138 * Sends UL Sch info to MAC from SCH
141 * @return ROK - success
144 * ****************************************************************/
145 int sendUlSchInfoToMac(UlSchedInfo *ulSchedInfo, Inst inst)
149 memset(&pst, 0, sizeof(Pst));
150 FILL_PST_SCH_TO_MAC(pst, inst);
151 pst.event = EVENT_UL_SCH_INFO;
153 return(*schMacUlSchInfoOpts[pst.selector])(&pst, ulSchedInfo);
156 * @brief resource allocation for PRACH
160 * Function : schPrachResAlloc
162 * This function handles PRACH allocation
164 * @param[in] SchCellCb *cell, cell cb
165 * @param[in] UlSchedInfo *ulSchedInfo, UL scheduling info
168 void schPrachResAlloc(SchCellCb *cell, UlSchedInfo *ulSchedInfo, SlotIndInfo prachOccasionTimingInfo)
171 uint8_t numPrachRb = 0;
173 uint8_t freqStart = 0;
174 uint8_t prachCfgIdx = 0;
175 uint8_t prachFormat = 0;
178 uint16_t prachSubframe = 0;
179 uint8_t prachStartSymbol = 0;
180 uint8_t prachOcas = 0;
181 uint8_t dataType = 0;
183 SchUlSlotInfo *schUlSlotInfo = NULLP;
185 puschScs = cell->cellCfg.schInitialUlBwp.bwp.scs;
186 schUlSlotInfo = cell->schUlSlotInfo[prachOccasionTimingInfo.slot];
187 prachCfgIdx = cell->cellCfg.schRachCfg.prachCfgIdx;
189 /* derive the prachCfgIdx table paramters */
190 x = prachCfgIdxTable[prachCfgIdx][1];
191 y = prachCfgIdxTable[prachCfgIdx][2];
192 prachSubframe = prachCfgIdxTable[prachCfgIdx][3];
194 if((prachOccasionTimingInfo.sfn%x) == y)
196 /* check for subFrame number */
197 if ((1 << prachOccasionTimingInfo.slot) & prachSubframe)
199 /* prach ocassion present in this subframe */
201 prachFormat = prachCfgIdxTable[prachCfgIdx][0];
202 prachStartSymbol = prachCfgIdxTable[prachCfgIdx][4];
203 prachOcas = prachCfgIdxTable[prachCfgIdx][6];
205 /* freq domain resource determination for RACH*/
206 freqStart = cell->cellCfg.schRachCfg.msg1FreqStart;
207 /* numRa determined as 𝑛 belonging {0,1,.., M − 1},
208 * where M is given by msg1Fdm */
209 numRa = (cell->cellCfg.schRachCfg.msg1Fdm - 1);
210 for(idx=0; idx<MAX_RACH_NUM_RB_IDX; idx++)
212 if(numRbForPrachTable[idx][0] == cell->cellCfg.schRachCfg.rootSeqLen)
214 if(numRbForPrachTable[idx][1] == cell->cellCfg.schRachCfg.prachSubcSpacing)
216 if(numRbForPrachTable[idx][2] == puschScs)
223 numPrachRb = numRbForPrachTable[idx][3];
224 dataType |= SCH_DATATYPE_PRACH;
225 /* Considering first slot in the frame for PRACH */
227 schUlSlotInfo->assignedPrb[idx] = freqStart+numPrachRb;
229 ulSchedInfo->dataType = dataType;
231 ulSchedInfo->prachSchInfo.numPrachOcas = prachOcas;
232 ulSchedInfo->prachSchInfo.prachFormat = prachFormat;
233 ulSchedInfo->prachSchInfo.numRa = numRa;
234 ulSchedInfo->prachSchInfo.prachStartSymb = prachStartSymbol;
238 uint16_t fillPucchResourceInfo(SchPucchInfo *schPucchInfo, Inst inst)
240 /* derive pucchResourceSet from schCellCfg */
241 SchCellCb *cell = schCb[inst].cells[inst];
242 SchPucchCfgCmn *pucchCfg = &cell->cellCfg.schInitialUlBwp.pucchCommon;
243 uint8_t pucchIdx = pucchCfg->pucchResourceCommon;
244 SchBwpParams *ulBwp = &cell->cellCfg.schInitialUlBwp.bwp;
246 schPucchInfo->fdAlloc.startPrb = ulBwp->freqAlloc.startPrb + pucchResourceSet[pucchIdx][3];
247 schPucchInfo->fdAlloc.numPrb = PUCCH_NUM_PRB_FORMAT_0;
248 schPucchInfo->tdAlloc.startSymb = pucchResourceSet[pucchIdx][1];
249 schPucchInfo->tdAlloc.numSymb = pucchResourceSet[pucchIdx][2];
250 schPucchInfo->pucchFormat = pucchResourceSet[pucchIdx][0];
252 /* set HARQ flag to true */
253 schPucchInfo->harqFlag = true;
254 schPucchInfo->numHarqBits = 1; /* 1 bit for HARQ */
256 /* set SR and UCI flag to false */
257 schPucchInfo->srFlag = true;
258 schPucchInfo->uciFlag = true;
264 * @brief resource allocation for UL
268 * Function : schUlResAlloc
270 * This function handles UL Resource allocation
272 * @param[in] SchCellCb *cell, cellCb
275 uint8_t schUlResAlloc(SchCellCb *cell, Inst schInst)
278 UlSchedInfo ulSchedInfo;
279 SchUlSlotInfo *schUlSlotInfo = NULLP;
280 SlotIndInfo ulTimingInfo;
281 memset(&ulSchedInfo, 0, sizeof(UlSchedInfo));
284 ADD_DELTA_TO_TIME(cell->slotInfo,ulTimingInfo,PHY_DELTA+SCHED_DELTA);
286 ulSchedInfo.cellId = cell->cellId;
287 ulSchedInfo.slotIndInfo.cellId = ulSchedInfo.cellId;
288 ulSchedInfo.slotIndInfo.sfn = ulTimingInfo.sfn;
289 ulSchedInfo.slotIndInfo.slot = ulTimingInfo.slot;
291 /* Schedule resources for PRACH */
292 schPrachResAlloc(cell, &ulSchedInfo, ulTimingInfo);
294 schUlSlotInfo = cell->schUlSlotInfo[ulTimingInfo.slot];
295 if(schUlSlotInfo->schPuschInfo)
297 ulSchedInfo.crnti = schUlSlotInfo->schPuschInfo->crnti;
298 ulSchedInfo.dataType |= SCH_DATATYPE_PUSCH;
299 memcpy(&ulSchedInfo.schPuschInfo, schUlSlotInfo->schPuschInfo,
300 sizeof(SchPuschInfo));
301 SCH_FREE(schUlSlotInfo->schPuschInfo, sizeof(SchPuschInfo));
302 schUlSlotInfo->schPuschInfo = NULL;
305 if(schUlSlotInfo->pucchPres)
307 ulSchedInfo.dataType |= SCH_DATATYPE_UCI;
308 fillPucchResourceInfo(&schUlSlotInfo->schPucchInfo, schInst);
309 memcpy(&ulSchedInfo.schPucchInfo, &schUlSlotInfo->schPucchInfo,
310 sizeof(SchPucchInfo));
311 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
315 ret = sendUlSchInfoToMac(&ulSchedInfo, schInst);
318 DU_LOG("\nSending UL Sch info from SCH to MAC failed");
321 schInitUlSlot(schUlSlotInfo);
325 /*******************************************************************
327 * @brief Fills pdcch and pdsch info for msg4
331 * Function : schDlRsrcAllocMsg4
334 * Fills pdcch and pdsch info for msg4
337 * @return ROK - success
340 * ****************************************************************/
341 uint8_t schDlRsrcAllocMsg4(DlMsgAlloc *msg4Alloc, SchCellCb *cell, uint16_t slot)
343 uint8_t coreset0Idx = 0;
345 uint8_t firstSymbol = 0;
346 uint8_t numSymbols = 0;
348 uint8_t offsetPointA;
349 uint8_t FreqDomainResource[6] = {0};
351 uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
352 uint8_t mcs = 4; /* MCS fixed to 4 */
353 SchBwpDlCfg *initialBwp;
355 PdcchCfg *pdcch = &msg4Alloc->dlMsgPdcchCfg;
356 PdschCfg *pdsch = &msg4Alloc->dlMsgPdschCfg;
357 BwpCfg *bwp = &msg4Alloc->bwp;
359 initialBwp = &cell->cellCfg.schInitialDlBwp;
360 offsetPointA = cell->cellCfg.ssbSchCfg.ssbOffsetPointA;
361 coreset0Idx = initialBwp->pdcchCommon.commonSearchSpace.coresetId;
363 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
364 numRbs = coresetIdxTable[coreset0Idx][1];
365 numSymbols = coresetIdxTable[coreset0Idx][2];
366 offset = coresetIdxTable[coreset0Idx][3];
368 /* calculate time domain parameters */
369 uint16_t mask = 0x2000;
370 for(firstSymbol=0; firstSymbol<14;firstSymbol++)
372 if(initialBwp->pdcchCommon.commonSearchSpace.monitoringSymbol & mask)
378 /* calculate the PRBs */
379 freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
382 bwp->freqAlloc.numPrb = initialBwp->bwp.freqAlloc.numPrb;
383 bwp->freqAlloc.startPrb = initialBwp->bwp.freqAlloc.startPrb;
384 bwp->subcarrierSpacing = initialBwp->bwp.scs;
385 bwp->cyclicPrefix = initialBwp->bwp.cyclicPrefix;
387 /* fill the PDCCH PDU */
388 pdcch->coresetCfg.startSymbolIndex = firstSymbol;
389 pdcch->coresetCfg.durationSymbols = numSymbols;
390 memcpy(pdcch->coresetCfg.freqDomainResource,FreqDomainResource,6);
391 pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
392 pdcch->coresetCfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
393 pdcch->coresetCfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
394 pdcch->coresetCfg.coreSetType = 0;
395 pdcch->coresetCfg.coreSetSize = numRbs;
396 pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
397 pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
399 pdcch->dci.rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
400 pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
401 pdcch->dci.scramblingRnti = 0;
402 pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
403 pdcch->dci.aggregLevel = 4;
404 pdcch->dci.beamPdcchInfo.numPrgs = 1;
405 pdcch->dci.beamPdcchInfo.prgSize = 1;
406 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
407 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
408 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
409 pdcch->dci.txPdcchPower.powerValue = 0;
410 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
412 /* fill the PDSCH PDU */
414 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
415 pdsch->rnti = cell->schDlSlotInfo[slot]->dlMsgInfo->crnti;
417 pdsch->numCodewords = 1;
418 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
420 pdsch->codeword[cwCount].targetCodeRate = 308;
421 pdsch->codeword[cwCount].qamModOrder = 2;
422 pdsch->codeword[cwCount].mcsIndex = mcs; /* mcs configured to 4 */
423 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
424 pdsch->codeword[cwCount].rvIndex = 0;
425 /* 38.214: Table 5.1.3.2-1, divided by 8 to get the value in bytes */
426 /* TODO : Calculate tbSize based of DL CCCH msg size */
427 tbSize = schCalcTbSize(2664/8); /* send this value to the func in bytes when considering msg4 size */
428 pdsch->codeword[cwCount].tbSize = tbSize;
430 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
431 pdsch->numLayers = 1;
432 pdsch->transmissionScheme = 0;
434 pdsch->dmrs.dlDmrsSymbPos = 2;
435 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
436 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
437 pdsch->dmrs.scid = 0;
438 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
439 pdsch->dmrs.dmrsPorts = 0;
440 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Setting to Type-A */
441 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
442 pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
443 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
444 /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
445 pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB;
446 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,mcs,numPdschSymbols);
447 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
448 pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
449 pdsch->pdschTimeAlloc.timeAlloc.numSymb = 12;
450 pdsch->beamPdschInfo.numPrgs = 1;
451 pdsch->beamPdschInfo.prgSize = 1;
452 pdsch->beamPdschInfo.digBfInterfaces = 0;
453 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
454 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
455 pdsch->txPdschPower.powerControlOffset = 0;
456 pdsch->txPdschPower.powerControlOffsetSS = 0;
458 pdcch->dci.pdschCfg = pdsch;
463 uint16_t schAllocPucchResource(SchCellCb *cell,uint16_t crnti, uint16_t slot)
465 uint8_t k1 = 1; /* dl-DataToUL-ACK RRC parameter will received from DU-APP msg4-pucch config */
466 uint16_t pucchSlot = (slot + k1) % SCH_NUM_SLOTS;
467 SchUlSlotInfo *schUlSlotInfo = NULLP;
469 schUlSlotInfo = cell->schUlSlotInfo[pucchSlot];
470 memset(&schUlSlotInfo->schPucchInfo, 0, sizeof(SchPucchInfo));
472 schUlSlotInfo->pucchPres = true;
473 schUlSlotInfo->schPucchInfo.rnti = crnti;
478 /*******************************************************************
480 * @brief Fills pdcch and pdsch info for dedicated DL msg
484 * Function : schDlRsrcAllocDlMsg
487 * Fills pdcch and pdsch info for dl msg
490 * @return ROK - success
493 * ****************************************************************/
494 uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t crnti,
495 uint16_t accumalatedSize, uint16_t slot)
499 uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
500 PdcchCfg *pdcch = NULLP;
501 PdschCfg *pdsch = NULLP;
504 SchControlRsrcSet coreset1;
505 SchPdschConfig pdschCfg;
507 pdcch = &dlMsgAlloc->dlMsgPdcchCfg;
508 pdsch = &dlMsgAlloc->dlMsgPdschCfg;
509 bwp = &dlMsgAlloc->bwp;
511 GET_UE_IDX(crnti, ueIdx);
512 ueCb = cell->ueCb[ueIdx-1];
513 coreset1 = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdcchCfg.cRSetToAddModList[0];
514 pdschCfg = ueCb.ueCfg.spCellCfg.servCellCfg.initDlBwp.pdschCfg;
517 bwp->freqAlloc.numPrb = MAX_NUM_RB;
518 bwp->freqAlloc.startPrb = 0;
519 bwp->subcarrierSpacing = cell->cellCfg.sib1SchCfg.bwp.subcarrierSpacing;
520 bwp->cyclicPrefix = cell->cellCfg.sib1SchCfg.bwp.cyclicPrefix;
522 /* fill the PDCCH PDU */
523 //Considering coreset1 also starts from same symbol as coreset0
524 pdcch->coresetCfg.startSymbolIndex = coresetIdxTable[0][3];
525 pdcch->coresetCfg.durationSymbols = coreset1.duration;
526 memcpy(pdcch->coresetCfg.freqDomainResource, coreset1.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
527 pdcch->coresetCfg.cceRegMappingType = coreset1.cceRegMappingType; /* non-interleaved */
528 pdcch->coresetCfg.regBundleSize = 6; /* must be 6 for non-interleaved */
529 pdcch->coresetCfg.interleaverSize = 0; /* NA for non-interleaved */
530 pdcch->coresetCfg.coreSetType = 1; /* non PBCH coreset */
531 //Considering number of RBs in coreset1 is same as coreset0
532 pdcch->coresetCfg.coreSetSize = coresetIdxTable[0][1];
533 pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
534 pdcch->coresetCfg.precoderGranularity = coreset1.precoderGranularity;
536 pdcch->dci.rnti = ueCb.crnti;
537 pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
538 pdcch->dci.scramblingRnti = 0;
539 pdcch->dci.cceIndex = 0; /* 0-3 for UL and 4-7 for DL */
540 pdcch->dci.aggregLevel = 4;
541 pdcch->dci.beamPdcchInfo.numPrgs = 1;
542 pdcch->dci.beamPdcchInfo.prgSize = 1;
543 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
544 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
545 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
546 pdcch->dci.txPdcchPower.powerValue = 0;
547 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
549 /* fill the PDSCH PDU */
551 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
552 pdsch->rnti = ueCb.crnti;
554 pdsch->numCodewords = 1;
555 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
557 pdsch->codeword[cwCount].targetCodeRate = 308;
558 pdsch->codeword[cwCount].qamModOrder = ueCb.ueCfg.dlModInfo.modOrder;
559 pdsch->codeword[cwCount].mcsIndex = ueCb.ueCfg.dlModInfo.mcsIndex;
560 pdsch->codeword[cwCount].mcsTable = ueCb.ueCfg.dlModInfo.mcsTable;
561 pdsch->codeword[cwCount].rvIndex = 0;
562 tbSize = schCalcTbSize(accumalatedSize);
563 pdsch->codeword[cwCount].tbSize = tbSize;
565 pdsch->dataScramblingId = cell->cellCfg.phyCellId;
566 pdsch->numLayers = 1;
567 pdsch->transmissionScheme = 0;
569 pdsch->dmrs.dlDmrsSymbPos = 2;
570 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
571 pdsch->dmrs.dlDmrsScramblingId = cell->cellCfg.phyCellId;
572 pdsch->dmrs.scid = 0;
573 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
574 pdsch->dmrs.dmrsPorts = 0;
575 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Setting to Type-A */
576 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
577 pdsch->dmrs.dmrsAddPos = pdschCfg.dmrsDlCfgForPdschMapTypeA.addPos;
578 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
579 pdsch->pdschFreqAlloc.freqAlloc.startPrb = 1;
580 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, ueCb.ueCfg.dlModInfo.mcsIndex, numPdschSymbols);
581 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
582 pdsch->pdschTimeAlloc.timeAlloc.startSymb = pdschCfg.timeDomRsrcAllociList[0].startSymbol;
583 pdsch->pdschTimeAlloc.timeAlloc.numSymb = pdschCfg.timeDomRsrcAllociList[0].symbolLength;
584 pdsch->beamPdschInfo.numPrgs = 1;
585 pdsch->beamPdschInfo.prgSize = 1;
586 pdsch->beamPdschInfo.digBfInterfaces = 0;
587 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
588 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
589 pdsch->txPdschPower.powerControlOffset = 0;
590 pdsch->txPdschPower.powerControlOffsetSS = 0;
592 pdcch->dci.pdschCfg = pdsch;
596 /**********************************************************************
598 **********************************************************************/