1 /*******************************************************************************
2 ################################################################################
3 # Copyright (c) [2017-2019] [Radisys] #
5 # Licensed under the Apache License, Version 2.0 (the "License"); #
6 # you may not use this file except in compliance with the License. #
7 # You may obtain a copy of the License at #
9 # http://www.apache.org/licenses/LICENSE-2.0 #
11 # Unless required by applicable law or agreed to in writing, software #
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13 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
14 # See the License for the specific language governing permissions and #
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16 ################################################################################
17 *******************************************************************************/
19 /************************************************************************
25 Desc: C source code for scheduler fucntions
29 **********************************************************************/
32 @brief This file implements the schedulers main access to MAC layer code.
34 #include "common_def.h"
35 #include "du_app_mac_inf.h"
40 #include "rg_sch_inf.h"
43 #include "tfu.x" /* TFU types */
44 #include "lrg.x" /* layer management typedefs for MAC */
45 #include "rgr.x" /* layer management typedefs for MAC */
46 #include "rg_sch_inf.x" /* typedefs for Scheduler */
47 #include "mac_sch_interface.h"
49 #include "sch_utils.h"
51 SchCb schCb[SCH_MAX_INST];
52 void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm);
55 SchCellCfgCfmFunc SchCellCfgCfmOpts[] =
57 packSchCellCfgCfm, /* LC */
58 MacProcSchCellCfgCfm, /* TC */
59 packSchCellCfgCfm /* LWLC */
64 * @brief Task Initiation function.
68 * Function : schActvInit
70 * This function is supplied as one of parameters during MAC's
71 * task registration. MAC will invoke this function once, after
72 * it creates and attaches this TAPA Task to a system task.
74 * @param[in] Ent Entity, the entity ID of this task.
75 * @param[in] Inst Inst, the instance ID of this task.
76 * @param[in] Region Region, the region ID registered for memory
78 * @param[in] Reason Reason.
82 uint8_t schActvInit(Ent entity, Inst instId, Region region, Reason reason)
84 Inst inst = (instId - SCH_INST_START);
86 /* Initialize the MAC TskInit structure to zero */
87 memset ((uint8_t *)&schCb[inst], 0, sizeof(schCb));
89 /* Initialize the MAC TskInit with received values */
90 schCb[inst].schInit.ent = entity;
91 schCb[inst].schInit.inst = inst;
92 schCb[inst].schInit.region = region;
93 schCb[inst].schInit.pool = 0;
94 schCb[inst].schInit.reason = reason;
95 schCb[inst].schInit.cfgDone = FALSE;
96 schCb[inst].schInit.acnt = FALSE;
97 schCb[inst].schInit.usta = FALSE;
98 schCb[inst].schInit.trc = FALSE;
99 schCb[inst].schInit.procId = ODU_GET_PROCID();
105 * @brief Scheduler instance Configuration Handler.
109 * Function : SchInstCfg
111 * This function in called by SchProcGenCfgReq(). It handles the
112 * general configurations of the scheduler instance. Returns
113 * reason for success/failure of this function.
115 * @param[in] RgCfg *cfg, the Configuaration information
117 * -# LCM_REASON_NOT_APPL
118 * -# LCM_REASON_INVALID_MSGTYPE
119 * -# LCM_REASON_MEM_NOAVAIL
121 uint8_t SchInstCfg(RgCfg *cfg, Inst dInst)
123 uint16_t ret = LCM_REASON_NOT_APPL;
124 Inst inst = (dInst - SCH_INST_START);
126 printf("\nEntered SchInstCfg()");
127 /* Check if Instance Configuration is done already */
128 if (schCb[inst].schInit.cfgDone == TRUE)
130 return LCM_REASON_INVALID_MSGTYPE;
132 /* Update the Pst structure for LM interface */
133 memcpy(&schCb[inst].schInit.lmPst,
134 &cfg->s.schInstCfg.genCfg.lmPst,
137 schCb[inst].schInit.inst = inst;
138 schCb[inst].schInit.lmPst.srcProcId = schCb[inst].schInit.procId;
139 schCb[inst].schInit.lmPst.srcEnt = schCb[inst].schInit.ent;
140 schCb[inst].schInit.lmPst.srcInst = schCb[inst].schInit.inst +
142 schCb[inst].schInit.lmPst.event = EVTNONE;
144 schCb[inst].schInit.region = cfg->s.schInstCfg.genCfg.mem.region;
145 schCb[inst].schInit.pool = cfg->s.schInstCfg.genCfg.mem.pool;
146 schCb[inst].genCfg.tmrRes = cfg->s.schInstCfg.genCfg.tmrRes;
148 schCb[inst].genCfg.forceCntrlSrbBoOnPCel = cfg->s.schInstCfg.genCfg.forceCntrlSrbBoOnPCel;
149 schCb[inst].genCfg.isSCellActDeactAlgoEnable = cfg->s.schInstCfg.genCfg.isSCellActDeactAlgoEnable;
151 schCb[inst].genCfg.startCellId = cfg->s.schInstCfg.genCfg.startCellId;
153 /* Initialzie the timer queue */
154 memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType)*RGSCH_TQ_SIZE);
155 /* Initialize the timer control point */
156 memset(&schCb[inst].tmrTqCp, 0, sizeof(CmTqCp));
157 schCb[inst].tmrTqCp.tmrLen = RGSCH_TQ_SIZE;
159 /* SS_MT_TMR needs to be enabled as schActvTmr needs instance information */
160 /* Timer Registration request to SSI */
161 if (ODU_REG_TMR_MT(schCb[inst].schInit.ent, dInst,
162 (int)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK)
164 RLOG_ARG0(L_ERROR,DBG_INSTID,inst, "SchInstCfg(): Failed to "
166 return (LCM_REASON_MEM_NOAVAIL);
169 /* Set Config done in TskInit */
170 schCb[inst].schInit.cfgDone = TRUE;
171 printf("\nScheduler gen config done");
177 * @brief Layer Manager Configuration request handler.
181 * Function : SchProcGenCfgReq
183 * This function handles the configuration
184 * request received at scheduler instance from the Layer Manager.
185 * -# Based on the cfg->hdr.elmId.elmnt value it invokes one of the
186 * functions rgHdlGenCfg() or rgHdlSapCfg().
187 * -# Invokes RgMiLrgSchCfgCfm() to send back the confirmation to the LM.
189 * @param[in] Pst *pst, the post structure
190 * @param[in] RgMngmt *cfg, the configuration parameter's structure
194 uint8_t SchProcGenCfgReq(Pst *pst, RgMngmt *cfg)
196 uint8_t ret = LCM_PRIM_OK;
197 uint16_t reason = LCM_REASON_NOT_APPL;
201 if(pst->dstInst < SCH_INST_START)
203 DU_LOG("\nInvalid inst ID");
204 DU_LOG("\nSchProcGenCfgReq(): "
205 "pst->dstInst=%d SCH_INST_START=%d", pst->dstInst,SCH_INST_START);
208 printf("\nReceived scheduler gen config");
209 /* Fill the post structure for sending the confirmation */
210 memset(&cfmPst, 0 , sizeof(Pst));
211 SchFillCfmPst(pst, &cfmPst, cfg);
213 memset(&cfm, 0, sizeof(RgMngmt));
220 cfm.hdr.elmId.elmnt = cfg->hdr.elmId.elmnt;
221 switch(cfg->hdr.elmId.elmnt)
224 reason = SchInstCfg(&cfg->t.cfg,pst->dstInst );
228 reason = LCM_REASON_INVALID_ELMNT;
229 DU_LOG("\nInvalid Elmnt=%d", cfg->hdr.elmId.elmnt);
233 if (reason != LCM_REASON_NOT_APPL)
238 cfm.cfm.status = ret;
239 cfm.cfm.reason = reason;
241 SchSendCfgCfm(&cfmPst, &cfm);
242 /* SPutSBuf(pst->region, pst->pool, (Data *)cfg, sizeof(RgMngmt)); */
245 }/*-- SchProcGenCfgReq --*/
248 * @brief slot indication from MAC to SCH.
252 * Function : MacSchSlotInd
254 * This API is invoked by PHY to indicate slot indication to Scheduler for
257 * @param[in] Pst *pst
258 * @param[in] SlotIndInfo *slotInd
263 uint8_t MacSchSlotInd(Pst *pst, SlotIndInfo *slotInd)
265 Inst inst = pst->dstInst-SCH_INST_START;
267 schProcessSlotInd(slotInd, inst);
270 } /* MacSchSlotInd */
272 /*******************************************************************
274 * @brief Processes Rach indication from MAC
278 * Function : MacSchRachInd
281 * Processes Rach indication from MAC
284 * @return ROK - success
287 * ****************************************************************/
288 uint8_t MacSchRachInd(Pst *pst, RachIndInfo *rachInd)
290 Inst inst = pst->dstInst-SCH_INST_START;
291 DU_LOG("\nSCH : Received Rach indication");
292 schProcessRachInd(rachInd, inst);
296 /*******************************************************************
298 * @brief Processes CRC indication from MAC
302 * Function : MacSchCrcInd
305 * Processes CRC indication from MAC
307 * @params[in] Post structure
309 * @return ROK - success
312 * ****************************************************************/
313 uint8_t MacSchCrcInd(Pst *pst, CrcIndInfo *crcInd)
315 switch(crcInd->crcInd[0])
318 DU_LOG("\nSCH : Received CRC indication. CRC Status [FAILURE]");
321 DU_LOG("\nSCH : Received CRC indication. CRC Status [PASS]");
324 DU_LOG("\nSCH : Invalid CRC state %d", crcInd->crcInd[0]);
332 * @brief inti cellCb based on cellCfg
336 * Function : schInitCellCb
338 * This API is invoked after receiving schCellCfg
340 * @param[in] schCellCb *cell
341 * @param[in] SchCellCfg *schCellCfg
346 uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg)
349 SCH_ALLOC(cell, sizeof(SchCellCb));
352 DU_LOG("\nMemory allocation failed in schInitCellCb");
356 cell->cellId = schCellCfg->cellId;
357 cell->instIdx = inst;
358 switch(schCellCfg->ssbSchCfg.scsCommon)
362 cell->numSlots = SCH_NUM_SLOTS;
366 DU_LOG("\nSCS %d not supported", schCellCfg->ssbSchCfg.scsCommon);
369 for(uint8_t idx=0; idx<SCH_NUM_SLOTS; idx++)
371 SchDlSlotInfo *schDlSlotInfo;
372 SchUlSlotInfo *schUlSlotInfo;
375 SCH_ALLOC(schDlSlotInfo, sizeof(SchDlSlotInfo));
378 DU_LOG("\nMemory allocation failed in schInitCellCb");
383 SCH_ALLOC(schUlSlotInfo, sizeof(SchUlSlotInfo));
386 DU_LOG("\nMemory allocation failed in schInitCellCb");
390 schInitDlSlot(schDlSlotInfo);
391 schInitUlSlot(schUlSlotInfo);
393 cell->schDlSlotInfo[idx] = schDlSlotInfo;
394 cell->schUlSlotInfo[idx] = schUlSlotInfo;
397 schCb[inst].cells[inst] = cell;
399 DU_LOG("\nCell init completed for cellId:%d", cell->cellId);
405 * @brief Fill SIB1 configuration
409 * Function : fillSchSib1Cfg
411 * Fill SIB1 configuration
413 * @param[in] Inst schInst : scheduler instance
414 * SchSib1Cfg *sib1SchCfg : cfg to be filled
415 * uint16_t pci : physical cell Id
416 * uint8_t offsetPointA : offset
419 void fillSchSib1Cfg(Inst schInst, SchSib1Cfg *sib1SchCfg, uint16_t pci, \
420 uint8_t offsetPointA)
422 uint8_t coreset0Idx = 0;
423 uint8_t searchSpace0Idx = 0;
424 //uint8_t ssbMuxPattern = 0;
426 uint8_t numSymbols = 0;
429 //uint8_t numSearchSpacePerSlot = 0;
431 uint8_t firstSymbol = 0; /* need to calculate using formula mentioned in 38.213 */
432 uint8_t slotIndex = 0;
433 uint8_t FreqDomainResource[6] = {0};
435 uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
437 PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg);
438 PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg);
439 BwpCfg *bwp = &(sib1SchCfg->bwp);
441 coreset0Idx = sib1SchCfg->coresetZeroIndex;
442 searchSpace0Idx = sib1SchCfg->searchSpaceZeroIndex;
444 /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
445 //ssbMuxPattern = coresetIdxTable[coreset0Idx][0];
446 numRbs = coresetIdxTable[coreset0Idx][1];
447 numSymbols = coresetIdxTable[coreset0Idx][2];
448 offset = coresetIdxTable[coreset0Idx][3];
450 /* derive the search space params from table 13-11 spec 38.213 */
451 oValue = searchSpaceIdxTable[searchSpace0Idx][0];
452 //numSearchSpacePerSlot = searchSpaceIdxTable[searchSpace0Idx][1];
453 mValue = searchSpaceIdxTable[searchSpace0Idx][2];
454 firstSymbol = searchSpaceIdxTable[searchSpace0Idx][3];
456 /* calculate the n0, need to add the formulae, as of now the value is 0
457 * Need to add the even and odd values of i during configuration
458 * [(O . 2^u + i . M ) ] mod numSlotsPerSubframe
459 * assuming u = 0, i = 0, numSlotsPerSubframe = 10
460 * Also, from this configuration, coreset0 is only on even subframe */
461 slotIndex = ((oValue * 1) + (0 * mValue)) % 10;
462 sib1SchCfg->n0 = slotIndex;
464 /* calculate the PRBs */
465 freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource);
468 bwp->freqAlloc.numPrb = MAX_NUM_RB; /* whole of BW */
469 bwp->freqAlloc.startPrb = 0;
470 bwp->subcarrierSpacing = 0; /* 15Khz */
471 bwp->cyclicPrefix = 0; /* normal */
473 /* fill the PDCCH PDU */
474 pdcch->coresetCfg.coreSetSize = numRbs;
475 pdcch->coresetCfg.startSymbolIndex = firstSymbol;
476 pdcch->coresetCfg.durationSymbols = numSymbols;
477 memcpy(pdcch->coresetCfg.freqDomainResource,FreqDomainResource,6);
478 pdcch->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
479 pdcch->coresetCfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
480 pdcch->coresetCfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
481 pdcch->coresetCfg.coreSetType = 0;
482 pdcch->coresetCfg.shiftIndex = pci;
483 pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
485 pdcch->dci.rnti = SI_RNTI;
486 pdcch->dci.scramblingId = pci;
487 pdcch->dci.scramblingRnti = 0;
488 pdcch->dci.cceIndex = 0;
489 pdcch->dci.aggregLevel = 4;
490 pdcch->dci.beamPdcchInfo.numPrgs = 1;
491 pdcch->dci.beamPdcchInfo.prgSize = 1;
492 pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
493 pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
494 pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
495 pdcch->dci.txPdcchPower.powerValue = 0;
496 pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
497 /* Storing pdschCfg pointer here. Required to access pdsch config while
498 fillig up pdcch pdu */
499 pdcch->dci.pdschCfg = pdsch;
501 /* fill the PDSCH PDU */
503 pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
504 pdsch->rnti = 0xFFFF; /* SI-RNTI */
506 pdsch->numCodewords = 1;
507 for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
509 pdsch->codeword[cwCount].targetCodeRate = 308;
510 pdsch->codeword[cwCount].qamModOrder = 2;
511 pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs;
512 pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
513 pdsch->codeword[cwCount].rvIndex = 0;
514 tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen);
515 pdsch->codeword[cwCount].tbSize = tbSize;
517 pdsch->dataScramblingId = pci;
518 pdsch->numLayers = 1;
519 pdsch->transmissionScheme = 0;
521 pdsch->dmrs.dlDmrsSymbPos = 2;
522 pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
523 pdsch->dmrs.dlDmrsScramblingId = pci;
524 pdsch->dmrs.scid = 0;
525 pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
526 pdsch->dmrs.dmrsPorts = 0;
527 pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Type-A */
528 pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS;
529 pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
531 pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
532 pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB; /* the RB numbering starts from coreset0,
533 and PDSCH is always above SSB */
534 pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols);
535 pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
536 pdsch->pdschTimeAlloc.rowIndex = 1;
537 pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */
538 pdsch->pdschTimeAlloc.timeAlloc.numSymb = numPdschSymbols;
539 pdsch->beamPdschInfo.numPrgs = 1;
540 pdsch->beamPdschInfo.prgSize = 1;
541 pdsch->beamPdschInfo.digBfInterfaces = 0;
542 pdsch->beamPdschInfo.prg[0].pmIdx = 0;
543 pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
544 pdsch->txPdschPower.powerControlOffset = 0;
545 pdsch->txPdschPower.powerControlOffsetSS = 0;
550 * @brief Fill SSB start symbol
554 * Function : fillSsbStartSymb
556 * This API stores SSB start index per beam
558 * @param[in] SchCellCb *cellCb
563 void fillSsbStartSymb(SchCellCb *cellCb)
567 scs = cellCb->cellCfg.ssbSchCfg.scsCommon;
568 uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM];
570 memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
571 /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */
577 cnt = 2;/* n = 0, 1 for SCS = 15KHz */
578 for(uint8_t idx=0; idx<cnt; idx++)
580 /* start symbol determined using {2, 8} + 14n */
581 ssbStartSymbArr[symbIdx++] = 2 + SCH_SYMBOL_PER_SLOT*idx;
582 ssbStartSymbArr[symbIdx++] = 8 + SCH_SYMBOL_PER_SLOT*idx;
587 DU_LOG("\nSCS %d is currently not supported", scs);
589 memset(cellCb->ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM));
590 memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM);
595 * @brief cell config from MAC to SCH.
599 * Function : macSchCellCfgReq
601 * This API is invoked by MAC to send cell config to SCH
603 * @param[in] Pst *pst
604 * @param[in] SchCellCfg *schCellCfg
609 uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg)
613 SchCellCfgCfm schCellCfgCfm;
615 Inst inst = pst->dstInst-1;
617 schInitCellCb(inst, schCellCfg);
618 cellCb = schCb[inst].cells[inst]; //cells is of MAX_CELLS, why inst
619 cellCb->macInst = pst->srcInst;
621 /* derive the SIB1 config parameters */
624 &(schCellCfg->sib1SchCfg),
625 schCellCfg->phyCellId,
626 schCellCfg->ssbSchCfg.ssbOffsetPointA);
627 memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg));
629 /* Initializing global variables */
630 cellCb->actvUeBitMap = 0;
631 cellCb->boIndBitMap = 0;
633 /* Fill and send Cell config confirm */
634 memset(&rspPst, 0, sizeof(Pst));
635 FILL_PST_SCH_TO_MAC(rspPst, pst->dstInst);
636 rspPst.event = EVENT_SCH_CELL_CFG_CFM;
638 schCellCfgCfm.cellId = schCellCfg->cellId;
639 schCellCfgCfm.rsp = RSP_OK;
641 ret = (*SchCellCfgCfmOpts[rspPst.selector])(&rspPst, &schCellCfgCfm);
647 /*******************************************************************
649 * @brief Processes DL RLC BO info from MAC
653 * Function : MacSchDlRlcBoInfo
656 * Processes DL RLC BO info from MAC
659 * @return ROK - success
662 * ****************************************************************/
663 uint8_t MacSchDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo)
668 SchUeCb *ueCb = NULLP;
669 SchCellCb *cell = NULLP;
670 SchDlSlotInfo *schDlSlotInfo = NULLP;
672 Inst inst = pst->dstInst-SCH_INST_START;
673 DU_LOG("\nSCH : Received RLC BO Status indication");
674 cell = schCb[inst].cells[inst];
676 GET_UE_IDX(dlBoInfo->crnti, ueIdx);
677 ueCb = &cell->ueCb[ueIdx-1];
678 lcId = dlBoInfo->lcId;
680 if(lcId == SRB1_LCID || lcId == SRB2_LCID || lcId == SRB3_LCID || \
681 (lcId >= MIN_DRB_LCID && lcId <= MAX_DRB_LCID))
683 SET_ONE_BIT(ueIdx, cell->boIndBitMap);
684 ueCb->dlInfo.dlLcCtxt[lcId].bo = dlBoInfo->dataVolume;
686 else if(lcId != SRB0_LCID)
688 DU_LOG("\nSCH : Invalid LC Id %d in MacSchDlRlcBoInfo", lcId);
692 slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA + BO_DELTA) % SCH_NUM_SLOTS;
693 schDlSlotInfo = cell->schDlSlotInfo[slot];
695 SCH_ALLOC(schDlSlotInfo->dlMsgInfo, sizeof(DlMsgInfo));
696 if(!schDlSlotInfo->dlMsgInfo)
698 DU_LOG("\nSCH : Memory allocation failed for dlMsgInfo");
699 schDlSlotInfo = NULL;
702 schDlSlotInfo->dlMsgInfo->crnti = dlBoInfo->crnti;
703 schDlSlotInfo->dlMsgInfo->ndi = 1;
704 schDlSlotInfo->dlMsgInfo->harqProcNum = 0;
705 schDlSlotInfo->dlMsgInfo->dlAssignIdx = 0;
706 schDlSlotInfo->dlMsgInfo->pucchTpc = 0;
707 schDlSlotInfo->dlMsgInfo->pucchResInd = 0;
708 schDlSlotInfo->dlMsgInfo->harqFeedbackInd = 0;
709 schDlSlotInfo->dlMsgInfo->dciFormatId = 1;
710 if(lcId == SRB0_LCID)
711 schDlSlotInfo->dlMsgInfo->isMsg4Pdu = true;
716 /*******************************************************************
718 * @brief Processes BSR indiation from MAC
722 * Function : MacSchBsr
725 * Processes DL BSR from MAC
727 * @params[in] Pst pst
728 * UlBufferStatusRptInd bsrInd
729 * @return ROK - success
732 * ****************************************************************/
733 uint8_t MacSchBsr(Pst *pst, UlBufferStatusRptInd *bsrInd)
735 Inst schInst = pst->dstInst-SCH_INST_START;
736 SchCellCb *cellCb = NULLP;
737 SchUeCb *ueCb = NULLP;
740 DU_LOG("\nSCH : Received BSR");
741 cellCb = schCb[schInst].cells[schInst];
742 ueCb = schGetUeCb(cellCb, bsrInd->crnti);
744 /* store dataVolume per lcg in uecb */
745 for(lcgIdx = 0; lcgIdx < bsrInd->numLcg; lcgIdx++)
747 ueCb->bsrInfo[lcgIdx].priority = 1; //TODO: determining LCG priority?
748 ueCb->bsrInfo[lcgIdx].dataVol = bsrInd->dataVolInfo[lcgIdx].dataVol;
753 /*******************************************************************
755 * @brief Processes SR UCI indication from MAC
759 * Function : MacSchSrUciInd
762 * Processes SR UCI indication from MAC
764 * @params[in] Post structure
766 * @return ROK - success
769 * ****************************************************************/
770 uint8_t MacSchSrUciInd(Pst *pst, SrUciIndInfo *uciInd)
772 Inst inst = pst->dstInst-SCH_INST_START;
775 SchCellCb *cellCb = schCb[inst].cells[inst];
777 DU_LOG("\nSCH : Received SR");
779 ueCb = schGetUeCb(cellCb, uciInd->crnti);
781 if(uciInd->numSrBits)
787 /**********************************************************************
789 **********************************************************************/